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Length: 6274 (0x1882)
Types: TextFile
Names: »TEST.S«
└─⟦18a2fd90d⟧ Bits:30005144 8" CR80 Floppy CR80FD_0132 ( CR/D/2479 CRD2479: En-CPU CPU/CACHE TEST- PROGRAMMER node: master: CRP5 )
└─⟦56889de57⟧
└─ ⟦this⟧ »TEST.S«
MAINMODULE CACHE_MEMORY_TESTS;
%PRINT
"***********************************************************************"
"
"THE FOLLOWING TEST-FACILITIES ARE INCLUDED:
"
" 1/ TEST OF CACHE-ENABLING/DISABLING:
" THE CACHE MAY BE ENABLED/DISABLED BY THE COMMANDS:
" 'ENABLE CACHE' , 'DISABLE CACHE'.
"
" 2/ REPETITIVE LOAD/ READS OF CACHE:
" 1K CONSECUTIVE DATA-MEMORY LOCATIONS ARE WRITTEN
" WITH A RECOGNIZABLE PATTERN (1,2,3,.......#3FF)+LOGPAGE.
" THE 1K LOCATIONS ARE READ TWICE, AND CHECKED.
" THE SAME PROCEDURE IS CARRIED OUT WITH ALL DATA
" DATA PAGES, EXCEPT LOG DATA PAGES 0,1 AND #3F.
" HAVING DONE THIS, ALL THE LOADED MEMORY LOCATIONS ARE
" READ, CHECKING FOR FAULTS.
" INPUT PARAMETERS: NUMBER OF RUNS(WHICH IS AGLOBAL PARAMETER).
" (AND THE GLOBAL VARIABLE CACHE_STATUS,
" CACHE_STATUS IS A BOOLIAN VARIABLE,
" CACHE_STATUS=1 : CACHE ENABLED,
" =0 : CACHE DISABLED.
"
" 3/ TEST OF THE CACHE-MEMORY ABILITY TO CLEAR CACHE-LOCATIONS
" TO WHICH OTHER CPUS/ADDRESSING MODULES WRITE.
" THIS TEST MUST COMPRISE TEST OF CHANNEL BUS CACHE-INTERFACE,
" AND PROCESSOR BUS CACHE-INTERFACE.
"
" 4/ TEST OF CACHE-CLEARING MECHANISM.
" ALGORITHM: MAP IN PHPAGE Y AS LOGPAGE 4.
" CLEAR LOGPAGE 4.
" MAP IN PHPAGE X AS LOGPAGE 3.
" WRITE PATTERN, READ END CHECK PATTERN.
" MAP IN PHPAGE Y AS LOGPAGE 3, AND PHPAGE X AS LOGPAGE
" 4.
" CLEAR CACHE.
" READ LOGPAGE 3 (=PHPAGE Y). THE PAGE MUST BE CLAERED,
" NU REMAINS OF PHPAGE X MAY EXIST IN CACHE.
"
"
"PERFORMANCE TEST: PERF 1,2,3..........
" UDVALGE INSTRUKTIONER UDFOERES ET STORT ANTAL GANGE, I EN PERIODE
" BESTEMT AF COUNT, OG FAST-TIMEREN. EXEKVERINGSTIDEN PR INSTRUK-
" TION UDREGNES.
"
"***********************************************************************
%SOURCE HEADER.S
%SOURCE @**DAMOS.D*GENS.D*GENERAL.S
%SOURCE CONSOLE.S
VAR
INPUTSTRING: ARRAY[0..15] OF INTEGER;
INPUT_LAST: INTEGER; "POINTS TO LAST VALID CHARACTER
INPUT_POINTER: INTEGER; "POINTER TO CURRENT CHARACTER
DICA: INTEGER; "=1: DISABLE CACHE, =0: ENABLE CACHE"
LEVEL: INTEGER;
RESULTS: ARRAY[0..#20] OF INTEGER; "RESULTS FROM TEST
ANTAL_RES: INTEGER; "NUMBER OF VALID ELEMENTS IN <RESULTS>
OUT_ENABLE: INTEGER; "1 ~ MAX OUTPUT
EXPECT_DATA: INTEGER;
ACTUAL_DATA: INTEGER;
ERROR_STATUS: INTEGER;
FAULT_ADDRESS: INTEGER;
CER_MC_VALUE: INTEGER;
KONTROL: INTEGER;
LOC_OUT_ENABLE: INTEGER;
LOC_LEVEL: INTEGER;
NEW_CER_VALUE: INTEGER;
OLD_CER_VALUE: INTEGER;
COUNT: INTEGER;
TEST: INTEGER;
CONST
TESTOUTPUT = 0;
%SOURCE TEST_CERS.S
%SOURCE INIT_DTT.S
%SOURCE ERROR_MESSAGE.S
%SOURCE CHECK_ERROR.S
%SOURCE TEST_1.S
%SOURCE UNDEF_TEST.S
%SOURCE KONTROL_LOAD.S
%SOURCE LEVEL_LOAD.S
%SOURCE TEST_2.S
%SOURCE TEST_5.S
%SOURCE TEST_8.S
%SOURCE TRACE_TRAP_TEST.S
%SOURCE TEST_6.S
%SOURCE TEST_3.S
%SOURCE TEST_7.S
%SOURCE TEST_4.S
%SOURCE PERF_1.S
%SOURCE PERF_2.S
%SOURCE PERF_3.S
%SOURCE PERF_4.S
%SOURCE COUNT_LOAD.S
%SOURCE TESTNUMBER.S
%SOURCE PERFNUMBER.S
%SOURCE INPUTERROR.S
%SOURCE TEST_ALL.S
BEGIN "MAIN PROGRAM"
CAD;
#0000=>R7;
#1=>R0=>DICA;
#F=>R0=>LEVEL;
1=>R0=>OUT_ENABLE;
#1234=>R0;
RCR;
R0 EXTRACT #F;
R0=>CER_MC_VALUE;
LDM(#7);
INIT_OC(R7,R6);
OUTNEWLINE(R6);
OUTTEXT(ADDRESS('JKZ CACHE MEMORY TEST PROGRAM(:0:)')=>R3,R6);
OUTNEWLINE(R6);
OUTTEXT(ADDRESS('CACHE ERROR REGISTER MASTER CLEAR VALUE: (:0:)')=>R3,R6);
CER_MC_VALUE=>R3;
OUTHEX(R3,R6);
OUTNEWLINE(R6);
FLUSHOUT(R6);
"START OF INPUT FROM CONSOLE"
WHILE R0=R0 DO
BEGIN "0"
OUTTEXT(ADDRESS('-->(:0:)')=>R3,R6);
FLUSHOUT(R6);
#0=>R0;
R0=>INPUT_POINTER;
WHILE R3<>#D DO
BEGIN
IN_BYTE(R3,R6);
R3=>R7;
R7=>INPUTSTRING[R0];
R7=>INPUT_LAST;
R0+1;
END;
0=>R0;
R0=>INPUT_POINTER;
"AT THIS POINT, THE ARRAY >INPUTSTRING< CONTAINS VALID CHARACTERS,
"THE LAST VALID CHARACTER DESIGNATED BY INPUT_LAST.
"INPUT_POINTER POINTS AT THE FIRST BYTE.
"START OF COMMAND INTERPRETER"
#0=>R4;
#43=>R1;
INPUTSTRING[R4]=>R2;
IF R2=R1 THEN
BEGIN
COUNT_LOAD(R6);
END
ELSE BEGIN "1"
#44=>R1;
#0=>R4;
INPUTSTRING[R4]=>R2;
IF R2=R1 THEN
BEGIN
#1=>R2;
R2=>DICA;
CAD;
OUTTEXT(ADDRESS('CACHE DISABLED(:0:)')=>R3,R6);
OUTNEWLINE(R6);
END
ELSE BEGIN "2"
#45=>R1;
#0=>R4;
INPUTSTRING[R4]=>R2;
IF R2=R1 THEN
BEGIN
#0=>R2;
R2=>DICA;
CAE;
OUTTEXT(ADDRESS('CACHE ENABLED(:0:)')=>R3,R6);
OUTNEWLINE(R6);
END
ELSE BEGIN "3"
#54=>R1;
#0=>R4;
INPUTSTRING[R4]=>R2;
IF R2=R1 THEN
BEGIN
TESTNUMBER(R6);
END
ELSE BEGIN "4"
#50=>R1;
#0=>R4;
INPUTSTRING[R4]=>R2;
IF R2=R1 THEN
BEGIN
PERFNUMBER(R6);
END
ELSE BEGIN
'K'=>R1;
IF R1=R2 THEN
BEGIN
KONTROL_LOAD(R6);
END
ELSE
BEGIN
'L'=>R1;
IF R1=R2 THEN
BEGIN
LEVEL_LOAD(R6);
END
ELSE
BEGIN
'A'=>R1;
IF R1=R2 THEN
BEGIN
TEST_ALL(R6);
END
ELSE
BEGIN
INPUTERROR(R6);
END;
END;
END;
END;
END; "4"
END; "3"
END; "2"
END; "1"
END; "0"
END; "MAINMODULE
ENDMODULE