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    Types: TextFile
    Names: »OBT.SRC«

└─⟦519079be6⟧ Bits:30005500 8" CR80 Floppy CR80FD_0029 ( WBOOTL.SYS W.D bootload program 81 10 01 ??? )
└─⟦519079be6⟧ Intel_ISIS_II
    └─ ⟦this⟧ »OBT.SRC« 

TextFile

	NAME	OBT\r
	TITLE	'ON BOARD TEST (OBT)'\r
;************************************************************************\r
;\r
;\r
;   * * * * * * * * *\r
;   * *     *     * *		CHRISTIAN ROVSING A/S\r
;   *   *   *   *   *\r
;   *     * * *     *		PROGRAMMER: IMJ\r
;   * * * * * * * * *\r
;   *     * * *     *		DATE: 810305\r
;   *   *   *   *   *\r
;   * *     *     * *\r
;   * * * * * * * * *\r
;\r
;\r
;-----------------------------------------------------------------------\r
;\r
;	MODULE:\r
;		ON BOARD TEST (OBT)\r
;\r
;-----------------------------------------------------------------------\r
;\r
;	FUNCTION: \r
;		THE MODULE CHECK SHADOW PROM, Z80 RAM AND\r
;		COMMUNICATION BETWEEN THE Z80-CPU AND THE\r
;		OTHER COMPLEX CIRTUITS ON THE LTU (CR8066D).\r
;		THE TEST IS EXECUTED AFTER POWER UP AND BY\r
;		ACTIVATING NMI INPUT.\r
;\r
;\r
;***********************************************************************\r
\r
\r
\r
	PUBLIC	OBT,ERROR,MDELAY\r
	EXTRN	TPROM,TRAM,TPIO1,TPIO2,TTIM1\r
	EXTRN	TTIM2,TTIM3,TSIO1,TSIO2,TDMA,TSIODMA\r
	EXTRN	WBOOTL\r
\r
\r
	CSEG\r
	DI\r
	IN	A,(APIO1+2)\r
	BIT	2,A		;IF POWER UP THEN\r
	JP	NZ,OBT		;  RUN TEST ROUTINE\r
				;ELSE\r
	JP	WBOOTL		;  BOOTLOAD WITHOUT H/W TEST\r
				;ENDIF\r
\r
\r
	ORG	66H\r
	JP	OBT		;ENTRY IF TEST ACTIVATED\r
\r
\r
	ORG	70H\r
OBT	DI\r
				;SET PIO 1 MODE\r
				;BEGIN\r
	LD	A,10000001B	;  PORT A: OUTPUT\r
				;  PORT B: OUTPUT\r
				;  PORT C (LOWER): INPUT\r
				;  PORT C (UPPUR): OUTPUT\r
	OUT	(APIO1+3),A	;END\r
\r
				;SET PIO 2 MODE\r
				;BEGIN\r
	LD	A,10001010B	;  PORT A: OUTPUT\r
				;  PORT B: INPUT\r
				;  PORT C (LOWER): OUTPUT\r
				;  PORT C (UPPER): INPUT\r
	OUT	(APIO2+3),A	;END\r
\r
				;RESET OUTPUT PORTS\r
	LD	A,0		;BEGIN\r
	OUT	(APIO2),A\r
	LD	A,0\r
	OUT	(APIO2+2),A\r
	LD	A,0FFH\r
	OUT	(APIO1),A	;  SET INTERNAL CLOCK MODE\r
	LD	A,90H\r
	OUT	(APIO1+1),A	;  TURN ON TEST LED\r
	LD	A,0DFH\r
	OUT	(APIO1+2),A	;  SET CLEAR\r
				;END\r
\r
	LD	SP,RAMEND+1\r
	LD	A,55H\r
	LD	B,00H\r
O1LOOP	DJNZ	O12NEXT\r
O1ERR	LD	A,0BH\r
	CALL	ERROR\r
O12NEXT	LD	HL,5555H	;FIND LAST RAM ADDRESS\r
	PUSH	HL		;BEGIN\r
	POP	HL\r
	PUSH	HL\r
	CP	H\r
	JR	NZ,O1LOOP\r
	CP	L\r
	JR	NZ,O1LOOP\r
				;END\r
	POP	HL\r
	LD	HL,0\r
	ADD	HL,SP\r
	DEC	HL\r
	LD	B,0EH		;TEST STACK AREA\r
O2LOOP	LD	A,55H		;FOR N = STACK TOP TO BOTTOM STEP - 1\r
	LD	(HL),A		;  WRITE DATA\r
	CP	(HL)		;  READ DATA\r
	JR	NZ,O1ERR	;  LOOP IF ERROR\r
	LD	A,0AAH\r
	LD	(HL),A\r
	CP	(HL)\r
	JR	NZ,O1ERR\r
	LD	A,0FFH\r
	LD	(HL),A\r
	CP	(HL)\r
	JR	NZ,O1ERR\r
	XOR	A\r
	LD	(HL),A\r
	CP	(HL)\r
	JR	NZ,O1ERR\r
	DEC	HL\r
	DJNZ	O2LOOP		;NEXT N\r
\r
	CALL	TPROM		;DO SHADOW PROM TEST\r
	CALL	TRAM		;DO RAM TEST\r
	CALL	TPIO1		;DO PIO1 TEST\r
	CALL	TPIO2		;DO PIO2 TEST\r
	IN	A,(APIO1+2)\r
	SET	5,A\r
	OUT	(APIO1+2),A	;RESET CLEAR\r
	CALL	TTIM1		;DO TIMER 1 (8253-1) TEST\r
	CALL	TTIM2		;DO TIMER 2 (8253-2) TEST\r
	CALL	TTIM3		;DO TIMER 3 (Z80-CTC) TEST\r
	CALL	TSIO1		;DO SIO 1 TEST\r
	CALL	TSIO2		;DO SIO 2 TEST\r
	CALL	TDMA		;DO DMA TEST\r
	CALL	TSIODMA		;DO DMA DATA TRANSFER TEST\r
	IN	A,(TESTPO)\r
	RES	TESTBI,A\r
	OUT	(TESTPO),A	;TURN OFF TEST LED\r
				;TEST COMPLETE\r
	JP	WBOOTL		;GO TO BOOT LOAD MODULE\r
\r
\r
\r
;-------PULSE TEST LED------------------------------------------ERROR-----\r
		;DESCRIP: THE TEST LED IS PULSED ACCORDING TO THE\r
		;	CONDENCE OF THE A REG.\r
		;RESTRICTIONS: DO FOREVER ROUTINE.\r
		;ENTRY: A - ERROR CODE\r
ERROR	LD	H,0\r
	LD	L,A\r
	LD	(SRAMB),HL	;SET ERROR MESSAGE TO CR80\r
	EI\r
	LD	H,A		;SAVE ERROR CODE\r
	LD	C,TESTPO\r
	IN	E,(C)\r
	RES	TESTBI,E\r
	OUT	(C),E		;TURN OFF TEST LED\r
	XOR	A		;DO FOREVER\r
E1LOOP	INC	A\r
	CP	1		;START WITH 2 SPACES\r
	JR	Z,OUTSP\r
	CP	2\r
	JR	Z,OUTSP\r
	CP	7\r
	JR	Z,OUTSP		;SPACE AFTER BIT 3\r
	LD	DE,500		;FOR BIT 0 TO 8\r
	CALL	MDELAY		;  DELAY 1 PERIOD\r
	IN	E,(C)\r
	SET	TESTBI,E\r
	OUT	(C),E		;  TURN ON TEST BIT\r
	LD	DE,500		;  IF BIT = 0 THEN\r
	RRC	L\r
	JR	C,OUT1\r
	LD	DE,1000		;    DELAY 2 PERIODS\r
	CALL	MDELAY\r
	JR	E1NEXT		;  ELSE\r
OUT1	LD	DE,333		;    DELAY .6 PERIOD\r
	CALL	MDELAY\r
E1NEXT	IN	E,(C)		;  ENDIF\r
	RES	TESTBI,E\r
	OUT	(C),E\r
	CP	11\r
	JP	NZ,E1LOOP	;NEXT BIT\r
	XOR	A\r
	JR	E1LOOP		;ENDDO\r
;\r
;\r
OUTSP	LD	DE,100		;DELAY 0.1 PERIOD\r
	CALL	MDELAY\r
	IN	E,(C)\r
	SET	TESTBI,E\r
	OUT	(C),E		;TURN ON TEST LED\r
	LD	DE,900\r
	CALL	MDELAY		;DELAY .9 PERIOD\r
	IN	E,(C)\r
	RES	TESTBI,E\r
	OUT	(C),E\r
	JP	E1LOOP		;RETURN TO ERROR LOOP\r
\r
\r
;-------DELAY MILLI SECOND(S)------------------------MDELAY------\r
		;DESCRIP: DELAY A SPECIFIED NUMBER OF\r
		;	MILLI SECOND.\r
		;RESTRICTIONS: RANGE 1 - FFFFH\r
		;		CPU CLOCK = 4 MHZ\r
		;ENTRY:	DE - NO. OF MILLISEC. TO DELAY\r
		;DESTROY: F,BC,DE\r
MDELAY	INC	D		;FOR N = REG. DE TO 0 STEP -1\r
M1LOOP	LD	B,0\r
M2LOOP	DJNZ	M2LOOP\r
	LD	B,50		;  DELAY 1 MILLI SECOND\r
M3LOOP	DJNZ	M3LOOP\r
	DEC	E\r
	JR	NZ,M1LOOP\r
	DEC	D\r
	JR	NZ,M1LOOP	;NEXT N\r
	RET\r
	END\r