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Length: 2548 (0x9f4) Types: TextFile Names: »TEST_6.S«
└─⟦18a2fd90d⟧ Bits:30005144 8" CR80 Floppy CR80FD_0132 ( CR/D/2479 CRD2479: En-CPU CPU/CACHE TEST- PROGRAMMER node: master: CRP5 ) └─⟦56889de57⟧ └─ ⟦this⟧ »TEST_6.S«
PROCEDURE TEST_6 (R6); "********************************************************************* " A tracetrap is generated #100 times. " After each tracetrap, cause-codes 1,2 and 3 are checked. " An error message is produced in case of errors. " " Following this, the level is raised, which should disable the " trace-trap-mechanism. "********************************************************************* VAR SAVE: ARRAY[0..7] OF INTEGER; BEGIN R7=>SAVE[7]; STC(6,ADDRESS(SAVE[7])=>R7); 0=>R0=>LOC_OUT_ENABLE; #100=>R0=>LOC_COUNT; WHILE R0<>0 DO BEGIN 0=>R0=>LOC_LEVEL; TRACE_TRAP_TEST(R6); RESULTS[3]=>R0; IF R0=1 THEN BEGIN OUTTEXT(ADDRESS('ERROR: EXPECTED INTERRUPT DID NOT ARRIVE (:0:)')=>R3,R6); OUTNEWLINE(R6); FLUSHOUT(R6); END ELSE BEGIN "COMPARE PRPC, CC2 AND EXPECTED-CC2. THESE MUST BE IDENTICAL. RESULTS[#10]=>R0; "PRPC FROMCONTEXT-RECORD RESULTS[0]=>R1; "CC2 RESULTS[#15]=>R2; "EXPECTED CC2. IF R0<>R1 THEN BEGIN OUTTEXT(ADDRESS('PRPC = (:0:)')=>R3,R6); R0=>R3; OUTHEX(R3,R6); OUTTEXT(ADDRESS(' CC2 = (:0:)')=>R3,R6); R1=>R3; OUTHEX(R3,R6); OUTTEXT(ADDRESS(' EXPECTED CC2 = (:0:)')=>R3,R6); R2=>R3; OUTHEX(R3,R6); OUTNEWLINE(R6); FLUSHOUT(R6); END; IF R0<>R2 THEN BEGIN OUTTEXT(ADDRESS('PRPC = (:0:)')=>R3,R6); R0=>R3; OUTHEX(R3,R6); OUTTEXT(ADDRESS(' CC2 = (:0:)')=>R3,R6); R1=>R3; OUTHEX(R3,R6); OUTTEXT(ADDRESS(' EXPECTED CC2 = (:0:)')=>R3,R6); R2=>R3; OUTHEX(R3,R6); OUTNEWLINE(R6); FLUSHOUT(R6); END; END; LOC_COUNT=>R0-1=>LOC_COUNT; END; 0=>R0=>LOC_OUT_ENABLE; #100=>R0=>LOC_COUNT; WHILE R0<>0 DO BEGIN #F=>R0=>LOC_LEVEL; TRACE_TRAP_TEST(R6); RESULTS[3]=>R0; IF R0=0 THEN BEGIN OUTTEXT(ADDRESS('ERROR: UNEXPECTED TRACETRAP (:0:)')=>R3,R6); OUTNEWLINE(R6); FLUSHOUT(R6); END; LOC_COUNT=>R0-1=>LOC_COUNT; END; UNS(7,ADDRESS(SAVE[0])=>R7); EXIT(R6); END; "END OF TEST6 "