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Length: 15497 (0x3c89)
Types: TextFile
Names: »OBT.LST«
└─⟦519079be6⟧ Bits:30005500 8" CR80 Floppy CR80FD_0029 ( WBOOTL.SYS W.D bootload program 81 10 01 ??? )
└─⟦519079be6⟧ Intel_ISIS_II
└─ ⟦this⟧ »OBT.LST«
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Z80 ASSEMBLER VER.3.3 1\r
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1 PAGESZ 48\r
18 LIST S\r
19 NAME OBT\r
20 ;************************************************************************\r
21 ;\r
22 ;\r
23 ; * * * * * * * * *\r
24 ; * * * * * CHRISTIAN ROVSING A/S\r
25 ; * * * * *\r
26 ; * * * * * PROGRAMMER: IMJ\r
27 ; * * * * * * * * *\r
28 ; * * * * * DATE: 810305\r
29 ; * * * * *\r
30 ; * * * * *\r
31 ; * * * * * * * * *\r
32 ;\r
33 ;\r
34 ;-----------------------------------------------------------------------\r
35 ;\r
36 ; MODULE:\r
37 ; ON BOARD TEST (OBT)\r
38 ;\r
39 ;-----------------------------------------------------------------------\r
40 ;\r
41 ; FUNCTION: \r
42 ; THE MODULE CHECK SHADOW PROM, Z80 RAM AND\r
43 ; COMMUNICATION BETWEEN THE Z80-CPU AND THE\r
44 ; OTHER COMPLEX CIRTUITS ON THE LTU (CR8066D).\r
45 ; THE TEST IS EXECUTED AFTER POWER UP AND BY\r
46 ; ACTIVATING NMI INPUT.\r
47 ;\r
48 ;\r
49 ;***********************************************************************\r
50 ;\r
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Z80 ASSEMBLER VER.3.3 2\r
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51 0000 EJEC\r
52 PUBLIC OBT,ERROR,MDELAY\r
53 EXTRN TPROM,TRAM,TPIO1,TPIO2,TTIM1\r
54 EXTRN TTIM2,TTIM3,TSIO1,TSIO2,TDMA,TSIODMA\r
55 EXTRN WBOOTL\r
56 ;\r
57 ;\r
58 CSEG\r
59 0000 F3 DI\r
60 0001 DB 72 IN A,(APIO1+2)\r
61 0003 CB 57 BIT 2,A ;IF POWER UP THEN\r
62 0005 C2 70 00 C JP NZ,OBT ; RUN TEST ROUTINE\r
63 ;ELSE\r
64 0008 C3 00 00 E JP WBOOTL ; BOOTLOAD WITHOUT H/W TEST\r
65 ;ENDIF\r
66 ;\r
67 ;\r
68 0066 ORG 66H\r
69 0066 C3 70 00 C JP OBT ;ENTRY IF TEST ACTIVATED\r
70 ;\r
71 ;\r
72 0070 ORG 70H\r
73 0070 F3 OBT DI\r
74 ;SET PIO 1 MODE\r
75 ;BEGIN\r
76 0071 3E 81 LD A,10000001B ; PORT A: OUTPUT\r
77 ; PORT B: OUTPUT\r
78 ; PORT C (LOWER): INPUT\r
79 ; PORT C (UPPUR): OUTPUT\r
80 0073 D3 73 OUT (APIO1+3),A ;END\r
81 0075 \r
82 ;SET PIO 2 MODE\r
83 ;BEGIN\r
84 0075 3E 8A LD A,10001010B ; PORT A: OUTPUT\r
85 ; PORT B: INPUT\r
86 ; PORT C (LOWER): OUTPUT\r
87 ; PORT C (UPPER): INPUT\r
88 0077 D3 23 OUT (APIO2+3),A ;END\r
89 0079 \r
90 ;RESET OUTPUT PORTS\r
91 0079 3E 00 LD A,0 ;BEGIN\r
92 007B D3 20 OUT (APIO2),A\r
93 007D 3E 00 LD A,0\r
94 007F D3 22 OUT (APIO2+2),A\r
95 0081 3E FF LD A,0FFH\r
96 0083 D3 70 OUT (APIO1),A ; SET INTERNAL CLOCK MODE\r
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Z80 ASSEMBLER VER.3.3 3\r
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97 0085 3E 90 LD A,90H\r
98 0087 D3 71 OUT (APIO1+1),A ; TURN ON TEST LED\r
99 0089 3E DF LD A,0DFH\r
100 008B D3 72 OUT (APIO1+2),A ; SET CLEAR\r
101 ;END\r
102 008D \r
103 008D 31 00 40 LD SP,RAMEND+1\r
104 0090 3E 55 LD A,55H\r
105 0092 06 00 LD B,00H\r
106 0094 10 05 009B O1LOOP DJNZ O12NEXT\r
107 0096 3E 0B O1ERR LD A,0BH\r
108 0098 CD F9 00 C CALL ERROR\r
109 009B 21 55 55 O12NEXT LD HL,5555H ;FIND LAST RAM ADDRESS\r
110 009E E5 PUSH HL ;BEGIN\r
111 009F E1 POP HL\r
112 00A0 E5 PUSH HL\r
113 00A1 BC CP H\r
114 00A2 20 F0 0094 JR NZ,O1LOOP\r
115 00A4 BD CP L\r
116 00A5 20 ED 0094 JR NZ,O1LOOP\r
117 ;END\r
118 00A7 E1 POP HL\r
119 00A8 21 00 00 LD HL,0\r
120 00AB 39 ADD HL,SP\r
121 00AC 2B DEC HL\r
122 00AD 06 0E LD B,0EH ;TEST STACK AREA\r
123 00AF 3E 55 O2LOOP LD A,55H ;FOR N = STACK TOP TO BOTTOM STEP - 1\r
124 00B1 77 LD (HL),A ; WRITE DATA\r
125 00B2 BE CP (HL) ; READ DATA\r
126 00B3 20 E1 0096 JR NZ,O1ERR ; LOOP IF ERROR\r
127 00B5 3E AA LD A,0AAH\r
128 00B7 77 LD (HL),A\r
129 00B8 BE CP (HL)\r
130 00B9 20 DB 0096 JR NZ,O1ERR\r
131 00BB 3E FF LD A,0FFH\r
132 00BD 77 LD (HL),A\r
133 00BE BE CP (HL)\r
134 00BF 20 D5 0096 JR NZ,O1ERR\r
135 00C1 AF XOR A\r
136 00C2 77 LD (HL),A\r
137 00C3 BE CP (HL)\r
138 00C4 20 D0 0096 JR NZ,O1ERR\r
139 00C6 2B DEC HL\r
140 00C7 10 E6 00AF DJNZ O2LOOP ;NEXT N\r
141 00C9 \r
142 00C9 CD 00 00 E CALL TPROM ;DO SHADOW PROM TEST\r
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Z80 ASSEMBLER VER.3.3 4\r
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143 00CC CD 00 00 E CALL TRAM ;DO RAM TEST\r
144 00CF CD 00 00 E CALL TPIO1 ;DO PIO1 TEST\r
145 00D2 CD 00 00 E CALL TPIO2 ;DO PIO2 TEST\r
146 00D5 DB 72 IN A,(APIO1+2)\r
147 00D7 CB EF SET 5,A\r
148 00D9 D3 72 OUT (APIO1+2),A ;RESET CLEAR\r
149 00DB CD 00 00 E CALL TTIM1 ;DO TIMER 1 (8253-1) TEST\r
150 00DE CD 00 00 E CALL TTIM2 ;DO TIMER 2 (8253-2) TEST\r
151 00E1 CD 00 00 E CALL TTIM3 ;DO TIMER 3 (Z80-CTC) TEST\r
152 00E4 CD 00 00 E CALL TSIO1 ;DO SIO 1 TEST\r
153 00E7 CD 00 00 E CALL TSIO2 ;DO SIO 2 TEST\r
154 00EA CD 00 00 E CALL TDMA ;DO DMA TEST\r
155 00ED CD 00 00 E CALL TSIODMA ;DO DMA DATA TRANSFER TEST\r
156 00F0 DB 71 IN A,(TESTPO)\r
157 00F2 CB A7 RES TESTBI,A\r
158 00F4 D3 71 OUT (TESTPO),A ;TURN OFF TEST LED\r
159 ;TEST COMPLETE\r
160 00F6 C3 00 00 E JP WBOOTL ;GO TO BOOT LOAD MODULE\r
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Z80 ASSEMBLER VER.3.3 5\r
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161 00F9 EJEC\r
162 ;-------PULSE TEST LED------------------------------------------ERROR-----\r
163 ;DESCRIP: THE TEST LED IS PULSED ACCORDING TO THE\r
164 ; CONDENCE OF THE A REG.\r
165 ;RESTRICTIONS: DO FOREVER ROUTINE.\r
166 ;ENTRY: A - ERROR CODE\r
167 00F9 26 00 ERROR LD H,0\r
168 00FB 6F LD L,A\r
169 00FC 22 00 40 LD (SRAMB),HL ;SET ERROR MESSAGE TO CR80\r
170 00FF FB EI\r
171 0100 67 LD H,A ;SAVE ERROR CODE\r
172 0101 0E 71 LD C,TESTPO\r
173 0103 ED 58 IN E,(C)\r
174 0105 CB A3 RES TESTBI,E\r
175 0107 ED 59 OUT (C),E ;TURN OFF TEST LED\r
176 0109 AF XOR A ;DO FOREVER\r
177 010A 3C E1LOOP INC A\r
178 010B FE 01 CP 1 ;START WITH 2 SPACES\r
179 010D 28 37 0146 JR Z,OUTSP\r
180 010F FE 02 CP 2\r
181 0111 28 33 0146 JR Z,OUTSP\r
182 0113 FE 07 CP 7\r
183 0115 28 2F 0146 JR Z,OUTSP ;SPACE AFTER BIT 3\r
184 0117 11 F4 01 LD DE,500 ;FOR BIT 0 TO 8\r
185 011A CD 61 01 C CALL MDELAY ; DELAY 1 PERIOD\r
186 011D ED 58 IN E,(C)\r
187 011F CB E3 SET TESTBI,E\r
188 0121 ED 59 OUT (C),E ; TURN ON TEST BIT\r
189 0123 11 F4 01 LD DE,500 ; IF BIT = 0 THEN\r
190 0126 CB 0D RRC L\r
191 0128 38 08 0132 JR C,OUT1\r
192 012A 11 E8 03 LD DE,1000 ; DELAY 2 PERIODS\r
193 012D CD 61 01 C CALL MDELAY\r
194 0130 18 06 0138 JR E1NEXT ; ELSE\r
195 0132 11 4D 01 OUT1 LD DE,333 ; DELAY .6 PERIOD\r
196 0135 CD 61 01 C CALL MDELAY\r
197 0138 ED 58 E1NEXT IN E,(C) ; ENDIF\r
198 013A CB A3 RES TESTBI,E\r
199 013C ED 59 OUT (C),E\r
200 013E FE 0B CP 11\r
201 0140 C2 0A 01 C JP NZ,E1LOOP ;NEXT BIT\r
202 0143 AF XOR A\r
203 0144 18 C4 010A JR E1LOOP ;ENDDO\r
204 ;\r
205 ;\r
206 0146 11 64 00 OUTSP LD DE,100 ;DELAY 0.1 PERIOD\r
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Z80 ASSEMBLER VER.3.3 6\r
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207 0149 CD 61 01 C CALL MDELAY\r
208 014C ED 58 IN E,(C)\r
209 014E CB E3 SET TESTBI,E\r
210 0150 ED 59 OUT (C),E ;TURN ON TEST LED\r
211 0152 11 84 03 LD DE,900\r
212 0155 CD 61 01 C CALL MDELAY ;DELAY .9 PERIOD\r
213 0158 ED 58 IN E,(C)\r
214 015A CB A3 RES TESTBI,E\r
215 015C ED 59 OUT (C),E\r
216 015E C3 0A 01 C JP E1LOOP ;RETURN TO ERROR LOOP\r
217 0161 \r
218 0161 \r
219 ;-------DELAY MILLI SECOND(S)------------------------MDELAY------\r
220 ;DESCRIP: DELAY A SPECIFIED NUMBER OF\r
221 ; MILLI SECOND.\r
222 ;RESTRICTIONS: RANGE 1 - FFFFH\r
223 ; CPU CLOCK = 4 MHZ\r
224 ;ENTRY: DE - NO. OF MILLISEC. TO DELAY\r
225 ;DESTROY: F,BC,DE\r
226 0161 14 MDELAY INC D ;FOR N = REG. DE TO 0 STEP -1\r
227 0162 06 00 M1LOOP LD B,0\r
228 0164 10 FE 0164 M2LOOP DJNZ M2LOOP\r
229 0166 06 32 LD B,50 ; DELAY 1 MILLI SECOND\r
230 0168 10 FE 0168 M3LOOP DJNZ M3LOOP\r
231 016A 1D DEC E\r
232 016B 20 F5 0162 JR NZ,M1LOOP\r
233 016D 15 DEC D\r
234 016E 20 F2 0162 JR NZ,M1LOOP ;NEXT N\r
235 0170 C9 RET\r
236 0171 END\r
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ERRORS = 0000\r
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ADMA 0000 APIO1 0070 APIO2 0020 ASIO1 0040 \r
ASIO2 0050 ATIM1 0010 ATIM2 0030 ATIM3 0060 \r
E1LOOP C 010A E1NEXT C 0138 ERROR C 00F9 M1LOOP C 0162 \r
M2LOOP C 0164 M3LOOP C 0168 MDELAY C 0161 MEMORY M 0000 \r
O12NEX C 009B O1ERR C 0096 O1LOOP C 0094 O2LOOP C 00AF \r
OBT C 0070 OUT1 C 0132 OUTSP C 0146 PROMEN 07FF \r
RAMEND 3FFF RAMSTA 2000 SRAMB 4000 SRAME 7FFF \r
STACK S 0000 TDMA E 0009 TESTBI 0004 TESTPO 0071 \r
TPIO1 E 0002 TPIO2 E 0003 TPROM E 0000 TRAM E 0001 \r
TSIO1 E 0007 TSIO2 E 0008 TSIODM E 000A TTIM1 E 0004 \r
TTIM2 E 0005 TTIM3 E 0006 WBOOTL E 000B \r