|
DataMuseum.dkPresents historical artifacts from the history of: CR80 Hard and Floppy Disks |
This is an automatic "excavation" of a thematic subset of
See our Wiki for more about CR80 Hard and Floppy Disks Excavated with: AutoArchaeologist - Free & Open Source Software. |
top - download
Length: 3498 (0xdaa)
Types: TextFile
Names: »WBOOTL.OLD«
└─⟦519079be6⟧ Bits:30005500 8" CR80 Floppy CR80FD_0029 ( WBOOTL.SYS W.D bootload program 81 10 01 ??? )
└─⟦519079be6⟧ Intel_ISIS_II
└─ ⟦this⟧ »WBOOTL.OLD«
PAGESZ 40\r ;*********************************************************************\r \r LIST S\r NAME WBOOTL\r TITLE 'WATCHDOG BOOTLOAD PROGRAM'\r ; FILE WBOOTL.SRC\r ; DATE 81 10 07 11 00 LPO\r ; DISK WBOOTL.SYS\r ; NOTES PROM CHECKSUM=42H ADDR 7FFH\r ; WD FIRMWARE CHECKSUM= 5DH PT\r \r ;FUNCTION:\r ; THIS MODULE IS LOCATED INTO THE SHADOW PROM ON THE WD-LTU\r ; EXECUTE BOOT LOADING OF THE WD-LTU, IE LOAD PRGM FROM PROM\r ; SITUATED ON WCA INTO SHARED RAM ON WD-LTU (CR8066D), THEN\r ; AFTER CHECKSUM CTRL, THE WD FIRMWARE IS MOVED TO PROGRAM\r ; MEMORY\r \r ;*********************************************************************\r PUBLIC WBOOTL\r LIST B,I,O,S,T,R,D\r \r PROMS EQU 0 ; PROM START ADDRESS\r PROME EQU 3FFFH ; PROM END ADDRESS\r RAMEND EQU 3FFFH ; Z80 RAM END\r SRAMB EQU 4000H ; FIRST SHARED RAM ADDRESS\r SRAME EQU 7FFFH ; LAST SHARED RAM ADDRESS\r BYTCOU EQU SRAMB+2 ; (MAX) BYTE COUNT\r STADR EQU SRAMB+4 ; FIRST DATA ADDRESS\r ARYADR EQU SRAMB+6 ; PROGRAM START ADDRESS\r CHECKS EQU 5DH ; WD FIRMWARE CHECKSUM\r \r CSEG ;PAGE\r WBOOTL LD SP,RAMEND+1 ; ADJUST SP\r DI\r LD B,200/13*4\r DJNZ $+0 ; DELAY 200 USEC\r \r WBL1 LD HL,SRAME-ARYADR-1\r LD (BYTCOU),HL ; LOAD MAX BYTE COUNT\r LD HL,ARYADR\r LD (STADR),HL ; LOAD BUFFER START ADDRESS\r \r LD BC,(BYTCOU) ; GET BYTE COUNT\r DEC BC ; STRIP CHECKSUM\r DEC BC\r LD HL,ARYADR\r XOR A ; INIT CHECKSUM\r INC B\r INC C\r LD DE,PROMS ; LOAD PROM START ADDRESS\r DEC DE\r WBL2 INC DE ; INCREMENT PROM ADDRESS POINTER\r PUSH AF\r PUSH BC\r \r WB1 CALL RCD ; RESET COMMAND DECODER\r LD C,22H ; LATCH ROM UPPER ADDRESS BYTE\r LD A,0F4H ; VIA PORT C (OPC0 TO OPC3)\r OUT (C),A ; (COMMAND 4)\r LD C,20H ; SEND UPPER ADDR BYTE VIA PORT A\r OUT (C),D\r LD C,22H ; LATCH ROM UPPER ADDR BYTE\r LD A,0FCH ; PLUS STROBE, (COMMAND 0CH)\r OUT (C),A\r \r CALL RCD\r LD C,22H ; READ ROM (OUTPUT ENABLE)\r LD A,0F3H ; (COMMAND 3)\r OUT (C),A\r LD C,20H ; SEND LOWER ADDR BYTE VIA PORT A\r OUT (C),E\r LD C,22H ; READ ROM PLUS STROBE\r LD A,0FBH ; (COMMAND 0BH)\r OUT (C),A\r LD C,21H ; RECEIVE DATA FROM SELECTED\r ; ROM ADDR VIA PORT B\r INI ; LOAD DATA INTO SHARED RAM\r \r POP BC\r POP AF\r ADD A,(HL) ; ADD DATA TO CHECKSUM\r EX AF,AF' ; SAVE CHECKSUM WHEN PROM DATA\r ; POINTER IS EXAMINED\r LD A,0FFH ; PROM END LOWER ADDR PART\r CP E\r JR NZ,WBL2 ; NEXT DATA\r LD A,3FH ; PROM END UPPER ADDR PART\r CP D\r JR NZ,WBL2\r ; DEC C\r ; JP NZ,WBL2 ; NEXT DATA\r ; DEC B\r ; JP NZ,WBL2\r EX AF,AF'\r CP CHECKS ; IF CHECKSUM ERROR THEN\r JR Z,WBL3\r ;# LD HL,SRAME-ARYADR-1\r ; LD (BYTCOU),HL ; LOAD MAX BYTE COUNT\r ; LD HL,ARYADR\r ; LD (STADR),HL ; LOAD BUFFER START ADDRESS\r ; JP WBL2 ; TRY AGAIN\r \r ; PRGM DATA ARE ACCEPTED AND\r ; NOW LOADED FROM SHARED RAM\r ; TO PROGRAM MEMORY\r WBL3 LD BC,(BYTCOU) ; GET BYTE COUNT\r DEC BC\r DEC BC\r LD HL,ARYADR+2 ; GET FIRST DATA ADDRESS\r LD DE,(ARYADR)\r LD (STADR),HL ; LOAD BUFFER START ADDRESS\r LDIR ; MOVE ALL DATA TO PROGRAM MEMORY\r \r CALL RCD\r LD C,22H ; LOAD COMMAND REGISTER (COMMAND 7)\r LD A,0F7H\r OUT (C),A\r LD C,20H\r LD A,0F0H ; RESET ONESHOT IN WCA\r OUT (C),A\r LD C,22H\r LD A,0FFH ; LOAD COMMAND REGISTER PLUS STROBE\r OUT (C),A\r \r CALL RCD\r LD C,22H\r LD A,0F7H\r OUT (C),A\r LD C,20H\r LD A,0F1H ; GIVE EXTERNAL MASTER CLEAR (EMC)\r OUT (C),A\r LD C,22H\r LD A,0FFH\r OUT (C),A\r HALT\r \r \r \r ;# RESET COMMAND DECODER\r RCD LD C,22H ; LOAD POINTER TO PORT C\r LD A,0F0H ; SET LOWER NIBLE LOW\r OUT (C),A\r LD A,0F8H ; SET BIT 3\r OUT (C),A\r RET\r END\r