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Length: 3083 (0xc0b)
Types: TextFile
Names: »TDMA.SRC«
└─⟦519079be6⟧ Bits:30005500 8" CR80 Floppy CR80FD_0029 ( WBOOTL.SYS W.D bootload program 81 10 01 ??? )
└─⟦519079be6⟧ Intel_ISIS_II
└─ ⟦this⟧ »TDMA.SRC«
NAME TDMA\r PUBLIC TDMA\r EXTRN ERROR\r CSEG\r ;******************************************************************************\r TITLE 'DMA TEST ROUTINE'\r ;******************************************************************************\r \r TDMA: IN A,(APIO1+2)\r SET 6,A ;DISABLE DMA - SIO2 TRANSFER\r OUT (APIO1+2),A\r LD C,ADMA\r LD HL,SRAMB+100H\r CALL T1DMA ;DO DMA TEST\r AND A ;IF NO ERROR THEN\r RET Z ; RETURN\r ;ELSE\r ADD A,80H ; LOAD ERROR CODE\r CALL ERROR ; GO TO ERROR ROUTINE\r ;ENDIF\r \r \r \r ;-------AMD 9517 (DMA) TEST ROUTINE ---------------------T1DMA--------\r ;\r ;DESCRIP: THE ROUTINE TEST THE AMD 9517\r ; MULTIMODE DMA CONTROLLER FOR I/O ERROR\r ; AND MEMORY TO MEMORY DATA TRANSFER.\r ;\r ;ENTRY: C - DMA BASE ADDRESS\r ; HL - MEMORY AREA START ADDRESS\r ;\r ;EXIT: A = 0 TEST COMPLETED WITHOUT ERROR\r ; A = 1 I/O ERROR\r ; A = 2 MEMORY TO MEMORY TRANSFER ERROR\r ;\r ;DESTROY: F,BC,DE,HL,IX\r ;\r ;TIME: !T-CYCLES\r ;\r ;DATE: 810301\r ;\r ;PROGRAMMER: IMJ\r ;\r T1DMA: PUSH BC ;DMAADR\r PUSH HL ;MEADR\r LD IX,0\r ADD IX,SP\r LD A,0DH\r ADD A,(IX+2)\r LD C,A\r OUT (C),A ;RESET DMA\r LD B,10H\r DJNZ $+0 ;DELAY FOR DMA RESET\r ;\r LD A,8\r D1LOOP: SRL A ;FOR CHANNEL 3 TO 0\r LD (IX+3),A\r ADD A,(IX+2)\r LD C,A\r LD E,1\r LD B,8\r D11LOOP: LD A,E ; FOR BIT 0 TO 7\r OUT (C),A ; RUNNING 1 AT LOW ADDRESS\r CPL\r OUT (C),A ; RUNNING 0 AT HIGHT ADDRESS\r IN L,(C)\r IN H,(C)\r XOR H\r JP NZ,D1ERROR ; QUIT IF I/O ERROR\r LD A,E\r XOR L\r JP NZ,D1ERROR ; QUIT IF I/O ERROR\r RLC E\r DJNZ D11LOOP ; NEXT BIT\r LD A,(IX+3)\r AND A\r JP NZ,D1LOOP ;NEXT CHANNEL\r ;\r POP HL ;MEADR\r PUSH HL ;MEADR\r LD DE,10H ;SET NO OF BYTE TO TRANSFER\r OUT (C),L\r OUT (C),H ;SET TRANSFER READ ADDRESS\r INC C\r OUT (C),E\r OUT (C),D\r INC C\r XOR A\r LD B,E\r D2LOOP: LD (HL),A ; RESET MEMORY FOR DMA TRANSFER\r INC HL\r INC A\r DJNZ D2LOOP\r LD A,0FFH\r LD B,E\r D3LOOP: LD (HL),A\r INC HL\r DJNZ D3LOOP\r ;\r DEC HL\r OUT (C),L ;SET WRITE TRANSFER ADDRESS\r OUT (C),H\r INC C\r OUT (C),E\r OUT (C),D\r LD D,(IX+2) ;LOAD DMA ADDRESS\r LD A,0BH\r ADD A,D\r LD C,A\r LD A,10001000B ;SET CHA 0 MODE: READ TRANSFER\r ; AUTO INCREMENT\r OUT (C),A\r LD A,10100101B ;SET CHA 1 MODE: WRITE TRANSFER\r ; AUTO DECREMENT\r OUT (C),A\r LD A,8\r ADD A,D\r LD C,A\r LD A,00011001B ;SET COMMAND: MEMORY-TO-MEMORY\r ; CONTROLLER ENABLED\r ; COMPRESSED TIMING\r ; ROTARY PRIORITY\r OUT (C),A\r LD A,0FH\r ADD A,D\r LD C,A\r LD A,0CH\r OUT (C),A\r LD A,9\r ADD A,D\r LD C,A\r LD A,4\r OUT (C),A ;ACTIVATE TRANSFER\r POP HL ;MEADR\r PUSH HL ;MEADR\r LD DE,1FH\r ADD HL,DE\r LD A,0\r LD B,0FH\r D4LOOP: CP (HL) ;TEST THE TRANSFERED DATA\r JP NZ,D2ERROR ;QUIT IF DATA ERROR\r INC A\r DEC HL\r DJNZ D4LOOP\r LD A,0FH\r CP (HL)\r JP NZ,D2ERROR ;GO IF LAST READ TRANSFER BYTE CHANGED\r XOR A ;SET TEST COMPLETED WITHOUT ERROR\r JR DEXIT\r D1ERROR: LD A,1 ;SET I/O ERROR\r JR DEXIT\r D2ERROR: LD A,2 ;SET DATA TRANSFER ERROR\r JR DEXIT\r DEXIT: POP HL ;ADJUST STACK POINTER\r POP HL\r RET\r END\r