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Length: 3282 (0xcd2)
Types: TextFile
Names: »WBOOT2.SRC«
└─⟦519079be6⟧ Bits:30005500 8" CR80 Floppy CR80FD_0029 ( WBOOTL.SYS W.D bootload program 81 10 01 ??? )
└─⟦519079be6⟧ Intel_ISIS_II
└─ ⟦this⟧ »WBOOT2.SRC«
PAGESZ 40\r ;*********************************************************************\r \r LIST S\r NAME WBOOTL\r TITLE 'WATCHDOG BOOTLOAD PROGRAM'\r ; FILE WBOOT2.SRC\r ; DATE 81 10 27 10 00 LPO\r ; DISK WBOOTL.SYS\r ; NOTES PROM CHECKSUM=42H ADDR 7FFH\r ; WD FIRMWARE CHECKSUM= 5DH PT\r \r ;FUNCTION:\r ; THIS MODULE IS LOCATED INTO THE SHADOW PROM ON THE WD-LTU\r ; EXECUTE BOOT LOADING OF THE WD-LTU, IE LOAD PRGM FROM PROM\r ; SITUATED ON WCA INTO SHARED RAM ON WD-LTU (CR8066D), THEN\r ; AFTER CHECKSUM CTRL, THE WD FIRMWARE IS MOVED TO PROGRAM\r ; MEMORY\r \r ;*********************************************************************\r \r \r \r PUBLIC WBOOTL\r LIST B,I,O,S,T,R,D\r \r PROMS EQU 0 ; PROM START ADDRESS\r PROME EQU 3FFFH ; PROM END ADDRESS\r RAMEND EQU 3FFFH ; Z80 RAM END\r SRAMB EQU 4000H ; FIRST SHARED RAM ADDRESS\r SRAME EQU 7FFFH ; LAST SHARED RAM ADDRESS\r PIO1 EQU 0070H\r PIO2 EQU 0020H\r \r \r \r CSEG ;PAGE\r WBOOTL LD SP,RAMEND+1 ; ADJUST SP\r DI\r \r LD C,PIO1+3 ; SELECT PIO1 FOR INITIALIZE\r LD A,81H\r OUT (C),A\r \r LD A,8AH ; SELECT PIO2 FOR INITIALIZE\r OUT (PIO2+3),A\r \r XOR A ; RESET OUTPUT PORTS\r OUT (PIO2),A\r XOR A\r OUT (PIO2+2),A\r \r LD B,20\r DJNZ $+0 ; DELAY CA 1 MSEC\r \r WBL1 LD HL,SRAMB\r XOR A ; INIT CHECKSUM\r LD C,A\r LD DE,PROMS ; LOAD PROM START ADDRESS\r DEC DE\r WBL2 INC DE ; INCREMENT PROM ADDRESS POINTER\r PUSH BC\r \r CALL RCD ; RESET COMMAND DECODER\r LD C,22H ; LATCH ROM UPPER ADDRESS BYTE\r LD A,0F4H ; VIA PORT C (OPC0 TO OPC3)\r OUT (C),A ; (COMMAND 4)\r LD C,20H ; SEND UPPER ADDR BYTE VIA PORT A\r OUT (C),D\r NOP\r NOP\r NOP\r NOP\r LD C,22H ; LATCH ROM UPPER ADDR BYTE\r LD A,0FCH ; PLUS STROBE, (COMMAND 0CH)\r OUT (C),A\r \r CALL RCD\r LD C,22H ; READ ROM (OUTPUT ENABLE)\r LD A,0F3H ; (COMMAND 3)\r OUT (C),A\r LD C,20H ; SEND LOWER ADDR BYTE VIA PORT A\r OUT (C),E\r NOP\r NOP\r NOP\r NOP\r LD C,22H ; READ ROM PLUS STROBE\r LD A,0FBH ; (COMMAND 0BH)\r OUT (C),A\r LD C,21H ; RECEIVE DATA FROM SELECTED\r ; ROM ADDR VIA PORT B\r ;# INI ; LOAD DATA INTO SHARED RAM\r \r CALL RCD\r NOP\r NOP\r IN A,(C) ;# SUBSTITUTE INI\r LD (HL),A ;#\r INC HL ;#\r \r POP BC\r LD A,C ; CHECKSUM COUNTER\r DEC HL\r ADD A,(HL) ; ADD DATA TO CHECKSUM\r INC HL\r LD C,A ; SAVE CHECKSUM WHEN PROM DATA\r ; POINTER IS EXAMINED\r \r LD A,0FFH ; PROM END LOWER ADDR PART\r CP E\r JR NZ,WBL2 ; NEXT DATA\r LD A,3FH ; PROM END UPPER ADDR PART\r CP D\r JR NZ,WBL2\r \r LD A,C\r DEC HL\r CP (HL) ; IF CHECKSUM ERROR THEN\r ;# JP NZ,WBL1 ; TRY AGAIN\r CALL RCD ;#\r NOP\r NOP\r \r ; PRGM DATA ARE ACCEPTED AND\r ; NOW LOADED FROM SHARED RAM\r ; TO PROGRAM MEMORY\r WBL3 LD BC,SRAME-SRAMB\r LD HL,SRAMB ; GET FIRST DATA ADDRESS\r LD DE,0\r LDIR ; MOVE ALL DATA TO PROGRAM MEMORY\r \r CALL RCD\r LD C,22H ; LOAD COMMAND REGISTER (COMMAND 7)\r LD A,0F7H\r OUT (C),A\r LD C,20H\r LD A,0F0H ; RESET ONESHOT IN WCA\r OUT (C),A\r LD C,22H\r LD A,0FFH ; LOAD COMMAND REGISTER PLUS STROBE\r OUT (C),A\r \r CALL RCD\r LD C,22H\r LD A,0F7H\r OUT (C),A\r LD C,20H\r LD A,0F1H ; GIVE EXTERNAL MASTER CLEAR (EMC)\r OUT (C),A\r LD C,22H\r LD A,0FFH\r OUT (C),A\r HALT\r \r \r \r ;# RESET COMMAND DECODER\r RCD LD C,22H ; LOAD POINTER TO PORT C\r LD A,0F0H ; SET LOWER NIBLE LOW\r OUT (C),A\r LD A,0F8H ; SET BIT 3\r OUT (C),A\r RET\r END\r