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Length: 3620 (0xe24)
Types: TextFile
Names: »TSIODM.SRC«
└─⟦519079be6⟧ Bits:30005500 8" CR80 Floppy CR80FD_0029 ( WBOOTL.SYS W.D bootload program 81 10 01 ??? )
└─⟦519079be6⟧ Intel_ISIS_II
└─ ⟦this⟧ »TSIODM.SRC«
LIST S\r NAME TSIODMA\r PUBLIC TSIODMA\r EXTRN ERROR,MDELAY\r CSEG\r ;******************************************************************************\r TITLE 'SIO-DMA DATA TRANSFER TEST ROUTINE'\r ;******************************************************************************\r \r ;DESCRIPT: THIS ROUTINE TEST THE DMA -> SIO DATA\r ; TRANSFER. THE DMA AND SIO'S ARE CONNECTED:\r ; DMA CHA 0 - SIO2 CHA A\r ; DMA CHA 1 - SIO2 CHA B\r ; DMA CHA 2 - SIO1 CHA A\r ; DMA CHA 3 - SIO1 CHA B\r ;EXIT: A = 0 TEST COMPLETED WITHOUT ERROR\r ; A = 91 DMA0 - SIO2A CONTROL ERROR\r ; A = 92 DMA1 - SIO2B CONTROL ERROR\r ; A = 93 DMA2 - SIO1A CONTROL ERROR\r ; A = 94 DMA3 - SIO1B CONTROL ERROR\r ; A = 95 DMA0 - SIO2A DATA TRANSFER ERROR\r ; A = 96 DMA0 - SIO2A DATA OVERFLOW ERROR\r ; A = 97 DMA1 - SIO2B DATA TRANSFER ERROR\r ; A = 98 DMA1 - SIO2B DATA OVERLFOW ERROR\r ; A = 99 DMA2 - SIO1A DATA TRANSFER ERROR\r ; A = 9A DMA2 - SIO1A DATA OVERFLOW ERROR\r ; A = 9B DMA3 - SIO1B DATA TRANSFER ERROR\r ; A = 9C DMA3 - SIO1B DATA OVERFLOW ERROR\r ;\r ;TIME: ~ 4,5 MILLI SEC.\r ;DATE: 810305\r ;PROBRAMMER: IMJ\r ;\r TSIODMA: DI\r OUT (ADMA+0D),A ;RESET DMA\r IN A,(APIO1+1)\r AND 11111100B ;SET LOOP TEST\r OUT (APIO1+1),A\r LD A,0FFH\r OUT (APIO1),A ;SET INTERNAL CLOCKS\r LD HL,6 ;SET ALL 4 CLOCKS TO 333 KHZ\r LD C,ATIM1\r OUT (C),L\r OUT (C),H\r INC C\r OUT (C),L\r OUT (C),H\r LD C,ATIM2\r OUT (C),L\r OUT (C),H\r INC C\r OUT (C),L\r OUT (C),H\r IN A,(APIO1+2)\r RES 6,A\r OUT (APIO1+2),A ;ENABLE DMA-SIO2 TRANSFER\r LD A,01001000B ;SET DMA MODE\r LD B,4\r SD1LOOP: OUT (ADMA+0BH),A ;ALL CHANNEL: SINGLE READ TRANSFER\r INC A\r DJNZ SD1LOOP\r LD A,01010000B ;SET DMA CONTROL\r OUT (ADMA+8),A\r LD HL,SRAMB+200H\r LD DE,2-1 ;SET BYTE COUNT TO BE TRANSMITTED PER. CHANNEL\r LD A,0\r LD B,4\r OUT (ADMA+0CH),A ;RESET F/L FF\r LD C,ADMA\r SD2LOOP: LD (HL),A ;FOR CHANNEL 0 TO 3\r OUT (C),L\r OUT (C),H ; SET READ ADDRESS\r INC C\r OUT (C),E\r OUT (C),D ; SET BYTE COUNT\r INC C\r INC A\r INC HL\r LD (HL),A\r INC A\r INC HL\r DJNZ SD2LOOP ;NEXT CHANNEL\r \r LD C,ASIO1+2\r CALL SETSIO ;INIT SIO1 CHA A\r INC C\r CALL SETSIO ;INIT SIO1 CHA B\r LD C,ASIO2+2\r CALL SETSIO ;INIT SIO2 CHA A\r INC C\r CALL SETSIO ;INIT SIO2 CHA B\r LD A,0\r OUT (ADMA+0FH),A ;RESET MASK'S\r LD DE,4\r CALL MDELAY ;WAIT UNTIL DATA TRANSMITTED\r IN A,(ADMA+8)\r LD E,A\r LD D,8\r LD B,4\r SD3LOOP: LD A,D ;FOR CHANNEL 3 TO 0 STEP -1\r AND E\r JR Z,SD1ERROR ; QUIT IF DMA TRANSFER NOT COMPLETED\r RRC D\r DJNZ SD3LOOP ;NEXT CHANNEL\r LD E,0\r LD D,5\r LD C,ASIO2\r CALL SDACH\r LD C,ASIO1\r CALL SDACH\r XOR A ;SET TEST COMPLETED \r JR SDEXIT\r ;\r ;\r SDACH: LD L,2 ;FOR SIO CHA A TO B\r SD4LOOP: LD B,2\r SD41LOOP: INC C ; FOR DATA 0 TO 1\r INC C\r IN A,(C)\r BIT 0,A ; QUIT IF DATA NOT RECEIVED\r JR Z,SD2ERROR\r LD A,1\r OUT (C),A\r IN A,(C)\r AND 70H\r JR NZ,SD2ERROR ; QUIT IF DATA ERROR\r DEC C\r DEC C\r IN A,(C)\r XOR E\r JR NZ,SD2ERROR ; QUIT IF DATA NOT THE EXPECTED\r INC E\r DJNZ SD41LOOP ; NEXT DATA\r INC D\r INC C\r INC C\r IN A,(C)\r BIT 0,A\r JR NZ,SD2ERROR\r DEC C\r INC D\r DEC L\r JR NZ,SD4LOOP ;NEXT CHANNEL\r INC D\r RET\r \r SD1ERROR: LD A,90H\r ADD A,B\r CALL ERROR ;GO TO ERROR ROUTINE\r SD2ERROR: LD A,90H\r ADD A,D\r CALL ERROR ;GO TO ERROR ROUTINE\r SDEXIT: RET ;EXIT IF TEST COMPLETED\r ;\r SETSIO: LD HL,SIOTAB\r LD B,(HL)\r INC HL\r OTIR\r RET\r SIOTAB: DB SIOEND-SIOTAB-1\r DB 18H ;RESET CHANNEL\r DB 4,01000111B ;ASYNC MODE\r DB 3,11000001B ;RX ENABLED\r DB 5,01101000B ;TX ENABLED\r DB 1,11000000B ;ACTIVATE READY\r SIOEND: NOP\r END\r