OctetView
0x00000…00100 (0, 0, 0) Sector 00444130303434 ┆ DA0044A ┆
0x00100…00200 (0, 0, 1) Sector 00000000000000 ┆ ┆
0x00200…00300 (0, 0, 2) Sector ff00e080ffffff ┆ ` p ` ┆
0x00300…00306 (0, 0, 3) WangDocument {d00=0x06, d01=0x75, d02=0x41, ptr=(56,0, 0), d05=0x00}
0x00306…0030c WangDocument {d00=0x06, d01=0x78, d02=0x41, ptr=(58,0, 0), d05=0x00}
0x0030c…00312 WangDocument {d00=0x06, d01=0x79, d02=0x41, ptr=(39,0, 0), d05=0x00}
0x00312…00318 WangDocument {d00=0x06, d01=0x80, d02=0x41, ptr=(58,0, 8), d05=0x00}
0x00318…0031e WangDocument {d00=0x06, d01=0x81, d02=0x41, ptr=(45,0, 0), d05=0x00}
0x0031e…00320 06 81 ┆ ┆
0x00320…00340 41 3f 08 00 06 83 41 4c 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ┆A? AL ┆
0x00340…00360 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ┆ ┆
[…0x4…]
0x003e0…00400 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 1e ┆ ┆
0x00400…00500 (0, 0, 4) Sector 00000000000000 ┆ ┆
0x00500…00600 (0, 0, 5) Sector 00444130303434 ┆ DA0044A ┆
0x00600…00700 (0, 0, 6) Sector 421c402600415b ┆B @& A[' U X% % PO P ; A C f x f V WD O 7 : % 8 0681A f L < {C < { ; 9 ` o k@ k : 9 8 % w x 0675A0678A0679A0680A0681A ┆
0x00700…00800 (0, 0, 7) Sector 00000000000000 ┆ ┆
0x00800…00900 (0, 0, 8) Sector aaaaaaaaaaaaaa ┆****************************************************************************************************************************************************************************************************************************************************************┆
[…0x7…]
0x01000…01100 (1, 0, 0) WangDocumentBody
[…0x2…]
0x01300…01400 (1, 0, 3) Sector 01049d00067541 ┆ uAt of the System Design (sec. 5.4). 5.1.4.1.9 The Power Supply TBD. 5.1.4.2 Documentation TBD. 5.1.4.3 Environmental Specification TBD. s a mailbox for time outs detected by the outgoing scan routine. frames. The only path for commu┆
0x01400…01500 (1, 0, 4) Sector 00000600067541 ┆ uA 1 Outgoing Processor This processor runs the routines associated with transmission of frames. The outgoing scan routine provides an entry into the "outgoing scan table" (in centr┆
0x01500…01600 (1, 0, 5) Sector aaaaaaaaaaaaaa ┆****************************************************************************************************************************************************************************************************************************************************************┆
[…0x2…]
0x01800…01900 (1, 0, 8) WangDocumentBody
0x01900…01a00 (1, 0, 9) Sector 010aff00067841 ┆ xAer of V24 control circuits to enable the DEC to control and monitor a CRYPTO link in case of a connected remote NICS TARE. Applied V24 circuits and baud rates are as shown in table 5.3.2-4. For explanation of the V24 Circuit numbers please refer t┆
0x01a00…01b00 (1, 0, 10) Sector 010b9400067841 ┆ xAo section 5.3.4 (Appendix A). 5.3.3 Test of Distribution Equipment TBD 5.3.4 APPENDIX A Definition of applied V24 circuits. TBD. of converting 1 V24/V28 channel into 1 optical link signal and vice versa. On the front panel are 2 optica┆
0x01b00…01c00 (1, 0, 11) Sector 0000ae00067841 ┆ . xA 1 Figure 5.3.2.5-1 Data Exchange Channel - Category 5 pto transceiver. The terminal OPTO TRANSCEIVER is capable of converting 1 V24/V┆
0x01c00…01d00 (1, 0, 12) Sector 010dff00067541 ┆ uA 1 The CR80D processor will only make changes in a protocol descriptor when its base address is removed from one or both scan tables, as necessary, in order not to interfere with ingo┆
0x01d00…01e00 (1, 0, 13) Sector 010eff00067541 ┆ uAing or outgoing processor (concurrent processing). Finally the CR80D processor can by issuing a RESET command, force the incoming and outgoing processor to remove all entries in their scan tables (closing all links). The RESET command is utilized┆
0x01e00…01f00 (1, 0, 14) Sector 010fff00067541 ┆ uA during initialization of the STI/TIA system. Interrupt to CR80D Upon request from Ingoing or Outgoing processor the Main Control processor is able to issue an interrupt to the CR80D system, this interrupt can by the CR80D CPU be read in the MAP┆
0x01f00…02000 (1, 0, 15) Sector 0100ff00067541 ┆ uA. The interrupt code issued is set on a DIL switch. 5.1.4.1.7.3 Mechanical & Electrical Specifications Mechanical dimensions of the TIA module Height: 412,6 mm ( 10 U crate) Width: 17,1 mm ( 1 Module) Depth: 160 mm The TIA i┆
0x02000…02100 (2, 0, 0) WangDocumentBody
[…0x18…]
0x03900…03a00 (3, 0, 9) Sector 030aaa00067641 ┆ * vA 1 Fig. 5.1.5.1.3.3-1 LTU Flatcable I/O Connector B(P), P = P+1 1 0 0 0 0 1 0 Write upper byte B(P) P=P+1 0 0 0 ┆
0x03a00…03b00 (3, 0, 10) Sector 030bff00067641 ┆ vA 1 5.1.5.1.4 The Floppy Disk Controller & Adapter TBD. 5.1.5.1.4.1 Mechanical & Electrical Specifications Mechanical Specification for the Floppy Disk Controller Height: 41┆
0x03b00…03c00 (3, 0, 11) Sector 030cff00067641 ┆ vA2,6 mm ( 10 U crate) Width: 17,1 mm ( 1 Module) Depth: 305 mm The Floppy Disk Controller is a front crate mounted module. Power Consumption for the Floppy Disk Controller + 5V: TBD +12V: TBD -12V: TBD Mechanical Specifi┆
0x03c00…03d00 (3, 0, 12) Sector 030dff00067641 ┆ vAcation for the Adapter Height: 412,6 mm ( 10 U crate) Width: 17,1 mm ( 1 Module) Depth: 160 mm Power Consumption for the Adapter Not applicable. Electrical Specifications for the Floppy Disk Controller/Adapter Flatcable Bus ┆
0x03d00…03e00 (3, 0, 13) Sector 030ea100067641 ┆ ! vA TBD. 5.1.5.1.5 The CCA (Configuration Control Adapter) This module is considered a part of the Watchdog Processor and is treated within sec. 5.4. tes B(0) and B(1). The pointer is auto incremented to 2. 7) Read Word B(P), B(P+1), Fetch ┆
0x03e00…03f00 (3, 0, 14) Sector 0000b600067641 ┆ 6 vA 1 5.1.5.1.6 The Power Supply TBD. 5.1.5.2 Documentation TBD. 5.1.5.3 Environment See section 3.1 kept ready for the next transfer. 8) Read Lower Byte B(P), P=P+1 ┆
0x03f00…04000 (3, 0, 15) Sector 0300ff00067541 ┆ uA frame to the buffer for incoming frames at the same time setting a FULL flag in a status byte in front of the buffer. This incoming buffer are located in the input Data RAM area. If the MUX no. was equal to the DIL-switch and no CRC-error was in┆
0x04000…04100 (4, 0, 0) WangDocumentBody
[…0x203…]
0x24400…24500 (36, 0, 4) Sector 2405ff00067841 ┆$ xA... 5.3.1 General .............................. 5.3.2 Distribution & Monitoring Equipment/ Facilities ........................... 5.3.2.1 DEC - Category 1 ................. 5.3.2.2 DEC - Category 2 .....┆
0x24500…24600 (36, 0, 5) Sector 2406ff00067841 ┆$ xA............ 5.3.2.3 DEC - Category 3 ................. 5.3.2.4 DEC - Category 4 ................. 5.3.2.5 DEC - Category 5 ................. 5.3.3 Test of Distribution Equipment ....... 5.3.4 Appendi┆
0x24600…24700 (36, 0, 6) Sector 24072c00067841 ┆$ , xAx A ........................... I! "(=6 *(=#"(=6 IM2&! w"2< hMI sM & E 0= u M% :^=~ Bl1{M40sI:^=~ J 1!"<6;!#<6 !&<6 ! "$<! <6 {M;(s! 9"c=! "(= Z=q#p!"<6 !&<6 ! "$<!#<6 ! <6 {M)(sC I! <6 ! "(= <q#p!"<6 !#<6 ! "$<!&<6$`i6 {M)(sM &M7 ┆
0x24700…24800 (36, 0, 7) Sector 2308ff00067841 ┆# xA 1 5.3 DISTRIBUTION, MONITORING & TEST (DM&T) DESIGN 5.3.1 General The aim of this section is to explain the design of the DM&T equipment/facilities as implemented in the present ┆
0x24800…24900 (36, 0, 8) WangDocumentBody
[…0x27…]
0x27000…27100 (39, 0, 0) WangDocumentHead {hdr=WangSectHead {next=(39,0, 1), len=0xff, h3=41067941}, f00=»0679A «, f01=»CPS/SDS/001 ISSUE 1 «, f02=»vhn «, f03=»BHJ «, f04=»Kapitel 5.4 «, f05=20-02-81 13:14, f06=» 1 «, f07=»30 «, f08=» 4623 «, f09=25-03-81 13:14, f10=» «, f11=»03 «, f12=» 74 «, f13=25-03-81 13:17, f14=12-10-81 08:58, f15=»0044A «, f16=» 14 «, f17=» 1 «, f18=»42 «, f19=» 144 «, f20=» 4772 «, f21=» «, f22=» «, f99=100010000110056610a10a80aaca15050000000000000038033400df}
0x27100…27200 (39, 0, 1) WangDocumentBody
[…0x9…]
0x27b00…27c00 (39, 0, 11) Sector 00006900068041 ┆ i ATARE connection. On each of the above mentioned items a ground connection terminal is provided. nted between neighbouring cabinets. A logical lay-out of 3-bay rack-assembly is shown on fig. 5.5.5-2. 5.5.5.2.2 Power Cabling The power cablin┆
0x27c00…27d00 (39, 0, 12) Sector 270d8200068041 ┆' A 1 8 Figs. gaps between doors and cabinet are blocked by gaskets of conducting material. The tightness of these gaskets is important ┆
0x27d00…27e00 (39, 0, 13) Sector 00006600068041 ┆ f A 1 5.5.5.2.4 Grounding TBD. end of the rack. The air leaves the rack through a perforated area in the top cover plate of the rack. 5.5.4.3 V24 Monitor Panel The V24 monitor p┆
0x27e00…27f00 (39, 0, 14) Sector 270fff00067941 ┆' yA.1.2.4 VDU & LP ..................... 5.4.1.3 Package Control .................. 5.4.1.3.1 Synchronization .............. 5.4.1.3.2 Configuration Control ........ 5.4.1.3.3 Error Reporting .............. ┆
0x27f00…28000 (39, 0, 15) Sector 2700ff00067941 ┆' yA 5.4.1.4 Characteristics .................. 5.4.1.4.1 Performance .................. 5.4.1.4.2 Security ..................... 5.4.2 Environment .......................... 5.4.2.1 Standard Hardware,┆
0x28000…28100 (40, 0, 0) WangDocumentBody
[…0x4f…]
0x2d000…2d100 (45, 0, 0) WangDocumentHead {hdr=WangSectHead {next=(45,0, 1), len=0xff, h3=41068141}, f00=»0681A «, f01=»CPS/SDS/001 ISSUE 1 «, f02=»vhn «, f03=»GJ «, f04=»Kapitel 5.6 «, f05=20-02-81 13:23, f06=» 3 «, f07=»22 «, f08=» 2464 «, f09=25-03-81 13:22, f10=» «, f11=»07 «, f12=» 200 «, f13=25-03-81 13:29, f14=12-10-81 08:58, f15=»0044A «, f16=» 37 «, f17=» 3 «, f18=»43 «, f19=» 588 «, f20=» 2991 «, f21=» «, f22=» «, f99=200010000110056610a10a80aaca1505000000000000003803b900df}
0x2d100…2d200 (45, 0, 1) WangDocumentBody
[…0xae…]
0x38000…38100 (56, 0, 0) WangDocumentHead {hdr=WangSectHead {next=(56,0, 1), len=0xff, h3=41067541}, f00=»0675A «, f01=»CPS/SDS/001 ISSUE 1 «, f02=»vhn «, f03=»SRA «, f04=»Kapitel 5 «, f05=20-02-81 12:47, f06=» 3 «, f07=»32 «, f08=» 12367 «, f09=01-05-81 15:10, f10=» «, f11=»07 «, f12=» 57 «, f13=01-05-81 15:27, f14=12-10-81 08:57, f15=»0044A «, f16=»117 «, f17=» 7 «, f18=»26 «, f19=» 1440 «, f20=» 19894 «, f21=» «, f22=» «, f99=310010000110056610a10a80aaca1505000000000000003803db01df}
0x38100…38200 (56, 0, 1) WangDocumentBody
[…0x1e…]
0x3a000…3a100 (58, 0, 0) WangDocumentHead {hdr=WangSectHead {next=(58,0, 1), len=0xff, h3=41067841}, f00=»0678A «, f01=»CPS/SDS/001 ISSUE 1 «, f02=»vhn «, f03=»SRA «, f04=»Kapitel 5.3 «, f05=20-02-81 13:09, f06=» «, f07=»30 «, f08=» 542 «, f09=01-05-81 15:49, f10=» «, f11=»02 «, f12=» 43 «, f13=01-05-81 15:53, f14=12-10-81 08:58, f15=»0044A «, f16=» 23 «, f17=» 1 «, f18=»32 «, f19=» 304 «, f20=» 7785 «, f21=» «, f22=» «, f99=220010000110056610a10a80aaca15050000000000000038036100df}
0x3a100…3a200 (58, 0, 1) WangDocumentBody
[…0x6…]
0x3a800…3a900 (58, 0, 8) WangDocumentHead {hdr=WangSectHead {next=(58,0, 9), len=0xff, h3=41068041}, f00=»0680A «, f01=»CPS/SDS/001 ISSUE 1 «, f02=»vhn «, f03=»BHB «, f04=»Kapitel 5.5 «, f05=20-02-81 13:20, f06=» «, f07=»19 «, f08=» 515 «, f09=01-05-81 16:11, f10=» «, f11=»00 «, f12=» 28 «, f13=01-05-81 16:15, f14=12-10-81 08:58, f15=»0044A «, f16=» 27 «, f17=» «, f18=»48 «, f19=» 256 «, f20=» 1930 «, f21=» «, f22=» «, f99=720010000110056610a10a80aaca15050000000000000038035b00df}
0x3a900…3aa00 (58, 0, 9) WangDocumentBody
[…0x6…]
0x3b000…3b100 (59, 0, 0) Sector 3b01ff00068141 ┆; Ations are passed via synchronization elements specified by the controlling process. The interfaces between DEVICE MANAGER and hardware are: 3) IO Instruction One of the CR80D instruction, if the device is located in the processor crate, and a┆
0x3b100…3b200 (59, 0, 1) Sector 3b02b100068141 ┆; 1 A DMA transferred IO command, if the device is located in an IO crate. 4) Interrupt Signal from a device that an IO operation has been completed fully or partially ssociated with a security clearance level for each compartment. Both entities ┆
0x3b200…3b300 (59, 0, 2) Sector 3b03ff00068141 ┆; A 1 5.6.1.2.3.1 Device Security As KERNEL objects, devices are protected by the security mechanisms described in 5.6.1.2.2. Each physical device, however, consists of a number of lo┆
0x3b300…3b400 (59, 0, 3) Sector 3b04ff00068141 ┆; Agical sub-devices. A disk device is by SFM subdivided into a number of files and items, each of which should be protected individually. A line terminating device similarly consists of a number of individual lines, each of which must also be protecte┆
0x3b400…3b500 (59, 0, 4) Sector 3b05ff00068141 ┆; Ad. So in addition to the device protection enforced by KERNEL, SFM and IOC respectively will enforce a protection on a subdevice level. The security rules described in 5.6.1.2.2 are the same, however. 5.6.1.2.4 Process Management Process ma┆
0x3b500…3b600 (59, 0, 5) Sector 3b06ff00068141 ┆; Anagement is concerned with implementation of software processes as a data type and with implementation of the functions available for operating on processes. As described in 5.6.1.1.1, a process may be defined as an incarnation of the data transfo┆
0x3b600…3b700 (59, 0, 6) Sector 3b07ff00068141 ┆; Armations obtained by execution of a program in a given context. A context is taken to mean a set of CPU registers (CPU resident or saved) including the program and data base registers PROG and BASE and the two Translation Table Registers and the two┆
0x3b700…3b800 (59, 0, 7) Sector 3a08ff00068141 ┆: A Translation Tables. A process is represented by a process descriptor (procdes) and it is identified by a process identifier (procid). A process may thus be referred to without knowing in which memory locations it resides. The only instant at whic┆
0x3b800…3b900 (59, 0, 8) Sector 3b09ff00068141 ┆; Ainformation of its own classification level or lower. The behaviour of an unstrusted process is unpredictable. The general security policy can now be stated: 1) Any process is allowed to read information from objects of security level lower th┆
0x3b900…3ba00 (59, 0, 9) Sector 3b0aff00068141 ┆; Aan or equal to its own level (within each compartment). 2) Any process is allowed to write information to objects of security level higher than or equal to its own level. 3) A trusted process is further allowed to write information to objects of┆
0x3ba00…3bb00 (59, 0, 10) Sector 3b0bff00068141 ┆; A security level lower than its own level. These rules imply that the flow of information is generally from lower to the same or higher security levels. Only trusted processes can reverse this direction. All security control information is kept i┆
0x3bb00…3bc00 (59, 0, 11) Sector 3b0cff00068141 ┆; An protected memory which is only accessible in system mode. 5.6.1.2.3 Device Management Processes may not execute I/O instructions directly. Neither are they directly activated by device interrupts. Both functions are carried out by device hand┆
0x3bc00…3bd00 (59, 0, 12) Sector 3b0d3800068141 ┆; 8 Alers within the KERNEL module DEVICE MANAGEMENT. tions has a directory, where objects may be catalogued. Each catalogue entry consists of an object indentifier and an access control list. Each entry of the access control list specifies the capabili┆
0x3bd00…3be00 (59, 0, 13) Sector 3b0eff00068141 ┆; A 1 A device is a system resource, which by some operating system must be granted to the process with the job of mediating access to the device. In CAMPS, SFM and IOC will be granted c┆
0x3be00…3bf00 (59, 0, 14) Sector 3b0fff00068141 ┆; Aontrol of disk and line devices respectively. The external function of Device Manager is: 1) IO Activation A procedure called by SFM or IOC, requesting a single operation or a sequence of operation to be performed on the device. Special cases┆
0x3bf00…3c000 (59, 0, 15) Sector 3b00ff00068141 ┆; A are activation of specific built-in test functions of the device. 2) IO Completion Notification A notification to SFM or IOC that a requested IO operation has been completed, either normally or abnormally (with one or more errors). IO notifica┆
0x3c000…3c100 (60, 0, 0) Sector 3c01ff00068141 ┆< A 1 5.6.1.2.2.1 Access Authorization Authorization of access to an object is based on - A general security policy, and - A discretionary access checking The security policy is b┆
0x3c100…3c200 (60, 0, 1) Sector 3c02ff00068141 ┆< Aased on a multilevel - multicompartment security system. Objects are associated with a security classification level for each compartment and subjects (processes) are associated with a security clearance level for each compartment. Both entities ┆
0x3c200…3c300 (60, 0, 2) Sector 3c03ff00068141 ┆< Aare described in a common type: - The security profile Discretionary access checking is based on - Identification of access classes of subjects (processes), and - Statements of access capabilities for explicitly enumerated access classes of ┆
0x3c300…3c400 (60, 0, 3) Sector 3c04ff00068141 ┆< Asubjects vis a vis a given object. The identification of an access class of subjects (processes) is based on a User Group Identification (UGI) which is common to all subjects in that class. Access rights are stated in an access control list whic┆
0x3c400…3c500 (60, 0, 4) Sector 3c05ff00068141 ┆< Ah is associated with each catalogued object. The access control list is a list of paired UGIs and stated access capabilities. Certain UGIs are reserved for special use: - System User Identifies a subject with all access rights - Public User┆
0x3c500…3c600 (60, 0, 5) Sector 3c06c800068141 ┆< H A Identifies any subject which is otherwise not found in an access control list The general access authorization mechanism described above is used whenever catalogued objects are accessed. e of resource. A process can never create more instance┆
0x3c600…3c700 (60, 0, 6) Sector 3c07ff00068141 ┆< A 1 Access to an object is authorized if the following conditions both are fulfilled: a) The access requested is allowed according to the access control list, or the object was inher┆
0x3c700…3c800 (60, 0, 7) Sector 3b08ff00068141 ┆; Aited from parent or created by the process itself b) The security profile of the calling process matches that of the object. The security profile check uses the concept of a trusted process: A trusted process is assumed to work correctly with ┆
0x3c800…3c900 (60, 0, 8) Sector 3c099100068141 ┆< A section 5.6.1.2.4. In CAMPS, the operating system functions are performed by SSC, having responsibility for all resource management. The process exchanges data with the environmental files and lines. It does not need to recognize other proces┆
0x3c900…3ca00 (60, 0, 9) Sector 3c0aff00068141 ┆< A 1 5.6.1.2.1.1 Access to Objects There are three ways for a process to gain access to an object: a) Creation The process which originally created the object has capabilities whi┆
0x3ca00…3cb00 (60, 0, 10) Sector 3c0bff00068141 ┆< Ach it specified itself at creation time. At that time Directory Functions checked if the specified capabilities were compatible with security rules. b) Inheritance A child may at creation time inherit specified objects with specified capabiliti┆
0x3cb00…3cc00 (60, 0, 11) Sector 3c0cff00068141 ┆< Aes from the parent. The capabilities versus a given object can only be a subset of those possessed by the parent. The capabilities of the child can never be changed. Directory functions check at creation time if the capabilities are consistent with ┆
0x3cc00…3cd00 (60, 0, 12) Sector 3c0dff00068141 ┆< Asecurity rules. c) Cataloguing Directory functions has a directory, where objects may be catalogued. Each catalogue entry consists of an object indentifier and an access control list. Each entry of the access control list specifies the capabili┆
0x3cd00…3ce00 (60, 0, 13) Sector 3c0eff00068141 ┆< Aties of a user group to the object. When a process wants access to a particular object, it calls the directory function Lookup Object, which then checks if the user group of the process has any capabilities to the object and if the access is consist┆
0x3ce00…3cf00 (60, 0, 14) Sector 3c0fff00068141 ┆< Aent with security rules. 5.6.1.2.2 Security KERNEL contains tools which may be used by SSC to enforce very rigid limitations upon the information exchange between processes, and access to objects by processes. As described in section 4.8, these┆
0x3cf00…3d000 (60, 0, 15) Sector 3c005000068141 ┆< P A tools are used as the second level in a two level checking mechanism. ent creation, deletion, transfer, and mapping 10. Set Time 11. Read Time, Schedule and Cancel Time Signal 12. Time Signal 13. Timer Interrupt 14. Error Report to Calling ┆
0x3d000…3d100 (61, 0, 0) Sector 3d014c00068141 ┆= L AProcess 15. Error Report to Parent FIGURE 5.6.1.1.4-1 (CONT.) sequence of machine instructions. The data associated with a process are called the process data. The instructions for manipulating the process data are collected in the assoc┆
0x3d100…3d200 (61, 0, 1) Sector 3d024a00068141 ┆= J A 1 tions (non privileged hardware instructions) together with the system commands provided by KER, SFM and IOC. Program and process data reside in completely separate parts of memory┆
0x3d200…3d300 (61, 0, 2) Sector 3d03ff00068141 ┆= A 1 5.6.1.2 Functions 5.6.1.2.1 Directory Functions Directory Functions are KERNEL tools for resource allocation. Examples of system resources, from here on called objects, are m┆
0x3d300…3d400 (61, 0, 3) Sector 3d04ff00068141 ┆= Aemory segments, processes, CPU's and synchronization elements. Objects are dynamically created and removed by processes, and exchanged between processes. KERNEL controls, that whenever a process has obtained access to an object, either by creating┆
0x3d400…3d500 (61, 0, 4) Sector 3d05ff00068141 ┆= A it or by obtaining it from another process, the process can not access or manipulate the object beyond a limit defined at creation time or time of granting the access. This limit is called the capabilities of the process with respect to the object.┆
0x3d500…3d600 (61, 0, 5) Sector 3d06ff00068141 ┆= A For each object a process can only grant a subset of the capabilities that it has got itself. The ability of a process to create new objects is further limited by a socalled claim on each type of resource. A process can never create more instance┆
0x3d600…3d700 (61, 0, 6) Sector 3d07ff00068141 ┆= As of a specific object type than defined by its claim for that object type. Even if KERNEL contains tools for limiting access to existing objects and limits ability to create new objects, it does not take any high level decisions about distributio┆
0x3d700…3d800 (61, 0, 7) Sector 3c08ff00068141 ┆< An of available resources between processes and the dynamic behaviour of the system in terms of creation and removal of objects. These decisions must be taken by special processes playing the role of operating systems. This is further described in┆
0x3d800…3d900 (61, 0, 8) Sector 3d09ff00068141 ┆= Aonment looks as if the process is executed within a monoprogrammed machine with a CPU, a memory and a set of peripheral files and/or lines. The process exchanges data with the environmental files and lines. It does not need to recognize other proces┆
0x3d900…3da00 (61, 0, 9) Sector 3d0aff00068141 ┆= Ases except that they may cause a slow down of the CPU. Processes may, however, cooperate in performing a specific task. They do so by exchanging data and synchronizing their activities. This is done by the process communication tools provided by K┆
0x3da00…3db00 (61, 0, 10) Sector 3d0bff00068141 ┆= AERNEL. Synchronization and data exchange between processes is done by means of synchronization elements as described in 5.6.1.2.6. Based upon synchronization elements, the I/O system implements special tools for data exchange with SFM and IOC. ┆
0x3db00…3dc00 (61, 0, 11) Sector 3d0cff00068141 ┆= A 5.6.1.1.4 Interfaces KERNEL interfaces to hardware and to all other CAMPS software packages. Three packages are of special interest: a) SSC Takes all high level decisions concerning resource allocation and resource sharing. b) SFM Contr┆
0x3dc00…3dd00 (61, 0, 12) Sector 3d0d8300068141 ┆= Aols all disk storage. c) IOC Controls all communication lines. The main interfaces are shown on the diagram overleaf. cal communication lines. In a rather crude model, the relations between KERNEL, SFM, IOC and the rest of CAMPS software is┆
0x3dd00…3de00 (61, 0, 13) Sector 3d0e9c00068141 ┆= A 1 Figure 5.6.1.1.4-1 KERNEL Interfaces 2.1.1 Access to Objects ........ 285 5.6.1.2.2 Security ..................... 285 5┆
0x3de00…3df00 (61, 0, 14) Sector 3d0fff00068141 ┆= A 1 1. I/O Activation 2. I/O Completion Notification 3. I/O Instruction 4. Device Interrupt 5. Process creation, deletion, activation, and deactivation 6. Timer Interrupt ┆
0x3df00…3e000 (61, 0, 15) Sector 3d00ff00068141 ┆= A 7. Send, Await and I/O System Functions 8. Page Fault Interrupt 9. Segment creation, deletion, transfer, and mapping 10. Set Time 11. Read Time, Schedule and Cancel Time Signal 12. Time Signal 13. Timer Interrupt 14. Error Report to Calling ┆
0x3e000…3e100 (62, 0, 0) Sector 3e01ff00068141 ┆> Ay the execution of an associated program. A program is defined as a sequence of machine instructions. The data associated with a process are called the process data. The instructions for manipulating the process data are collected in the assoc┆
0x3e100…3e200 (62, 0, 1) Sector 3e02ff00068141 ┆> Aiated program. The available instructions are the CR80D user instructions (non privileged hardware instructions) together with the system commands provided by KER, SFM and IOC. Program and process data reside in completely separate parts of memory┆
0x3e200…3e300 (62, 0, 2) Sector 3e03ff00068141 ┆> A, and the same program may well be executed by several processes. Execution of processes may be truly parallel if the machine contains more than one CPU. Otherwise execution is pseudo-parallel, meaning that execution of the running process may at ┆
0x3e300…3e400 (62, 0, 3) Sector 3e04ff00068141 ┆> Aany place in the program be interrupted and another process may then resume execution from a point in the program where it was previously interrupted. Process data and program associated with a given process are specified by two sets of Memory Tra┆
0x3e400…3e500 (62, 0, 4) Sector 3e05ff00068141 ┆> Anslation Tables belonging to the process. They are loaded into the map module each time the process resumes execution. (See figure 5.6.1.1.1-1) 5.6.1.1.2 Security Security is closely related to the process concept in that all system resources ┆
0x3e500…3e600 (62, 0, 5) Sector 3e06bc00068141 ┆> < Aare allocated to and exchanged between processes. So security actually amounts to controlling the access to system resources, including information carrying resources, by processes. ..... 310 5.6.2.2 External Interfaces .............. 310 ┆
0x3e600…3e700 (62, 0, 6) Sector 3e079c00068141 ┆> A 1 Fig. 5.6.1.1.1-1 Relations between HW and SW packages 200 25 03 81 13 29 25 03 81 13 33 0044A 37 3 43 588 2991 f ! *J 8 : _┆
0x3e700…3e800 (62, 0, 7) Sector 3d08ff00068141 ┆= A 1 KERNEL implements the basic tools for protection of resources as described in more detail in section 5.6.1.2.2. 5.6.1.1.3 Process Environment From "within" a process the envir┆
0x3e800…3e900 (62, 0, 8) Sector 3e09ff00068141 ┆> Avel hardware objects, such as CPUs, memory modules, memory mapping module, I/O busses, I/O devices, and a set of operations on those objects by means of the CR80D instruction set. The main purpose of most pieces of system software is to hide certa┆
0x3e900…3ea00 (62, 0, 9) Sector 3e0aff00068141 ┆> Ain hardware features, replacing them with a new set of features, which are more suitable for the application area at hand. This can be viewed as an abstraction of the actual physical machine into a virtual machine, which will be the only one accessi┆
0x3ea00…3eb00 (62, 0, 10) Sector 3e0bff00068141 ┆> Able by application software. Actually this abstraction process is repeated a number of times and gives rise to several layers of system software. Each layer transforms the underlying virtual machine into a new one, which is then provided to upper la┆
0x3eb00…3ec00 (62, 0, 11) Sector 3e0cff00068141 ┆> Ayers. KERNEL constitutes the lowest level of system software in this sense. The next level of abstraction above the KERNEL is constituted by SFM and IOC respectively: - SFM transforms each disk device (controller) into a set of disk units, each ┆
0x3ec00…3ed00 (62, 0, 12) Sector 3e0dff00068141 ┆> Aconsisting of a number of disk files. - IOC transforms each line termination device (LTU or TDX Host IF) into a set of logical communication lines. In a rather crude model, the relations between KERNEL, SFM, IOC and the rest of CAMPS software is┆
0x3ed00…3ee00 (62, 0, 13) Sector 3e0e2a00068141 ┆> * A shown on the diagram 5.6.1.1-1. 5.6.1.2 Functions ........................ 284 5.6.1.2.1 Directory Functions .......... 284 5.6.1.2.1.1 Access to Objects ........ 285 5.6.1.2.2 Security ..................... 285 5┆
0x3ee00…3ef00 (62, 0, 14) Sector 3e0f8400068141 ┆> A 1 5.6.1.1-1 urity .......... 289 5.6.1.2.4 Process Management ........... 289 5.6.1.2.4.1 Process Hierarchy ........ 2┆
0x3ef00…3f000 (62, 0, 15) Sector 3e00ff00068141 ┆> A 1 5.6.1.1.1 Process Concept The most important new concept introduced by KERNEL is that of a process. A process is defined as the transformation of a given set of data performed b┆
0x3f000…3f100 (63, 0, 0) Sector 3f01ff00068141 ┆? A 5.6.1.2.5.2 Time Slicing ............. 294 5.6.1.2.5.3 Process Scheduling Interfaces ............... 294 5.6.1.2.6 Process Communication ........ 294 5.6.1.2.6.1 Synchronization Elements . 294 5.6.1.2┆
0x3f100…3f200 (63, 0, 1) Sector 3f02ff00068141 ┆? A.6.2 Basic Process Communication Functions ................ 295 5.6.1.2.6.3 IO System ................ 296 5.6.1.2.7 Page Management .............. 300 5.6.1.2.7.1 Page Manager Concepts .... 301 5.6.1.2.7.┆
0x3f200…3f300 (63, 0, 2) Sector 3f03b400068141 ┆? 4 A2 Page Manager Functions ... 304 5.6.1.2.7.3 Page Manager Security Aspects .................. 307 5.6.1.2.8 Timer Management ............. 307 ┆
0x3f300…3f400 (63, 0, 3) Sector 3f04ff00068141 ┆? A 1 5.6.1.3 Kernel Control ................... 308 5.6.1.3.1 Parameter Control ............ 308 5.6.1.3.2 Initialization ............... 309 5.6.1.3.3 Error Ha┆
0x3f400…3f500 (63, 0, 4) Sector 3f05ff00068141 ┆? Andling ............... 309 5.6.1.4 Characteristics .................. 309 5.6.1.4.1 Availability ................. 310 5.6.1.4.2 Security ..................... 310 5.6.1.5 Design and Construction .......... 310 5.6.1┆
0x3f500…3f600 (63, 0, 5) Sector 3f06ff00068141 ┆? A.6 Documentation ..................... 310 5.6.2 Environment .......................... 310 5.6.2.1 Standard Hardware, Firmware and Software ......................... 310 5.6.2.2 External Interfaces .............. 310 ┆
0x3f600…3f700 (63, 0, 6) Sector 3f073800068141 ┆? 8 A 5.6.2.3 Subsystem Interfaces ............. 310 GJ Kapitel 5.6 20 02 81 13 23 3 22 2464 25 03 81 13 22 07 200 25 03 81 13 29 25 03 81 13 33 0044A 37 3 43 588 2991 f ! *J 8 : _┆
0x3f700…3f800 (63, 0, 7) Sector 3e08ff00068141 ┆> A 1 5.6 KERNEL 5.6.1 Summary of Requirements 5.6.1.1 General Description KERNEL is the interface between CAMPS software and hardware. The CR80D hardware provides a set of low le┆
0x3f800…3f900 (63, 0, 8) WangDocumentHead {hdr=WangSectHead {next=(63,0, 9), len=0xff, h3=41068141}, f00=»0681A «, f01=»CPS/SDS/001 ISSUE 1 «, f02=»vhn «, f03=»GJ «, f04=»Kapitel 5.6 «, f05=20-02-81 13:23, f06=» 3 «, f07=»22 «, f08=» 2464 «, f09=25-03-81 13:22, f10=» «, f11=»07 «, f12=» 200 «, f13=25-03-81 13:29, f14=25-03-81 13:33, f15=»0044A «, f16=» 37 «, f17=» 3 «, f18=»43 «, f19=» 588 «, f20=» 2991 «, f21=» «, f22=» «, f99=200010000110056610a10a80aaca1505000000000000003803b900df}
0x3f900…3fa00 (63, 0, 9) Sector 3f0a2500068141 ┆? % A ? ? ? ? > > > > = = = = < < < ; ; : : : : 9 9 9 8 8 8 8 8 7 7 6 6 6 5 5 - - vn: Operat]r: Forfatter: Kommentarer: STATISTIK AKTIVITET DATO TID ANV.TID ANSLAG Oprettet / / / AKTIVITET DATO TID ANV.TID ANSLAG Oprettet / / ┆
0x3fa00…3fb00 (63, 0, 10) Sector 3f0b9d00068141 ┆? A 1 CPS/SDS/001 OKH/810227 CAMPS SYSTEM DESIGN SPECIFICATION CAMPS /=6WC*-!/=6)M2&*/=MM, > I!e=6 !Z="(=e*$<kas#r 9x2"<! <6 M8)I:^=~ B#.!#<6 ! <6 M&&:!<~ J#.:!<2.=M2┆
0x3fb00…3fc00 (63, 0, 11) Sector 3f0cff00068141 ┆? A 1 1 TABLE OF CONTENTS 5.6 KERNEL ..................................... 277 5.6.1 Summary of Requirements ┆
0x3fc00…3fd00 (63, 0, 12) Sector 3f0dff00068141 ┆? A.............. 277 5.6.1.1 General Description .............. 277 5.6.1.1.1 Process Concept .............. 279 5.6.1.1.2 Security ..................... 279 5.6.1.1.3 Process Environment .......... 281 5.6.1.1.4 Inte┆
0x3fd00…3fe00 (63, 0, 13) Sector 3f0eff00068141 ┆? Arfaces ................... 281 5.6.1.2 Functions ........................ 284 5.6.1.2.1 Directory Functions .......... 284 5.6.1.2.1.1 Access to Objects ........ 285 5.6.1.2.2 Security ..................... 285 5┆
0x3fe00…3ff00 (63, 0, 14) Sector 3f0fff00068141 ┆? A.6.1.2.2.1 Access Authorization ..... 286 5.6.1.2.3 Device Management ............ 287 5.6.1.2.3.1 Device Security .......... 289 5.6.1.2.4 Process Management ........... 289 5.6.1.2.4.1 Process Hierarchy ........ 2┆
0x3ff00…40000 (63, 0, 15) Sector 3f00ff00068141 ┆? A90 5.6.1.2.4.2 Process Attributes ....... 292 5.6.1.2.4.3 Process Management Functions ................ 292 5.6.1.2.5 Process Scheduling ........... 293 5.6.1.2.5.1 Priorities ............... 293 ┆
0x40000…40100 (64, 0, 0) Sector 4001ff00067541 ┆@ uAignals The CR80D System is based on serial transmission of the interrupt code from the interrupting I/O module using the lines INA (A32) and INR (A33). The interrupt code consists of 8 bits, of which 2 are priority bits and the remaining 6 bit┆
0x40100…40200 (64, 0, 1) Sector 4002ff00067541 ┆@ uAs are the I/O module number. The 8 bits are transmitted within one [1 (1MHZ) cycle each bit synchronized to the [2 (8 MHZ) clock. The interrupt code is transmitted on the INR line (fig 5.1.3.1-4). INR is an open collector line. Thus all the I/O ┆
0x40200…40300 (64, 0, 2) Sector 40039700067541 ┆@ uAmodules can transmit on the same line, which means that if one module is transmitting an "L" and another an "H", the line will contain the "L". lso the inverter circuitry supporting the PU I/O interrupt system (sec. 5.1.3.1.1b). Within a CU each ┆
0x40300…40400 (64, 0, 3) Sector 4004ff00067541 ┆@ uA 1 INA is an open collector line too. It is driven from the Main Bus termination boards (MBT or CIA), one in each end of the Bus. The contents of INA is INR inverted. Each of the in┆
0x40400…40500 (64, 0, 4) Sector 4005ff00067541 ┆@ uAterrupting I/O modules compares each of the eight bits returning from INA with the bit it is transmitting to INR. If the compare does not match, which means that a module with a higher priority interrupt code is transmitting at the same time, the mo┆
0x40500…40600 (64, 0, 5) Sector 4006ff00067541 ┆@ uAdule disables the transferring of its code to INR until the next 1 MHZ period. In this way the contents of INR will be unique and correspond to the highest priority interrupt transmitted during that period. The module which detects this situation┆
0x40600…40700 (64, 0, 6) Sector 4007ff00067541 ┆@ uA has got its interrupt acknowledge and will stop the interrupt sending. If two modules interrupting at the same time have the same priority, it is the module with the highest address that overrides the other. Figure 5.┆
0x40700…40800 (64, 0, 7) Sector 34082a00067541 ┆4 * uA1.3.1.1-4 The I/O Interrupt System with the MAP module. - The CB is not available to the CPUs but is used by the STI(Host I/F) and MAP modules for information exhange with the connected subsystems (I/O subsystem, TDX subsystem). The cache memory┆
0x40800…40900 (64, 0, 8) Sector 4009ff00067541 ┆@ uA section of a CPU though, has monitoring access to the CB (sec. 5.1.4.1.3). Concerning the mechanical, electrical and timing characteristics the two buses are identical. The buses and their connection in the system are illustrated in fig. 5.1.3.1.┆
0x40900…40a00 (64, 0, 9) Sector 400a0c00067541 ┆@ uA1-1. row, motherboard or individual connectors in the middle row and individual connectors in the lower row. Cables external to the crate assembly (subsystem interface cables) are connected to interface adapter modules in the rear crate. Adapter m┆
0x40a00…40b00 (64, 0, 10) Sector 400bff00067541 ┆@ uA 1 Figure 5.1.3.1.1-1 Connection, Mainbuses in a PU In the Channel unit two transfer buses are available for information exchange between the I/O modules and the PU┆
0x40b00…40c00 (64, 0, 11) Sector 400cff00067541 ┆@ uAs. These two buses are functionally equal and are used as back up for each other in redundant systems. The buses and their connection in the system are shown in figure 5.1.3.1.1-2 below. Figure 5.1.3.1.1-2 Connection, Main ┆
0x40c00…40d00 (64, 0, 12) Sector 400d1400067541 ┆@ uABuses in a CU Figure 5.1.2-2 he Power Supply ............. 110 5.1.4.2 Documentation .................... 110 5.1.4.3 Environment ....┆
0x40d00…40e00 (64, 0, 13) Sector 400eff00067541 ┆@ uA 1 In the following a detailed description of the mechanical and electrical characteristics of the buses are given. The interface specifications for the four buses are the same (The C┆
0x40e00…40f00 (64, 0, 14) Sector 400fff00067541 ┆@ uAR80D Main Bus specifications) except for supply voltages; dualized supply for a CU module and single supply for a PU module. a) Master Timing Two signals [1(A35) and [2(A38) (both generated on the MAP) are available for I/O interrupt timing and┆
0x40f00…41000 (64, 0, 15) Sector 4000ff00067541 ┆@ uA for internal timing in the modules connected to the DMB. The timing signals are shown below in fig. 5.1.3.1-3, [1 being a 1 MHz clock and [2 a 8 MHz clock. [1 is derived from [2. Figure 5.1.3.1.1-3 Timing Signals b) I/O Interrupt S┆
0x41000…41100 (65, 0, 0) Sector 4101e700067541 ┆A g uAarallel addressing and data transfer along with associated handshake signal lines (ref. fig. 5.1.3.1-2). Fig. 5.1.3.1-3 shows how CR80D modules Plugs onto the DMB. Figure 5.1.3.1-1 CR80D Mother Board ................ 152 ┆
0x41100…41200 (65, 0, 1) Sector 4102ff00067541 ┆A uA 1 The DMB in a PU and a CU is terminated in both ends by termination boards to form a set of transmission lines suitable as the communication path between the modules. Within a PU┆
0x41200…41300 (65, 0, 2) Sector 4103ff00067541 ┆A uA each DMB is terminated in each end by a Main Bus Termination module (MBT). This module contains, apart from the passive terminating circuitry, also the inverter circuitry supporting the PU I/O interrupt system (sec. 5.1.3.1.1b). Within a CU each ┆
0x41300…41400 (65, 0, 3) Sector 4104f900067541 ┆A y uADMB is terminated in one end by a MBT, and in the other end by a CIA (sec. 5.1.5.1.1), which apart from the CIA circuitry described contains the passive terminating circuitry and the inverter circuitry supporting the CU I/O interrupt system. ral de┆
0x41400…41500 (65, 0, 4) Sector 41058b00067541 ┆A uA 1 Figure 5.1.3.1-2 5.1.5) Furthermore, other subsystems interfaced from the PU and the CU, if any, are referenced. To provide a mo┆
0x41500…41600 (65, 0, 5) Sector 4106ff00067541 ┆A uA 1 Figure 5.1.3.1-3 D Modules on the DMBs 5.1.3.1.1 Functional Description of the CR80D Main Bus (DMB) In a Processor Unit (PU) two transfer buses are availab┆
0x41600…41700 (65, 0, 6) Sector 4107ff00067541 ┆A uAle for module intercommunication; the Processor Bus (PB) and the Channel Bus (CB). The two buses are from a functional point of view different: - The PB is used by CPU modules for data and instruction communication with memory modules and for set-┆
0x41700…41800 (65, 0, 7) Sector 4008ff00067541 ┆@ uAup, status and control communication with the MAP module. - The CB is not available to the CPUs but is used by the STI(Host I/F) and MAP modules for information exhange with the connected subsystems (I/O subsystem, TDX subsystem). The cache memory┆
0x41800…41900 (65, 0, 8) Sector 4109ff00067541 ┆A uAuit boards) for module interconnections and also edge connectors for front-rear crate interconnections. As an example the front crate back panel is shown on fig. 5.1.2-2. The rear crate has no main buses, but it has a control and power bus in the ┆
0x41900…41a00 (65, 0, 9) Sector 410aff00067541 ┆A uAupper row, motherboard or individual connectors in the middle row and individual connectors in the lower row. Cables external to the crate assembly (subsystem interface cables) are connected to interface adapter modules in the rear crate. Adapter m┆
0x41a00…41b00 (65, 0, 10) Sector 410b6300067541 ┆A c uAodules are connected to modules in the front crate by flat cables as shown in fig. 5.1.2-3. Specifications ........... 97 > S C_* ┆
0x41b00…41c00 (65, 0, 11) Sector 410c8900067541 ┆A uA 1 Figure 5.1.2-1 .1.7.1 The TIA .................. 100 5.1.4.1.7.2 The STI .................. 104 5.1.4.1.7.3 Mechanic┆
0x41c00…41d00 (65, 0, 12) Sector 410d8900067541 ┆A uA 1 Figure 5.1.2-2 he Power Supply ............. 110 5.1.4.2 Documentation .................... 110 5.1.4.3 Environment ....┆
0x41d00…41e00 (65, 0, 13) Sector 410e8900067541 ┆A uA 1 Figure 5.1.2-3 5.1.5.1.1 The CIA Module ............... 114 5.1.5.1.1.1 Mechanical & Electrical Specifica┆
0x41e00…41f00 (65, 0, 14) Sector 410fff00067541 ┆A uA 1 5.1.3 CR80D Buses 5.1.3.1 CR80D Main Buses (DMB) The CR80D Main Buses are: - The Processor Bus (PB) and Channel Bus (CB) in the Processsor Unit (PU). - The I/O Bus A and I/┆
0x41f00…42000 (65, 0, 15) Sector 4100ff00067541 ┆A uAO Bus B in the Channel Unit (CU). Each of the 4 DMB appears physically as a printed circuit (PCB), called a motherboard, equipped with module connectors. The motherboard (fig. 5.1.3.1-1) provides a parallel bus structure with 50 lines used for p┆
0x42000…42100 (66, 0, 0) Sector 4201ff00067541 ┆B uA...... 149 5.1.5.1.4 The Floppy Disk Controller & Adapter ...................... 152 5.1.5.1.4.1 Mechanical & Electrical Specification ............ 152 5.1.5.1.5 The CCA ...................... 152 ┆
0x42100…42200 (66, 0, 1) Sector 4202a300067541 ┆B # uA 5.1.5.1.6 The Power Supply ............. 153 5.1.5.2 Documentation .................... 153 5.1.5.3 Environment ...................... 153 ┆
0x42200…42300 (66, 0, 2) Sector 4203ff00067541 ┆B uA 1 5 SYSTEM BREAK-DOWN This chapter presents a more detailed specification of the major H/W and S/W packages which have been identified in chapter 4. 5.1 CR80D SYSTEM DESIGN ┆
0x42300…42400 (66, 0, 3) Sector 4204ff00067541 ┆B uA 5.1.1 Scope The scope of this document is: - to supply documentation and functional specification of the present CR80D H/W configuration - to define a baseline document for the CR80D H/W configuration This section will provide a general de┆
0x42400…42500 (66, 0, 4) Sector 4205ff00067541 ┆B uAscription of the two main CR80D assemblies - the Processor Unit Assembly (PU) (sec. 5.1.4) - the Channel Unit Assembly (CU) (sec. 5.1.5) Furthermore, other subsystems interfaced from the PU and the CU, if any, are referenced. To provide a mo┆
0x42500…42600 (66, 0, 5) Sector 4206ff00067541 ┆B uAre comprehensive understanding of the CR80D system each of the assemblies are broken down into basic functional elements (i.e. crate, buses and modules) each given a detailed functions/mechanical description. 5.1.2 CR80D Crate Assembly The CR80┆
0x42600…42700 (66, 0, 6) Sector 42079900067541 ┆B uAD modules/elements are mechanical self contained units housed in a standard 19" mechanical frame, the CR80D crate assembly shown on fig. 5.1.2-1. & Construction ............ 35 5.1.4.1.1 Functional Description of the CR80D Contr┆
0x42700…42800 (66, 0, 7) Sector 4108ff00067541 ┆A uA 1 The crate assembly consists of a front crate and a rear crate (interface adapter crate) placed back to back. On the back panels of the two crates are bus motherboards (Printed circ┆
0x42800…42900 (66, 0, 8) Sector 4209ff00067541 ┆B uA...... 43 5.1.4.1.3.2 The CACHE Memory CTRL .... 47 5.1.4.1.3.3 Mechanical & Electrical Specifications ........... 53 5.1.4.1.4 The MAP and Map Interface Adapter (MIA) ........................ 54 ┆
0x42900…42a00 (66, 0, 9) Sector 420aff00067541 ┆B uA 5.1.4.1.4.1 The MAP Module ........... 56 5.1.4.1.4.2 The MIA Module ........... 75 5.1.4.1.4.3 Mechanical & Electrical Specifications ........... 89 5.1.4.1.5 Intentionally Left Blank ..... 93 5┆
0x42a00…42b00 (66, 0, 10) Sector 420b8d00067541 ┆B uA.1.4.1.6 The RAM Module ............... 94 5.1.4.1.6.1 Mechanical & Electrical Specifications ........... 97 > S C_* ┆
0x42b00…42c00 (66, 0, 11) Sector 420cff00067541 ┆B uA 1 5.1.4.1.7 The STI/TIA Modules .......... 98 5.1.4.1.7.1 The TIA .................. 100 5.1.4.1.7.2 The STI .................. 104 5.1.4.1.7.3 Mechanic┆
0x42c00…42d00 (66, 0, 12) Sector 420dff00067541 ┆B uAal & Electrical Specifications ........... 109 5.1.4.1.8 The CCA Module ............... 110 5.1.4.1.9 The Power Supply ............. 110 5.1.4.2 Documentation .................... 110 5.1.4.3 Environment ....┆
0x42d00…42e00 (66, 0, 13) Sector 420eff00067541 ┆B uA.................. 110 5.1.5 I/O Sub-System ....................... 111 5.1.5.1 Design & Construction ............ 113 5.1.5.1.1 The CIA Module ............... 114 5.1.5.1.1.1 Mechanical & Electrical Specifica┆
0x42e00…42f00 (66, 0, 14) Sector 420fff00067541 ┆B uAtions ........... 121 5.1.5.1.2 The Disk CTRL & DCA .......... 122 5.1.5.1.2.1 The Disk CTRL ............ 122 5.1.5.1.2.2 The DCA .................. 135 5.1.5.1.2.3 Mechanical & Electrical Specifications┆
0x42f00…43000 (66, 0, 15) Sector 4200ff00067541 ┆B uA ........... 138 5.1.5.1.3 The LTU & Adapter ............ 141 5.1.5.1.3.1 The LTU .................. 141 5.1.5.1.3.2 The V24/V28(L) Adapter ... 149 5.1.5.1.3.3 Mechanical & Electrical Specification ......┆
0x43000…43100 (67, 0, 0) Sector 4301ff00067641 ┆C vA 1 5.1.5.1.1 The CIA Module The Channel Interface Adapter is the interface between the Data Channel and the dual bus structure of the Channel Unit (fig. 5.1.5.1.1-1). Two versions o┆
0x43100…43200 (67, 0, 1) Sector 4302ff00067641 ┆C vAf the CIA are available, one for interfacing the Data Bus A (CIA-A) and one for interfacing the Data Bus B (CIA-B). The two versions are functionally identical, but the printed circuit board either has an edge connector towards the A-Bus or the B-B┆
0x43200…43300 (67, 0, 2) Sector 43037300067641 ┆C s vAus (figs. 5.1.5.1.1-2 and -3) Fig. 5.1.5.1.1-1 DATA CHANNEL INTERFACES SYSTEM DESIGN SPECIFICATION CAMPS /=6WC*-!/=6)M2&*/=MM, > I!e=6 !Z="(=e*$<kas#r 9x2"<! <6 M8)I:^=~ B#.!#<6 ! <6 M&&:!<~ J#.:!<2.=M2┆
0x43300…43400 (67, 0, 3) Sector 4304b300067641 ┆C 3 vA 1 Fig. 5.1.1.5.1.1-2 The CIA-A Fig. 5.1.5.1.1-3 The CIA-B nt) I/O bus configuration. The system is equipped with three types of I/O c┆
0x43400…43500 (67, 0, 4) Sector 4305ff00067641 ┆C vA 1 The main function of the CIA is to transfer data between the I/O bus and the Data Channel. The CIA is master to the I/O bus but slave to the Data Channel. This means that a trans┆
0x43500…43600 (67, 0, 5) Sector 4306ff00067641 ┆C vAfer is initiated from the Data Channel, which then awaits for the CIA to complete the transfer. Interrupts from the Channel Unit modules are stored in the CIA to be fetched by the Data Channel. The CIA also undertakes several support functions t┆
0x43600…43700 (67, 0, 6) Sector 4307ff00067641 ┆C vAowards the I/O Bus: a) Clock generation b) Power supervision c) Power up reset d) Bus termination The functional blocks of the CIA are shown in fig. 5.1.5.1.1-4. a) Data Transfer The information path of the Data Channel is shared by addr┆
0x43700…43800 (67, 0, 7) Sector 2108a500067641 ┆! % vAesses, data and error messages. Thus a transfer is divided into three phases. This transfer description is mainly a repetition of parts of sec. 5.1.4.1.4.2. :8=F 28=I!#<:"<>R<2> I E*#<& "< DM L<M% :#<F 2#<> I:g= Ro2M/2 Rl2> IC13!?=4~~ B|2> I:A=!┆
0x43800…43900 (67, 0, 8) Sector 4309a100067641 ┆C ! vA 1 Fig. 5.1.5-1 THE I/O SYSTEM INTERFACES /4!e=6 !f=6 !g=6 !h=6 Ml+M;) RE3C#4: 2i=:g=~ JV3C/4!"<6 #6 MB&! =6 !,<6 :]=2'< AMD MB&!,<6 ! ┆
0x43900…43a00 (67, 0, 9) Sector 430aff00067641 ┆C vA 1 5.1.5.1 Design & Construction The design implements an I/O subsystem that has low overhead, fast transfer rates, no overruns, and no interrupts to the system until a logical entit┆
0x43a00…43b00 (67, 0, 10) Sector 430bff00067641 ┆C vAy of work is completed (i.e., no character by character interrupts from the terminals). The design produced an I/O system that is extremely simple. The heart of the CR80D I/O subsystem is the Data Channel. All bulk I/O is done on a direct memory┆
0x43b00…43c00 (67, 0, 11) Sector 430cff00067641 ┆C vA access (DMA) basis. With the block size determined by the individual application. All I/O controllers are buffered to some degree so that all transfers over the I/O channel are at memory speed (2M words/second) and never wait for mechanical motio┆
0x43c00…43d00 (67, 0, 12) Sector 430dff00067641 ┆C vAn since the transfers always come from a buffer in the I/O controller, rather than from the actual I/O device. For setup, control and status between PU and I/O controllers, programmed I/O (direct from CPUs) can be used concurrently with the Data C┆
0x43d00…43e00 (67, 0, 13) Sector 430eff00067641 ┆C vAhannel DMA transfers. Transfer on the Data Channel does not put any load on the program execution, because the transfer concept is implemented in hardware. The memory system priority on the PU Channel bus always permits I/O accesses (in an on-li┆
0x43e00…43f00 (67, 0, 14) Sector 430fff00067641 ┆C vAne, transaction oriented environment, it is rare that a system is not I/O bound). In the following sections a detailed explanation of the basic modules within a CU is given: - CR80D Channel Interface Adapter (CIA) - CR80D Disk Controller - CR8┆
0x43f00…44000 (67, 0, 15) Sector 4300d500067641 ┆C U vA0D Disk Controller Adapter (DCA) - CR80D Line Termination Unit (LTU) - CR80D V24/V28 (L) Adapter - CR80D Power Supply (PSU) - CR80D Floppy disk Controller - CR80D Floppy disk Controller Adapter (SFA) ┆
0x44000…44100 (68, 0, 0) WangDocumentHead {hdr=WangSectHead {next=(68,0, 1), len=0xff, h3=41067641}, f00=»0676A «, f01=»CPS/SDS/001 ISSUE 1 «, f02=»vhn «, f03=»SRA «, f04=»Kapitel 5.1.5 «, f05=20-02-81 12:56, f06=» 3 «, f07=»06 «, f08=» 4030 «, f09=25-03-81 13:09, f10=» «, f11=»00 «, f12=» 2 «, f13=23-03-81 12:16, f14=25-03-81 13:32, f15=»0044A «, f16=» 44 «, f17=» 5 «, f18=»03 «, f19=» 616 «, f20=» 6515 «, f21=» «, f22=» «, f99=920010000110056610a10a80aaca1505000000000000003803c800df}
0x44100…44200 (68, 0, 1) Sector 44022c00067641 ┆D , vA D D C C C C C ! ! ! ! ENTOVERSIGT Dokument nr: Dokumentnavn: Operat]r: Forfatter: Kommentarer: STATISTIK AKTIVITET DATO TID ANV.TID ANSLAG Oprettet / / / ┆
0x44200…44300 (68, 0, 2) Sector 44039d00067641 ┆D vA 1 CPS/SDS/001 SRA/810227 CAMPS SYSTEM DESIGN SPECIFICATION CAMPS /=6WC*-!/=6)M2&*/=MM, > I!e=6 !Z="(=e*$<kas#r 9x2"<! <6 M8)I:^=~ B#.!#<6 ! <6 M&&:!<~ J#.:!<2.=M2┆
0x44300…44400 (68, 0, 3) Sector 4404ff00067641 ┆D vA 1 5.1.5 The I/O Subsystem The I/O subsystem is composed of one Channel Unit (CU) with a dualized (redundant) I/O bus configuration. The system is equipped with three types of I/O c┆
0x44400…44500 (68, 0, 4) Sector 4405ff00067641 ┆D vAontrollers (interfaces between the I/O buses and the I/O devices): - Disk controllers, which via the Disk Controller adapter interfaces the disk drivers to the I/O sub-system. - Floppy disk controller, which via an adapter is connected to a dual┆
0x44500…44600 (68, 0, 5) Sector 4406ff00067641 ┆D vA floppy disk drive. - Line Termination Units (LTU's), which via the V24/V28 adapters are used for driving the heavy communication protocols towards the TARE-, CCIS-, and SCARS system. The I/O subsystem interfaces to (fig. 5.1.5-1): - the Proce┆
0x44600…44700 (68, 0, 6) Sector 4407ff00067641 ┆D vAssor Sub-System through the dualized CIA (sec. 5.1.5.1.1) - Data Channel (sec. 5.1.4.1.5) - MIA (sec. 5.1.4.1.4.2) link. - the Watchdog Processor through the serial configuration control bus and the CCA (sec. 5.1.5.1.4). - the TARE-, CCIS-, and ┆
0x44700…44800 (68, 0, 7) Sector 43084600067641 ┆C F vASCARS-circuits via the V24/V28(L) adapters (sec. 5.1.5.1.3.2). M2&! "(=~~ BW2I! <6 M /M?.I*:="8=IM2&MP'Mc2! m"2< [MI !?=6 : #wI>K!8=>R 2!8=6 #4 E*8=k L<M% :8=F 28=I!#<:"<>R<2> I E*#<& "< DM L<M% :#<F 2#<> I:g= Ro2M/2 Rl2> IC13!?=4~~ B|2> I:A=!┆
0x44800…44900 (68, 0, 8) WangDocumentHead {hdr=WangSectHead {next=(68,0, 9), len=0xff, h3=41067541}, f00=»0675A «, f01=»CPS/SDS/001 ISSUE 1 «, f02=»vhn «, f03=»SRA «, f04=»Kapitel 5 «, f05=20-02-81 12:47, f06=» 3 «, f07=»32 «, f08=» 12367 «, f09=01-05-81 15:10, f10=» «, f11=»07 «, f12=» 57 «, f13=01-05-81 15:27, f14=01-05-81 16:22, f15=»0044A «, f16=»117 «, f17=» 7 «, f18=»26 «, f19=» 1440 «, f20=» 19894 «, f21=» «, f22=» «, f99=310010000110056610a10a80aaca1505000000000000003803db01df}
0x44900…44a00 (68, 0, 9) Sector 440a7500067541 ┆D u uA D D B B B A A A A A A A @ @ @ 4 4 4 3 3 3 3 3 3 3 3 3 2 2 2 2 1 1 1 1 1 1 1 0 0 0 0 0 0 / / / / . . . - Oprett┆
0x44a00…44b00 (68, 0, 10) Sector 440ba500067541 ┆D % uA 1 CPS/SDS/001 SRA/810430 CAMPS SYSTEM DESIGN SPECIFICATION ISSUE 1 CAMPS /=6)M2&*/=MM, > I!e=6 !Z="(=e*$<kas#r 9x2"<! <6 M8)I:^=~ B#.!#<6 ! <6 M&&:!<~ J#.:!<2.=M2┆
0x44b00…44c00 (68, 0, 11) Sector 440cff00067541 ┆D uA 1 1 TABLE OF CONTENTS 5 SUBSYSTEM SPECIFICATION ...................... 3 5.1 CR80D SYSTEM DESIGN ......┆
0x44c00…44d00 (68, 0, 12) Sector 440dff00067541 ┆D uA................ 3 5.1.1 Scope ................................ 3 5.1.2 CR80D Crate Assy. .................... 3 5.1.3 CR80D Buses .......................... 8 5.1.3.1 CR80D Main Buses (DMB) ........... 8 5.1.3.1┆
0x44d00…44e00 (68, 0, 13) Sector 440eff00067541 ┆D uA.1 Functional Description of the CR80D Main Bus (DMB) ......... 11 5.1.3.1.2 Electrical Description of the CR80D Main Bus ............... 22 5.1.3.2 The CR80D Data Channel (DDC)...... 26 5.1.3.2.1 Funct┆
0x44e00…44f00 (68, 0, 14) Sector 440fff00067541 ┆D uAional Description of the DDC .......................... 26 5.1.4 Processor Sub-System (PRS) ........... 33 5.1.4.1 Design & Construction ............ 35 5.1.4.1.1 Functional Description of the CR80D Contr┆
0x44f00…45000 (68, 0, 15) Sector 4208ff00067541 ┆B uAol Bus (DCB) ...... 35 5.1.4.1.2 Electrical Description of the DCB .......................... 42 5.1.4.1.3 Central Processing Unit and CACHE Memory (CPU/CACHE) ..... 43 5.1.4.1.3.1 The CPU ............┆
0x45000…45100 (69, 0, 0) Sector 45019f00067841 ┆E xA 1 FIGURE 5.3.2-3 CHANNEL UNIT ASSEMBLY and external circuits, both in a collocated and a remote configuration. The main difference b┆
0x45100…45200 (69, 0, 1) Sector 4502b800067841 ┆E 8 xA 1 TABLE 5.3.2-4 Data Exchange Channel, Category Characteristics of terminals in collocated configurations are: 1 ┆
0x45200…45300 (69, 0, 2) Sector 4503ff00067841 ┆E xA 1 In the following paragraphs each DEC category is described. Furthermore, monitoring facilities for each category will be indicated. Where applicable the mechanical dimensions of ┆
0x45300…45400 (69, 0, 3) Sector 4504ff00067841 ┆E xAthe involved modules will be referenced to as: - Standard CR80S module, or - Standard CR80D front crate module, or - Standard CR80D rear crate module For further explanation of the CR80S and CR80D mechanics please refer to section 5.5. 5.3.┆
0x45400…45500 (69, 0, 4) Sector 4505ff00067841 ┆E xA2.1 DEC - Category 1 Fig. 5.3.2.1-1 shows the cat. 1 DEC along with facilities to monitor the DEC traffic. The OPTO Transceivers perform the conversion from the V24/V28 circuitry signals to serial opto signals and vice versa. The V24 circuits tr┆
0x45500…45600 (69, 0, 5) Sector 4506ff00067841 ┆E xAansferred via the distribution equipment and the baud rates are as shown in table 5.3.2-4. For explanation of the V24 circuit numbers please refer to Appendix A (subsection 5.3.4). The DEC is formed by one LTUX channel and the associated distribut┆
0x45600…45700 (69, 0, 6) Sector 4507ff00067841 ┆E xAion equipment. The LTUX is a standard CR80S module placed in a TDX crate as shown in fig. 5.3.2-2. The LTUX is capable of handling max. 4 DECs depending on transmission speed and protocols. The V24/V28 MONITOR module shown is not normally mounted.┆
0x45700…45800 (69, 0, 7) Sector 2308ff00067841 ┆# xA But when plugged into the TDX crate for maintenance purposes it enables monitoring of the LTUX V24/V28 signals via Cannon plugs on its front panel. The V24/V28 MONITOR module is a standard CR80S module providing monitoring access to all 4 V24/V28 c┆
0x45800…45900 (69, 0, 8) Sector 4509ff00067841 ┆E xActrical interface specification between a line terminating unit and its associated distribution equipment. This I/F conforms to the CCITT V24/V28 recommendations. To adapt this internal standard interface to the various interface requirements of the┆
0x45900…45a00 (69, 0, 9) Sector 450aff00067841 ┆E xA terminals and external circuits, collocated or remote, three main types of distribution equipment are involved: - Optical link distribution - Low level V24/V28 distribution - Statistical mux/demux distribution 5 categories of DECs are imple┆
0x45a00…45b00 (69, 0, 10) Sector 450bff00067841 ┆E xAmented to satisfy interface and security requirements when connecting terminals and external circuits to CAMPS. These are as shown in fig. 5.3.2-1. The line termination modules are placed within CAMPS in either a TDX CRATE ASSEMBLY shown in fig. 5┆
0x45b00…45c00 (69, 0, 11) Sector 450c4000067841 ┆E @ xA.3.2-2 or a CHANNEL UNIT ASSEMBLY shown in fig. 5.3.2-3. 1 TABLE OF CONTENTS 5.3 DISTRIBUTION, MONITORING & TEST (DM&T) DESIGN ................................┆
0x45c00…45d00 (69, 0, 12) Sector 450dc900067841 ┆E I xA 1 Some of the modules of the Distribution Equipment are also placed in either a TDX crate assembly or a Channel Unit assembly. ............. 209 5.3.2.2 DEC - Category 2 .....┆
0x45d00…45e00 (69, 0, 13) Sector 450ea100067841 ┆E ! xA 1 FIGURE 5.3.1-1 CAMPS H/W CONFIGURATION ................ 217 5.3.3 Test of Distribution Equipment ....... 217 5.3.4 Appendi┆
0x45e00…45f00 (69, 0, 14) Sector 450fa500067841 ┆E % xA 1 FIGURE 5.3.2-1 DATA EXHANGE CHANNEL MATRIX !"<6 !&<6 ! "$<!#<6 ! <6 {M)(sC I! <6 ! "(= <q#p!"<6 !#<6 ! "$<!&<6$`i6 {M)(sM &M7 ┆
0x45f00…46000 (69, 0, 15) Sector 45009d00067841 ┆E xA 1 FIGURE 5.3.2-2 TDX Crate Assembly s section is to explain the design of the DM&T equipment/facilities as implemented in the present ┆
0x46000…46100 (70, 0, 0) Sector 4601ff00067841 ┆F xACAMPS H/W configuration shown in fig. 5.3.1-1. 5.3.2 Distribution & Monitoring Equipment/Facilities The present CAMPS system interfaces to terminals and external circuits, both in a collocated and a remote configuration. The main difference b┆
0x46100…46200 (70, 0, 1) Sector 4602ff00067841 ┆F xAetween a collocated and a remote configuration is that data exchange in the remote configuration involves VF-Modem links carrying encrypted data (crypto/modem link). The types of terminals in collocated configurations are: 1 ┆
0x46200…46300 (70, 0, 2) Sector 4603ff00067841 ┆F xA - Visual Display Unit (VDU) - Medium Speed Teleprinter (MSP) - Low Speed Channel Device (i.e TTY) (LSC) - Optical Character Reader (OCR) - Paper Tape Puncher (PTP) - Paper Tape Reader (PTR) The re┆
0x46300…46400 (70, 0, 3) Sector 4604ff00067841 ┆F xAmote terminal configuration is only applicable to a subset of these namely: - VDU - MSP Furthermore, the remote terminal concept involves a statistical multiplexing/demultiplexing system minimizing the number of crypto/modem links. The types ┆
0x46400…46500 (70, 0, 4) Sector 46053e00067841 ┆F > xAof external circuits in collocated configurations are: ktion annulleret Ukendt kommando JA eller ANNULLER Kun tal Kun mellemrum eller retur Under redigering nu Ukendt dokument Fundet I brug nu Allerede p> systemdiskette ┆
0x46500…46600 (70, 0, 5) Sector 4606ff00067841 ┆F xA 1 - NICS/TARE - SCARS - CCIS The remote external circuits configuration is only applicable to NICS TARE. Terminals and external circuits, collocated or remote, are connected to┆
0x46600…46700 (70, 0, 6) Sector 4607ff00067841 ┆F xA CAMPS via the Distribution Equipment. The path for data exchange between CAMPS and one collocated/remote terminal type or one collocated/remote external circuit type will in the following be referenced to as a Data Exchange Channel (DEC). A DEC c┆
0x46700…46800 (70, 0, 7) Sector 4508ff00067841 ┆E xAontains distribution equipment and a line terminating unit. Two types of line terminating units exist - Line terminating unit of the LTU type (I/O BUS I/F) - Line terminating units of the LTUX type (TDX BUS I/F) Common to all DECs is the ele┆
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0x46900…46a00 (70, 0, 9) Sector 460a1700067841 ┆F xA F F F F E E E E E E E # # # # " " " " DOKUMENTOVERSIGT Dokument nr: Dokumentnavn: Operat]r: Forfatter: Kommentarer: STATISTIK AKTIVITET DATO TID ANV.TID ANSLAG Oprettet / / ┆
0x46a00…46b00 (70, 0, 10) Sector 460ba500067841 ┆F % xA 1 CPS/SDS/001 SRA/810430 CAMPS SYSTEM DESIGN SPECIFICATION ISSUE 1 CAMPS /=6)M2&*/=MM, > I!e=6 !Z="(=e*$<kas#r 9x2"<! <6 M8)I:^=~ B#.!#<6 ! <6 M&&:!<~ J#.:!<2.=M2┆
0x46b00…46c00 (70, 0, 11) Sector 460cff00067841 ┆F xA 1 1 TABLE OF CONTENTS 5.3 DISTRIBUTION, MONITORING & TEST (DM&T) DESIGN ................................┆
0x46c00…46d00 (70, 0, 12) Sector 460dff00067841 ┆F xA... 201 5.3.1 General .............................. 201 5.3.2 Distribution & Monitoring Equipment/ Facilities ........................... 201 5.3.2.1 DEC - Category 1 ................. 209 5.3.2.2 DEC - Category 2 .....┆
0x46d00…46e00 (70, 0, 13) Sector 460eff00067841 ┆F xA............ 211 5.3.2.3 DEC - Category 3 ................. 213 5.3.2.4 DEC - Category 4 ................. 215 5.3.2.5 DEC - Category 5 ................. 217 5.3.3 Test of Distribution Equipment ....... 217 5.3.4 Appendi┆
0x46e00…46f00 (70, 0, 14) Sector 460f2c00067841 ┆F , xAx A ........................... 217 I! "(=6 *(=#"(=6 IM2&! w"2< hMI sM & E 0= u M% :^=~ Bl1{M40sI:^=~ J 1!"<6;!#<6 !&<6 ! "$<! <6 {M;(s! 9"c=! "(= Z=q#p!"<6 !&<6 ! "$<!#<6 ! <6 {M)(sC I! <6 ! "(= <q#p!"<6 !#<6 ! "$<!&<6$`i6 {M)(sM &M7 ┆
0x46f00…47000 (70, 0, 15) Sector 4600ff00067841 ┆F xA 1 5.3 DISTRIBUTION, MONITORING & TEST (DM&T) DESIGN 5.3.1 General The aim of this section is to explain the design of the DM&T equipment/facilities as implemented in the present ┆
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0x47100…47200 (71, 0, 1) Sector 47021b00068041 ┆G A G G , , , , , + + + + + * * * * * * ) ) ) ) ( ( ( ( ( ( DOKUMENTOVERSIGT Dokument nr: Dokumentnavn: Operat]r: Forfatter: Kommentarer: STATISTIK AKTIVITET DATO TID ANV.TID ANSLAG Oprettet / / : : ┆
0x47200…47300 (71, 0, 2) Sector 4703a500068041 ┆G % A 1 CPS/SDS/001 BHB/810430 CAMPS SYSTEM DESIGN SPECIFICATION ISSUE 1 CAMPS /=6)M2&*/=MM, > I!e=6 !Z="(=e*$<kas#r 9x2"<! <6 M8)I:^=~ B#.!#<6 ! <6 M&&:!<~ J#.:!<2.=M2┆
0x47300…47400 (71, 0, 3) Sector 4704ff00068041 ┆G A 1 1 TABLE OF CONTENTS 5.5 RACK AND CABLING ........................... 234 5.5.1 Introduction .............┆
0x47400…47500 (71, 0, 4) Sector 4705ff00068041 ┆G A.............. 234 5.5.2 CR80D, Modules, and Assemblies ......... 238 5.5.2.1 CR80D Processor and Channel Unit ... 238 5.5.2.2 CR80D Watchdog Processor Unit ...... 245 5.5.2.3 Cooling of CR80D Crates ............ 247 5.5.3 CR80S, ┆
0x47500…47600 (71, 0, 5) Sector 4706ff00068041 ┆G AModules, and Assemblies ......... 250 5.5.3.1 CR80S TDX Crate Assembly ........... 250 5.5.3.2 Cooling of CR80S Crates ............ 253 5.5.4 Rack-Mounted Peripherals and Special Assemblies ............................. 255 5.5┆
0x47600…47700 (71, 0, 6) Sector 4707ff00068041 ┆G A.4.1 Disk Drives ........................ 255 5.5.4.2 Dual Floppy Disk Drive Unit ........ 255 5.5.4.3 V24 Monitor Panel .................. 256 5.5.4.4 Main Switch Unit ................... 256 5.5.4.5 V24 Filter Box .................┆
0x47700…47800 (71, 0, 7) Sector 2c08ff00068041 ┆, A... 257 5.5.4.6 Power Line Filters ................. 257 5.5.5 Racks .................................. 259 5.5.5.1 Single Rack Specifications ......... 259 5.5.5.2 3-Bay Rack-Assembly ................ 263 5.5.5.2.1 TEMPEST Shi┆
0x47800…47900 (71, 0, 8) Sector 4709ff00067541 ┆G uAignals The CR80D System is based on serial transmission of the interrupt code from the interrupting I/O module using the lines INA (A32) and INR (A33). The interrupt code consists of 8 bits, of which 2 are priority bits and the remaining 6 bit┆
0x47900…47a00 (71, 0, 9) Sector 470aff00067541 ┆G uAs are the I/O module number. The 8 bits are transmitted within one [1 (1MHZ) cycle each bit synchronized to the [2 (8 MHZ) clock. The interrupt code is transmitted on the INR line (fig 5.1.3.1-4). INR is an open collector line. Thus all the I/O ┆
0x47a00…47b00 (71, 0, 10) Sector 470b9700067541 ┆G uAmodules can transmit on the same line, which means that if one module is transmitting an "L" and another an "H", the line will contain the "L". ry, also the inverter circuitry supporting the PU I/O interrupt system (sec. 5.1.3.1.1b). Within a CU ┆
0x47b00…47c00 (71, 0, 11) Sector 470cff00067541 ┆G uA 1 INA is an open collector line too. It is driven from the Main Bus termination boards (MBT or CIA), one in each end of the Bus. The contents of INA is INR inverted. Each of the in┆
0x47c00…47d00 (71, 0, 12) Sector 470dff00067541 ┆G uAterrupting I/O modules compares each of the eight bits returning from INA with the bit it is transmitting to INR. If the compare does not match, which means that a module with a higher priority interrupt code is transmitting at the same time, the mo┆
0x47d00…47e00 (71, 0, 13) Sector 470eff00067541 ┆G uAdule disables the transferring of its code to INR until the next 1 MHZ period. In this way the contents of INR will be unique and correspond to the highest priority interrupt transmitted during that period. The module which detects this situation┆
0x47e00…47f00 (71, 0, 14) Sector 470fff00067541 ┆G uA has got its interrupt acknowledge and will stop the interrupt sending. If two modules interrupting at the same time have the same priority, it is the module with the highest address that overrides the other. Figure 5.┆
0x47f00…48000 (71, 0, 15) Sector 47002a00067541 ┆G * uA1.3.1.1-4 The I/O Interrupt System with the MAP module. - The CB is not available to the CPUs but is used by the STI(Host I/F) and MAP modules for information exhange with the connected subsystems (I/O subsystem, TDX subsystem). The cache memory┆
0x48000…48100 (72, 0, 0) Sector 4801ff00067541 ┆H uA section of a CPU though, has monitoring access to the CB (sec. 5.1.4.1.3). Concerning the mechanical, electrical and timing characteristics the two buses are identical. The buses and their connection in the system are illustrated in fig. 5.1.3.1.┆
0x48100…48200 (72, 0, 1) Sector 48020c00067541 ┆H uA1-1. row, motherboard or individual connectors in the middle row and individual connectors in the lower row. Cables external to the crate assembly (subsystem interface cables) are connected to interface adapter modules in the rear crate. Adapter m┆
0x48200…48300 (72, 0, 2) Sector 4803ff00067541 ┆H uA 1 Figure 5.1.3.1.1-1 Connection, Mainbuses in a PU In the Channel unit two transfer buses are available for information exchange between the I/O modules and the PU┆
0x48300…48400 (72, 0, 3) Sector 4804ff00067541 ┆H uAs. These two buses are functionally equal and are used as back up for each other in redundant systems. The buses and their connection in the system are shown in figure 5.1.3.1.1-2 below. Figure 5.1.3.1.1-2 Connection, Main ┆
0x48400…48500 (72, 0, 4) Sector 48051400067541 ┆H uABuses in a CU Figure 5.1.2-2 he Power Supply ............. 5.1.4.2 Documentation .................... 5.1.4.3 Environment ....┆
0x48500…48600 (72, 0, 5) Sector 4806ff00067541 ┆H uA 1 In the following a detailed description of the mechanical and electrical characteristics of the buses are given. The interface specifications for the four buses are the same (The C┆
0x48600…48700 (72, 0, 6) Sector 4807ff00067541 ┆H uAR80D Main Bus specifications) except for supply voltages; dualized supply for a CU module and single supply for a PU module. a) Master Timing Two signals [1(A35) and [2(A38) (both generated on the MAP) are available for I/O interrupt timing and┆
0x48700…48800 (72, 0, 7) Sector 4708ff00067541 ┆G uA for internal timing in the modules connected to the DMB. The timing signals are shown below in fig. 5.1.3.1-3, [1 being a 1 MHz clock and [2 a 8 MHz clock. [1 is derived from [2. Figure 5.1.3.1.1-3 Timing Signals b) I/O Interrupt S┆
0x48800…48900 (72, 0, 8) Sector 4809e700067541 ┆H g uAarallel addressing and data transfer along with associated handshake signal lines (ref. fig. 5.1.3.1-2). Fig. 5.1.3.1-3 shows how CR80D modules Plugs onto the DMB. Figure 5.1.3.1-1 CR80D Mother Board ................ ┆
0x48900…48a00 (72, 0, 9) Sector 480aff00067541 ┆H uA 1 The DMB in a PU and a CU is terminated in both ends by termination boards to form a set of transmission lines well suitable as the communication path between the modules. Within┆
0x48a00…48b00 (72, 0, 10) Sector 480bff00067541 ┆H uA a PU each DMB is terminated in each end by a Main Bus Termination module (MBT). This module contains, apart from the passive terminating circuitry, also the inverter circuitry supporting the PU I/O interrupt system (sec. 5.1.3.1.1b). Within a CU ┆
0x48b00…48c00 (72, 0, 11) Sector 480cfe00067541 ┆H ~ uAeach DMB is terminated in one end by a MBT, and in the other end by a CIA (sec. 5.1.5.1.1), which apart from the CIA circuitry described contains the passive terminating circuitry and the inverter circuitry supporting the CU I/O interrupt system. e┆
0x48c00…48d00 (72, 0, 12) Sector 480d8b00067541 ┆H uA 1 Figure 5.1.3.1-2 5.1.5) Furthermore, other subsystems interfaced from the PU and the CU, if any, are referenced. To provide a mo┆
0x48d00…48e00 (72, 0, 13) Sector 480eff00067541 ┆H uA 1 Figure 5.1.3.1-3 D Modules on the DMBs 5.1.3.1.1 Functional Description of the CR80D Main Bus (DMB) In a Processor Unit (PU) two transfer buses are availab┆
0x48e00…48f00 (72, 0, 14) Sector 480fff00067541 ┆H uAle for module intercommunication; the Processor Bus (PB) and the Channel Bus (CB). The two buses are from a functional point of view different: - The PB is used by CPU modules for data and instruction communication with memory modules and for set-┆
0x48f00…49000 (72, 0, 15) Sector 4800ff00067541 ┆H uAup, status and control communication with the MAP module. - The CB is not available to the CPUs but is used by the STI(Host I/F) and MAP modules for information exhange with the connected subsystems (I/O subsystem, TDX subsystem). The cache memory┆
0x49000…49100 (73, 0, 0) Sector 4901ff00067541 ┆I uAuit boards) for module interconnections and also edge connectors for front-rear crate interconnections. As an example the front crate back panel is shown on fig. 5.1.2-2. The rear crate has no main buses, but it has a control and power bus in the ┆
0x49100…49200 (73, 0, 1) Sector 4902ff00067541 ┆I uAupper row, motherboard or individual connectors in the middle row and individual connectors in the lower row. Cables external to the crate assembly (subsystem interface cables) are connected to interface adapter modules in the rear crate. Adapter m┆
0x49200…49300 (73, 0, 2) Sector 49036300067541 ┆I c uAodules are connected to modules in the front crate by flat cables as shown in fig. 5.1.2-3. ecifications ........... 5IC$3I > S C_* ┆
0x49300…49400 (73, 0, 3) Sector 49048900067541 ┆I uA 1 Figure 5.1.2-1 .1.7.1 The TIA .................. 5.1.4.1.7.2 The STI .................. 5.1.4.1.7.3 Mechanic┆
0x49400…49500 (73, 0, 4) Sector 49058900067541 ┆I uA 1 Figure 5.1.2-2 he Power Supply ............. 5.1.4.2 Documentation .................... 5.1.4.3 Environment ....┆
0x49500…49600 (73, 0, 5) Sector 49068900067541 ┆I uA 1 Figure 5.1.2-3 5.1.5.1.1 The CIA Module ............... 5.1.5.1.1.1 Mechanical & Electrical Specifica┆
0x49600…49700 (73, 0, 6) Sector 4907ff00067541 ┆I uA 1 5.1.3 CR80D Buses 5.1.3.1 CR80D Main Buses (DMB) The CR80D Main Buses are: - The Processor Bus (PB) and Channel Bus (CB) in the Processsor Unit (PU). - The I/O Bus A and I/┆
0x49700…49800 (73, 0, 7) Sector 4808ff00067541 ┆H uAO Bus B in the Channel Unit (CU). Each of the 4 DMB appears physically as a printed circuit (PCB), called a motherboard, equipped with module connectors. The motherboard (fig. 5.1.3.1-1) provides a parallel bus structure with 50 lines used for p┆
0x49800…49900 (73, 0, 8) Sector 4909ff00067541 ┆I uA...... 5.1.5.1.4 The Floppy Disk Controller & Adapter ...................... 5.1.5.1.4.1 Mechanical & Electrical Specification ............ 5.1.5.1.5 The CCA ...................... ┆
0x49900…49a00 (73, 0, 9) Sector 490aa300067541 ┆I # uA 5.1.5.1.6 The Power Supply ............. 5.1.5.2 Documentation .................... 5.1.5.3 Environment ...................... ┆
0x49a00…49b00 (73, 0, 10) Sector 490bff00067541 ┆I uA 1 5 SYSTEM BREAK-DOWN This chapter presents a more detailed specification of the major H/W and S/W packages which have been identified in chapter 4. 5.1 CR80D SYSTEM DESIGN ┆
0x49b00…49c00 (73, 0, 11) Sector 490cff00067541 ┆I uA 5.1.1 Scope The scope of this document is: - to supply documentation and functional specification of the present CR80D H/W configuration - to define a baseline document for the CR80D H/W configuration This section will provide a general de┆
0x49c00…49d00 (73, 0, 12) Sector 490dff00067541 ┆I uAscription of the two main CR80D assemblies - the Processor Unit Assembly (PU) (sec. 5.1.4) - the Channel Unit Assembly (CU) (sec. 5.1.5) Furthermore, other subsystems interfaced from the PU and the CU, if any, are referenced. To provide a mo┆
0x49d00…49e00 (73, 0, 13) Sector 490eff00067541 ┆I uAre comprehensive understanding of the CR80D system each of the assemblies are broken down into basic functional elements (i.e. crate, buses and modules) each given a detailed functions/mechanical description. 5.1.2 CR80D Crate Assembly The CR80┆
0x49e00…49f00 (73, 0, 14) Sector 490f9900067541 ┆I uAD modules/elements are mechanical self contained units housed in a standard 19" mechanical frame, the CR80D crate assembly shown on fig. 5.1.2-1. & Construction ............ 5.1.4.1.1 Functional Description of the CR80D Contr┆
0x49f00…4a000 (73, 0, 15) Sector 4900ff00067541 ┆I uA 1 The crate assembly consists of a front crate and a rear crate (interface adapter crate) placed back to back. On the back panels of the two crates are bus motherboards (Printed circ┆
0x4a000…4a100 (74, 0, 0) Sector 4a01ff00067541 ┆J uA...... 5.1.4.1.3.2 The CACHE Memory CTRL .... 5.1.4.1.3.3 Mechanical & Electrical Specifications ........... 5.1.4.1.4 The MAP and Map Interface Adapter (MIA) ........................ ┆
0x4a100…4a200 (74, 0, 1) Sector 4a02ff00067541 ┆J uA 5.1.4.1.4.1 The MAP Module ........... 5.1.4.1.4.2 The MIA Module ........... 5.1.4.1.4.3 Mechanical & Electrical Specifications ........... 5.1.4.1.5 Intentionally Left Blank 5.1.4.1.6 T┆
0x4a200…4a300 (74, 0, 2) Sector 4a038200067541 ┆J uAhe RAM ...................... 5.1.4.1.6.1 Mechanical & Electrical Specifications ........... 5IC$3I > S C_* ┆
0x4a300…4a400 (74, 0, 3) Sector 4a04ff00067541 ┆J uA 1 5.1.4.1.7 The STI/TIA Modules .......... 5.1.4.1.7.1 The TIA .................. 5.1.4.1.7.2 The STI .................. 5.1.4.1.7.3 Mechanic┆
0x4a400…4a500 (74, 0, 4) Sector 4a05ff00067541 ┆J uAal & Electrical Specifications ........... 5.1.4.1.8 The CCA Module ............... 5.1.4.1.9 The Power Supply ............. 5.1.4.2 Documentation .................... 5.1.4.3 Environment ....┆
0x4a500…4a600 (74, 0, 5) Sector 4a06ff00067541 ┆J uA.................. 5.1.5 I/O Sub-System ....................... 5.1.5.1 Design & Construction ............ 5.1.5.1.1 The CIA Module ............... 5.1.5.1.1.1 Mechanical & Electrical Specifica┆
0x4a600…4a700 (74, 0, 6) Sector 4a07ff00067541 ┆J uAtions ........... 5.1.5.1.2 The Disk CTRL & DCA .......... 5.1.5.1.2.1 The Disc CTRL ............ 5.1.5.1.2.2 The DCA .................. 5.1.5.1.2.3 Mechanical & Electrical Specifications┆
0x4a700…4a800 (74, 0, 7) Sector 4908ff00067541 ┆I uA ........... 5.1.5.1.3 The LTU & Adapter ............ 5.1.5.1.3.1 The LTU .................. 5.1.5.1.3.2 The V24/V28(L) Adapter ... 5.1.5.1.3.3 Mechanical & Electrical Specification ......┆
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0x4a900…4aa00 (74, 0, 9) Sector 4a0a6e00067541 ┆J n uA@ J J J I I I I I I H H H H H G G G F F F F F F E E E E E E E D D D D D C C C C B B B B B B B A A A / / Oprettet / / / / ┆
0x4aa00…4ab00 (74, 0, 10) Sector 4a0b9d00067541 ┆J uA 1 CPS/SDS/001 SRA/810227 CAMPS SYSTEM DESIGN SPECIFICATION CAMPS /=6WC*-!/=6)M2&*/=MM, > I!e=6 !Z="(=e*$<kas#r 9x2"<! <6 M8)I:^=~ B#.!#<6 ! <6 M&&:!<~ J#.:!<2.=M2┆
0x4ab00…4ac00 (74, 0, 11) Sector 4a0cff00067541 ┆J uA 1 1 TABLE OF CONTENTS 5 SUBSYSTEM SPECIFICATION ...................... 5.1 CR80D SYSTEM DESIGN ......┆
0x4ac00…4ad00 (74, 0, 12) Sector 4a0dff00067541 ┆J uA................ 5.1.1 Scope ................................ 5.1.2 CR80D Crate Assy. .................... 5.1.3 CR80D Buses .......................... 5.1.3.1 CR80D Main Buses (DMB) ........... 5.1.3.1┆
0x4ad00…4ae00 (74, 0, 13) Sector 4a0eff00067541 ┆J uA.1 Functional Description of the CR80D Main Bus (DMB) ......... 5.1.3.1.2 Electrical Description of the CR80D Main Bus ............... 5.1.3.2 The CR80D Data Channel (DDC)...... 5.1.3.2.1 Funct┆
0x4ae00…4af00 (74, 0, 14) Sector 4a0fff00067541 ┆J uAional Description of the DDC .......................... 5.1.4 Processor Sub-System (PRS) ........... 5.1.4.1 Design & Construction ............ 5.1.4.1.1 Functional Description of the CR80D Contr┆
0x4af00…4b000 (74, 0, 15) Sector 4a00ff00067541 ┆J uAol Bus (DCB) ...... 5.1.4.1.2 Electrical Description of the DCB .......................... 5.1.4.1.3 Central Processing Unit and CACHE Memory (CPU/CACHE) ..... 5.1.4.1.3.1 The CPU ............┆
0x4b000…4b100 (75, 0, 0) Sector 4b01ff00068341 ┆K A 1 2) Message View Transformation between the stored structure of a message and the structure needed by application modules. 3) Security and Access Control Message Mon┆
0x4b100…4b200 (75, 0, 1) Sector 4b02ff00068341 ┆K Aitor is the central point for the CAMPS specific high level security and access control functions. 4) Message Transition Control Tools by which application modules can cooperate in controlling the state and processing flow of messages. ┆
0x4b200…4b300 (75, 0, 2) Sector 4b03ff00068341 ┆K A5) Checkpoint and Recovery 6) SFM Interface Functions Functions for access to items containing messages. 4) Trace Function A system testing tool enabling a trace of CAMPS module activities. 5.8.1.1.2 Package Interfaces a) Interfac┆
0x4b300…4b400 (75, 0, 3) Sector 4b04ff00068341 ┆K Ae to KER CSF makes use of KER facilities to perform its functions. Especially important are the following KER functions: 1) Page Management Used to implement data sharing and protect shared data against illegal access in user mode, when n┆
0x4b400…4b500 (75, 0, 4) Sector 4b057b00068341 ┆K { Aeeded. 2) Process Communication Used to synchronize access to shared data and to implement queuing functions. 1.2 Package Interfaces .......... 5.8.1.1.3 External Interfaces ......... 5.8.1.2 Functions ....................... ┆
0x4b500…4b600 (75, 0, 5) Sector 4b06ff00068341 ┆K A 1 3) Real Time Clock Used to implement timer management. As CSF manages shared, but protected data, it will mostly execute in system mode, invoked by MON calls. b) Interfac┆
0x4b600…4b700 (75, 0, 6) Sector 4b07ff00068341 ┆K Ae to SFM Message Monitor within CSF is the interface mechanism to the Message Management System (MMS) component of SFM. This means that all access from CAMPS application modules to MMS will go through Message Monitor. In addition, CSF makes u┆
0x4b700…4b800 (75, 0, 7) Sector 4a08ff00068341 ┆J Ase of SFM to save all data in case of a CLOSE DOWN. c) Other Interfaces As a support package, CSF is used by all CAMPS packages as shown on the interface charts. The interfaces to KER are not specifically shown on those charts. 5.8.1.1.3 Ex┆
0x4b800…4b900 (75, 0, 8) Sector 4b09ff00068341 ┆K A............ 5.8.1.3 CSF Control ..................... 5.8.1.3.1 Parameter Control ........... 5.8.1.3.2 Initialization .............. 5.8.1.3.3 Error Handling .............. 5.8.1.4 Characteristics ..........┆
0x4b900…4ba00 (75, 0, 9) Sector 4b0aff00068341 ┆K A....... 5.8.1.4.1 Performance ................. 5.8.1.4.2 Availability ................ 5.8.1.4.3 Security .................... 5.8.1.5 Design and Construction ......... 5.8.1.6 Documentation ..................┆
0x4ba00…4bb00 (75, 0, 10) Sector 4b0bf900068341 ┆K y A. 5.8.2 Environment ......................... 5.8.2.1 Standard Hardware, Firmware and Software ........................ 5.8.2.2 External Interfaces ............. 5.8.2.3 Sub-system Interfaces ........... ┆
0x4bb00…4bc00 (75, 0, 11) Sector 4b0cff00068341 ┆K A 1 5.8 CAMPS SYSTEM FUNCTIONS 5.8.1 Summary of Requirements 5.8.1.1 General Description 5.8.1.1.1 Purpose CSF is a package of support functions, which together with KER, IOC┆
0x4bc00…4bd00 (75, 0, 12) Sector 4b0dff00068341 ┆K A, and TMP form the software environment for CAMPS packages. CSF contains four groups of functions: 1) Shared Data Support Tools for synchronizing access to shared variables and for management of shared buffer pools. 2) Audit Collection Supp┆
0x4bd00…4be00 (75, 0, 13) Sector 4b0eff00068341 ┆K Aort Tools for collection of statistics, log, and report records on behalf of the packages handling those auditing data. 3) Monitor Functions a) Timer Monitor supplying various timer facilities. b) Queue Monitor with tools for queuing of m┆
0x4be00…4bf00 (75, 0, 14) Sector 4b0fff00068341 ┆K Aessages and other events between CAMPS modules. c) Message Monitor, which together with SFM package supplies a set of tools for message management and control of message flow. It performs the following tasks: 1) Message Referencing Tool┆
0x4bf00…4c000 (75, 0, 15) Sector 4b005000068341 ┆K P As for referencing messages via queue elements or message identification. ┆
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0x4c100…4c200 (76, 0, 1) Sector 4c022600068341 ┆L & A L L K K K J J J J J J J J J I I I H H H H G G G F F F E E D D D C C C B B A A UMENTOVERSIGT Dokument nr: Dokumentnavn: Operat]r: Forfatter: Kommentarer: STATISTIK AKTIVITET DATO TID ANV.TID ANSLAG Oprettet / / : : ┆
0x4c200…4c300 (76, 0, 2) Sector 4c039d00068341 ┆L A 1 CPS/SDS/001 OKH/810227 CAMPS SYSTEM DESIGN SPECIFICATION CAMPS /=6WC*-!/=6)M2&*/=MM, > I!e=6 !Z="(=e*$<kas#r 9x2"<! <6 M8)I:^=~ B#.!#<6 ! <6 M&&:!<~ J#.:!<2.=M2┆
0x4c300…4c400 (76, 0, 3) Sector 4c04ff00068341 ┆L A 1 1 TABLE OF CONTENTS 5.8 CAMPS System Functions ................ 5.8.1 Summary of Requirements ........┆
0x4c400…4c500 (76, 0, 4) Sector 4c05ff00068341 ┆L A..... 5.8.1.1 General Description ............. 5.8.1.1.1 Purpose ..................... 5.8.1.1.2 Package Interfaces .......... 5.8.1.1.3 External Interfaces ......... 5.8.1.2 Functions ....................... ┆
0x4c500…4c600 (76, 0, 5) Sector 4c06ff00068341 ┆L A 5.8.1.2.1 Shared Data Functions ....... 5.8.1.2.2 Audit Collection Functions .. 5.8.1.2.3 Monitor Functions ........... 5.8.1.2.3.1 Queues .................. 5.8.1.2.3.2 Queue Elements .......... 5.┆
0x4c600…4c700 (76, 0, 6) Sector 4c07ff00068341 ┆L A8.1.2.3.3 Queue Monitor Functions . 5.8.1.2.3.4 Queue Monitor Design Considerations .......... 5.8.1.2.3.5 Message Monitor ......... 5.8.1.2.3.6 Message Monitor Functions 5.8.1.2.3.7 Security and Access┆
0x4c700…4c800 (76, 0, 7) Sector 4b08ff00068341 ┆K A Control ................. 5.8.1.2.3.8 Message Monitor Recovery 5.8.1.2.3.9 Message Monitor Design Considerations .......... 5.8.1.2.3.10 Timer Monitor ......... 5.8.1.2.4 Trace Function ..┆
0x4c800…4c900 (76, 0, 8) Sector aaaaaaaaaaaaaa ┆****************************************************************************************************************************************************************************************************************************************************************┆
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