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CHAPTER 5
Page #
DOCUMENT III TECHNICAL PROPOSAL Apr. 29, 1982
LIST OF CONTENTS Page
5. EQUIPMENT CHARACTERISTICS 3
5.1 Introduction 3
5.2 Network Configuration 3
5.3 System Configuration 5
5.3.1 Network Elements 5
5.3.1.1 Computing Elements 5
5.3.1.2 CR80 General Description 6
5.3.1.2.1 The Processor Units (PU) 8
5.3.1.2.2 The Channel Units (CU) 9
5.3.1.2.3 Bus Structures 11
5.3.1.2.4 Watchdog System 13
5.3.1.2.5 CR80 Modules 15
5.3.1.2.6 Peripheral Equipment 20
5.3.1.2.7 Mechanical Dimensions 21
5.3.1.2.7.1 Rack Dimensions 21
5.3.1.2.7.2 Peripheral Dimensions 22
5.3.1.2.8 Power Consumption 23
5.3.2 H/W Monitor 25
5.3.2.1 Automatic Test Equipment 26
5.3.3 Network elements 27
5.3.3.1 Nodal Switch Processor 28
5.3.3.2 Nodal Control Processor 29
5.3.3.3 Network Management Processor 30
5.3.3.4 Electronic Mail Processor 31
5.3.3.5 Channel Units 32
5.3.4 Network Nodes General 34
5.3.4.1 Node Toronto 34
5.3.4.1.1 Configuration 36
5.3.4.1.2 Equipment List 38
5.3.4.2 Node Montreal 39
5.3.4.2.1 Configuration 40
5.3.4.2.2 Equipment List 42
5.3.4.3 Node Winnipeg 43
5.3.4.3.1 Configuration 44
5.3.4.3.2 Equipment List 46
5.3.5 Electronic Mail Host 47
5.3.5.1 Configuration 48
5.3.5.2 Equipment List 50
5.3.6 Standard Expansion 51
5.3.6.1 Expansion Element Configurations 53
5.3.6.2 Equipment List 54
LIST OF CONTENTS Page
5.4 Electrical Interfaces 57
5.4.1 Host Interfaces 57
5.4.1.1 Univac Interface 57
5.4.1.2 IBM Interface 57
5.4.1.3 Other Host Interfaces 57
5.4.2 Communication Interfaces 58
5.4.2.1 X20 bis, X21 bis, V24 58
5.4.2.2 X21 58
5.4.2.3 X35 60
5.4.3 LIA-S Option 61
5. E̲Q̲U̲I̲P̲M̲E̲N̲T̲ ̲C̲H̲A̲R̲A̲C̲T̲E̲R̲I̲S̲T̲I̲C̲S̲
5.1 I̲n̲t̲r̲o̲d̲u̲c̲t̲i̲o̲n̲
The scope of this chapter is to show how the proposed
network are configured with dedicated CR80 processor
systems.
A description of the flexible CR80 architecture are
given in section 5.3, and at last the configuration
drawings and equipment lists for the different computers
are given.
5.2 N̲e̲t̲w̲o̲r̲k̲ ̲C̲o̲n̲f̲i̲g̲u̲r̲a̲t̲i̲o̲n̲
The proposed network are based on 3 sites, and can
in a modular way be expanded to an unlimited number
of sites.
The sites themselves are computer systems built around
a high speed dualized "site supra net" with a speed
of 16 M bps. which can be expanded up to 256 M bps.
Around the "site supra net" the different CR80 computer
systems are placed, as shown in figure III 5.2.1.
The types of CR80 computer systems which are proposed
to interface to the "site supra net" are:
NSP: Nodal Switch Processor
NCP: Nodal Control Processor
NMH: Network Management Host
EMH: Electronic Mail Host
It is underlined that each of the above mentioned systems
are totally independent computer systems, only connected
to one or more of the others by the "Site Supra Net".
In this way it is seen that expansion with new or existing
functions are simply done by adding new CR80 computer
systems to the existing "Site Supra Net".
PROPOSED NETWORK CONFIGURATION…01…Fig. III.5.2.1
5.3 S̲y̲s̲t̲e̲m̲ ̲C̲o̲n̲f̲i̲g̲u̲r̲a̲t̲i̲o̲n̲
5.3.1 N̲e̲t̲w̲o̲r̲k̲ ̲E̲l̲e̲m̲e̲n̲t̲s̲
Each individual subsystem is described, and on related
figures the subsystem is shown in block diagrams. Furthermore
rach and crate layout is shown.
5.3.1.1 C̲o̲m̲p̲u̲t̲i̲n̲g̲ ̲E̲l̲e̲m̲e̲n̲t̲s̲
The overall proposed computing elements are CR80 system
elements.
5.3.1.2 C̲R̲8̲0̲ ̲G̲e̲n̲e̲r̲a̲l̲ ̲D̲e̲s̲c̲r̲i̲p̲t̲i̲o̲n̲
The Network elements are constructed by means of the
modular fault tolerant CR80 computer system by use
of various standard modules (Printed Circuit Boards)
organized in units which are interconnected by galvanic
isolated transfer bus structured as illustrated below,
and shortly described in the following.
Figure III 5.3.1.2.1
The CR80 system units are housed in 19" Crates (Card
Magazine) for installation in standard 19" Racks as
shown in figure below.
Figure III 5.3.1.2.2
5.3.1.2.1 T̲h̲e̲ ̲P̲r̲o̲c̲e̲s̲s̲o̲r̲ ̲U̲n̲i̲t̲s̲ ̲(̲P̲U̲)̲
The PU is a multiprogrammable multiprocessor (up to
5 central processor Units CPU's) utilizing virtual
memory (16 mega 16 bits words) and demand paging. Messages
are transmitted from one PU to the memory of another
via the Supra Net. As all data transfers via the Supra
Net are approved by both PU's Memory Map, full hardware
protection against unintended interference between
PU's is ensured.
The PU is highly flexible because the selectance of
contained modules can be changed. The modules are interfaced
via a dual bus structure for reduction of bus contention
as shown in figure below.
Figure III 5.3.1.2.1.1
5.3.1.2.2 T̲h̲e̲ ̲C̲h̲a̲n̲n̲e̲l̲ ̲U̲n̲i̲t̲s̲ ̲(̲C̲U̲)̲
contain the CR80 I/O Controller modules for interfacing
towards peripheral equipment, communication lines etc.
The CU has an internal dual transfer bus structure
to ensure that no single failure can stop operation
of more than one I/O Controller as shown in the figure
below.
Figure III 5.3.1.2.2.1
The transfer buses, Data Bus A and Data Bus B, are
connected to two different PU's to ensure continuous
access to the controller modules (CTRL, LTU). The characteristics
of Data Bus A and Data Bus B correspond to the internal
buses of the PU.
The CIA-modules constitute the interface between the
word oriented internal transfer buses and the byte
oriented Data Channels.
The I/O Controller modules are all based on the same
principle for interfacing to the Channel Unit bus structure
and for the external interfaces as illustrated in figure
below.
Figure III 5.3.1.2.2.2
The interface to the CR80 system employs a multiported
RAM memory through which the data are exchanged. The
program for the Controller module CPU is either resident
in PROM chips or is down loaded from the CR80. The
DISK CTRL, TAPE CTRL and PRINTER CTRL modules employ
PROM's while the Line Termination Modules (LTU) used
for interfacing communication lines, terminals etc.
are loaded with programs from the CR80 meaning that
different protocols can be supported without hardware
changes.
The physical interface to the peripherals, communication
lines etc. is an adapter module located at the rear
of the CU Crate. For interfacing to communication lines,
a special adapter module (LIA-S) is available. This
module is able to select a spare LTU module to be used
instead of a failing module. The spare LTU can be back
up for a number of active LTU's (n out of n+l redundancy).
As the internal bus structure is dualized, the power
input is taken from two separate sources to ensure
that a failure in one power source cannot stop the
CU Operation.
5.3.1.2.3 B̲u̲s̲ ̲S̲t̲r̲u̲c̲t̲u̲r̲e̲
A CR80 computing system are organized around several
busses, which are described in this seciton.
A schematic overview showing the interconnection of
the different buses and Units are given in figure III
5.3.1.2.3.1
Figure III 5.3.1.2.3.1…01…CR80 Bus Structure
Internal in a Processing Unit two buses are available
for data transfer, electrically and functionally they
are identically, the only difference are type of module
which are connected to them.
To the Processor Bus, the CPU's and Memory are connected,
and to the Channel Bus, DMA modules and memory are
connected.
A more detailed description of the Processing Units
and the modules used in it are given in section 5.3.1.2.1.
The two buses are located on each motherboard, mounted
in the back of the PU-crate.
Internal in a Channel Unit two buses are used for data
transfer, Data Bus A and Data Bus B, which are identically,
and further use the same signals as the Processor and
Channel Busses. These two busses are located on each
motherboard, mounted in the back of the CU-crates.
The Data Channel is a flat cable bus connecting one
Processing Bus and one Channel Bus (located in the
same PU) with one or more Data Busses (located in one
or more CU's.
This is done by means of the Data Channel interface
modules (MAP-MIA), CIA-A & CIA-B; for detailed information
ref. appendix A & B.
The Supra Bus is used to high speed data transfer between
processing units. The bus itself is a twisted wire
with screen.
The Configuration Control Bus ia used in the Watchdog
Subsystem. The traffic on the configuration control
bus are directives from the Watchdog about switching
of LTU's, and informaton to the Watchdog about the
Crate Power Supply Voltage levels.
5.3.1.2.4 W̲a̲t̲c̲h̲d̲o̲g̲ ̲S̲y̲s̲t̲e̲m̲
The proposed watchdog system, are shown below:
Fig. III.5.3.1.2.4.1
the redundant NCP have to do more than just monitoring
and supervise the other PU's on site, but only the
elements associated with the watchdog function are
shown.
The Watchdog (WD) consist of four parts:
o A normal LTU
o A Watchdog Controller Adapter (WCA)
o A Watchdog Panel Controller (WPC)
o A Watchdog panel
The interconnection is shown below.
Figure III 5.3.1.2.4.2
The Watchdog is used only for local supervision and
control, the network supervision and Control are carried
out by the Network Control Centers (NCC).
5.3.1.2.5 C̲R̲8̲0̲ ̲M̲o̲d̲u̲l̲e̲s̲
The proposed CR80 computers are built with a few standard
modules and some adapters, the modules proposed to
be used in the Air Canada Data Network are given, with
a short list of chararacteristics, on the following
pages:
M̲A̲P̲ ̲C̲R̲8̲0̲2̲0̲M̲/̲0̲0̲0̲P̲C̲/̲0̲0̲
CHARACTERISTICS:
o Extend the CR80 CPU address space to 16 mega words
by logical-to-physical address translation.
o Gives protection of every part of the address space:
Absent indication, read only access, No access,
Full access.
o Microprocessor included for interrupt processing,
DMA, and AV24 handling.
o DMA controller performs move of data buffers within
the total address space-including I/O Modules.
o Data Channel and V24 communications port.
o System control functions included:
Channel- and Processor Bus Arbitration, Clock generation,
250 us Fast Timer, Real time clock, Power failure
detection, Master Clear, PU Disable, Maintenance
Module.
o BIT. A built-in test procedure is initiated upon
power up and a red test LED is extinguished after
app. 10 sec. if it has been carried out successfully.
C̲P̲U̲/̲C̲A̲C̲H̲E̲ ̲C̲R̲8̲0̲0̲3̲M̲/̲x̲x̲x̲x̲x̲/̲x̲x̲
CHARACTERISTICS:
o 16 bit general purpose CPU with interface 1K word
cache memory for use in the CR80 system.
o Internal test facilities, providing extensive online
and off-line test capabilities.
o Can be used in multiprocessor system.
o Operates with and without MAP module.
o Cache memory transparent to software
o A built in test procedure is initiated upon power
up and a red test LED is extinguished after app.
1 sec. if the test has been carried out successfully.
o One mode of instruction is used to implement the
CR80 standard instruction set.
o A second mode of instruction is used to implement
an instruction set well suited for high level languages
like Algol, PASCAL, ADA, etc. This mode also allows
customer defined instructions to be implemented.
R̲A̲M̲ ̲C̲R̲8̲0̲1̲6̲M̲/̲1̲2̲8̲P̲C̲/̲0̲0̲
CHARACTERISTICS:
o 128KW Random Access Memory for the CR80 system.
o Dual ported, for Processor Bus and Channel Bus
Interface.
o Part of the memory can be disabled.
o A maximum of 2.6M access per second.
o 2.54% occupatin due to refresh.
D̲I̲S̲K̲ ̲C̲T̲R̲L̲ ̲C̲R̲8̲0̲4̲4̲M̲/̲=̲4̲1̲A̲B̲/̲x̲x̲
CHARACTERISTICS:
o Disk Controller/Formatter combined with 32K memory
for CR80 system.
o Disk Controller accessible as an I/O module.
o RAM accessible as a normal memory module.
o Interfaces 1-4 disk drives.
o Any combination of drives from CDC's SMD, MMD,
and CMD families is possible.
o The dual channel feature of the disk drives is
supported.
o Main disk operations are:
Seek, Read, Write, Seek and Read, Seek and Write,
Format, Read address field.
o BIT. A built.in test procedure is initiated upon
power up and a red test LED is extinguished after
app. 10 sec. if the test has been carried out successfully.
L̲T̲U̲ ̲C̲R̲8̲0̲6̲6̲M̲/̲x̲x̲x̲A̲B̲/̲x̲x̲
CHARACTERISTICS:
o Standard CR80 I/O module
o Standard CR80 RAM with 16K word memory.
o Dual bus interface for channel bus interface.
o I/O address is setable.
o RAM location is setable.
o Bootloader PROM 2K or 4K selected by strap.
o 1 to 4 V24/V28 communication lines.
S̲T̲I̲ ̲C̲R̲8̲0̲2̲1̲M̲/̲0̲1̲0̲-̲C̲/̲0̲0̲
CHARACTERISTICS:
o Interface from the CR80 computers to the Supra
Net.
o On board 32K byte RAM for descriptors.
o One u-processor for Outgoing data and one U-processor
for ingoing data.
o DMA capability for data transfer to/from CR80 memory
via the channel Bus.
S̲t̲.̲ ̲F̲D̲ ̲C̲T̲R̲L̲ ̲C̲R̲8̲0̲4̲7̲M̲/̲x̲x̲x̲A̲B̲/̲x̲x̲
CHARACTERISTICS:
o Floppy disk controller for the CR80 system.
o Interfaces up to 4 Floppy disk drives.
o Single and 2-sided diskettes.
o IBM 3740 Data Format (single density).
o Dualized bus I/F for high reliable data exchange
in channel units (redundant system)
o Parity check/generation, at each module access.
o The switching between A-Bus and B-Bus I/F is fully
software controlled.
o I/O Interrupt after each operation.
o Internal Buffer RAM contains 64 words (1 sector)
o Obtainable speed app. 1 word/2 usec.
o BIT. A built-in test procedure is initiated upon
power up and a red test LED is extinguished after
app. 10 sec. if it has been carried out successfully.
P̲a̲r̲a̲l̲l̲e̲l̲ ̲C̲T̲R̲L̲,̲ ̲L̲i̲n̲e̲ ̲P̲r̲i̲n̲t̲e̲r̲ ̲A̲p̲p̲l̲.̲ ̲C̲R̲8̲0̲4̲6̲M̲/̲0̲4̲0̲A̲B̲/̲0̲0̲
CHARACTERISTICS:
o Parallel Controller combined with 16K memory.
o Controller accessable as an I/O module.
o RAM accessable as a normal memory module with 16
bits data and 2 bits parity.
o Connection of up to 4 line printers selected from
the Data Products Corporation or Control Data Corporation
series of line printers.
o Dual bus port.
o Memory Transfer Rates:
To/from Main Bus: 2M words/sec.
To line printer: 250K byte/sec.
o BIT. A built.in test procedure is activated on
power up.
U̲N̲I̲V̲A̲C̲ ̲I̲/̲F̲ ̲C̲R̲8̲0̲3̲7̲M̲/̲0̲4̲0̲A̲B̲/̲0̲0̲
CHARACTERISTICS:
o Interface from CR80 to a UNIVAC series 1100 ISI
input/output channel pair, combined with 16K memory.
o Interface controller accessible as an I/O module.
o RAM serves as data buffer and is accessible as
a normal memory module with 16 bits data and 2
bits parity.
o Dual bus ports.
o Data transfer to/from UNIVAC: 1 Mchar/sec. (max).
o BIT. A built-in test procedure is initiated upon
power up and a red test LED is extinguished after
app. 1 sec. if the test has been carried out successfully.
I̲B̲M̲ ̲C̲H̲.̲ ̲I̲/̲F̲ ̲C̲R̲8̲0̲3̲9̲M̲/̲0̲4̲0̲A̲B̲/̲0̲0̲
CHARACTERISTICS:
o Interface from CR80 to an IBM 360/370 Block Multiplexer
channel.
o Interface controller accessible as an I/O Module.
o RAM serves as data buffer and is accessible as
a normal memory module with 16 bits data and 2
parity bits.
o Dual bus parts
o Data transfer to/from IBM channel 200 Kbyte/sec.
o BIT. A built-in test procedure is initiated upon
power up and a RED is estinguished after approximately
10 sec. If the test has been carried out successfully.
5.3.1.2.6 P̲e̲r̲i̲p̲h̲e̲r̲a̲l̲ ̲E̲q̲u̲i̲p̲m̲e̲n̲t̲
Below is listed the proposed peripheral equipment for
each individual system for 1985 requirement.
S̲w̲i̲t̲c̲h̲i̲n̲g̲ ̲N̲o̲d̲e̲s̲
Q̲t̲y̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲D̲e̲s̲c̲r̲i̲p̲t̲i̲o̲n̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲C̲R̲ ̲N̲o̲.̲
1 80 + 2 Mb Disc CR8302-1080
N̲e̲t̲w̲o̲r̲k̲ ̲M̲a̲n̲a̲g̲e̲m̲e̲n̲t̲ ̲H̲o̲s̲t̲
Q̲t̲y̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲D̲e̲s̲c̲r̲i̲p̲t̲i̲o̲n̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲C̲R̲ ̲N̲o̲.̲
3 VDU CR8350-1005
1 Band Printer B600 CR8331-1600
1 SMD Disc 300Mb CR8300-1300
2 MMD Disc 80 + 2 Mb CR8202-1080
1 Tape Deck CR8320-1001
E̲l̲e̲c̲t̲r̲o̲n̲i̲c̲ ̲M̲a̲i̲l̲ ̲H̲o̲s̲t̲
Q̲t̲y̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲D̲e̲s̲c̲r̲i̲p̲t̲i̲o̲n̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲C̲R̲ ̲N̲o̲.̲
1 Printer TI 820 CR8391-1820
5 VDU CR8350-1005
1 Matrix Printer CR8333-1064
(80 cps)
1 Disc SMD 300 Mb CR8300-1300
2 Disc MMD 80 + 2 Mb CR8202-1080
1 Tape Deck CR8320-1001
N̲e̲t̲w̲o̲r̲k̲ ̲C̲o̲n̲t̲r̲o̲l̲ ̲C̲e̲n̲t̲e̲r̲
Q̲t̲y̲ D̲e̲s̲c̲r̲i̲p̲t̲i̲o̲n̲ C̲R̲ ̲N̲o̲.̲
1 Printer Ti 820 CR8391-1820
1 VDU CR8350-1005
** 4 Coulor Terminal
1 Matrix Printer CR8333-1064
(80 cps)
* 2 Disc MMD 80 + 2 Mb CR8202-1080
* Shared with the switching nodes.
** The Coulor Terminal is not to be found
in our CR80 handbook but its data are
given below:
Physical Dimensions: H x W x D =
0,44 x 0,49 x
0,57
Weight: 42,5 kg
Display: 19…0e…"…0f…
Colour: Eight foreground
and eight background
colours
5.3.1.2.7 M̲e̲c̲h̲a̲n̲i̲c̲a̲l̲ ̲D̲i̲m̲e̲n̲s̲i̲o̲n̲s̲
5.3.1.2.7.1 R̲a̲c̲k̲ ̲D̲i̲m̲e̲n̲s̲i̲o̲n̲s̲
All CR80 hardware modules are placed in
19" non-corrosive metal frames with a
height of 10 U (445 mm) and a weight of
26 kg. These crates are again inserted
into racks in this way it is possible
to built up large computer systems in
a very modular way.
If necessary more racks can be assembled
side by side in a unlimited number to
form a large subsystem by using a mech.
kit.
In the Air Canada proposal this flexibility
have been of great value because of the
many subsystems of different size and
because of the expansion requirements.
Each rack is useful in 36 U (1602 mm)
and in 19" width. The overall dimensions
of each rack is shown below:
o Height: 1,8 m
o Width : 0,6 m
o Depth : 1,05
m
The overall rack dimensions for each individual
proposed subsystem is listed below:
Description Dimensions (HxWxD)
(m)
Node: 1,8 x 3,00 x
1,05
Electronic Mail Host: 1,8 x 2,4 x
1,05
Network Management Host: 1,8 x 1,8 x
1,05
Network Control Center: 1,8 x 1,2 x
1,05
5.3.1.2.7.2 P̲e̲r̲i̲p̲h̲e̲r̲a̲l̲ ̲D̲i̲m̲e̲n̲s̲i̲o̲n̲s̲
All peripheral except from MMD disc drives and
Tape Deck are placed outside the rack.
Below are listed dimentions of all proposed peripheral
equipment:
Description Dimensions (HxWxD)
(m)
Disc Drive SMD 0,86 x 0,48 x 0,86
Line Printer (ex.pedestal) 0,38 x 0,77 x 0,64
Operators Console 0,18 x 0,57 x 0,40
VDU 0,33 x 0,43 x 0,41
Matrix Printer 0,20 x 0,65 x 0,58
5.3.1.2.8 P̲o̲w̲e̲r̲ ̲C̲o̲n̲s̲u̲m̲p̲t̲i̲o̲n̲
Below is listed the power consumption of each individual
subsystem including terminals and peripherals in each
individual geographic area.
Power consumption of each piece of equipment proposed
can be found in table III 5.3.1.7.4.
S̲i̲t̲e̲ ̲T̲o̲r̲o̲n̲t̲o̲:̲
Node 6,0 KW
Electronic Mail Host 5,8 "
Network Control Center 5,8 "
Network Management Host 4,2 "
Total Power Consumption ̲2̲1̲,̲8̲ ̲K̲W̲ ̲
S̲i̲t̲e̲ ̲M̲o̲n̲t̲r̲e̲a̲l̲:̲
Node 6,0 KW
Network Control Center 5,5 "
Total Power Consumption ̲1̲1̲,̲5̲ ̲K̲W̲
S̲i̲t̲e̲ ̲W̲i̲n̲n̲i̲p̲e̲g̲:̲
Node 6,0 KW
Network Control Center ̲ ̲4̲,̲2̲ ̲ ̲"̲
Total Power Consumption ̲1̲0̲,̲2̲ ̲K̲W̲ ̲
T̲a̲b̲l̲e̲ ̲5̲.̲3̲.̲1̲.̲8̲.̲1̲ ̲ ̲E̲Q̲U̲I̲P̲M̲E̲N̲T̲ ̲P̲O̲W̲E̲R̲ ̲C̲O̲N̲S̲U̲M̲P̲T̲I̲O̲N̲
Description Type No. Power Consumption (W)
STI CR8021M 38
128K RAM CR8016M 31
CPU CACHE CR8003M 90
MAP CR8020M 65
MIA CR8071M 21
CCA CR8089M 20
CIA CR8081M 15
SBA CR8072M 17
DISC CTRL CR8044M 37
DUAL PAR CTRL CR8046M 37
LTU CR8066M 25
WPC CR8040M 32
WCA CR8076M 13
DCA CR8084M 6
PCA CR8086M 8
LIA-S CR8083M 3
UNIVAC CTRL CR8037M 39
MBT CR8055M 2
TAPE CTR CR8045M 37
F.D. CTRL CR8047M 18
TCA CR8085M 8
DISC MMD CR8302 400
DISC SMD CR8300 900
F.D. DRIVE CR8308 110
TAPE DECK CR8320 500
LINE PRINTER CR8331 275
VDU CR8350 120
O.P. CONSOLE CR8390 250
FAN UNIT CR8105 150
5.3.2 H̲/̲W̲ ̲M̲o̲n̲i̲t̲o̲r̲
An external H/W monitor is provided as part of the
Watch Dog system.
At the OC connected to the Watch Dog, the following
statistics can be displayed:
o CPU load in every CPU in every PU connected to
the Node.
o Queue status in all PU's connected to the Node.
o Disc Load.
o Number of Disc Accesses
o Traffic Load on each LTU channel connected to the
Node.
o Buffer status in LTU's.
o Protocol statistics from LTU's, retransmission
counters, CRC error counts, etc.
Because of the wide use of micro-processors, the processing
power is distributed throughout the system. This means
that nearly every piece of H/W is able to maintain
statistics about its own load and status, leaving the
H/W-monitors just to fetch and display the information.
CPU Load:
Because of the architecture of the CR80 CPU, a CPU
always has to run a process. Therefore each CPU has
an Idle Process, which it will run, when nothing else
has to be done.
Measuring CPU load is therefore very simple. It is
just a question of measuring the process time, and
dividing the idle process time by the total process
time.
Queue Status:
Each process will maintain queue status, showing whether
it has enough resources
Disc Load/Access:
The file management system will maintain statistics
about number of disc accesses and disc load.
LTU:
All LTU's will maintain statistics on a channel basis,
and the statistics will include the following:
Number of re-transmissions
CRC error count
Traffic load
Buffer status.
5.3.2.1 A̲u̲t̲o̲m̲a̲t̲i̲c̲ ̲T̲e̲s̲t̲ ̲E̲q̲u̲i̲p̲m̲e̲n̲t̲
As an option, automatic equipment to supervise the
RS-232 lines is proposed.
A general description of the proposed equipment is
given in appendix F.
5.3.3 N̲e̲t̲w̲o̲r̲k̲ ̲E̲l̲e̲m̲e̲n̲t̲s̲
The proposed network is built up around five major
network elements:
a. Nodal Switch Processor
b. Nodal Control Processor
c. Network Management Processor
d. Electronic Mail Processor
e. Channel Units
A detailed description of each elements is found in
the sections overleaf.
5.3.3.1 N̲o̲d̲a̲l̲ ̲S̲w̲i̲t̲c̲h̲ ̲P̲r̲o̲c̲e̲s̲s̲o̲r̲
Each Node is equipped with a various number of Nodal
Switch Processors (NSP) and one out of n is dedicated
to be the back up processor. The connection between
each processor is made by help of the site supra bus
which physically is implemented as a coaxial cable.
NODAL SWITCH PROCESSOR…01…FIG.III.5.3.3.1.1
Hardwarewise each nodal switch processor consists of
a CR80 processing Unit (CPU) each equipped with four
CPU Cache and 4 x 128K word RAM in a dual bus configuration.
A PU is shown on the figure below.
PROCESSOR UNIT…01…FIG.III.5.3.3.1.2
5.3.3.2 N̲o̲d̲a̲l̲ ̲C̲o̲n̲t̲r̲o̲l̲ ̲P̲r̲o̲c̲e̲s̲s̲o̲r̲
At each node a dualized Nodal Control Processor resides.
It is what hardware concerns very similar to the switch
processors, it only differs on quantity of modules.
Connections to the nodal switch processors are made
by connections to the site suprabus, while connection
to the electronic mail host is made on the local suprabus.
NODAL CONTROL PROCESSOR…01…FIG. III.5.3.3.2.1
NODAL CONTROL CONFIGURATION…01…FIG. III.5.3.3.2.2
5.3.3.3 N̲e̲t̲w̲o̲r̲k̲ ̲M̲a̲n̲a̲g̲e̲m̲e̲n̲t̲ ̲P̲r̲o̲c̲e̲s̲s̲o̲r̲
Similar to the NCP, network management processor (NMP)
is connected to the site suprabus net, but has no connection
to the backup processor.
Hardwarewise the NMP is very similar to the NCP but
differs in quantity of STI and SBA modules.
The NMP configuration is shown below.
NETWORK MANAGEMENT CONFIGURATION…01…FIG. III. 5.3.3.3.1
5.3.3.4 E̲l̲e̲c̲t̲r̲o̲n̲i̲c̲ ̲M̲a̲i̲l̲ ̲P̲r̲o̲c̲e̲s̲s̲o̲r̲
The electronic mail processor (EMP) is very similar
to the NSP. These can be a number of EMPs which all
are connected to a local supra bus net and with one
EMP dedicated as a backup processor.
ELECTRONIC MAIL PROCESSOR…01…FIG. III. 5.3.3.4.1
All EMP's are exact copies and are implemented by help
of processor Units. The detailed CR80 hardware configuration
is shown below.
ELECTRONIC MAIL CONFIGURATION…01…FIG. III 5.3.3.4.2
5.3.3.5 C̲h̲a̲n̲n̲e̲l̲ ̲U̲n̲i̲t̲s̲
The last network element is the channel unit (CU) which
basically is very different from the previous described
elements.
Channel Units contains all I/O devices such as disc
controllers, line termination units, tape controllers
etc., and therefore vary in size and equipment from
one application to another.
Below is shown a typical CU with all Air Canada applicable
modules.
CHANNEL UNIT CONFIGURATION…01…FIG. III 5.3.3.5.1
Channel Units in NSP configuration are all equipped
with LTU's with quantities depending on the application.
Each NSP channel unit is configured in one of the following
ways:
o 7 Access LTU + 1 Host I/F
o 10 Access LTU + 1 Trunk LTU
o 9 Access LTU + 2 Trunk LTU
All LTU's have four I/O channels. For LTU's used for
access lines, two channels are used, while trunk LTU's
only use one channel.
Channel units used in NCC, NMH and EMH are equipped
with I/O devices in order to control all peripheral
equipment.
5.3.4 N̲e̲t̲w̲o̲r̲k̲ ̲N̲o̲d̲e̲s̲ ̲G̲e̲n̲e̲r̲a̲l̲
Three basically equal nodes are proposed. Although
they vary in size and complexity and each configuration
is shown separately on the pages overleaf. They are
all built around the four network elements. Each node
is equipped with a number of nodal switching processors
and with one processor acting as a back up. They will
at regular time intervals send status information to
the nodal control processor which will take proper
action and close a defective processor if necessary
and at the same time make the back up active via the
watchdog. The closed processor is hereafter completely
isolated and maintenance and diagnostic programs can
be run without interrupting the operational part of
the system. Furthermore, the nodal control processors
themselves are dualized and controlled by the watchdog.
Besides controlling the switching elements the nodal
control processors are dedicated to be network control
centers, which means that besides a geographical back
up each control center has a dualized configuration.
5.3.4.1 N̲o̲d̲e̲ ̲T̲o̲r̲o̲n̲t̲o̲
The Toronto node is the largest of the three nodes.
It consists of four systems:
1. Switching System
2. Control System (NCC)
3. Network Management Host
4. Electronic Mail Host
1. The Switching System is in 1985 configuration proposed
with four processor units (PU), included one for
back up purposes, and six channel units configured
as described in section 5.3.3.5. In figure 5.3.4.1.2.1
the baseline configuration with projected growth
is shown. It is possible to implement the future
growth without interrupting the operational system
by adding more PU's and CU's.
The future growth will be as follows:
Year 56Kbps Access Access IBM GTU PU
CU
RACK
M W lines lines
̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲
̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲
1985 2 3 69 0 - -
-
-
1986 2 4 81 0 7 0 1 1
1987 2 4 89 0 4 1 0 0
1988 2 4 98 0 4 0 0 0
1989 2 5 107 0 6 0 1 1
1990 2 5 118 0 5 0 0 0
1991 2 6 130 0 7 1 1 1
2. The Nodal Control processors are identical for
all three sites and implemented with two PU's,
with one dedicated as back up, a watchdog and a
CU.
The watchdog is equipped with two operator consoles,
a printer and a VDU for operator interference and
error printouts.
Four graphical coulor displays, two MMD 80Mb discs
and a line printer are connected to the channel
unit, besides a number of LTU's which serves as
interface for the maintenance and diagnostic bus.
3. The Network Management Host is a singular stand-alone
computer with two CU's connected to the PU. It
is equipped with two 80Mb discs and one 300Mb SMD
disc besides a tape deck and a fast 600 lpm band
printer.
4. The last system connected to the Toronto node is
the Electronic Mail Host which is a dualized stand-alone
computer with its own watchdog system. It is connected
to the switching processor via a local suprabus
net.
5.3.4.1.1 C̲o̲n̲f̲i̲g̲u̲r̲a̲t̲i̲o̲n̲
TEGNING
TEGNING
5.3.4.1.2 E̲q̲u̲i̲p̲m̲e̲n̲t̲ ̲L̲i̲s̲t̲
5.3.4.2 N̲o̲d̲e̲ ̲M̲o̲n̲t̲r̲e̲a̲l̲
The Montreal Node has two major systems:
1. Switching System
2. Control System
1. The Switching System is in 1985 configuration proposed
with 4 PU's and 7 CU's.
The projected growth in H/W is shown in the table
below:
Year 56Kbps Trunk Access IBM LTU PU
CU
RACK
T W lines lines
̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲
̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲
1985 2 3 81 33 - -
-
-
1986 2 4 95 34 7 0 1 1
1987 2 4 104 38 6 0 0 0
1988 2 4 115 42 7 1 1 1
1989 2 5 126 46 8 0 1 0
1990 2 5 139 50 9 0 0 0
1991 2 6 153 55 11 0 1 1
2. The Control System is exact copy of the NCC described
in the Toronto Node section.
5.3.4.2.1 C̲o̲n̲f̲i̲g̲u̲r̲a̲t̲i̲o̲n̲
TEGNING
TEGNING
5.3.4.2.2 E̲q̲u̲i̲p̲m̲e̲n̲t̲ ̲L̲i̲s̲t̲
TEGNING
5.3.4.3 N̲o̲d̲e̲ ̲W̲i̲n̲n̲i̲p̲e̲g̲
The Winnipeg Node is equipped, what network elements
concerns, similar to the Montreal Node but with 4 PU's
and 7 CU's.
The projected growth is shown in the table below:
Year 56Kbps Trunk Access IBM LTU PU
CU
RACK
T W lines lines
̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲
̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲
1985 3 3 58 8 - - - -
1986 4 4 68 9 8 0 1 1
1987 4 4 74 9 3 1 0 0
1988 4 4 82 10 4 0 1 1
1989 5 5 90 11 7 0 0 0
1990 5 5 99 13 6 1 1 1
1991 6 6 109 14 7 0 1 0
5.3.4.3.1 C̲o̲n̲f̲i̲g̲u̲r̲a̲t̲i̲o̲n̲
TEGNING
…02…TEGNING
5.3.4.3.2 E̲q̲u̲i̲p̲m̲e̲n̲t̲ ̲L̲i̲s̲t̲
5.3.5 E̲l̲e̲c̲t̲r̲o̲n̲i̲c̲ ̲M̲a̲i̲l̲ ̲H̲o̲s̲t̲
The Electronic Mail Host is described in the Toronto
Node section and the configuration is shown overleaf.
5.3.5.1 C̲o̲n̲f̲i̲g̲u̲r̲a̲t̲i̲o̲n̲
TEGNING
TEGNING
5.3.5.2 E̲q̲u̲i̲p̲m̲e̲n̲t̲ ̲L̲i̲s̲t̲
5.3.6 S̲t̲a̲n̲d̲a̲r̲d̲ ̲E̲x̲p̲a̲n̲s̲i̲o̲n̲
The expansion from the baseline configuration through
the remaining of this decenial to 1991 will be heavily
dependent on the evolution of the Air Canada network.
It will depend on how traffic evolves and on how allocation
of host computers and concentrator trunk connections
takes place.
The CR80 provides Air Canada with a computer architecture
well suited towards this dynamic environment. It provides
an architecture which enables evolution to take place
in small increments taylored to the needs. Increments
based, as the baseline configuraton, on standard CR80
modules.
Based on the projected expansion of the Air Canada
Data Network represented by
- traffic statistics (Fig. III, 2.3.2.1)
- interaction profile (Fig. III, 2.3.2.2
and the traffic model presented in Appendix D. The
results of this modelling are presented in section
3.5.
To enable a graceful evolution, we propose the use
of the following three basic expansion elements:
o Empty rack with
- mains filter
- power distribution
o Nodal Switch Processor, with
- 4 CPU/CACHEs
- 4 128 K RAM
- MAP/SCM/IO
- STI
- Crate, Power Supply, etc.
o Nodal Channel Unit with
- 11 Line Terminating Units
- Crate, Power Supply, etc.
Based on the above expansion elements the following
projected 86 through 91 expansions will have to take
place
Toronto Montreal Winnipeg
a b c a b c a b c
1985 minor adjustments
1986 1 0 1 1 0 1
1987 0 1 0 0 0 0
1988 0 0 0 1 1 1 as Montreal
1989 1 1 1 0 0 1
1990 0 0 0 0 0 0
1991 1 1 1 1 0 1
Configuration adjustments from the above may be required,
if the future load assignment differs from the projecte.
However, this will only result in re-assignment of
basic expansion elements within the scope of the proposed
architecture.
5.3.6.1 E̲x̲p̲a̲n̲s̲i̲o̲n̲ ̲E̲l̲e̲m̲e̲n̲t̲ ̲C̲o̲n̲f̲i̲g̲u̲r̲a̲t̲i̲o̲n̲s̲
a. E̲m̲p̲t̲y̲ ̲R̲a̲c̲k̲
b. N̲o̲d̲a̲l̲ ̲S̲w̲i̲t̲c̲h̲i̲n̲g̲ ̲P̲r̲o̲c̲e̲s̲s̲o̲r̲
c. N̲o̲d̲a̲l̲ ̲C̲h̲a̲n̲n̲e̲l̲ ̲U̲n̲i̲t̲
5.3.6.2 E̲q̲u̲i̲p̲m̲e̲n̲t̲ ̲L̲i̲s̲t̲
a. E̲m̲p̲t̲y̲ ̲R̲a̲c̲k̲
b. N̲o̲d̲a̲l̲ ̲S̲w̲i̲t̲c̲h̲i̲n̲g̲ ̲P̲r̲o̲c̲e̲s̲s̲o̲r̲
c. N̲o̲d̲a̲l̲ ̲C̲h̲a̲n̲n̲e̲l̲ ̲U̲n̲i̲t̲
5.4 E̲l̲e̲c̲t̲r̲i̲c̲a̲l̲ ̲I̲n̲t̲e̲r̲f̲a̲c̲e̲s̲
This section gives the details regarding the electrical
interfaces (V28, X21, etc.) used in the proposed network.
5.4.1 H̲o̲s̲t̲ ̲I̲n̲t̲e̲r̲f̲a̲c̲e̲
This section gives details regarding the proposed Host
I/F's.
5.4.1.1 U̲N̲I̲V̲A̲C̲ ̲I̲n̲t̲e̲r̲f̲a̲c̲e̲
The UNIVAC I/F CR8037M is, together with the UNIVAC
I/F adapter CR8079M, able to connect a CR80 to the
Univac 1100 ISI channel pair, with a maximum throughput
of 1M char/sec.
The data transfer to/from the UNIVAC computer via the
data buffers is located in the UNIVAC I/F, and the
buffers form a part of the CR80 memory space.
Furthermore, the UNIVAC I/F conforms to the specifications
given in UNIVAC 1110 PROCESSOR I/O Interfaces, SP2025.
5.4.1.2 I̲B̲M̲ ̲I̲/̲F̲
The IBM Channel I/F CR8039M operates, together with
its CR807M adapter, on an IBM 360/370 Block Multiplexer
Channel, with a transfer rate of 200k Bytes/sec. Otherwise
the interface satisfies the specifications given in:
IBM System 360 and System 370 I/C Interface Channel
to Control Unit Original Equipment Manufacturers
Information (GA22-6974-3).
5.4.1.3 O̲t̲h̲e̲r̲ ̲H̲o̲s̲t̲ ̲I̲n̲t̲e̲r̲f̲a̲c̲e̲s̲
AT present, an ICL I/F is available.
The ICL I/F is constructed in the same way as the two
other Host Interfaces, i.e. with internal data buffers
which form a part of the CR80 memory space.
The ICL I/F CR8039 connects up to eight ICL Main Frames
to the CR80 via ICL I/F adapters, with a maximum data
transfer rate of 400K bytes/sec.
5.4.2 C̲o̲m̲m̲u̲n̲i̲c̲a̲t̲i̲o̲n̲ ̲I̲n̲t̲e̲r̲f̲a̲c̲e̲s̲
The communication interfaces for the proposed initial
configurations are located in the Channel Units and
consist of line termination modules (LTUs) and line
interface adapters LIA's as shown in figure 5.4.2 overleaf.
L̲I̲A̲ ̲M̲o̲d̲u̲l̲e̲
Two types are available at present, but only the LIA-N
type is proposed:
LIA-N Non-switching LIA which interfaces up to four
LTU communication ports to the communication
lines.
LIA-S Switching LIA which when controlled from the
CCA can select a spare LTU instead of a failing
one.
5.4.2.1 X̲2̲0̲ ̲b̲i̲s̲,̲ ̲X̲2̲1̲ ̲b̲i̲s̲,̲ ̲V̲2̲4̲
The LTU modules used for these interfaces are identical
with CR8066M/XXAB/XX, and are available at present.
Please refer to Appendix B. The Application S/W is
down loaded from the CR80 processor unit as described
in the software section of this technical proposal.
The LIA used will be the non-switching type (LIA-N).
For LIA characteristics, please refer to "CR80 Minicomputer
Handbook".
5.4.2.2 X̲2̲1̲
The LTU modules used for this interface are indentical
with the former LTU, except for the electrical characteristics
and functions of the interchange circuits which are
changed to comply with X21. Up to two channels are
available for bit rates up to an dincluding 9600 bit/s.
As for the former LTU, the Application S/W will be
down-loaded from the CR80 PU.
The LIA to be used for this interface will be a modified
version of the LIA-N in order to comply with the connector
specifications.
Fig. III 5.4.2.1
5.4.2.3 X̲7̲5̲
The LTU modules used for this interface are identical
to the presently available LTU's except for the line
interface which will be changed to comply with X75.
Only one port will be available which can be operated
at 56000 bit/s.
As fo the existing LTU, the Application S/W will be
down loaded from the CR80 PU.
5.4.3 L̲I̲A̲-̲S̲ ̲O̲p̲t̲i̲o̲n̲
To achieve the high reliability required in advanced
communication systems, different kinds of redundancy
can by used. A unique n our of n+1 redundancy concept
can be used in connection with communication lines.
this method means that the functions of a failed LTU
can be automatically taken over by the spare LTU, electronically
controlled by enabling the appropriate LIA-S.
The resultant RMA model of th n out n+1 LTU/LIA-S concept
is a simple series connection of the n LIA-S common
circuits with slightly increasing values of FPMH and
B dependent of n.
The equations are:
MTTR = 0.5 hour
LAMBDA = n(0.28+(n+1)0.0014)FPMH
B = n(0.14+(n+1)0.0008)10…0e…6…0f…
where n can be a maximum of 16.
This results in the following values:
̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲
̲ ̲ ̲ ̲ ̲ ̲
LTU Model LAMBDA B MTTR RELIABILITY
̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲
̲ ̲ ̲ ̲ ̲ ̲
8+1 spare 2.3 FPMH 0.5 hour 99.99988%
̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲
̲ ̲ ̲ ̲ ̲ ̲
16+1 spare 4.9 FPMH 0.5 hour 99.99975%
̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲
̲ ̲ ̲ ̲ ̲ ̲
N out of N+1 LTU's
Electrical Bock Diagram
Figure 5.4.3.1
The LIA-S is a simple and thus highly reliable element.
In essence, it consists of a multipole single throw
FET switch and a small control circuit. The FET switch
switches all the communication lines connected to an
LTU at the same time. Either the communication lines
are connecte through switch section A of the LIA-S
to the normal LTU I/O circuitry or through switch section
B to the spare LTU I/O circuitry.
