OctetView
0x00000…00100 (0, 0, 0) Sector 01754130313735 ┆ uA0175A ┆
0x00100…00200 (0, 0, 1) Sector 00000000000000 ┆ ┆
0x00200…00300 (0, 0, 2) Sector ff0080ffffffff ┆ ` x ┆
0x00300…00306 (0, 0, 3) WangDocument {d00=0x21, d01=0x92, d02=0x41, ptr=(22,0, 8), d05=0x00}
0x00306…0030c WangDocument {d00=0x21, d01=0x98, d02=0x41, ptr=(41,0, 0), d05=0x00}
0x0030c…00312 WangDocument {d00=0x22, d01=0x01, d02=0x41, ptr=(63,0, 8), d05=0x00}
0x00312…00320 22 01 41 46 00 00 00 00 00 00 00 00 00 00 ┆" AF ┆
0x00320…00340 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ┆ ┆
[…0x5…]
0x003e0…00400 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 12 ┆ ┆
0x00400…00500 (0, 0, 4) Sector 00000000000000 ┆ ┆
0x00500…00600 (0, 0, 5) Sector 01754130313735 ┆ uA0175A ┆
0x00600…00700 (0, 0, 6) Sector 421c402600415b ┆B @& A[' / X% % PO P ; ! A C f x f V W O : 2198A f < {C < { ; ` i I 2192A2198A ┆
0x00700…00800 (0, 0, 7) Sector 00000000000000 ┆ ┆
[…0x8…]
0x01000…01100 (1, 0, 0) WangDocumentBody
0x01100…01200 (1, 0, 1) Sector 01020d00219141 ┆ ! Avely. rmance with the requirements in SRS Reference Comments: TEST WITNESSES TEST QA QAR .1.4.1.9), ref. 3 and ref. ┆
0x01200…01300 (1, 0, 2) Sector 00004a00219141 ┆ J ! A 1 1 TEST STEPS TEST NO.: 5/7 FUNCTION: Verification of H/W Design, Terminal Key Switch. SRS REFERENCE: ┆
0x01300…01400 (1, 0, 3) Sector 00000600219141 ┆ ! A 3.4.5.7 a.5 Case Test Step No. Station Action Expected Results 7.1 N/A Examine ref. 4 Conformance with the requirements 7.2 N/A E┆
0x01400…01500 (1, 0, 4) Sector 00000000000000 ┆ ┆
[…0x3…]
0x01800…01900 (1, 0, 8) WangDocumentBody
[…0x42…]
0x05b00…05c00 (5, 0, 11) Sector 00000000000000 ┆ ┆
[…0x4…]
0x06000…06100 (6, 0, 0) WangDocumentBody
[…0x107…]
0x16800…16900 (22, 0, 8) WangDocumentHead {hdr=WangSectHead {next=(22,0, 9), len=0xff, h3=41219241}, f00=»2192A «, f01=»CPS/TPR/005 «, f02=»SRA «, f03=»SRA «, f04=»M> ikke slettes «, f05=24-05-82 17:21, f06=» 2 «, f07=»44 «, f08=» 4767 «, f09=21-06-82 11:28, f10=» «, f11=»03 «, f12=» 73 «, f13=18-06-82 18:03, f14=04-07-84 09:04, f15=»0175A «, f16=» 75 «, f17=» 5 «, f18=»07 «, f19=» 1008 «, f20=» 7003 «, f21=» «, f22=» «, f99=020063000110052710110290aaca15050000000000000042034901df}
0x16900…16a00 (22, 0, 9) WangDocumentBody
[…0x126…]
0x29000…29100 (41, 0, 0) WangDocumentHead {hdr=WangSectHead {next=(41,0, 1), len=0xff, h3=41219841}, f00=»2198A «, f01=»CPS/TPR/005 «, f02=»SRA «, f03=»SRA «, f04=»M> ikke slettes «, f05=26-05-82 14:02, f06=» «, f07=»29 «, f08=» 1052 «, f09=18-06-82 20:03, f10=» «, f11=»11 «, f12=» 38 «, f13=18-06-82 19:00, f14=04-07-84 09:05, f15=»0175A «, f16=» 70 «, f17=» 1 «, f18=»06 «, f19=» 940 «, f20=» 2054 «, f21=» «, f22=» «, f99=020013000110052710110490aaca15050000000000000042033301df}
0x29100…29200 (41, 0, 1) WangDocumentBody
[…0xb…]
0x29d00…29e00 (41, 0, 13) Sector 290eff00219841 ┆) ! AMount a Disk Pack with the DSMT test software in Disk Drive no. 2, close the lid and push the drive back in rack B. Activate the WRITE PROTECT pushbutton. f) Activate "START" push button on Disk Drive No. 2 and wait until the "READY" indicator sta┆
0x29e00…29f00 (41, 0, 14) Sector 290f8300219841 ┆) ! Ays "ON". g) Insert a scratch Floppy Disk in each of the two drives in the Floppy Disk drive of rack B, and close the lids. 07 06 82 19 43 08 292 07 06 82 19 52 07 06 82 21 25 0175A 70 37 1068 1344 f *J B S _┆
0x29f00…2a000 (41, 0, 15) Sector 2900d600219841 ┆) V ! A 1 3.7.4.2.3 Test Steps The teststeps for testgroup no. 7, testprocedure no. 2 (7/2), is given in the following preceded by a testoverview. LTU No. 1 switch AAEN/AUTO/BAEN is set to┆
0x2a000…2a100 (42, 0, 0) WangDocumentBody
[…0x157…]
0x3f800…3f900 (63, 0, 8) WangDocumentHead {hdr=WangSectHead {next=(63,0, 9), len=0xff, h3=41220141}, f00=»2201A «, f01=»CPS/TPR/005 «, f02=»SRA «, f03=»SRA «, f04=»M> ikke slettes «, f05=27-05-82 09:46, f06=» 2 «, f07=»35 «, f08=» 5509 «, f09=21-06-82 11:28, f10=» «, f11=»00 «, f12=» 2 «, f13=18-06-82 19:01, f14=09-07-82 13:22, f15=»0175A «, f16=» 71 «, f17=» 3 «, f18=»25 «, f19=» 1136 «, f20=» 6908 «, f21=» «, f22=» «, f99=020073000110052710110290aaca15050000000000000042036501df}
0x3f900…3fa00 (63, 0, 9) WangDocumentBody
[…0x6…]
0x40000…40100 (64, 0, 0) Sector 4001ff41220141 ┆@ A" A2201A Redigeringskopi tpr 7/3 SRA SRA M> ikke slettes 27 05 82 09 46 2 35 5509 09 06 82 17 42 40 1115 09 06 82 18 32 10 06 82 09 16 0175A 71 3 15 1164 6624 (0 s f *J B e _┆
0x40100…40200 (64, 0, 1) Sector 40024700220141 ┆@ G " A @ @ ? ? ? ? > > > = = = = < < < < ; ; ; : : : 9 9 9 8 8 8 8 7 7 7 6 6 6 5 5 5 4 4 4 3 3 3 2 2 2 1 1 1 0 0 0 / / / . . . - - - , , , + + + + * * AKTIVITET DATO TID ANV.TID ANSLAG Oprettet / / : : rettet / / : : ┆
0x40200…40300 (64, 0, 2) Sector 40039700220141 ┆@ " A 1 SRA/820609 # REDIGERET TESTPROCEDURE 7/3 CAMPS ~ B%-!/=6WC*-!/=6)M2&*/=MM, > I!e=6 !Z="(=e*$<kas#r 9x2"<! <6 M8)I:^=~ B#.!#<6 ! <6 M&&:!<~ J#.:!<2.=M2┆
0x40300…40400 (64, 0, 3) Sector 4004ff00220141 ┆@ " A 1 3.7.4.3 Test Procedure 3 This testprocedure serves to verify the Watchdog Processor System i.e. the Watchdog Processor Unit (WDP), the Configuration Control Bus Adapter (CCBA), th┆
0x40400…40500 (64, 0, 4) Sector 4005ff00220141 ┆@ " Ae Channel Unit Control Panel (CUCP), the TDX Bus Switching Modules (BSM-Xs) and the Configuration Control Adapters (CCAs). The DSMT configuration under test is given in appendix A. 3.7.4.3.1 Test Set Up One copy of the documents mentioned in se┆
0x40500…40600 (64, 0, 5) Sector 4006ff00220141 ┆@ " Ac 3.7.3 must be present in the testroom. The test is performed via an Operator Console (OC) which is a printer and keyboard with V24/V28 interface, a Medium Speed Printer (MSP) , a TEST VDU#1, a TEST VDU#2, all with OPTO interface and a TEST VDU#┆
0x40600…40700 (64, 0, 6) Sector 4007ff00220141 ┆@ " A3 with V24/V28 interface. The above mentioned testequipment is connected to the DSMT system as follows: 1. Substitute the leftmost OPTO transceiver in the rack C Adapter crate with a V24/V28(L/L) adapter (1 channel), and connect the OC to the V┆
0x40700…40800 (64, 0, 7) Sector 3f08ff00220141 ┆? " A24 connector on the front panel of the adaptor. 2. Connect the MSP to the remaining OPTO transceiver in the Adapter crate in rack C. 3. Remove the cable connected to the V24/V28(L/L) adapter in the adapter crate pos. 18 and substitute the adap┆
0x40800…40900 (64, 0, 8) Sector 40090700220141 ┆@ " A 3.13 OC Enter from the OC: Refer to appendix D CCB(CR) sec. 7.12 98 01 0F 00 0C 00(CR) (Set Master Clear PU#1, Maintenance Mode) 3.14 N/A Depress both CONTROL N/A SHIFT and CLEAR on TEST VDU#1. 3.15 OC Enter from the OC: Refer to ap┆
0x40900…40a00 (64, 0, 9) Sector 400aff00220141 ┆@ " A 1 1 TEST STEPS TEST NO.: 7/3/4 FUNCTION: Watchdog Processor System Test SRS REFERENCE: N/A ┆
0x40a00…40b00 (64, 0, 10) Sector 400bff00220141 ┆@ " A Case Test Step No. Station Action Expected Results 4.12 OC Enter from the OC: Refer to appendix D CCB(CR) sec. 8.11 94 02 0F 00(CR┆
0x40b00…40c00 (64, 0, 11) Sector 400cff00220141 ┆@ " A) 4.13 OC Enter from the OC: Refer to appendix D CCB(CR) sec. 8.12 98 02 0F 00 0C 00(CR) (Set Master Clear PU#2, Maintenance Mode) 4.14 N/A Depress both CONTROL N/A SHIFT and CLEAR on TEST VDU#2. 4.15 OC Enter from the OC: Refer to ap┆
0x40c00…40d00 (64, 0, 12) Sector 400dff00220141 ┆@ " Apendix D CCB(CR) sec. 8.13 98 02 0F 00 04 00(CR) (Release Master Clear PU#2, Maintenance Mode) Comments: TEST WITNESSES TEST QA QAR ┆
0x40d00…40e00 (64, 0, 13) Sector 400eff00220141 ┆@ " A 1 1 TEST STEPS TEST NO.: 7/3/4 FUNCTION: Watchdog Processor System Test SRS REFERENCE: N/A ┆
0x40e00…40f00 (64, 0, 14) Sector 400fff00220141 ┆@ " A Case Test Step No. Station Action Expected Results 4.16 OC Enter from the OC: Refer to appendix D CCB(CR) sec. 8.14 98 02 0F 00 00┆
0x40f00…41000 (64, 0, 15) Sector 4000ff00220141 ┆@ " A 00(CR) (PU#2 Normal Mode) 4.17 OC Enter from the OC: Refer to appendix D CCB(CR) sec. 8.15 98 02 0F 00 08 00(CR) (Set Master Clear PU#2, Normal Mode) 4.18 N/A Depress both CONTROL N/A SHIFT and CLEAR on TEST VDU#2. 4.19 OC Enter from┆
0x41000…41100 (65, 0, 0) Sector 4101ff00220141 ┆A " A Case Test Step No. Station Action Expected Results 4.1 OC Enter from the OC: Refer to appendix D CCB(CR) sec. 8.1 A4 02 0E(CR) 4.┆
0x41100…41200 (65, 0, 1) Sector 4102ff00220141 ┆A " A2 OC Enter from the OC: Refer to appendix D CCB(CR) sec. 8.2 A4 02 01(CR) 4.3 OC Enter from the OC: Refer to appendix D CCB(CR) sec. 8.3 A4 02 02(CR) 4.4 OC Enter from the OC: Refer to appendix D CCB(CR) sec. 8.4 A4 02 03(CR) 4.5 OC E┆
0x41200…41300 (65, 0, 2) Sector 4103ff00220141 ┆A " Anter from the OC: Refer to appendix D CCB(CR) sec. 8.5 A4 02 0F(CR) 4.6 OC Enter from the OC: Refer to appendix D CCB(CR) sec. 8.6 94 02 0F 00(CR) Comments: ┆
0x41300…41400 (65, 0, 3) Sector 41043b00220141 ┆A ; " A TEST WITNESSES TEST QA QAR the OC: Refer to appendix D CCB(CR) sec. 7.8 98 01 0F 00 01 00(CR) (Disable PU#1) 3.10 OC Enter from the OC: Refer to appendix D CCB(CR) sec. 7.9 94 01 0F 00(CR) 3.11 OC Enter from the ┆
0x41400…41500 (65, 0, 4) Sector 4105ff00220141 ┆A " A 1 1 TEST STEPS TEST NO.: 7/3/4 FUNCTION: Watchdog Processor System Test SRS REFERENCE: N/A ┆
0x41500…41600 (65, 0, 5) Sector 4106ff00220141 ┆A " A Case Test Step No. Station Action Expected Results 4.7 OC Enter from the OC: Refer to appendix D CCB(CR) sec. 8.7 98 02 0F 00 00 0┆
0x41600…41700 (65, 0, 6) Sector 4107ff00220141 ┆A " A0(CR) 4.8 Intentionally deleted 4.9 OC Enter from the OC: Refer to appendix D CCB(CR) sec. 8.8 98 02 0F 00 01 00(CR) (PU#2 disable) 4.10 OC Enter from the OC: Refer to appendix D CCB(CR) sec. 8.9 94 02 0F 00(CR) 4.11 OC Enter from the O┆
0x41700…41800 (65, 0, 7) Sector 4008ff00220141 ┆@ " AC: Refer to appendix D CCB(CR) sec. 8.10 98 02 0F 00 04 00(CR) (PU#2 enable, Maintenance Mode) Comments: TEST WITNESSES TEST QA QAR┆
0x41800…41900 (65, 0, 8) Sector 4109ff00220141 ┆A " A) 3.13 OC Enter from the OC: Refer to appendix D CCB(CR) sec. 7.12 98 01 0F 00 0C 00(CR) (Set Master Clear PU#1, Maintenance Mode) 3.14 N/A Depress both CONTROL N/A SHIFT and CLEAR on TEST VDU#1. 3.15 OC Enter from the OC: Refer to ap┆
0x41900…41a00 (65, 0, 9) Sector 410aff00220141 ┆A " Apendix D CCB(CR) sec. 7.13 98 01 0F 00 04 00(CR) (Release Master Clear PU#1, Maintenance Mode) Comments: TEST WITNESSES TEST QA QAR ┆
0x41a00…41b00 (65, 0, 10) Sector 410bff00220141 ┆A " A 1 1 TEST STEPS TEST NO.: 7/3/3 FUNCTION: Watchdog Processor System Test SRS REFERENCE: N/A ┆
0x41b00…41c00 (65, 0, 11) Sector 410cff00220141 ┆A " A Case Test Step No. Station Action Expected Results 3.16 OC Enter from the OC: Refer to appendix D CCB(CR) sec. 7.14 98 01 0F 00 00┆
0x41c00…41d00 (65, 0, 12) Sector 410dff00220141 ┆A " A 00(CR) (PU#1 Normal Mode) 3.17 OC Enter from the OC: Refer to appendix D CCB(CR) sec. 7.15 98 01 0F 00 08 00(CR) (Set Master Clear PU#1, Normal Mode) 3.18 N/A Depress both CONTROL N/A SHIFT and CLEAR on TEST VDU#1. 3.19 OC Enter from┆
0x41d00…41e00 (65, 0, 13) Sector 410eff00220141 ┆A " A the OC: Refer to appendix D CCB(CR) sec. 7.16 98 01 0F 00 00 00(CR) (Release Master Clear PU#1, Normal Mode) 3.20 N/A Examine TEST VDU#1 Display in accordance Display with appendix D sec. 1.1 ┆
0x41e00…41f00 (65, 0, 14) Sector 410f6900220141 ┆A i " A Comments: TEST WITNESSES TEST QA QAR e OC: Refer to appendix D CCB(CR) sec. 7.3 A4 01 02(CR) 3.4 OC Enter from the OC: Refer to appendix D CCB(CR) sec. 7.4 A4 01 03(CR) 3.5 OC E┆
0x41f00…42000 (65, 0, 15) Sector 4100ff00220141 ┆A " A 1 1 TEST STEPS TEST NO.: 7/3/4 FUNCTION: Watchdog Processor System Test SRS REFERENCE: N/A ┆
0x42000…42100 (66, 0, 0) Sector 42013b00220141 ┆B ; " A TEST WITNESSES TEST QA QAR 1 TEST STEPS TEST NO.: 7/3/1 FUNCTION: Watchdog Processor System Test SRS REFERENCE: N/A ┆
0x42100…42200 (66, 0, 1) Sector 4202ff00220141 ┆B " A 1 1 TEST STEPS TEST NO.: 7/3/3 FUNCTION: Watchdog Processor System Test SRS REFERENCE: N/A ┆
0x42200…42300 (66, 0, 2) Sector 4203ff00220141 ┆B " A Case Test Step No. Station Action Expected Results 3.7 OC Enter from the OC: Refer to appendix D CCB(CR) sec. 7.7 98 01 0F 00 00 0┆
0x42300…42400 (66, 0, 3) Sector 4204ff00220141 ┆B " A0(CR) 3.8 Intentionally deleted 3.9 OC Enter from the OC: Refer to appendix D CCB(CR) sec. 7.8 98 01 0F 00 01 00(CR) (Disable PU#1) 3.10 OC Enter from the OC: Refer to appendix D CCB(CR) sec. 7.9 94 01 0F 00(CR) 3.11 OC Enter from the ┆
0x42400…42500 (66, 0, 4) Sector 4205ff00220141 ┆B " AOC: Refer to appendix D CCB(CR) sec. 7.10 98 01 0F 00 04 00(CR) (Enable PU#1, Maintenance mode) Comments: TEST WITNESSES TEST QA QA┆
0x42500…42600 (66, 0, 5) Sector 42060800220141 ┆B " AR Case Test Step No. Station Action Expected Results 1.5 OC Enter from the OC: Refer to appendix D PU2(CR) sec. 5.3 10 02 00 00 54┆
0x42600…42700 (66, 0, 6) Sector 4207ff00220141 ┆B " A 1 1 TEST STEPS TEST NO.: 7/3/3 FUNCTION: Watchdog Processor System Test SRS REFERENCE: N/A ┆
0x42700…42800 (66, 0, 7) Sector 4108ff00220141 ┆A " A Case Test Step No. Station Action Expected Results 3.12 OC Enter from the OC: Refer to appendix D CCB(CR) sec. 7.11 94 01 0F 00(CR┆
0x42800…42900 (66, 0, 8) Sector 4209ff00220141 ┆B " A 1 1 TEST STEPS TEST NO.: 7/3/2 FUNCTION: Watchdog Processor System Test SRS REFERENCE: N/A ┆
0x42900…42a00 (66, 0, 9) Sector 420aff00220141 ┆B " A Case Test Step No. Station Action Expected Results 2.1 OC Enter from the OC: Refer to appendix D CCB(CR) sec. 6.1 A4 01 03(CR) 2.┆
0x42a00…42b00 (66, 0, 10) Sector 420bff00220141 ┆B " A2 N/A The EN/DIS switch on N/A the CCBA front panel is set to DIS 2.3 OC Enter from the OC: Refer to appendix D CCB(CR) sec. 6.2 A4 01 03(CR) 2.4 N/A The EN/DIS switch on N/A the CCBA front panel is set to EN ┆
0x42b00…42c00 (66, 0, 11) Sector 420c8600220141 ┆B " A Comments: TEST WITNESSES TEST QA QAR All WDP test N/A 1. WDP V24 interfaces N/A 2. WDP CCBA interface┆
0x42c00…42d00 (66, 0, 12) Sector 420dff00220141 ┆B " A 1 1 TEST STEPS TEST NO.: 7/3/3 FUNCTION: Watchdog Processor System Test SRS REFERENCE: N/A ┆
0x42d00…42e00 (66, 0, 13) Sector 420eff00220141 ┆B " A Case Test Step No. Station Action Expected Results 3.1 OC Enter from the OC: Refer to appendix D CCB(CR) sec. 7.1 A4 01 0E(CR) 3.┆
0x42e00…42f00 (66, 0, 14) Sector 420fff00220141 ┆B " A2 OC Enter from the OC: Refer to appendix D CCB(CR) sec. 7.2 A4 01 01(CR) 3.3 OC Enter from the OC: Refer to appendix D CCB(CR) sec. 7.3 A4 01 02(CR) 3.4 OC Enter from the OC: Refer to appendix D CCB(CR) sec. 7.4 A4 01 03(CR) 3.5 OC E┆
0x42f00…43000 (66, 0, 15) Sector 4200ff00220141 ┆B " Anter from the OC: Refer to appendix D CCB(CR) sec. 7.5 A4 01 0F(CR) 3.6 OC Enter from the OC: Refer to appendix D CCB(CR) sec. 7.6 94 01 0F 00(CR) Comments: ┆
0x43000…43100 (67, 0, 0) Sector 4301ff00220141 ┆C " A 1 1 TEST STEPS TEST NO.: 7/3/1 FUNCTION: Watchdog Processor System Test SRS REFERENCE: N/A ┆
0x43100…43200 (67, 0, 1) Sector 4302ff00220141 ┆C " A Case Test Step No. Station Action Expected Results 1.1 N/A The EN/DIS switch on N/A the CCBA front panel is set to EN 1.2 OC Exam┆
0x43200…43300 (67, 0, 2) Sector 4303ff00220141 ┆C " Aine print out on Refer to appendix D the OC sec 5.1 1.3 N/A Examine TEST VDU#1 and Displays in compli- TEST VDU#2 displays ance with appendix D sec. 1.1 1.4 OC Enter from the OC: Refer to appendix D PU1(CR) sec. 5.2 10 01 00 00 54 45 ┆
0x43300…43400 (67, 0, 3) Sector 4304b000220141 ┆C 0 " A53 54 0D 0A(CR) Comments: TEST WITNESSES TEST QA QAR r crate of each TU is set to "ON". Configuration Control Bus Adapter (CCBA), th┆
0x43400…43500 (67, 0, 4) Sector 4305ff00220141 ┆C " A 1 1 TEST STEPS TEST NO.: 7/3/1 FUNCTION: Watchdog Processor System Test SRS REFERENCE: N/A ┆
0x43500…43600 (67, 0, 5) Sector 4306ff00220141 ┆C " A Case Test Step No. Station Action Expected Results 1.5 OC Enter from the OC: Refer to appendix D PU2(CR) sec. 5.3 10 02 00 00 54┆
0x43600…43700 (67, 0, 6) Sector 4307ff00220141 ┆C " A 45 53 54 0D 0A(CR) 1.6 OC Enter from the OC: Refer to appendix D LPR(CR) sec. 5.4 10 01 00 00 0D 0A MSP print out: 54 45 53 54 0D 0A(CR) (CR)(LF)TEST(CR)(LF) ┆
0x43700…43800 (67, 0, 7) Sector 42085300220141 ┆B S " A Comments: TEST WITNESSES TEST QA QAR emaining Mains Switche is set to "ON". e) Mount a Disk Pack with the DSMT test software in Disk Drive no. 2, close the lid and push the drive back in rack B. Activate the┆
0x43800…43900 (67, 0, 8) Sector 4309ff00220141 ┆C " A WRITE PROTECT pushbutton. f) Activate "START" push button on Disk Drive No. 2 and wait until the "READY" indicator stays "ON". g) Insert a scratch Floppy Disk in each of the two drives in the Floppy Disk drive of rack B, and close the lids. 3┆
0x43900…43a00 (67, 0, 9) Sector 430a9100220141 ┆C " A.7.4.3.3 Test Steps The teststeps for testgroup no. 7, testprocedure no. 3 (7/3), is given in the following preceded by a testoverview. on the CCA module front panel is set away from RESET b) The CCA address switch on the CCA printed circuit┆
0x43a00…43b00 (67, 0, 10) Sector 430bff00220141 ┆C " A 1 1 TEST OVERVIEW TEST NO.: 7/3 FUNCTION: Watchdog Processor Functional Capabilities ┆
0x43b00…43c00 (67, 0, 11) Sector 430cff00220141 ┆C " A Test Case/ Reference Action SRS Reference All WDP test N/A 1. WDP V24 interfaces N/A 2. WDP CCBA interface┆
0x43c00…43d00 (67, 0, 12) Sector 430dab00220141 ┆C + " A N/A 3. PU#1 CCA test N/A 4. PU#2 CCA test N/A 5. CU CCA test N/A 6. TU#1 BSM-X test N/A 7. TU#2 BSM-X test N/A 8. TU#3 BSM-X test N/A 9. TU#4 BSM-X test N/A 2 switch ON/OFF is set to ON c) The CH 3 switch ON/OFF is set to ON d) The ┆
0x43d00…43e00 (67, 0, 13) Sector 430eff00220141 ┆C " A 1 1 TEST OVERVIEW TEST NO.: 7/3 FUNCTION: Watchdog Processor Functional Capabilities ┆
0x43e00…43f00 (67, 0, 14) Sector 430fff00220141 ┆C " A Test Case/ Reference Action SRS Reference 10. TU#5 BSM-X test N/A 11. TU#6 BSM-X test N/A 12. TU#7 BSM┆
0x43f00…44000 (67, 0, 15) Sector 43006000220141 ┆C ` " A-X test N/A 13. TU#8 BSM-X test N/A 14. TU#9 BSM-X test N/A 15. TU#10 BSM-X test N/A witches in Computer racks: 1) Power switch (2) on each Mains switch is set to "OFF". 2) Power switch (2) on the Disk Drive rear panel is set to "ON" 3┆
0x44000…44100 (68, 0, 0) Sector 4401ff00220141 ┆D " A) Power switch (1) on the Floppy Disk Drive rear panel is set to "ON". 4) Power switch (1) on the Watchdog Processor Unit rear panel is set to "ON". 5) Power switch (2) in the rear crate of PU#1 is set to "ON" 6) Power switch (2) in the rea┆
0x44100…44200 (68, 0, 1) Sector 4402ff00220141 ┆D " Ar crate of the CU is set to "ON" 7) Power switch (2) in the rear crate of the PU#2 is set to "ON". 8) Power switch (2) in the rear panel of each 80D fan unit is set to "ON". 9) Power switch (2) in the rear crate of the Adaptor Crate is set ┆
0x44200…44300 (68, 0, 2) Sector 4403ff00220141 ┆D " Ato "ON" 10) Power switch (1) in the rear panel of the 80S Blower Unit is set to "ON" 11) Power switch (1) on each CR80D Power supply (6 front crate mounted modules) is set to "ON". k) Setting of Power Switche in Line Termination racks: 1)┆
0x44300…44400 (68, 0, 3) Sector 4404d300220141 ┆D S " A Power Switch (2) on each Mains Switch is set to "OFF". 2) Power Switch (1) on the rear panel of each 80S Blower Unit is set to "ON". 3) Power Switch (2) in the rear crate of each TU is set to "ON". Configuration Control Bus Adapter (CCBA), th┆
0x44400…44500 (68, 0, 4) Sector 4405ff00220141 ┆D " A 1 4) Power Switch (1) on each CR80S Power Supply (1 in the front crate of each TU) is set to "ON". k) PU#2 cable interchanges Interchange the TIA#1 (rear crate, slot 15) TDX co┆
0x44500…44600 (68, 0, 5) Sector 4406ff00220141 ┆D " Annection and the TIA#2 (rear crate, slot 16) TDX connection. 3.7.4.3.2 Test Initialization The testengineers and testwitnesses are in the testroom and ready to perform and supervise the test. Power Up the DSMT System as follows (Refer to append┆
0x44600…44700 (68, 0, 6) Sector 4407ff00220141 ┆D " Aix A): a) Power Up all connected terminals i.e. VDUs, MSPs, OC, Communication Analyzers, PTP/PTR, as applicable. b) The input Power Switch on the front panel of each Frequency Stabilizer is set to "ON". c) The power switch (2) on Mains switch ┆
0x44700…44800 (68, 0, 7) Sector 4308ff00220141 ┆C " Ano. 1 is set to "ON" wait 15 secs. d) The power switch (2) on each of the remaining Mains Switche is set to "ON". e) Mount a Disk Pack with the DSMT test software in Disk Drive no. 2, close the lid and push the drive back in rack B. Activate the┆
0x44800…44900 (68, 0, 8) Sector 4409a200220141 ┆D " " A4 switch AAEN/AUTO/BAEN is set to AUTO k) The LTU No. 5 switch AAEN/AUTO/BAEN is set to AUTO l) The SD.FD.CTRL switch AAEN/AUTO/BAEN is set to AUTO rate pos. 17 and substitute the adapter with an OPTO transceiver. Connect the TEST VDU#2 to t┆
0x44900…44a00 (68, 0, 9) Sector 440aff00220141 ┆D " A 1 e) Switch settings in CU rear crate modules: 1) a) The RESET switch on the CCA module front panel is set away from RESET b) The CCA address switch on the CCA printed circuit┆
0x44a00…44b00 (68, 0, 10) Sector 440bff00220141 ┆D " A board (PCB) is set to 03 hexadecimal. f) Switch settings in WDP rear crate modules: 1) The EN/DIS switch on the front panel of the CCBA is set to DIS. g) Switch settings in TU modules 1) All BSM-Xs: a) The AUTO/MAN/OFF switch is set t┆
0x44b00…44c00 (68, 0, 11) Sector 440cff00220141 ┆D " Ao AUTO. b) The BUS 1/Bus 2 switch is set to BUS 1. c) The address switch on each BSM-X is set to 1X hexadecimal, where X equals the number of the TU in which the actual BSM-X is situated. E. g. the BSM-X in TU#5 is given the address 15 hexad┆
0x44c00…44d00 (68, 0, 12) Sector 440dff00220141 ┆D " Aecimal. (This should be carried out prior to the test but can be verified at this point). 2) All LTUX-Ss: a) The CH 1 switch ON/OFF is set to ON b) The CH 2 switch ON/OFF is set to ON c) The CH 3 switch ON/OFF is set to ON d) The ┆
0x44d00…44e00 (68, 0, 13) Sector 440eff00220141 ┆D " ACH 4 switch ON/OFF is set to ON h) Switch settings on frequency stabilizer rack: 1) The input power switch on all three stabilizers are set to off. 2) The three rotary switches on the By-Pass panel are all set to the Frequency Stabilizer pos┆
0x44e00…44f00 (68, 0, 14) Sector 440f0d00220141 ┆D " Aition. ) Asynchronous communication 2) 7 bit character length 3) Even parity check/generation 4) 1 stop bit 5) 1200 Baud communication speed b) Switch settings in PU#1 and PU#2 front crate modules: 1) The NRM/MAIN switch on the MAP modu┆
0x44f00…45000 (68, 0, 15) Sector 4400ff00220141 ┆D " A 1 i) Setting of power switches in Computer racks: 1) Power switch (2) on each Mains switch is set to "OFF". 2) Power switch (2) on the Disk Drive rear panel is set to "ON" 3┆
0x45000…45100 (69, 0, 0) Sector 4501ff00220141 ┆E " A 1 3) The host number switch (S1) on the PU#2 STI is set to #01 as follows: S1,4 : CLOSED S1,3 : CLOSED S1,2 : CLOSED S1,1 : OPEN c) Switch settings in PU#1 and PU#2 r┆
0x45100…45200 (69, 0, 1) Sector 4502ff00220141 ┆E " Aear crate modules: 1) The Baudrate select switches 1-4 (S1) on the MAP Interface Adapter (MIA) Printed Circuit Board (PCB) is set to #7 which corresponds to a transmission speed of 1200 Baud: Switch 1: OPEN Switch 2: OPEN Switch 3: O┆
0x45200…45300 (69, 0, 2) Sector 45031f00220141 ┆E " APEN Switch 4: CLOSED SRA/820527 # REDIGERET TESTPROCEDURE 7/3 CAMPS ~ B%-!/=6WC*-!/=6)M2&*/=MM, > I!e=6 !Z="(=e*$<kas#r 9x2"<! <6 M8)I:^=~ B#.!#<6 ! <6 M&&:!<~ J#.:!<2.=M2┆
0x45300…45400 (69, 0, 3) Sector 4504b000220141 ┆E 0 " A 1 FIGURE 3.7.4.3.1-1 Connection of the testequipment Watchdog Processor Unit (WDP), the Configuration Control Bus Adapter (CCBA), th┆
0x45400…45500 (69, 0, 4) Sector 4505ff00220141 ┆E " A 1 2) a) The RESET switch on the Configuration Control Adaptor (CCA) front panel is set away from RESET. b) PU#1: The CCA address switch on the CCA printed circuit board (PCB┆
0x45500…45600 (69, 0, 5) Sector 4506ff00220141 ┆E " A) is set to 01 hexadecimal. PU#2: The CCA address switch on the CCA printed circuit board (PCB) is set to 02 hexadecimal. d) Switch settings in CU front crate modules. 1) Switches on the Channel Unit Control Panel (CUCP) front panel is ┆
0x45600…45700 (69, 0, 6) Sector 4507ff00220141 ┆E " Aset as: a) The CU Bus A Switch DIS/AUTO is set to AUTO b) The CU Bus B switch DIS/AUTO is set to AUTO c) The Disk Ctrl. No. 1 switch AAEN/AUTO/BAEN is set to AUTO d) The Disk Ctrl. No. 2 switch AAEN/AUTO/BAEN is set to AUTO e) Th┆
0x45700…45800 (69, 0, 7) Sector 4408ff00220141 ┆D " Ae Disk Ctrl. No. 3 switch AAEN/AUTO/BAEN is set to AUTO f) The LTU No. 1 switch AAEN/AUTO/BAEN is set to AUTO g) The LTU No. 2 switch AAEN/AUTO/BAEN is set to AUTO h) The LTU No. 3 switch AAEN/AUTO/BAEN is set to AUTO i) The LTU No. ┆
0x45800…45900 (69, 0, 8) Sector 4509ff00220141 ┆E " Ater with an OPTO transceiver. Connect the TEST VDU#1 to this OPTO transceiver. 4. Remove the cable connected to the V24/V28(L/L) adapter in the adapter crate pos. 17 and substitute the adapter with an OPTO transceiver. Connect the TEST VDU#2 to t┆
0x45900…45a00 (69, 0, 9) Sector 450aad00220141 ┆E - " Ahis OPTO transceiver. 5. Disconnect the two V24 cables connected to the J1 and J2 connectors on the leftmost Back Panel 8 located in the rear of the Adapter crate. =*(=N#FMC 2.=M ':>=V V u:A=!>= AH1 R^4 ]M, C 4:>=2A=Ms!:g=~ Jr4Mj2:g=~ B}4C75! ┆
0x45a00…45b00 (69, 0, 10) Sector 450bff00220141 ┆E " A 1 6. Disconnect the V24 cable connected to the MIA in PU#1 and connect TESTCABLE#1 between above mentioned (para. 5) J1 and the MIA. 7. Disconnect the V24 cable connected to the ┆
0x45b00…45c00 (69, 0, 11) Sector 450cff00220141 ┆E " AMIA in PU#2 and connect TESTCABLE#2 between above mentioned (para. 5) J2 and the MIA. 8. Disconnect the two V24 cables connected to J1 and J2 respectively on the WCA front panel in the rear crate of the WDP. 9. Connect TESTCABLE#3 between the ┆
0x45c00…45d00 (69, 0, 12) Sector 450dff00220141 ┆E " Aabove mentioned (para. 8) J1 and J2. The testequipment is now connected to the DSMT system as shown in fig. 3.7.4.3.1-1. Carry out/control the following: a) OC, TEST VDU#1, TEST VDU#2, TEST VDU#3 and MSP set up: The communication part of th┆
0x45d00…45e00 (69, 0, 13) Sector 450eff00220141 ┆E " Ae OC and MSP is set to: 1) Asynchronous communication 2) 7 bit character length 3) Even parity check/generation 4) 1 stop bit 5) 2400 Baud communication speed The communication part of the TEST VDU#1, TEST VDU#2 and TEST VDU#3 is set t┆
0x45e00…45f00 (69, 0, 14) Sector 450fff00220141 ┆E " Ao: 1) Asynchronous communication 2) 7 bit character length 3) Even parity check/generation 4) 1 stop bit 5) 1200 Baud communication speed b) Switch settings in PU#1 and PU#2 front crate modules: 1) The NRM/MAIN switch on the MAP modu┆
0x45f00…46000 (69, 0, 15) Sector 45006800220141 ┆E h " Ale front panel is set to NRM. 2) The EN/DIS switch on the MAP module front panel is set to EN. ┆
0x46000…46100 (70, 0, 0) WangDocumentHead {hdr=WangSectHead {next=(70,0, 1), len=0xff, h3=41220141}, f00=»2201A «, f01=»Redigeringskopi tpr 7/3 «, f02=»SRA «, f03=»SRA «, f04=»M> ikke slettes «, f05=27-05-82 09:46, f06=» 2 «, f07=»35 «, f08=» 5509 «, f09= - - : , f10=» «, f11=» «, f12=» «, f13=27-05-82 12:29, f14=27-05-82 13:30, f15=»0175A «, f16=» 71 «, f17=» 2 «, f18=»35 «, f19=» 1252 «, f20=» 5509 «, f21=» «, f22=» «, f99=020010000110056610110280aaca15050000000000000042036401df}
0x46100…46200 (70, 0, 1) Sector 46024700220141 ┆F G " A F F E E E E D D D C C C C B B B B A A A @ @ @ @ ? ? ? > > > = = = < < < ; ; ; : : : 9 9 9 8 8 8 7 7 7 6 6 6 5 5 5 4 4 4 3 3 3 3 2 2 2 1 1 1 0 0 AKTIVITET DATO TID ANV.TID ANSLAG Oprettet / / : : rettet / / : : ┆
0x46200…46300 (70, 0, 2) Sector 46039700220141 ┆F " A 1 SRA/820527 # REDIGERET TESTPROCEDURE 7/3 CAMPS ~ B%-!/=6WC*-!/=6)M2&*/=MM, > I!e=6 !Z="(=e*$<kas#r 9x2"<! <6 M8)I:^=~ B#.!#<6 ! <6 M&&:!<~ J#.:!<2.=M2┆
0x46300…46400 (70, 0, 3) Sector 4604ff00220141 ┆F " A 1 3.7.4.3 Test Procedure 3 This testprocedure serves to verify the Watchdog Processor System i.e. the Watchdog Processor Unit (WDP), the Configuration Control Bus Adapter (CCBA), th┆
0x46400…46500 (70, 0, 4) Sector 4605ff00220141 ┆F " Ae Channel Unit Control Panel (CUCP), the TDX Bus Switching Modules (BSM-Xs) and the Configuration Control Adapters (CCAs). The DSMT configuration under test is given in appendix A. 3.7.4.3.1 Test Set Up One copy of the documents mentioned in se┆
0x46500…46600 (70, 0, 5) Sector 4606ff00220141 ┆F " Ac 3.7.3 must be present in the testroom. The test is performed via an Operator Console (OC) which is a printer and keyboard with V24/V28 interface, a Medium Speed Printer (MSP) , a TEST VDU#1, a TEST VDU#2, all with OPTO interface and a TEST VDU#┆
0x46600…46700 (70, 0, 6) Sector 4607ff00220141 ┆F " A3 with V24/V28 interface. The above mentioned testequipment is connected to the DSMT system as follows: 1. Substitute the leftmost OPTO transceiver in the rack C Adapter crate with a V24/V28(L/L) adapter (1 channel), and connect the OC to the V┆
0x46700…46800 (70, 0, 7) Sector 4508ff00220141 ┆E " A24 connector on the front panel of the adaptor. 2. Connect the MSP to the remaining OPTO transceiver in the Adapter crate in rack C. 3. Remove the cable connected to the V24/V28(L/L) adapter in the adapter crate pos. 18 and substitute the adap┆
0x46800…46900 (70, 0, 8) Sector 00000000000000 ┆ ┆
[…0x67…]
