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Types: Wang Wps File
Notes: CPS/TMA/012 (Week 8)
Names: »2869A «
Derivation
└─⟦974e3658d⟧ Bits:30006161 8" Wang WCS floppy, CR 0241A
└─ ⟦this⟧ »2869A «
WangText
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…0e… 2869A/HH
JJD/821006
CR80 REVIEW 8:1:1 45
CAMPS…0f…
Identify the CR80 components, and explain their function
and interaction.
Review quiz
Situation questions during lesson
Questionare at conclusion of lesson
CAMPS Classroom
DI/I
Overheads
Whiteboard
CR80 Handbook 82/83
Student Textbook
…0e… 2869A/HH/
JJD/821006
CR80 BUS STANDARD 8:1:2 45
CAMPS…0f…
Divide the CR80 bussignals into 4 classes based on
the functions which they perform
explain the difference between:
processorbus - channelbus
channelbus - databus
explain the interrupt sequence
Review quiz
Situation questions during lesson
Questionare at conclusion of lesson
CAMPS Classroom
DI
Overheads
Whiteboard
CR80 Handbook 82/83
Student Textbook
…0e… 2869A/HH/
JJD/821006
CR80 DATA CHANNEL 8:1:3 45
CAMPS…0f…
Divide datachannel transfers into 3 groups and explain
the differences.
Review quiz
Situation questions during lesson
Questionare at conclusion of lesson
CAMPS Classroom
GW/L
Overheads
Whiteboard
CR80 Handbook 82/83
Student Textbook
…0e… 2869A/HH/
JJD/821006
CPU/CACHE CPU PART 8:1:4 45
CAMPS…0f…
Divide the CPU/CACHE into 4 functional blocks and explain
their interaction.
Explain the CPU registers.
Review quiz
Situation questions during lesson
Questionare at conclusion of lesson
CAMPS Classroom
Lecture
Overheads
Whiteboard
CR80 Handbook 82/83
Student Textbook
CPU/CACHE Product Specification CSD/005/PSP/032 Issue
3
…0e… 2869A/HH/
JJD/821006
CPU/CACHE CPU PART 8:1:5 45
CAMPS…0f…
Explain basic CPU operation
Discern between bit-slice processors and conventional
microprocessors.
Explain the two types of pipelining.
Explain the term microprogrammed.
Review quiz
Situation questions during lesson
Questionare at conclusion of lesson
CAMPS Classroom
L
Overheads
Whiteboard
CPU/CACHE PRODUCT SPECIFICATION CSD/005/PSP/32
CR80 Handbook
AMD 2910 Datasheets
Osborne: "An Introduction To Microcomputers", vol II
…0e… 2869A/HH/
JJD/821006
CPU/CACHE CPU PART 8:1:6 45
CAMPS…0f…
Describe the CPU detailed mode of operation
Review quiz
Situation questions during lesson
Questionare at conclusion of lesson
CAMPS Classroom
L
Overheads
Whiteboard
CPU/CACHE PRODUCT SPECIFICATION CSD/005/PSP/32
CR80 Handbook
AMD 2910 Datasheets
Osborne: "An Introductiin To Microcomputers", vol II
2869A/HH/
8:1:1
JJD/821006
CR80 REVIEW I /DI
INTRODUCTION HO 1, 2, Explain the purpose of the three weeks:
3 Low-level examination of the CR80
Off-line tools: DAMU and MAP exerciser
Manual operation of modules
Disassemble/assemble the CR80
REVIEW QUIZ Each lesson is reviewed
CR80 REVIEW OH 1
POWER PU: Combined, consumption
CU: Each bus, but power combine on module
BUSSES A̲l̲m̲o̲s̲t̲ identidal
MBT Purpose: Voltagelevel control
Part of interrupt system
MAP System control memory mapping (virtual memory)
Intra-memory DMA
CONTROL BUS Buscontrol, CPU notification
MIA Data-channel control, controlled from MAP
DAMU proms, V24 connection
CPU's Processing power: 1 0.6 MI/S
2 1.1 MI/S 80% CACHEHitrate
3 1.5 MI/S
CACHE: High-speed internal memory
RAM 128K words (16x2 bits) max 1M in PU
max 16M total
STI DMA device to TDX-system
2869A/HH/
8:1:1 JJD/821006
CR80 REVIEW I /DI
CIA OH 1 Slave buscontrol towards channel unit buses
polled by MIA (MAP), CU timing
DISC. Combined module: I/O module + 16K main memory
CONTROLLER Max 4 drives
COMBINED Whiteboard drawing
MODULES
OH 2
LTU Workprogram dynamically changeable!
4 communication lines
FLOPPY DISC Only I/O module
CONTROLLER
Whiteboard drawing:
2869A/HH/
8:1:1 JJD/821006
CR80 REVIEW I /DI
ADAPTERS LIA-N, SFA: No active logic connection to
rear plugs only
DCA: Separator function
DATA FLOW, 1 CPU req bus (via control bus)
2 MAP acknowledges (via control bus)
3 CPU address + data (or I/O)
4 MAP performs mapping (not when I/O)
5 Internal access
Yes No
Map takes over
address lines Activate MIA
6 Device answers 6 MIA transmit to
CIA
on data lines
7 CIA de multiplexes
7 CPU reads bus
8 CIA drives CU lines
9 CIA multiplexes
and
transmits back to
MIA (if read)
10 MIA transfers to
MAP
11 MAP transfers to
bus
12 CPU reads bus
2869A/HH/
8:1:2 JJD/821006
CR80 BUS STANDARD I /DI
BUS CONCEPT
4 MAJOR GROUPS Data, address, control,
interrupts
DATA 16 bits + 2 parity bits
ADDRESS 20 bit in PU = 1M word
24 bit external to PU = 4 CU number bits
1M word in each
channel unit
CONTROL Students Instructor
̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲
̲ ̲ ̲ ̲ ̲
Clocks [1: 1MHz, [2: 8MHz
R/W R/W
Memory or I/O LSO, LSI
00 I/O
01 Memory lower byte
10 Memory upper byte
11 Memory word
OH 1 Transfer start TRQ
Transfer stop RS B̲o̲t̲h̲ ̲R̲A̲M̲ ̲a̲n̲d̲ ̲I̲/̲O̲!
MAP address addressbits 16 + 17
OH 2 Interrupt INR, INA
+ 12 volts
Power + 5 volts
- 12 volts
OH 1 Mapping control AE, BD
Master clear MC
2869A/HH/
8:1:3 JJD/821006
CR80 DATA CHANNEL I /DI
DATA CHANNEL OH 1 1 Transfer address/data to/from the CU's
controlled by the MAP translation tables.
OH 2 2 Perform the interrupt polling of the CU's
3 TYPES OF Single addressing
TRANSFER Set-up
Reduced transfer
3 PHASES Address, data, termination
SINGLE Address phase: 3 cycles ̲ ̲ ̲ ̲ ̲ ̲ ̲
ADDRESSING C̲U̲ ̲ ̲M̲S̲B̲
̲ ̲ ̲ ̲ ̲ ̲ ̲
̲ ̲ ̲ ̲l̲s̲b̲
Data phase: 2 cycles ̲ ̲ ̲ ̲ ̲ ̲ ̲
L̲o̲w̲e̲r̲ ̲ ̲
U̲p̲p̲e̲r̲ ̲ ̲
Termination: Resets the channel = all CIA's
are "listening" again
SET-UP Address phase: 2 + 1 cycle ̲ ̲ ̲ ̲ ̲ ̲ ̲
C̲U̲ ̲ ̲M̲S̲B̲
̲ ̲ ̲ ̲ ̲ ̲ ̲
Load transfer counter (6 bit) ̲ ̲ ̲ ̲ ̲ ̲ ̲
T̲C̲ ̲ ̲ ̲ ̲ ̲ Address
̲ ̲ ̲ ̲ ̲ ̲ ̲
̲ ̲ ̲ ̲ ̲ ̲ ̲
Last address = s̲t̲a̲r̲t̲
Termination
Address is stored on the CIA-board specified
in the CU field
2869A/HH/
8:1:3 JJD/821006
CR80 DATA CHANNEL I /DI
REDUCED Address phase: 1 cycle ̲ ̲ ̲ ̲ ̲ ̲ ̲
(BLOCK ̲ ̲ ̲ ̲ ̲C̲U̲
TRANSFER) (CU = 1-F)
Data phase 2 cycles
Termination
Maximum number of transfers CIA: 256 words
before reinitialization MIA: 64 words
BLOCK Is used when internal DMA is in progress
TRANSFER S̲t̲a̲r̲t̲e̲d̲ by the MAP, conducted by the MIA
FIFO MAP loads/unloads a FIFO in MIA
MIA stops and signal MAP if FIFO full/empty
before transfer counter is zero
NOTE MAP can insert a single address transfer
while a block transfer is in progress
2869A/HH/
8:1:4 JJD/821006
CPU/CACHE CPU PART I /DI
CPU/CACHE
BLOCK DIAGRAM OH 1 CPU
P-bus interface can operate in parallel with
CPU
Test memory 4K word PROM + 64 words RAM
Built-in-test, power on
CACHE 1K word high-speed buffer
copies of main memory
CPU 16 bit word lenght
2x64K words of memory
64K words program
64K words data
USER/SYSTEM 15 No access control
STATE 14
System . Write
. Access control in CPU (Bound)
1
User 0 Access control in MAP
PROGRAMMERS OH 2 R0-R7 Accumulator or index or intermidiate
store
VIEW Base = Start address of data area
Prog = Start address of program
(= instruction) area
Prpc = Program counter
MODIFY Address (both data and program)
Relative address
Module address
Parameter
Timer = -1 each 1/250 usec, when negative
CPU is interrupted
2869A/HH/
8:1:4 JJD/821006
CPU/CACHE CPU PART I /DI
Bound: Write-protection in system state
1-14, but not level 15
Effective address bound register
1̲5̲ ̲ ̲ ̲ ̲1̲2̲ ̲1̲1̲ ̲ ̲ ̲ ̲ ̲8̲ ̲7̲ ̲ ̲ ̲ ̲ ̲ ̲4̲ ̲3̲ ̲ ̲ ̲ ̲ ̲0̲
̲
EXR EXR : P̲.̲ ̲L̲e̲v̲e̲l̲ ̲P̲r̲i̲o̲ ̲ ̲ ̲ ̲ ̲L̲e̲v̲e̲l̲ ̲ ̲ ̲ ̲V̲i̲e̲w̲ ̲ ̲
̲ ̲
VIEW 0-15, defines which two 64 K areas the CPU
can access now
LEVEL CPU level 0-15 (0 = user state)
PRIORITY The priority of the task that the CPU executes
PREVIOUS The level the CPU was executing just before
LEVEL this task was started
CER Counts the number of detected CACHE parity
errors
1 CACHE enabled
MSB of CER
0 CACHE disabled
PSW OH 3 Bit 14: Other CPU's, DMA or I/O modules
12: Not used in CAMPS
1: Interrupt after execution of each
instruction (debugging)
2869A/HH/
8:1:5 JJD/821006
CPU/CACHE CPU PART I /DI
CPU
OPERATION OH 1
CONTEXT When the CPU is forced to change the contents
SWITCHING of a̲l̲l̲ internal registers, thereby start
a new process. Before switching the CPU stores
the current register contents in a special
area within the process called the P̲rocess
P̲arameter B̲lock, PPB
BIT-SLICE OH 2 Basic ALU, specify Operand A
Operand B
Operation
Destination
AMD 2901 + sequencer AMD 2910
PIPELINING I OH 3+4 = internal delay compensation
Faster CPU
PIPELINING II = Instruction prefetch
MICRO- OH 2 Controlsignals from a PROM
PROGRAMMED
CPU
2869A/HH/
8:1:6 JJD/821006
CPU/CACHE CPU PART I /DI
CPU
BLOCK DIAGRAM OH 1 2910 sequencer: intelligent address counter
Fault register: errors from P-bus access
Control register: control CACHE memory +
PBTC
PROTOCOL Always try CACHE, no copy: halt cpu and initiate
P-bus cycle
Preprom: "Table of contents"
M̲i̲c̲r̲o̲p̲r̲o̲m̲
Preprom
̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲
̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ Shift
Operation Move Micro
Code Start P̲r̲o̲g̲r̲a̲m̲ ̲ ̲
"Move" L̲o̲c̲a̲t̲i̲o̲n̲ Add
Micro-
P̲r̲o̲g̲r̲a̲m̲ ̲ ̲
̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ "Move"
Micro-
P̲r̲o̲g̲r̲a̲m̲ ̲ ̲
Mask PROM:
To enable specification of single bit
Interrupt circuit:
Based on the event supply a 3-bit code which
causes a micro program jump
2869A/HH/
8:1:6 JJD/821006
CPU/CACHE CPU PART I /DI
EXECUTION OF OH 1
ONE INSTRUCTION Operation code MOV 7.x6 R1
Move the content of location base +
register 6 + 7 into CPU register 1.
Basis: Mov code is in opcoderegister
Next instruction is in next inst.
register
1 Add 7 (from instruction itself) to the content
of register 6
2 Add this result to the baseregister and store
result in address register
3 Fetch data from this address
4 Move data from inputregister into register
1
5 Add 1 to PRPC and restore PRPC
6 Use updated PRPC as an address
7 Fetch next instruction = M̲O̲V̲ ̲+̲ ̲2̲
8 Store previous instruction in opcoderegister
9 Store MOV + 2 in next instr.register
Memory
̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲
M̲O̲V̲ ̲7̲x̲6̲ ̲R̲1̲ In opcode register in CPU
M̲O̲V̲ ̲+̲ ̲1̲ ̲ ̲ ̲ In next instruction register
M̲O̲V̲ ̲+̲ ̲2̲ ̲ ̲ ̲ Fetched during above seq.
WORK
ASSIGNMENT HO 1
HO 1…01…TIDSPLAN FOR UGE 8, 9 og 10
OH 1…01…Fig. 6.3-1…01…Training Plan (3-3083)
OH 2…01…4-1657…86…1 …02… …02… …02… …02… …02…
OH 1…01…TRQ, RS…86…1 …02… …02… …02… …02… …02…
OH 2…01…INR kredsl]bet…86…1 …02… …02… …02… …02… …02…
OH 1…01…CAMPS CR80 3-3083…86…1 …02… …02… …02… …02… …02…
OH 2…01…(OH 7 i uge 2)…86…1 …02… …02… …02… …02… …02…
OH 1…01…4-1961…86…1 …02… …02… …02… …02… …02…
…01…OH 2…01…4-1970…86…1 …02… …02… …02… …02… …02…
OH 3…01…PSW…86…1 …02… …02… …02… …02… …02…
OH 1…01…Ny tegning…86…1 …02… …02… …02… …02… …02…
OH 2…86…1 …02… …02… …02… …02… …02…
OH 3…01…1690…86…1 …02… …02… …02… …02… …02…
OH 4…01…1689…86…1 …02… …02… …02… …02… …02…
OH 1…01…6-666…01…side 31 i TP…86…1 …02… …02… …02… …02… …02…
HO…01…Vedlagt i kladde
W̲O̲R̲K̲ ̲A̲S̲S̲I̲G̲N̲M̲E̲N̲T̲
The nine microprogram steps listed on the whiteboard
must be arranged into a parallel lapse to achieve fast
CPU operation. Insert the 9 steps in the framework
below.
INPUT BUS OUTPUT BUS ADDRESS BUS P-BUS TIMING
+ CONTROL
̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲
̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲
1
̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲
̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲
2
̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲
̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲
3
̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲
̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲
4
̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲
̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲
5
̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲
̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲
6
̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲
̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲
7
̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲
̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲
8
̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲
̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲
9
̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲
̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲
…0e… 2869A/rt
JJD/821005
REVIEW QUIZ 8:2:1 45
CAMPS…0f…
8 out of 10
Answers should be correct
CAMPS Classroom
QUIZ Duration: 30 minutes
QUIZ
Student Text Book
Student Hand-Out
Student Notes
As above
…0e… 2869A/rt
JJD/821005
CPU/CACHE CACHE PART 8:2:2 45
CAMPS…0f…
Describe the Cache concept and advantages
Explain the Hit decoder mode of operation
Review Quiz
Situation questions during the lesson
Questionare at conclusion of lesson
CAMPS Classroom
Lecture
Overheads
Whiteboard
Student Textbook
CR80 Handbook 82/83
CSD/005/PSP/032
…0e… 2869A/rt
JJD/821005
CPU/CACHE CACHE PART 8:2:3 45
CAMPS…0f…
Explain the Cache mode of operation
Review Quiz
Situation questions during the lesson
Evaluation of work-assignment
Questionare at conclusion of lesson
CAMPS Classroom
GW, L
Overheads
Whiteboard
CSD/005/PSP/032: CPU/CACHE
CR80 Handbook 82/83
Student Textbook
…0e… 2869A/rt
JJD/821005
MAP MODULE 8:2:4 45
CAMPS…0f…
Explain the purpose of Segment Registers and
Translation tables
Define a CPU view
Explain logical and physical addresses
List the seven major map functions
Explain the master clear events
Review Quiz
Situation questions during the lesson
Questionare at conclusion of lesson
CAMPS Classroom
L
Overheads
Whiteboard
CSD/005/PSP/037
CR80 Handbook 82/83
Student Textbook
…0e… 2869A/rt
JJD/821005
MIA 8:2:5 45
CAMPS…0f…
List the major functions of the MIA
Describe the Interrupt polling algorithm
Review Quiz
Situation questions during the lesson
Questionare at conclusion of lesson
CAMPS Classroom
L
Overheads
Whiteboard
CSD/005/PSP/058:
MAP Interface Adapter
Student Textbook
…0e… 2869A/rt
JJD/821005
RAM 8:2:6 45
CAMPS…0f…
Explain RAM addressing
Recognize the 4332 RAM-CHIP
Corrolate databit position and
RAM chip position
Review Quiz
Situation questions during the lesson
Practical exercise in which students
locate defective RAMchip by means of
map exerciser (lesson 9.x.x)
CAMPS Classroom
L, GW
RAM board
Overheads
Whiteboard
4332 DATA-SHEETS
4116 DATA-SHEETS
Student Textbook
…0e… 2869A/rt
JJD/821005
REVIEW QUIZ 8:3:1 45
CAMPS…0f…
8 of 10 answers must be correct
CAMPS Classroom
Quiz Duration: 30 minutes
Quiz
Student Textbook
Student Hand-Outs
Student Notes
As above
…0e… 2869A/rt
JJD/821005
DAMU 8:3:2 45
CAMPS…0f…
Interpret and compose DAMU commands
Situation questions during lesson
Hands-on exercises during lessons
8.2.3 - 8.2.6
CAMPS Classroom
CAMPS Training System
L, De
Whiteboard
DAMOS Bootloader: CSS/3500/PSP/0029
MAP MODULE: CSS/005/PSP/0037
…0e… 2869A/rt
JJD/821005
DAMU 8:3:3 45
CAMPS…0f…
Configure MAP Translation tables
Use Damu commands set-parity,dump,patch
multipatch, copy, search and negated search
DAMU exercises
CAMPS Classroom
CAMPS Training System
L, GW, H, S
Whiteboard
as for 8:3:2
…0e… 2869A/rt
JJD/821005
DAMU 8:3:4 45
CAMPS…0f…
Configure MAP Translation tables
Use Damu commands set-parity,dump,patch
multipatch, copy, search and negated search
DAMU exercises
CAMPS Training System
GW, M, S
Whiteboard
as for 8:3:2
…0e… 2869A/rt
JJD/821005
DAMU 8:3:5 45
CAMPS…0f…
Configure MAP Translation tables
Use Damu commands set-parity,dump,patch
multipatch, copy, search and negated search
Unit mapping, erase memory
DAMU exercises
CAMPS Training System
GW, M, S
Whiteboard
as for 8:3:2
…0e… 2869A/rt
JJD/821005
DAMU 8:3:6 45
CAMPS…0f…
Configure MAP Translation tables
Use Damu commands set-parity,dump,patch
multipatch, copy, search and negated search
Unit mapping, erase memory
DAMU exercises
CAMPS Training System
GW, M, S
Whiteboard
as for 8:3:2
…0e… 2869A/rt
JJD/821005
MAP EXERCISER 8:4:2 45
CAMPS…0f…
Perform patch, dump, multipatch by means of
map commands
Configure the map tables to any physical page
multipatch, copy, search and negated search
page
Locate defective RAM chips by
means of MAP exerciser
MAP exerciser workassignments
Situation questions during lesson
CAMPS Classroom
CAMPS Training System
S, H, I
Defective RAM Board (Parity Chip)
Whiteboard
MAP specification CSD/005/PSP/0037
DAMOS Bootloader CSS/3500/PSP/0029
…0e… 2869A/rt
JJD/821005
MAP EXERCISER 8:4:3 45
CAMPS…0f…
Perform patch, dump, multipatch by means of
map commands
Configure the map tables to any physical page
multipatch, copy, search and negated search
page
Locate defective RAM chips by
means of MAP exerciser
MAP exerciser workassignments
Situation questions during lesson
CAMPS Classroom
CAMPS Training System
S, H, I
Defective RAM Board (Parity Chip)
Whiteboard
MAP specification CSD/005/PSP/0037
DAMOS Bootloader CSS/3500/PSP/0029
…0e… 2869A/rt
JJD/821005
MAP EXERCISER 8:4:4 45
CAMPS…0f…
Perform patch, dump, multipatch by means of
map commands
Configure the map tables to any physical page
multipatch, copy, search and negated search
page
Locate defective RAM chips by
means of MAP exerciser
MAP exerciser workassignments
Situation questions during lesson
CAMPS Classroom
CAMPS Training System
S, H, I
Defective RAM Board (Parity Chip)
Whiteboard
MAP specification CSD/005/PSP/0037
DAMOS Bootloader CSS/3500/PSP/0029
…0e… 2869A/rt
JJD/821005
MAP INTERRUPT HANDLING 8:4:5 45
CAMPS…0f…
Interpret an interrupt vector
list the two interrupt paths to the map
explain the i.v. flow on each path
explain purpose and contents of
iv records, CPU records and
timer
Exercises during lesson 9:5:4 - 9:5:5
Review Quiz
Situation questions during lesson
CAMPS Classroom
L
Whiteboard
Overheads
MAP product spec. CSD/005/PSP/0037
DAMOS Bootloader CSS/3500/PSP/0029
…0e… 2869A/rt
JJD/821005
MAP INTERRUPT HANDLING 8:4:6 45
CAMPS…0f…
Describe map interrupt handling
and queueing protocol
Situation questions during lesson
Review Quiz
CAMPS Classroom
GW, L
Whiteboard
Overheads
As for 8:4:5
…0e… 2869A/rt
JJD/821005
REVIEW QUIZ 8:5:1 45
CAMPS…0f…
8 out of 10 answers must be correct
CAMPS Classroom
Quiz Duration: 60 minutes
Quiz
Student Textbook
Student Hand-out
Student Notes
As above
…0e… 2869A/rt
JJD/821005
REVIEW QUIZ 8:5:2 45
CAMPS…0f…
8 out of 10 answers must be correct
CAMPS Classroom
Quiz
Student Textbook
Student Hand-Cuts
Student Notes
As above
…0e… 2869A/rt
JJD/821005
CPU INTERRUPT HANDLING 8:5:3 45
CAMPS…0f…
Explain lay-out and purpose of the PPB
Describe the action on vectorized
interrupts
Describe CPU action on internal interrupts
Review Quiz
Situation Questions during lesson
Questionare at conclusion of lesson
CAMPS Classroom
L
Whiteboard
Overhead
CPU Cache Product Specification
CSD/005/PSP/003253
…0e… 2869A/rt
JJD/821005
INTERRUPT EXERCISE 8:5:4 45
CAMPS…0f…
Control map queuing by means of map
exerciser
Exercise
CAMPS Training system
GW, H
Whiteboard
CSD/005/PSP/37
CSD/005/PSP/0032
…0e… 2869A/rt
JJD/821005
INTERRUPT EXERCISE 8:5:5 45
CAMPS…0f…
Verify correct CPU reaction to map
notification
Exercise
CAMPS Training system
GW, H
Whiteboards
CSD/005/PSP/37
CSD/005/PSP/0032
…0e… 2869A/rt
JJD/821005
WEEK SUM-UP 8:5:6 45
CAMPS…0f…
Lesson is used to summarize the week
clear out misunderstandings
Evaluate the week
and explain the purpose/contents of the
following week
CAMPS Classroom
DI, I
Whiteboard
None
REVIEW QUIZ 8.2.1
1. How many address-sourcing modules are possible
within one processor unit?
2. Explain the difference between logical address
and physical address
3. List the differences between processor bus and
channelbus
4. Explain the use of bus signals LSO, LS1
5. Name the peripheral controller that is accessed
by I/O commands only
6. What is the purpose of the CPU/CACHE preprom?
7. Which CPU/CACHE register controls CACHE
Enabling/Disabling?
8. What is the purpose of the "bound" register
9. Explain the difference between system state and
user-state.
10. Why must incoming data have two registers in the
CPU?
JJD 821005 H.O.1
CPU/CACHE
WORKASSIGNMENT I CAMPS
Explain mode of operation of the circuit shown below.
The RAM is 1024 x 8 bits.
R/W = 0 when read, R/W = 1, when write.
How can signal X be interpreted?
is an exclusive or gate.
JJD 821005 H.O.1
CPU/CACHE
WORKASSIGNMENT I CAMPS
List all the possible events that the CACHE-Controller
must be able to handle, and your suggestion to how
the CACHE-Controller should handle each event.
EXAMPLE:
EVENT CONTROLLER ACTION
̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲
̲ ̲ ̲
Addressed location N̲O̲T̲ in Switch control to
PBTC
when CPU R̲E̲A̲D̲S̲ and take a copy
…0f…2869A 8:2:6
JJD 830216 H.O.1
RAM ADDRESSING
WORKASSIGNMENT I CAMPS…0f…
Knowing the 4164 addressing and given the 20 CR80 Addresslines,
try to set up an addressline decoder which specify
one memory word of the total 1M word memory area.
The decoder must take into account that the 1M word
memory area is located on 2 RAM boards!
CR80 ADDRESSLINES
̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲
̲ ̲
̲1̲9̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲0̲
̲
2869A/rt/
8:2:2
JJD/821006
CPU/CACHE CACHE PART L /GW
CACHE CONCEPT OH 1
CACHE
ADVANTAGES Bus Load decreases System Speed
Average Acces time
decreases increases
FUNCTIONAL 0.H 2 Control Registers
DIAGRAM CACHE: Output: type of operation
Input: CACHE error
PBTC: Output: type of operation
Input: bus access errors
Hit detector I: Logical address HIT
Hit detector II: Physical address HIT
HIT
DETECTOR H.O 1 Workassignment I
2869A/rt/
8:2:3 JJD/821006
CPU/CACHE CACHE PART
CACHE
MODE OF OPE-
RATION H.O.1 Work Assignment
̲ ̲ ̲ ̲ ̲E̲V̲E̲N̲T̲ C̲A̲C̲H̲E̲ ̲C̲O̲N̲T̲R̲O̲L̲L̲E̲R̲ ̲A̲C̲T̲I̲O̲N̲ Read,not
in
CACHE PBTC
+
copy
into
CACHE
set valid bit
Read,in CACHE,no Present data to CPU
Errors
Read,in CACHE,but
parity error
Read,in CACHE,but
not valid PBTC + copy into CACHE
set valid bit
Read,in CACHE,but
read in user,stored
In system
Write,not in CACHE PBTC
No CACHE update
Write,in CACHE Initiate PBTC,
Update CACHE,set valid
bit
Write,in CACHE but PBTC
parity,valid or
state no update
not ok
PBTC bus fault Delete CACHE Location
(Time-out,parity,
page,fault, access
protection)
Change of view Delete a̲l̲l̲ CACHE locations
Map access CACHE dont care
I/O access - " "
Other address-sour-
cing,module access
main memory locations
copied into local
CACHE Delete Location
P-bus or C-bus
CACHE Test Perform destructive
test
CACHE OFF Command from CPU
LED CPU still operatio-
nal
2869A/rt/
8:2:4 JJD/821006
MAP MODULE L
MAP Memory Mapping
Major Functions Addressing: 256 Kword
- 1M -16 Mwords
1/0 modules 64 - 992 (992 = 1024 - 32)
Controls Data-Channel
P.U.Bus Control
P.U.Timing
Interrupt Handling
Memory 0.H.1 Optimize memory use
Mapping easy access control
easy exchange of working area
(possibility of virtual memory implementation)
Implementa-
tion 0.H.2 Logical - Physical address
Note View and translation table are n̲o̲t̲ in any
way corrolated
which tables to which view is CPU internal
affairs entirely
CPU view The two tables p̲r̲e̲s̲e̲n̲t̲l̲y̲ ̲used when addressing
data or program.
Addressing CPU: 128K (Logical)
MAP + 8 BIT = 16M (Physical)
1/0 6 BIT Address = 64 possible 1/0 Device
MAP: + 4 Crate No = 1024 Devices
CPU uses 32: 992 "
2869A/rt/
8:2:4 JJD/821006
MAP MODULE L
P.U. Bus O.H.3 P3 Connector BRQ - BG
Control 9 External Devices + 1 MAP internal
cyclic, no HOGGING,
P.U. Timing Clock Generation
+
Control Generation of Master Clear:
+5 Volt below 1V
Programmed clear
ECL activated (A41)
Push Button
Power Failure Detection
Interrupt to map +5, +12, -12V or
PFL (A40)
Real time clock 47 bit counter
Fast timer 250 microseconds
(Tie a Process to time)
Interrupt
Handling Later
Access
Status Register
…06…1 …02… …02… …02… …02… …02… …02… …02… …02… …02… …02…
…02… …02… …02… …02… …02… …02…
1 5 14 13 12 11 8 7 XXX 3 2 1 0
Access
Protection
bits
Priority
Error
Upper
TT-byte
Priority
Error
Lower
TT-byte
Time-out
(MAP)
CIA
status
CIA
status
valid
MIA
status
2869A/rt/
8:2:5 JJD/821006
MIA L
MIA Control the data channel,
Major Function Perform the interrupt
polling of C.U.s
Drive the V24 interface
Support the DAMOS bootloader PROMS (DAMU)
MAP/MIA
TRANSFER OHI MAP commands on MAP ̲COMMAND BUS (MC-BUS)
(3-3418) Associated Address/Data Information on
MAP-MIA Bus (MM-BUS)
Single
Transfer MIA adds Parity+2 control bits to address
Write Data inclusive Parity from Map
MIA two control bits
N̲o̲ parity check performed by MIA
MIA awaits DA, MAP informed
via STE
READ O̲K̲: MIA check parity MAP notified, reads
data
O.H.2 E̲R̲R̲O̲R̲M̲E̲S̲S̲A̲G̲E̲ ̲F̲R̲O̲M̲ ̲C̲I̲A̲:̲, Load Ste, 4 LSBs
Notify MAP, MAP read Ste
No answer: MIA resets channel ( )DA
M̲I̲A̲ loads error message into ste
(4 MSB) notify map, map reads
Ste
SET-UP O.H 1 MAP supply CU number + start address and
number of transfers max 64
MIA keeps copy of CU number and sends the
total address + command bits out on data
channel
The addressed CU (=CIA) loads the address
into a counter and is ready to perform block
transfer.
2869A/rt/
8:2:5 JJD/821006
MIA L
Block =1 to 64 Reduced Transfers
Transfer
Reduced Performed by M̲I̲A̲, sends out the CU Address
Transfer (and Data if write)
Data loaded/unloaded into a FIFO
which is emptied/filled by MAP
Based on status signals from MIA
Write No parity check in MIA, but in CIA unload
FIFO
Read Parity check by MIA, load FIFO
Error OH 3 Transfer stops, MIA loads BTE, notify MAP
MAP reinitiate from SET-Up
Interrupt Polled Cyclic, all 15 CUs
if interrupt stop polling, load code
into register, notify MAP, MAP reads
register + channel no register, MIA continues
Serial I/O OH1 One chip, controlled fully by M̲A̲P̲ by
(V24) special commands
Baudrate Switchselectable on MIA
PROM DAMOS bootloader
Single Transfer
U̲p̲p̲e̲r̲ 4K of P̲h̲y̲s̲i̲c̲a̲l̲ memory
FFFOOO - FFFFFF
2869A/rt/
8:2:6 JJD/821006
RAM
RAM CHIP O.H 1 2 x 4116
4332
RAS, CAS
RAM H.O.1
Addressing O.H.2 Workassignment
O.H.3
Chip
Location O.H.3
(4-1698)
REVIEW QUIZ 8.3.1
1. Describe the CACHE concept and advantages
2. The CPU writes into a main store location
Describe CACHE reaction(s)
3. How does the CPU disable the CACHE?
4. When does the CACHE disable the CACHE
5. Can the CPU still operate if the CACHE RAM
is disabled?
6. When, how and why are CACHE locations deleted?
7. Define the CPU view
8. Explain logical and physical addresses
9. List the seven major functions performed
by the MAP
10. When is the PU master cleared?
…0f…2869A 8:3:3 - 8:3:6
JJD/830202
H.O.1
DAMU EXERCISE
CONFIGURATION
CAMPS…0e…
N̲O̲T̲E̲:̲ ̲A̲L̲L̲ ̲N̲U̲M̲B̲E̲R̲S̲ ̲A̲R̲E̲ ̲I̲N̲ ̲D̲E̲C̲I̲M̲A̲L̲ ̲N̲O̲T̲A̲T̲I̲O̲N̲
1) Initialize DAMU (Power on or Masterclear) ZP
2) Verify Initialization parameters by means of DAMU
3) Change Translation Tables to DATA = 00, and
Program = 01
4) Using DAMU command OC and the MAP instructions
for mapping control (PSP 37 page 61)
set up logical datapage 4 to be mapped in as physical
page 100
Note: Access protection must be full access.
5) Verify result by setting up logical datapage 5
to the s̲a̲m̲e̲ physical page, and using page 5, patch
a pattern = A5A5 into Location FF. Dump location
FF.
u̲s̲i̲n̲g̲ ̲D̲a̲t̲a̲p̲a̲g̲e̲ ̲4̲ and verify pattern.
6) Now set up logical datapage 5 to be physical page
101 (full access). write a pattern into 5 locations
in datapage 4 and copy
these 5 locations into datapage 5. Verify by dump.
7) Write B00B into all of datapage 4
Write ABBA into location 9
Verify by means of search and negated search.
8) Set up logical datapage 6 to be physical page 103
(Full access) and copy one location from page 4
into logical page 6.
Write down your conclusions!
…0f…2869A 8:3:3 - 8:3:6
JJD/830216 H.O.1
DAMU EXERCISE
CONFIGURATION CAMPS…0e…
9) Change logical datapage 6 to logical page 7, and
try to copy from page 4 into page 7.
Write down your conclusions!
10) Erase the location in page 4 that you copies from
and perform a copy b̲a̲c̲k̲w̲a̲r̲d̲s̲ from page 7 into page
4.
Write down your conclusions!
11) Load Read-Time-Counter (RTC) in MAP module and
verify that it is counting..
12) Enable the SMD disc controller on to the bus, and
setup 32 logical datapages to match the SMD disc
controller RAM area u̲s̲i̲n̲g̲ ̲o̲n̲l̲y̲ ̲o̲n̲e̲ ̲D̲A̲M̲U̲ ̲c̲o̲m̲m̲a̲n̲d̲!
13) Explain the difference between these two commands
PD6 0 A5A5
PD 1800 A5A5
Verify answer by means of dump
14) Issue UMF
Explain result
15) P̲r̲o̲v̲e̲ by means of DAMU commands that the CPU is
in system state when executing DAMU
16) Perform a floppy dump of physical pages 3FFC -
3FFF (the DAMU Program)
17) Erase A̲l̲l̲ physical memory = write 0000
into all locations.
Verify by spot tests.
18) Using MAP system control commands on page 11 in
PSP 37,
issue a programmed clear to the MAP.
19) Perform a read of the PU number switch on the MAP
module and verify the result.
2869A/rt/
8:3:2
JJD/821006
DAMU L
DAMU Low-Level off-line system operation,
Purpose Analysis or diagnostic
Implementation 4K PROM, located on
MIA board
Connection V24 PLUG on MIA board
Requirements 1 CPU, MAP, MIA, RAM (lower 2̲ physical pages)
Initialization All D̲a̲t̲a̲ Segment registers
= 00
(MAP) All program " " = 01
Translation tables:
Table 00 (̲D̲A̲T̲A̲)̲
Page 0: Physical Page 0000, full access
Page 63: " " 0001, " "
Table 01:
Page 0 - 3: Physical Pages 3FFC - 3FFF, read
(MIA PROM)
Page 63: 3FFF
O̲t̲h̲e̲r̲ ̲t̲a̲b̲l̲e̲s̲ ̲A̲l̲l̲ ̲a̲b̲s̲e̲n̲t̲
View 15 (F)
CPU System State, tables 3F and 3E
DAMU
Syntax O:H.1
Use of DAMU Power on or master clear
Set parity ZP crate Read/Rewrite, CPU parity
2869A/rt/
8:3:2 JJD/821006
DAMU L
View Confirms Initialization Parameters
Utility
Change Insert table 0 (Data) and table 1
View (Program) as DAMU workarea
Configuration V̲W̲ ̲0̲1̲0̲0̲
(Loads 00 into Datasegment and 01 Into Program
segment)
Dump
Command O.H.2
Patch
Command 0.4.3
Demonstration Configuration, Dump, Patch
2869A/rt/
8:3:3 JJD/821006
DAMU L/GW
Configu- H.0.1 Work assignement
ration
2869A/rt/
8:3:4 JJD/821006
DAMU
Configu- H.0.1 Work assignement
ration
UM 1 Corrolation between unit mapping
and physical page
1̲5̲ ̲ ̲ ̲ ̲ ̲ ̲1̲2̲ ̲1̲1̲ ̲ ̲ ̲ ̲ ̲ ̲8̲ ̲ ̲7̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲4̲ ̲ ̲3̲ ̲ ̲ ̲ ̲2̲ ̲ ̲1̲ ̲ ̲ ̲ ̲0̲
CRATE SECTION AREA PAGE
̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲
Protection
Bits
2869A/rt/
8:3:5 JJD/821006
DAMU
H.0.1 Work assignement
2869A/rt/
8:3:6 JJD/821006
DAMU GW,H,S
H.0.1 Work assignement
Sum-up Pages crossing i̲f̲ ̲d̲e̲f̲i̲n̲e̲d̲ when
Dump, patch, multipatch, search, N.search
Physical gaps accepted, Logical gaps not
accepted.
Um
% Indicates ROM memory
View View of no importance in DAMU,
because t̲r̲a̲n̲s̲l̲a̲t̲i̲o̲n̲ ̲t̲a̲b̲l̲e̲s̲ are not affected
by change of view (view O-F )
Patch Can patch d̲i̲f̲f̲e̲r̲e̲n̲t̲ word patterns into successive
locations
E.G. PD1 040 A5A5 5A5A B00B....
Floppy Save on disc from sector 1 and
Dump on wards
Initialization sequence
BA 1001
BV 0000 (OR 0001)
BM N.C
BT FD500
2869A/rt/
8:4:2 JJD/821006
MAP EXERCISER S,H,I
Introduction Low-Level(=Below DAMU) off-line
to MAP system Operation, Analysis, Diagnostic
Maintenance Mode
Implementation MAP Processor, Microprogram
(1853 68-2)
Special Mode, Switch 2
Use CB-DMA Device, C̲B̲ Device 0
Connection V24 on MIA board
Requirements MAP + MIA (+MBT)
Initialization Switch 2 in Pos: Maintenance
Mode
Switch 3 in Pos: Enable
Master Clear or Power on
Leds Power, Maint, Halt, Inh are on
* Prompt for command input
Useful
Information SR1 is mounted
SR4 is removed
SR5 is removed
Use of
Map
Exerciser H.O.1 Workassignment
pt 6 When solved, exercised on a defective RAM
board
2869A/rt/
8:4:5 JJD/821006
MAP Interrupt Handling L
Definition of Event, Unrelated and uncontrolled by the
Interrupts the current program, or fault condition caused
by program
Caused by Peripheral modules, fast timer, trace, page
fault, illegal instr., trap, parity error,
time ̲out access fault (user)
bound violation (system), privileged inst.
Stack over/underflow
Emergency
Vectored Collected, Controlled, Processed and forwarded
by MAP-Module
Not Vectored CPU i̲n̲t̲e̲r̲n̲a̲l̲ interrupts
Interrupt 9 6 5 0
Vector ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲
X CRATE MODULE 10 bits = 1024IV.s
̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲
R 3F Power Failure
0 3E Real Time
0 0-1F CPU-CPU INT
0 3D IM-DMA IN MAP
0 3C V24 Interface
REST: Available other modules
IV PATHS O.H.1 1) P.U: Channel-Bus only
2) C.U: CIA Collects from Databus
MIA polls CIAs and notify MAP,
MAP reads IV from MIA registers
MAP RAM OH2 Each IV has a IV record
Specifying which CPU and IV priority
2869A/rt/
8:4:5 JJD/821006
MAP Interrupt Handling L
IV RECORD ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲6̲ ̲ ̲ ̲ ̲ ̲ ̲4̲ ̲ ̲ ̲3̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲0̲ ̲ ̲
CPU PRIO
̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲
0-4, 7 = POOL
IV TIMER Simulate Interrupt from the
associated IV
Units: 1 second
000 = no counting
CPU Records Each CPU, priority of c̲u̲r̲r̲e̲n̲t̲ process enable/disable
notification
̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲4̲ ̲ ̲ ̲3̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲0̲ ̲ ̲
PRIO
̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲
E/D
CPU
Notification Controlbus INT0-INT2 + strobe
CPU Reads Notification descriptor for
Reaction CPU, 8948 + CPU number
Notification Interrupt Vector
Descriptor
2869A/rt/
8:4:6 JJD/821006
MAP Interrupt Handling GW,L
Interrupt OH1
Flow-chart
Queuing 90 queues = 15 levels to each CPU = 75
15 levels for the pool = ̲1̲5̲
90
first in-first out scheme
IVQCB O.H.2 specify FIRST and LAST LISTelement (Bit 7
0/1) in each queue.
Addressing in the IVQCB area is based on
the IVRecord corresponding to the IV which
is to be queued.
Contents of FIRST is the IV which is first
in the queue a̲n̲d̲ at the same time address
to the next IV in the queue, stored or
LIST ELEMENT in the LIST ELEMENT area. This location again
point to the next IV in the queue and so
on.
LAST is specified in IVQCB location LAST
and the content of the corresponding IV location
in the list element area is FFXX.
I/A IV in the LIST ELEMENT area is not queued
contents is 4000
Empty Queue FIRST: UNKNOWN, but LAST = FFXX
…0f…2869A 8:4:2
JJD 830216 H.O.1
MAP EXERCISER, SELF-STUDY
OPERATION CAMPS…0f…
NOTE: ALL NUMBERS ARE IN HEXADECIMAL NOTATION
1. Set P.U. into maintenance mode and master clear
2. Set-up both segmentregisters to 1
3. Initiate page 4 in table 1 to
physical page 64
4. Construct the map commands that substitutes DAMU
commands patch, multipatch and dump
5. Verify our MAP commands by switching to DAMU
and dump/patch the locations used in 4.
Note: Remember to initiate DAMU to physical page 4
6. Work out a flowchart to locate defective RAM
chips (i̲n̲c̲l̲u̲d̲i̲n̲g̲ paritychips) by means of MAP
commands.
It is assumed that the logical address of the
defective location is known.
Hint: use command ignore
JJD 821005 H.O.1
REVIEW QUIZ
8:5:1 CAMPS
1. List the two basic types of interrupts
2. Explain the two interrupt paths from the CR80 system
to the MAP
3. Explain the purpose of the IVRecord
4. Explain the purpose and the use of the timer
5. Explain the purpose of the CPU record
6. The content of a FIRST location in the IVQCB area
is 063. Which crate and module are pointed out
to be the first in this queue?
7. The contents of location 063 in the LIST ELEMENT
area is 03C…0f…H…0e…. What does this mean?
8. The content of 03C in the LIST ELEMENT area is
FF30…0f…H…0e…. What does this mean?
9. Referring to questions 6-8, what is the content
of the LAST location in the IVQCB area?
10. Location 8C in the LIST ELEMENT area is 4000…0f…H…0e….
What does this indicate?
…0f…2869A
JJD 830216
H.O.1
EXERCISE
8:5:3 - 8:5:5
CAMPS…0e…
MAP QUEUING EXERCISE
SELECT MAINTENANCE MODE AND MASTER CLEAR THE CR80
NOTE: Maintenance Mode, inhibit and h̲a̲l̲t̲ must be active
1. Determine the lay-out of the floppy disc
controller interrupt vector
2. Enable the floppy disc controller on to the channel
unit bus
3. Set-up the IV record for the floppy disc controller
to be CPU number 0, priority A.
4. Set-up the CPU record for the CPU number 0 to priority
F, interrupt d̲i̲s̲a̲b̲l̲e̲ not possible.
5. Read out first, last and the list element for the
floppy disc controller IV b̲e̲f̲o̲r̲e̲ interrupt.
FIRST:
LAST:
LIST ELEMENT:
Explain results.
6. Insert a discette into the floppy drive (any of
them) and close the door.
(this will make the floppy disc controller interrupt
the CR80!)
7. Read out first, last and list element for the floppy
disc controller.
Explain results.
…0f…2869A 8:5:3-8:5:5
JJD 830216
H.O.1
INTERRUPT EXERCISE
Part II
CAMPS…0e…
8. Lower the CPU priority to 9 and enable interrupts
9. Read out again first, last and list element for
the floppy disc controller. Explain results.
Read out CPU-record and the notification descriptor
for CPU 0 and make you conclusions.
10. Enable the P.U. Crate
11. Read out again first, last and list element for
the floppy disc controller
FIRST:
LAST:
LIST ELEMENT:
Explain results!
12. Read out notification descriptor for the CPU 0
13. Read out CPU-Record for CPU 0
Explain result
14. (OPTIONAL)
Set-up the RTC and the INT-TIME register in the
MAP to generate an interrupt, and confirm the interrupt
via MAP-RAM.
…0f…2869A 8:5:3-8:5:5
JJD 830216 H.O.1
INTERRUPT EXERCISE
Part II
CAMPS…0e…
l5. Force the MIA to insert an interrupt which requests
the channel unit to output the testpattern and
read the response to verify.
l6. Read out the number of parity errors in interrupts
from the channel unit.
17. Master Clear the PU and notify CPU No. 2
Switch to normal mode and explain output on the
console. (Issue Master Clear and try again - this
time Notify CPU No. 1 to verify your explanation).
18. Master Clear the PU and (using maintenance mode)
change the segment registers for CPU No. 1 to 8
(both data and program). Now Notify CPU 1 and switch
to normal mode and explain output on the console.
19. Locate the PPB of DAMU and erase the entire page!
Try to use DAMU (dump, patch or the like) and explain
your results.
2869A/rt/
8:5:3
JJD/821006
CPU Interrupt Handling L
Process Process related variable used by the CPU
Parameter (CPU noteblock)
Block
Layout O.H.1 Logical datapage 63, 1024 words
View CPU translation MAP: for each view (O - F)
a set of values to be stored in the MAP segment
registers
1̲5̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲8̲ ̲ ̲ ̲7̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲0̲ ̲
PROG. DATA
̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲
set up by S/W
Bound System State, write protection
address bound
Bound 15 = FFFF: No bound
Level indicated by EXR register in CPU
FFEO used during I/O interrupts (IV 32)
to point out the physical location of the
n̲e̲w̲ logical datapage
Context Start of area dedicated to the stack: FFDE
Stack SRP of area dedicated to the stack: FFDF
actual stack pointer: FFDD
Context
Record OH2 the total picture of a given process
2869A/rt/
8:5:3 JJD/821006
CPU Interrupt Handling L
Interrupt
Processing
MAP notification P3 Control Bus INT0 - INT2 + strobe specifying
CPU number
CPU
Processing
IV 31 O.H.3 New PRPC depending of interrupt cause takes
care of all local interrupt and CPU interrupts
IV 32 O.H.4
2869A/rt/
8:5:4 JJD/821006
Interrupt Exercise GW,H
Exercise H.O.1 Ensure that P.U. is disabled and halted
2869A/rt/
8:5:5 JJD/821006
Interrupt Exercise GW,H
Exercise H.O.1
Optional Set-up the notification descriptor
Excercise for CPU to 003F (Power Failure!)
Use N-command to notify CPU 0
Explain result
…0f… 2869A/ktd
JJD/830216
CR80 REVIEW Week 8
CAMPS…0e…
1 Given the 5 busses in the CR80, list the signals that
are a̲c̲t̲u̲a̲l̲l̲y̲ ̲u̲s̲e̲d̲ on each of them.
Processor Bus:
Channel Bus:
Data Bus A:
Data Bus B:
P.U. Control Bus:
2. List all the CR80 modules (-STI) and explain the purpose
of each of them.
3. Describe the use of the Data Channel
(HINT: SINGLE, SET-UP and REDUCED TRANSFER)
4. Define a CPU (or DMA) "view".
5. Explain the difference between the LTU and the rest
of the I/O modules.
6. Explain the major differences between the floppy disc
controller and the rest of the I/O modules
(HINT: ON-BOARD-MEMORY)
7. Can the CPU access any modules on the Channel Bus?
If yes - which module, and how. If No - why not.
…0f… 2869A/ktd
JJD/830216
CR80 REVIEW Week 8
CAMPS…0e…
8. Explain the interrupt transmission system in the CR80
(use drawing A).
9. Describe the MAP interrupt h̲a̲n̲d̲l̲i̲n̲g̲ in the CR80.
10. How does an I/O module recognize when it is addressed?
11. Explain CPU states system and user.
12. Explain the CACHE principle.
13. Explain the program - process concept used in the CR80.
14. Explain (in reasonable detail) what happens when power
is switched on in A) PU and B) CU.
15. List the 4 events that will cause a Master Clear in
the PU.
