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⟦1fbad8054⟧ Wang Wps File
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Types: Wang Wps File
Notes: CPS/SDS/050
Names: »4595A «
Derivation
└─⟦ea7a1ecf3⟧ Bits:30006190 8" Wang WCS floppy, CR 0437A
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WangText
2…06…1…0b…1…02…0…08…0…0f…0 /…0a…/…01….…08….…0c….…00…. -…08…-…0b…-…00…-
,…09…,…00…,
+…09…+…0d…+…86…1
…02…
…02… …02…
…02…CPS/SDS/050
…02…851220…02……02…
CAMPS LITSYNC
FIRMWARE
DETAILED DESIGN
SPECIFICATION…02……02…CAMPS
7.23 P̲R̲O̲C̲E̲D̲U̲R̲E̲ ̲H̲O̲S̲T̲ ̲A̲C̲K̲
F̲U̲N̲C̲T̲I̲O̲N̲
This Procedure sends ACK blocks for reception blocks
which the host has acknowledged as receiving. It handles
both LCB and data.
E̲N̲T̲R̲Y̲
Called by HIF ̲COMMAND
D̲E̲S̲C̲R̲I̲P̲T̲I̲O̲N̲
HOST ̲ACK(CHANNO,INDEX):
/*CHECK IF HOST IS ACKNOWLEDGING LCB*/
IF BUFFER(INDEX).Pl .EQ. LCB ̲LDU(CHANNO) THEN
/*FORMAT ACKL*/
FRAME = ACKL ̲ADDR(CHANNO);
FRAME.C1 = ACKL ̲SIZE ̲L;
FRAME.C2 = ACKL ̲SIZE ̲M;
FRAME.TYPE = ACKL;
FRAME.BID = LCB ̲SEQ(CHANNO);
SET XSTATE7 ̲HEADER(CHANNO);
/* SET RECEIVER TO ACCEPT NEXT LCB */
R ̲L ̲ STATE(CHANNO) = ACCEPT;
/* RETURN EMPTY CONTROL BLOCK TO HOST */
PUSH(INDEX, CHANNO, HOST ̲EMPTIES);
CLEAR(INDEX);
LCB ̲LDU(CHANNO) = NULL;
RETURN;
ELSE
/* DATA SEGMENT */
/* VERIFY CORRECT LDU */
IF BUFFER(INDEX).P1 = LDU ̲DATA ̲1(CHANNO) THEN
/* FORMAT BLOCK */
PTR = ACK ̲ADDR(CHANNO).ACK ̲IN;
FRAME = ACK ̲BASE+(ACK ̲ADDR(CHANNO).ACK ̲INxFRAME
̲SISE);
FRAME.C1 = ACK ̲SIZE#L;
FRAME.C2 = ACK ̲SIZE ̲M;
FRAME.TYPE = ACK;
ACK ̲CIRCLE(PTR) = EOS ̲1(CHANNO);
FRAME.BID = EOS ̲1(CHANNO);
/* UPDATE INTERNAL POINTERS */
LAST ̲ACKED(CHANNO) = EOS ̲1(CHANNO);
EOS ̲1(CHANNO) = EOS ̲2(CHANNO);
EOS ̲2(CHANNO) = NULL;
EOS ̲1COMPLETION = EOS ̲2 ̲COMPLETION
EOS2 ̲COMPLETION = FALSE;
INCREMENT ACK ̲ADDR(CHANNO).ACK ̲IN MOD ACK ̲TAB ̲LEN;
LDU ̲DATA ̲1(CHANNO) = LDU ̲DATA ̲2(CHANNO);
LDU ̲DATA ̲2(CHANNO) = NULL;
PUSH(CHANNO,INDEX,DISCARD ̲CTRL);
RETURN;
ELSE
CALL STATE ̲ERROR(CHANNO,INDEX,LDU ̲ERR);
RETURN;
END /* HOST ̲ACK */
7.24 P̲R̲O̲C̲E̲D̲U̲R̲E̲ ̲I̲N̲I̲T̲ ̲H̲O̲S̲T̲ ̲B̲U̲F̲F̲E̲R̲S̲
F̲U̲N̲C̲T̲I̲O̲N̲
To initialize the buffers associated with 2 LTU channels.
E̲N̲T̲R̲Y̲
Called at startup of system.
D̲E̲S̲C̲R̲I̲P̲T̲I̲O̲N̲
INIT ̲HOST ̲BUFFERS
initialize buffers for STKEMP
initialize buffers for HSTEMP
initialize buffers for HRXSTK
initialize buffers for STKTXE
initialize buffers for STKRXE
RETURN
7.25 P̲R̲O̲C̲E̲D̲U̲R̲E̲ ̲I̲N̲I̲T̲ ̲H̲O̲S̲T̲I̲F̲
F̲U̲N̲C̲T̲I̲O̲N̲
Initialize Host interface area
Called at startup of system.
D̲E̲S̲C̲R̲I̲P̲T̲I̲O̲N̲
INIT ̲HOSTIF:
For all channels do
IF ̲TS1:=ENABLED;
IF ̲TS2:=DISABLED
IF ̲RS1:=ENABLED;
IF ̲RS2:=DISABLED;
/* END FOR */
7.26 P̲R̲O̲C̲E̲D̲U̲R̲E̲ ̲I̲N̲I̲T̲I̲A̲T̲E̲ ̲T̲R̲A̲N̲S̲M̲I̲S̲S̲I̲O̲N̲
F̲U̲N̲C̲T̲I̲O̲N̲
Called by XMITER to initiate transmission
D̲E̲S̲C̲R̲I̲P̲T̲I̲O̲N̲
INITTX:
TXBUF ̲PT:= buffer pointer
TXBUF ̲CNT:= buffer count
convert 16 bit count into 14 bit in C1,C2
enable SI0 transmitter
enable TX interrupt
CALL TXINT ̲1
RETURN;
7.27 P̲R̲O̲C̲E̲D̲U̲R̲E̲ ̲L̲E̲V̲E̲L̲1̲ ̲C̲L̲O̲S̲E̲
F̲U̲N̲C̲T̲I̲O̲N̲
To disable level 1.
D̲E̲S̲C̲R̲I̲P̲T̲I̲O̲N̲
LEVEL1 ̲CLOSE(CHANNO):
adjust clock selection reflecting the close
L1 ̲STAT:= SYN8;
LO ̲STAT:= 4;
reset DTR;
reset RTS;
RSYN:= IDLE;
RETURN;
7.28 P̲R̲O̲C̲E̲D̲U̲R̲E̲ ̲L̲1̲H̲A̲N̲D̲L̲
F̲U̲N̲C̲T̲I̲O̲N̲
This task supports the remote tare DTE handshake handling.
It is scheduled periodically and goes through a sequence
of states.
D̲E̲S̲C̲R̲I̲P̲T̲I̲O̲N̲
L1HANDL:
update DSR status
JP (RSYN)/*go to current state */
Idle state:
RE ̲O:
RETURN;
Begin link setup procedure, set 108 ON
RE ̲1:
set 108 ON (DTR)
L1CNT:=5; /*retry count */
L1STAT:=SYN1;
RSYN:=RE ̲2;
RETURN;
Wait for 107 or 109 to turn ON
RE ̲2:
IF DSR is UP then
set RTS ON
L1STAT:= SYN3;
RSYN:= RE ̲3;
L1CNT:= 3;
ELSE
DEC(L1CNT);
IF L1CNT=0 then RSYN:=RE ̲6;
IF DCD is not set then
L1STAT:= SYN7;
RSYN:= RE ̲4;
L1CNT:= 5;
send MANUAL SYNC report
END /*DCD not SET */
END /*DSR not UP */
Waiting for DCD to turn ON
RE ̲3:
IF DCD is ON then
L1CNT.= 5;
RSYN:= RE ̲4
ELSE
/*DCD is DOWN */
DEC(L1CNT);
IF L1CNT = 0 then RSYN:=RE ̲6
END /*DCD is DOWN */
Waiting for CTS to turn ON
RE ̲4:
IF CTS is UP then
L1STAT:= SYN4;
RSYN:= RE ̲5;
SCHED(L1HANDL,CHANNO,LEV1TO);
ELSE
/*CTS is not UP */
DEC(L1CNT);
IF L1CNT=0 then RSYN:=RE ̲6;
END /*CTS is not UP */
Link is UP - monitor handshake interface signals.
RE ̲5:
IF not all signals UP then
RSYN:= RE ̲2;
L1STAT:= SYN 2;
END /* not all signals UP */
SCHED(L1HANDL, CHANNO, LEV1TO);
Try link setup again
RE ̲6:
L1STAT:= SYN5;
turn DTR and RTS OFF
DEC(SYNRET);
IF SYNRET=0 then
/*link fails to come UP */
SYNRET:= MAXSYN;
RSYN:= RE ̲0;
L1STAT:= SYN8;
CALL CLEANUP
send fatal error report
ELSE
RSYN:= RE ̲1;
END
7.29 P̲R̲O̲C̲E̲D̲U̲R̲E̲ ̲M̲O̲N̲I̲T̲O̲R̲
F̲U̲N̲C̲T̲I̲O̲N̲
Handles all scheduling functions for both channels
of the LTU.
E̲N̲T̲R̲Y̲
This procedure is executed upon a return from any of
the LTU processes. It determines the next process to
be executed and jumps to it.
D̲E̲S̲C̲R̲I̲P̲T̲I̲O̲N̲
Monitor: update the scheduling table
attempt to schedule foreground processes
attempt to schedule background processes
JUMP to MONITOR
/* MONITOR */
END; /* MONITOR */
Entry point at LTU startup
START:
initialize stackpointer
CALL INHARD
CALL INITHB
CALL INIT ̲IF ̲AREA
JP MONITOR
7.30 P̲R̲O̲C̲E̲D̲U̲R̲E̲ ̲M̲O̲V̲E̲ ̲D̲A̲T̲A̲
F̲U̲N̲C̲T̲I̲O̲N̲
To mode data from a host segment buffer to an LTU block
buffer, the following global variables apply:
DATA ̲SRC(CHANNO) - indicates the location of data
within the segment buffer;
DATA ̲DEST(CHANNO) - indicates the location of data
within the block buffer;
T ̲BYTECOUNT(CHANNO)- indicates bytes left to be moved
P ̲INDEX(CHANNO) - number of words to be moved
This procedure moves a maximum of MAX ̲BLOCK bytes before
existing to allow other procedures to execute. On exit
this procedure either reschedules itself or schedules
STORE ̲SEC ̲BUFFER.
E̲n̲t̲r̲y - called by SOTRE ̲SEC ̲BUFFER.
D̲E̲S̲C̲R̲I̲P̲T̲I̲O̲N̲
MOVE ̲DATA(CHANNO):
/* DETERMINE IF ENTIRE BLOCK HAS BEEN TRANSFERRED */
IF P ̲INDEX(CHANNO) .NE. ZERO THEN
FOR COUNT = 0 TO MIN(MOVE ̲MAX,P ̲INDEX(CHANNO));
DATA ̲DEST(CHANNO) = DATA ̲SRC(CHANNO);
INCREMENT DATA ̲DEST(CHANNO);
INCREMENT DATA ̲SRC(CHANNO);
DECREMENT T ̲BYTECOUNT(CHANNO);
END
SCHEDULE (MOVE ̲DATA,CHANNO);
RETURN;
ELSE
SCHEDULE (MOVE ̲SEC ̲BUFFER,CHANNO);
RETURN;
END; /* MOVE ̲DATA */
7.31 P̲R̲O̲C̲E̲D̲U̲R̲E̲ ̲M̲O̲V̲E̲ ̲R̲X̲ ̲D̲A̲T̲A̲
F̲U̲N̲C̲T̲I̲O̲N̲
To move data from a receiver buffer identified as the
source to the gather area.
Insert pointer into the pending table.
D̲E̲S̲C̲R̲I̲P̲T̲I̲O̲N̲
MOVE ̲RX ̲DATA(INDEXS,CHANNO):
update pending table entry
LOOP:
find free GATHER bit
move data
IF not finished then
GOTO LOOP
END /*LOOP*/
update:
EOS ̲1, EOA ̲2, EOS ̲1I, EOS ̲2I, EOS ̲1C, EOS ̲"C
INC(EOSCNT)
END /*MOVE ̲RX ̲DATA*/
7.32 P̲R̲O̲C̲E̲D̲U̲R̲E̲ ̲O̲P̲E̲N̲ ̲C̲O̲M̲P̲L̲E̲T̲E̲
F̲U̲N̲C̲T̲I̲O̲N̲
Sends status block to host showing that OPEN ̲EDC COMMAND
has been executed and the line is up.
E̲N̲T̲R̲Y̲
Called by RX ̲DISPATCH.
D̲E̲S̲C̲R̲I̲P̲T̲I̲O̲N̲
OPEN ̲COMPLETE(CHANNO):
TEMP = POP(STACK ̲OF ̲EMPTIES ̲RX,CHANNO);
BUFFER(TEMP).TYPE = SIGNLE ̲LDU ̲STATUS;
BUFFER(TEMP).CODE = CHANNEL ̲STATUS;
BUFFER(TEMP).LDU#ID = OPEN ̲LDU(CHANNO);
OPEN ̲LDU(CHANNO) = NULL;
BUFFER(TEMP).COMMAND = OEPN ̲EDC;
BUFFER(TEMP). P1 = 0;
PUSH(INDEX,STATUS ̲RETURN,CHANNO);
LTU ̲ST:= RUNNING;
RETURN
END; /* OPEN ̲COMPLETE */
7.33 P̲R̲O̲C̲E̲D̲U̲R̲E̲ ̲O̲P̲E̲N̲ ̲E̲D̲C̲
F̲U̲N̲C̲T̲I̲O̲N̲
This procedure may be called by the host to initiate
LEVEL 1 and EDC protocol or it may be called by the
host after LEVEL 1 has been initialized by manual sync,
to initialize only the EDC protocol. If LEV1 ̲STATE
= SYN6 then both levels must be initialized. If LEV1
̲STATE = SYN4 then only the EDC is to be initialized.
This procedure exists after setting all state tables
and scheduling the XMITTER. The XMITTER will attempt
to send SETB. A response to the OPEN ̲EDC command will
be sent to the host when one of the following occurs:
1) ACK is received for SETB and a SETB has already
been received;
2) SETB is received and ACK has previously been received
in response to SETB;
3) Error status results from LEV1 synchronization
(RE ̲SYNCHRONIZER);
4) Close command is received from host;
5) ACKTO expires the maximum number of times;
D̲E̲S̲C̲R̲I̲P̲T̲I̲O̲N̲
OPEN ̲EDC(CHANNO):
LTU ̲STATE(CHANNO) = OPENING;
TSTATE(CHANNO) = TSTATE1;
/* SCHEDULE SETB BLOCK */
FRAME = SETB ̲ADDR(CHANNO);
FRAME.C1 = SETB ̲SIZE ̲L;
FRAME.C2 = SETB ̲SIZE ̲M;
FRAME.BID = ZERO;
FRAME.TYPE = SETB;
/*SCHEDULE RR BLOCK */
FRAME = RR ̲ADDR(CHANNO);
FRAME.C1 = RR ̲SIZE ̲L;
FRAME.C2 = RR ̲SIZE ̲M
FRAME.BID = ZERO
FRAME.TYPE = RR;
ACK ̲ONE(CHANNO) = NULL;
NEXT ̲ACK(CHANNO) = ONE;
CLEAR RCOUNT(CHANNO);
OPEN ̲LDU(CHANNO) = BUFFER(INDEX).LDU ̲ID;
NEXT ̲EXPECTED(CHANNO) = NULL ̲1;
SET XSTATE8 ̲HEADER(CHANNO);
SET XSTATE7 ̲HEADER(CHANNO);
SET ̲XMIT ̲PRIORITY(XSTATE8);
SCHEDULE(ACKTO,CHANNO,ACKTO ̲DELTA);
LEV1 ̲STATE(CHANNO) = SYN0;
CALL RE ̲SYNCHRONIZER(CHANNO);
CALL HIF ̲COMMAND ̲RETURN(CHANNO,INDEX);
END; /* OPEN ̲EDC */
7.34 P̲R̲O̲C̲E̲D̲U̲R̲E̲ ̲P̲O̲P̲L̲
F̲U̲N̲C̲T̲I̲O̲N̲
Remove item from stack.
7.35 P̲R̲O̲C̲E̲D̲U̲R̲E̲ ̲P̲U̲S̲H̲L̲
F̲U̲N̲C̲T̲I̲O̲N̲
Insert item on stack.
7.36 P̲R̲O̲C̲E̲D̲U̲R̲E̲ ̲P̲O̲P̲S̲
F̲U̲N̲C̲T̲I̲O̲N̲
Remove item from queue.
7.37 P̲R̲O̲C̲E̲D̲U̲R̲E̲ ̲P̲U̲S̲H̲S̲
F̲U̲N̲C̲T̲I̲O̲N̲
Insert item in queue.
7.38 P̲R̲O̲C̲E̲D̲U̲R̲E̲ ̲Q̲U̲E̲U̲E̲ ̲A̲C̲K̲
F̲U̲N̲C̲T̲I̲O̲N̲
To format an ACK block for transmission. The bid is
identical to the last ACK transmitted.
D̲E̲S̲C̲R̲I̲P̲T̲I̲O̲N̲
QUEUE ̲ACK(CHANNO):
PTR = ACK ̲ADDR(CHANNO).ACK ̲IN;
FRAME = ACK ̲BASE+(ACK ̲ADDR(CHANNO),ACK ̲IN*FRAME ̲SIZE);
FRAME.C1 = ACK ̲SIZE ̲L;
FRAME.C2 = ACK ̲SIZE ̲M;
FRAME.TYPE = ACK;
FRAME.BID = LAST ̲ACKED(CHANNO);
ACK ̲CIRCLE(PTR) = LAST ̲ACKED(CHANNO);
INCREMENT ACK ̲ADDR(CHANNO).ACK ̲IN MOD ACK ̲TAB ̲LEN;
RETURN;
END; /* QUEUE ̲ACK */
7.39 P̲R̲O̲C̲E̲D̲U̲R̲E̲ ̲Q̲U̲E̲U̲E̲ ̲L̲C̲B̲
F̲U̲N̲C̲T̲I̲O̲N̲
To format an LCB block for transmission by the XMITTER.
E̲N̲T̲R̲Y̲
Called by HIF ̲TX ̲IN
D̲E̲S̲C̲R̲I̲P̲T̲I̲O̲N̲
QUEUE ̲LCB(CHANNO,INDEX):
LCB ̲INDEX(CHANNO) = INDEX;
SET LCB ̲IN ̲PROGRESS(CHANNO) = TRUE;
CLEAR LCOUNT(CHANNO);
/* PLACE LCB LENGTH IN XMITTER TABLE */
LCB ̲ADDR(CHANNO).ADDR = BUFFER(INDEX).ADDRESS;
LCB ̲ADDR(CHANNO).LEN = BUFFER(INDEX).BYTECOUNT;
/* INITIALIZE FRAME HEADER */
BUFFER(INDEX).C1 = BUFFER(INDEX).BYTECOUNT1;
BUFFER(INDEX).C2 = BUFFER(INDEX).BYTECOUNT2;
BUFFER(INDEX).TYPE = LCB;
BUFFER(INDEX).BID = LCB#BID(CHANNO);
SCHEDULE(ACKLTO,CHANNO);
SET XSTATE2 ̲HEADER(CHANNO);
CALL SET ̲XMIT ̲PRIORITY(CHANNO,XSTATE2);
RETURN;
END; /*QUEUE ̲LCB */
7.40 P̲R̲O̲C̲E̲D̲U̲R̲E̲ ̲Q̲U̲E̲U̲E̲ ̲N̲A̲K̲
F̲U̲N̲C̲T̲I̲O̲N̲
To queue NAK blocks to the XMITTER.
E̲N̲T̲R̲Y̲
Called by RX ̲DISPATCH.
D̲E̲S̲C̲R̲I̲P̲T̲I̲O̲N̲
QUEUE ̲NAK(BID,CHANNO):
SET NAK ̲AVAIL(CHANNO);
INDEX = NAK ̲ADDR(CHANNO).NAK ̲IN;
INCREMENT NAK ̲ADDR(CHANNO).NAK ̲IN MODULO NAK ̲TABLE#LEN;
IF BID = (NEXT ̲EXPECTED(CHANNO)+1) MOD O ̲T ̲E THEN
/* SEND NAKI */
BUFFER(INDEX).BID = BID;
BUFFER(INDEX).TYPE = TYPE ̲1;
BUFFER(INDEX).LEN = FOUR;
ELSE
/* SEND NAKIJ */
NAK ̲CIRCLE(CHANNO,INDEX) = TYPE ̲2;
BUFFER(INDEX).BID1 = NEXT ̲EXPECTED(CHANNO);
BUFFER(INDEX).TYPE = TYPE ̲2;
BUFFER(INDEX).LEN = FIVE;
CALL SET ̲XMIT ̲PRIORITY(CHANNO,XSTATE5);
RETURN;
END; /* QUEUE ̲NAK */
7.41 P̲R̲O̲C̲E̲D̲U̲R̲E̲ ̲Q̲U̲E̲U̲E̲ ̲N̲A̲K̲F̲
F̲U̲N̲C̲T̲I̲O̲N̲
To queue NAKF block to XMITTER, and set internal flags.
E̲N̲T̲R̲Y̲
Called by RX ̲DISPATCHER.
D̲E̲S̲C̲R̲I̲P̲T̲I̲O̲N̲
QUEUE ̲NAKF(CHANNO,BID):
SET NAK ̲AVAIL(CHANNO);
INDEX = NAK ̲ADDR(CHANNO).NAK ̲IN;
NAK ̲CIRCLE(CHANNO,INDEX) = TYPE3,
NEXT ̲EXPECTED(CHANNO) = LAST ̲GOOD(CHANNO);
R ̲STATE(CHANNO) = NAKF;
BUFFER(INDEX).BID = BID;
BUFFER(INDEX).TYPE = TYPE ̲3;
BUFFER(INDEX).LEN = FOUR;
SET ̲XMIT ̲PRIORITY(CHANNO,XSTATE5);
END; /* QUEUE ̲NAKF */
7.42 P̲R̲O̲C̲E̲D̲U̲R̲E̲ ̲Q̲U̲E̲U̲E̲ ̲S̲T̲A̲T̲U̲S̲
F̲U̲N̲C̲T̲I̲O̲N̲
To format a status buffer for return to the host.
D̲E̲S̲C̲R̲I̲P̲T̲I̲O̲N̲
If ERROR ̲CODE = 0 then a TXCANCEL is reported else
an asynchroneous report.
QUEUE ̲STATUS(CHANNO,LDU,ERROR ̲CODE):
TEMP = POP(CHANNO,STACK ̲OF ̲EMPTIES ̲RX);
BUFFER(TEMP).TYPE = SINGLE ̲LDU ̲STATUS;
IF ERROR ̲CODE.NE.0 THEN
BUFFER(TEMP).CODE = ASUNCHRONEOUS ̲REPORT;
BUFFER(TEMP).COMMAND = STAT;
BUFFER(TEMP).LDU ̲ID = NULL;
BUFFER(TEMP)P1 = ERROR ̲CODE;
ELSE
BUFFER(TEMP).CODE = TRANSMISSION ̲STATUS;
BUFFER(TEMP).COMMAND = TX ̲CANCELLED;
BUFFER(TEMP).LDU ̲ID = LDU;
PUSH(TEMP,CHANNO,STATUS ̲RETURN);
END; /* QUEUE ̲STATUS */
7.43 P̲R̲O̲C̲E̲D̲U̲R̲E̲ ̲R̲E̲D̲E̲F̲I̲N̲E̲ ̲P̲A̲R̲A̲M̲E̲T̲E̲R̲S̲
F̲U̲N̲C̲T̲I̲O̲N̲
To modify internal parameters used by the protocol,
and to validate these parameters.
E̲N̲T̲R̲Y̲
Called by HIF ̲COMMAND.
D̲E̲S̲C̲R̲I̲P̲T̲I̲O̲N̲
REDEFINE ̲ PARAMETERS (CHANNO, INDEX):
/*VERIFY AND STORE BLOCKSIZE*/
DO CASE OF CONTROL(INDEX).Pl)
ZERO: CLOCK ̲SIZE = 32 ̲BYTES;
CONTINUE;
ONE: BLOCK ̲SIZE = 64 ̲BYTES;
CONTINUE
TWO: BLOCK ̲SIZE = 128 ̲BYTES;
CONTINUE;
THREE: BLOCK ̲SIZE = 256 ̲BYTES;
CONTINUE;
FOUR: BLOCK ̲SIZE = 512 ̲BYTES;
CONTINUE;
DEFAULT:CALL RED ̲ERROR(CHANNO,INDEX,R8):
RETURN;
/* STORE ACK TOMEOUT AND ACKL TIMEOUT */
ACKTO ̲DELTA = CONTROL(INDEX).P2
ACKLTO ̲DELTA = CONTROL(INDEX).P3
/* VERIFY AND STORE BLOCK RETRY COUNT */
IF (CONTROL(INDEX.P5.GT.BLOCK ̲RETRY ̲MAX.OR.(CONTROL
(INDEX).P5.LT.BLOCK ̲RETRY ̲MIN) THEN
CALL RED ̲ERROR(CHANNO,INDEX,R9);
RETURN;
ELSE NCOUNT ̲MAX = CONTROL(INDEX).P5;
/*VERIFY AND STORE LCB RETRY COUNT */
IF (CONTROL(INDEX).P6.GT.LCB ̲RETRY ̲MAX) .OR. (CONTROL(INDEX).P6.LT.LCB
̲RETRY ̲MIN) THEN
CALL RED ̲ERROR/CHANNO,INDEX,R10);
RETURN;
ELSE LCOUNT ̲MAX = CONTROL(INDEX).P6;
/*VERIFY AND STORE RR RETRY COUNT*/
IF (CONTROL(INDEX).P7.GT.RR ̲RETRY ̲MAX) .OR. (CONTROL(INDEX).P7.LT.RR
̲RETRY ̲MIN) THEN
CALL RED ̲ERROR(CHANNO;INDEX;R11);
RETURN;
ELSE
RCOUNT ̲MAC = CONTROL(INDEX).P7;
/*RED ̲ERROR WILL RETURN HOST BUFFER*/
CALL RED ̲ERROR(CHANNO;INDEX;R0);
END; /*REDEFINE ̲PARAMETERS*/
7.44 P̲R̲O̲C̲E̲D̲U̲R̲E̲ ̲R̲E̲D̲ ̲E̲R̲R̲O̲R̲
F̲U̲N̲C̲T̲I̲O̲N̲
This procedure formats a status buffer to be returned
to the host; also if an error is found in the new parameters
for the EDC protocol.
E̲N̲T̲R̲Y̲
Called by REDEFINE ̲PARAMETERS
D̲E̲S̲C̲R̲I̲P̲T̲I̲O̲N̲
RED ̲ERROR(CHANNO,INDEX,CODE):
/*ALLOCATE STATUS BUFFER */
TEMP = POP(CHANNO,STACK ̲OF ̲EMPTIES ̲RX);
BUFFER(TEMP).TYPE = SINGLE ̲LDU ̲STATUS;
BUFFER(TEMP).CODE = CHANNEL ̲STATUS;
BUFFER(TEMP).P1 = CODE;
PUSH(TEMP,CHANNO,STATUS ̲RETURN);
CLEAR(INDEX);
/*RETURN HOST BUFFER */
PUSH(INDEX,CHANNO,HOST ̲EMPTIES);
RETURN;
END; /* RED ̲ERROR */
7.45 P̲R̲O̲C̲E̲D̲U̲R̲E̲ ̲R̲E̲S̲Y̲N̲C̲H̲R̲O̲N̲I̲Z̲E̲R̲
F̲U̲N̲C̲T̲I̲O̲N̲
This procedure supports the level 1 protocol either
local or remote Tare.
The procedure is called by OPEN ̲EDC to open the Tare
channel, by CTS shift to handle a manual SYNS, or by
DCD shift to handle DCD lost condition.
RE ̲SYN:
IF L1STAT .NE. SYN8 THEN
SYNRET:= MAXSYN;
IF IF ̲STAT = LOCAL THEN
L0STAT:= 2;
set DTR
set RTS
L0STAT:= 3;
L1STAT:= SYN4;
ELSE
/* remote Tare */
RSYN:= 1;
SCHED(L1HANDL,CHANNO);
RETURN;
7.46 P̲R̲O̲C̲E̲D̲U̲R̲E̲ ̲R̲E̲L̲E̲A̲S̲E̲ ̲B̲U̲F̲F̲E̲R̲(̲C̲H̲A̲N̲N̲O̲)̲
I̲n̲p̲u̲t̲
CHANNO.
F̲U̲N̲C̲T̲I̲O̲N̲
This function frees buffers which have been queued
to the XMITTER. In other words it performs output completion
for buffers which have been queued for transmission.
A buffer is released by resetting the "outstanding"
flag associated with the buffer. This indicates to
the sending procedure that the XMITTER has released
control of the buffer.
Outstanding flags are determined by the type of the
buffer. The buffer type is reflected in the XSTATE
associated with the buffer and is stored in the variable
CURRENT ̲TRANSMISSION(CHANNO). Any information needed
to release the buffer is stored in the tables associated
with XSTATE such as XSTATE ̲HEADER and XSTATE ̲ADDR.
D̲E̲S̲C̲R̲I̲P̲T̲I̲O̲N̲
RELEASE ̲BUFFER: XMIT ̲IN ̲PROGRESS = RESET;
DO CASE OF (CURRENT ̲TRANSMISSION(CHANNO))
XSTATE8: RESET XSTATE8 ̲HEADER(CHANNO);
RETURN,
XSTATE7: RESET XSTATE7 ̲HEADER(CHANNO);
RETURN;
XSTATE6: RESET XSTATE6 ̲HEADER(CHANNO);
RETURN;
XSTATE5: DISABLE INTERRUPTS;
INCREMENT NAK ̲CIRCLE(CHANNO).NAK ̲OUT MODULO
NAK ̲TAB ̲LEN;
IF finished then
RESET XSTATE5 ̲HEADER(CHANNO);
ENBALE INTERRUPTS;
RETURN;
XSTATE4: DISABLE INTERRUPTS;
INCREMENT ACK ̲CIRCLE(CHANNO).ACK ̲OUT
MODULO ACK ̲TAB ̲LEN;
IF finished then
RESET XSTATE4 ̲HEADER(CHANNO)
ENABLE INTERRUPTS;
RETURN;
XSTATE3: TEMP = RETRAN ̲ADDR(CHANNO).RETRAN ̲OUT;
INCREMENT RETRAN ̲ADDR(CHANNO).RETRAN ̲OUT
MODULO RETRAN ̲CIRCLE.LEN;
IF RETRAN ̲ADDR(CHANNO).RETRAN ̲OUT .EQ.
RETRAN ̲ADDR(CHANNO).RETRAN ̲IN THEN
RESET XSTATE3 ̲HEADER(CHANNO);
TEMP2=RETRANCIRCLE(CHANNO,TEMP).TRAN ̲CIRCLE
̲OFFSET;
RESET TRAN ̲CIRCLE(CHANNO).OUTSTANDING
(TEMP2);
RETURN;
XSTATE2: TEMP=TRAN ̲ADDR(CHANNO).TRAN ̲OUT;
INCREMENT TRAN ̲ADDR(CHANNO).TRAN ̲OUT MODULO
XMIT ̲CIRCLE ̲LEN;
IF TRAN ̲ADDR(CHANNO).TRAN ̲OUT .EQ;
TRAN ̲ADDR(CHANNO).TRAN ̲IN THEN
RESET XSTATE2 ̲HEADER(CHANNO);
TEMP2=XMIT ̲CIRCLE(CHANNO,TEMP).TRAN ̲CIRCLE
̲OFFSET;
IF TEMP2 .NE.NULL THEN
RESET TRAN ̲CIRCLE(CHANNO).OUTSTANDING
(TEMP2);
RETURN;
7.47 P̲R̲O̲C̲E̲D̲U̲R̲E̲ ̲R̲E̲M̲O̲V̲E̲ ̲E̲L̲E̲M̲E̲N̲T̲
F̲U̲N̲C̲T̲I̲O̲N̲
Removes an item from a queue
7.48 P̲R̲O̲C̲E̲D̲U̲R̲E̲ ̲R̲E̲ ̲Q̲U̲E̲U̲E̲ ̲L̲C̲B̲(̲C̲H̲A̲N̲N̲O̲)̲
F̲U̲N̲C̲T̲I̲O̲N̲
To initialize an LCB Block for transmission by XMITTER.
E̲N̲T̲R̲Y̲
Called by ACKLTO.
D̲E̲S̲C̲R̲I̲P̲T̲I̲O̲N̲
RE ̲QUEUE ̲LCB(CHANNO):
RETRAN ̲CIRCLE(CHANNO,RETRAN ̲IN).ADDR=BUFFER(INCEX).ADDR;
RETRAN ̲CIRCLE(CHANNO,RETRAN ̲IN).LEN=BUFFER(INDEX).
BYTECOUNT;
RETRAN ̲CIRCLE(CHANNO,RETRAN ̲IN).OFFSET = NULL;
INCREMENT RETRAN ̲IN(CHANNO) MOD RETRAN ̲CIRCLE ̲LEN;
INCREMENT LCOUNT(CHANNO);
SCHEDULE(ACKLTO,CHANNO);
SET XSTATE3 ̲HEADER(CHANNO);
/* UPDATE STATISTICS */
INCREMENT TX ̲R ̲L ̲COUNT(CHANNO);
CALL SET ̲XMIT ̲PRIORITY(CHANNO,XSTATE3);
RETURN;
END; /* RE ̲QUEUE ̲LCB */
7.49 P̲R̲O̲C̲E̲D̲U̲R̲E̲ ̲R̲E̲P̲O̲R̲T̲ ̲P̲R̲O̲T̲O̲C̲O̲L̲
F̲U̲N̲C̲T̲I̲O̲N̲
This procedure returns to the host the state of the
LEVEL1 and EDC protocol.
E̲N̲T̲R̲Y̲
Called by HIF ̲COMMAND.
D̲E̲S̲C̲R̲I̲P̲T̲I̲O̲N̲
REPORT ̲PROTOCOL(CHANNO,INDEX):
POP(STACK ̲OF ̲EMPTIES ̲RX,INDEX,CHANNO);
BUFFER(INDEX).TYPE=SINGLE ̲LTU ̲STATUS;
BUFFER(INDEX).CODE=CHANNEL ̲STATUS;
BUFFER(INDEX).P2=LEV1 ̲STATE(CHANNO);
DO CASE OF (LTU ̲STATE(CHANNO))
DISABLED: EDC ̲STATE = 0DISABLED;
END; /* CASE 1 */
ENABLED: EDC ̲STATE = 1CLOSED;
END; /* CASE 2 */
INITIALIZED: IF LEV1 ̲STATE .EQ. SYN4 THEN
EDC ̲STATE = 2 ̲LEVEL ̲ONE ̲ENABLED;
ELSE
EDC ̲STATE = 3 ̲RECEIVER ̲STARTUP;
END; /* CASE 3 */
OPENING: EDC ̲STATE = OPENING;
BUFFER(INDEX).P1 = TSTATE;
END; /* CASE 4 */
RUNNING: EDC ̲STATE = RUNNING;
END; /* CASE 5 */
ERROR: EDC ̲STATE =7 ̲EDC ̲CLOSE ̲ERROR;
END /* CASE 6 */
CLOSE: EDC ̲STATE = 8 ̲CLOSE;
END; /* CASE 7 */
BUFFER(INDEX).P3 =EDC ̲STATE;
PUSH(INDEX,CHANNO,STATUS ̲RETURN);
CLEAR(INDEX); PUSH(HSTEMP,INDEX,CHANNO);
RETURN
END;
7.50 P̲R̲O̲C̲E̲D̲U̲R̲E̲ ̲R̲X̲ ̲D̲I̲S̲P̲A̲T̲C̲H̲E̲R̲
F̲U̲N̲C̲T̲I̲O̲N̲
This procedure dispatches received buffers which have
been placed in the INPUT ̲QUEUE. All buffers in the
INPUT&QUEUE have no parity error in the length, type
or bid. The CRC may or may not be correct. This status
is indicated in the field CRC ̲STATUS in the BUFFER
̲HEADER.
NOTE: BID = BUFFER(INDEX). BID:
NEXT ̲EXPECTED = NEXT ̲EXPECTED(CHANNO);
LAST ̲ACKED = LAST ̲ACTED(CHANNO).
D̲E̲S̲C̲R̲I̲P̲T̲I̲O̲N̲
RX ̲DISPATCH(CHANNO):
IF INPUT ̲QUEUE(CHANNO) .NE. EMPTY THEN
REMOVE BUFFER INDEX FROM INPUT ̲QUEUE(CHANNO);
IF CRC ̲STATUS .EQ. ERROR THEN
IF BUFFER(INDEX). TYPE .EQ. (D.OR.EOS.OR.EOM) THEN
IF EOS ̲COUNT(CHANNO) .LT. TWO
/* NOT MAXIMUM SEGMENTS */
IF BUFFER(INDEX).BID .EQ. NEXT ̲EXPECTED(CHANNO)
THEN QUEUE ̲NAK(BID,CHANNO):
PUSH (INDEX,STACK ̲OF ̲EMPTIES ̲RX);
RETURN;
ELSE /* VERIFY THAT BID IS RETRANSMITTED */
IF (NEXT ̲EXPECTED-BID) MOD 128 .LT.
(NEXT&EXPECTED)(CHANNO)-LAST ̲ACKED) MOD 128
THEN CALL SERVICE ̲INVALID ̲RETRANSMISSIONS
(CHANNO,INDEX);
RETURN:
ELSE /* OUT OF RANGE, IGNORE */
PUSH(INDEX,STACK ̲OF ̲EMPTIES ̲RX,CHANNO);
ELSE /* MAXIMUM SEGMENTS */
IF (NEXT ̲EXPECTED(CHANNO)-BID) MOD O ̲T ̲E .LT.
(NEXT ̲EXPECTED(CHANNO)-LAST ̲ACKED)(CHANNO)
MOD O ̲T ̲E THEN
CALL SERVICE ̲INVALID ̲RETRANS MISSIONS
(CHANNO,INDEX);
RETURN;
ELSE
PUSH(INDEX,CHANNO,STACK ̲OF ̲EMPTIES ̲RX);
RETURN;
ELSE /* NO CRC ERROR */
*/ HANDLE BUFFER TYPE = DATA,LCB,SETF,RR,LCB,ACK,
NAK,ACKL */
DO CASE OF (BUFFER(INDEX).TYPE)
D̲A̲T̲A̲:̲
/* HANDLE DATA BUFFER */
DO CASE OF R ̲STATE(CHANNO));
/* R ̲STATE=NAKF, RECEIVER HAS SENT NAKF, EXPECTS
TO SEE NEXT ̲EXPECTED */
N̲A̲K̲F̲:̲ IF BUFFER (INDEX).BID .EQ. NEXT ̲EXPECTED
(CHANNO) THEN
CALL SERVICE ̲NEXT ̲EXPECTED(CHANNO,INDEX);
RETURN;
ELSE
PUSH (INDEX,STACK ̲OF ̲EMPTIES ̲RX);
RETURN;
END; /* CASE OF NAKF */
/* R ̲STATE=MAX ̲SEGMENTS, TWO SEGMENTS HAVE BEEN RECEIVED,
IN PART, OR TOTALLY */
MAX ̲SEGMENTS: IF (NEXT ̲EXPECTED(CHANNO)-BID) MOD O
̲T ̲E .LT. NEXT ̲EXPECTED(CHANNO)-LAST
̲ACKED)
(CHANNO) MOD O ̲T ̲E THEN
/* RETRANSMISSION */
SERVICE ̲RETRANSMISSIONS(INDEX,CHANNO);
RETURN;
ELSE
/* NOT RETRY,THEREFORE, DO NOT ACCEPT
*/
PUSH(INDEX,STACK ̲OF ̲EMPTIES ̲RX,CHANNO);
RETURN;
END; /*MAX ̲SEGMENTS */
/* R ̲STATE = READY TO RECEIVE */
READY ̲TO ̲RECEIVE(INDEX,CHANNO):
IF BID = NEXT ̲EXPECTED(CHANNO) THEN
SERVICE ̲NEXT ̲EXPECTED(INDEX,CHANNO);
RETURN;
ELSE
/* CHECK IF RETRANSMISSION */
IF (NEXT ̲EXPECTED(CHANNO)-BID) MOD O ̲T ̲E .LT.
(NEXT ̲EXPECTED(CHANNO)-LAST ̲ACKED) MOD O ̲T ̲E
THEN SERVICE ̲RETRANSMISSION(INDEX,CHANNO);
RETURN;
ELSE /* SOME BLOCKS ARE MISSING */
IF EOS ̲COUNT(CHANNO) .GT. ZERO THEN
/*WITH ONE SEGMENT RECEIVED, BID MUST BE WITHIN
16*/
IF (BID-NEXT ̲EXPECTED(CHANNO)) MOD O ̲T ̲E .LT. SIXTEEN
THEN
/* BID IS WITHIN ONE SEGMENT */
IF(BID-NEXT ̲EXPECTED(CHANNO) MOD O ̲T ̲E .LT. FOUR
THEN
TEMP=(BID-BID ̲BASE(CHANNO)) MOD THREE ̲TWO
QUEUE ̲NAK(CHANNO,BID);
INCREMENT NEXT ̲EXPECTED (CHANNO) MOD O ̲T ̲E
LAST ̲GOOD(CHANNO) = BID;
PENDING ̲TABLE(CHANNO, TEMP)=INDEX;
NEXT ̲EXPECTED(CHANNO)=(BID+1)MODULO O ̲T ̲E
IF BUFFER(INDEX) .TYPE .EQ. (EOS.OR.EOM) THEN
INCREMENT EOS ̲COUNT(CHANNO);
SET EOS ̲2(CHANNO)=BID;
SET EOS ̲2 ̲INDEX(CHANNO) = INDEX;
RSSTATE(CHANNO) = MAX ̲SEGMENTS;
RETURN;
ELSE /* INVALID BLOCK */
QUEUE ̲NAKF(CHANNO,LAST ̲GOOD(CHANNO));
RETURN;
ELSE /* OUT OF RANGE */
PUSH(INDEX,STACK ̲OF ̲EMPTIES ̲RX,CHANNO);
RETURN;
ELSE /* WITH NO SEGMENT RECEIVED, BID MUST BE WITHIN
32*/
IF (BID-NEXT ̲EXPECTED)MOD O ̲T ̲E .LT. THREE ̲TWO
/* IN RANGE, NO SEGMENTS */
IF (BID-NEXT ̲EXPECTED)MOD O ̲T ̲E .LT. FOUR THEN
TEMP=(BID-BID ̲BASE) MOD THREE ̲TWO
QUEUE ̲NAK(CHANNO;BID);
LAST ̲GOOD(CHANNO)=BID;
NEXT ̲EXPECTED=(BID+1)MODULO O ̲T ̲E
IF BUFFER(INDEX). TYPE .EQ. (EOS.OR.EOM)
THEN
INCREMENT EOS ̲COUNT(CHANNO);
SET EOS ̲1INDEX(CHANNO)=INDEX;
SET EOS ̲1(CHANNO) = BID
RETURN;
ELSE /* INVALID BLOCK */
QUEUE ̲NAKF(CHANNO,LAST ̲GOOD(CHANNO));
RETURN;
ELSE /* OUT OF RANGE, IGNORE */
PUSH(INDEX,STACK ̲OF ̲EMPTIES ̲RX);
RETURN;
END; /* CASE OF R ̲STATE = READY TO RECEIVE */
END; /* CASE OF DATA */
/* BLOCK TYPE = LCB */
LCB: /* ONE LCB AT A TIME. R ̲L ̲STATE SHOWS CURRENT
POSITION */
IF R ̲L ̲STATE(CHANNO) .EQ. ACCEPT THEN
IF BUFFER(INDEX). BID .NE. LCB ̲SEQ ̲RX(CHANNO) THEN
R ̲L ̲STATE(CHANNO) = BUSY;
LCB ̲SEQ ̲RX(CHANNO) = BUFFER(INDEX).BID;
LCB ̲INDEX ̲RX(CHANNO) = INDEX;
RETURN;
ELSE
/* RETRANSMIT ACKL */
FRAME = ACKL ̲ADDR(CHANNO);
FRAME.C1 = ACKL ̲SIZE ̲L;
FRAME.C2 = ACKL ̲SIZE ̲M;
FRAME.TYPE = ACKL;
FRAME.BID = LCB ̲SEQ(CHANNO);
SET XSTATE7 ̲HEADER(CHANNO);
PUSH(INDEX,STACK ̲OF ̲EMPTIES ̲RX,CHANNO);
RETURN;
ELSE /* IGNORE */
PUSH(INDEX,STACK ̲OF ̲EMPTIES ̲RX);
RETURN;
END; /* CASE OF LCB */
/* BLOCK TYPE = RR */
RR(J): IF NAK ̲AVAIL
/* SEND NAK */
SET XSTATE4 ̲HEADER(CHANNO)
CLEAR NAK ̲AVAIL;
SET ̲XMIT ̲PRIORITY(XSTATE5,CHANNO);
ELSE
QUEUE ̲ACK (LAST ̲ACKNOWLEDGED, CHANNO);
SET ̲XMIT ̲PRIORITY (XSTATE4,CHANNO);
/* VERIFY RR */
IF J .GT. NEXT ̲EXPECTED THEN
QUEUE ̲NAKF(CHANNO,LAST ̲GOOD(CHANNO));
SET ̲XMIT ̲PRIORITY(XSTATES5.CHANNO);
/* INCREMENT STATISTICS COUNT */
INCREMENT RX ̲RR ̲COUNT;
PUSH (INDEX,STACK ̲OF ̲EMPTIES ̲RX);
END; /* RR */
/* CASE OF SETF */
SETB(J):
/* IF NEXT ̲EXPECTED = NULL ̲2 THEN A SETB HAS BEEN
TRANSMITTED BY MY TRANSMITTER AND AN ACK RECEIVED.
THIS MEANS THAT THE TRANSMITTER IS UP AND OPEN
̲EDC IS WAITING FOR THE RECEIVER TO BE INSTALLED
VIA SETF. HERE IT IS. */
IF TSTATE = TSTATE2 THEN
IF NEXT ̲EXPECTED = NULL ̲2 THEN
CANCEL (CHANNO, ACKTO);
IF ACKTOS .EQ. PENDING THEN
CALL OPEN ̲COMPLETE(CHANNO);
TSTATE(CHANNO) = TSTATE3;
ENDIF;
ELSE /* NOT PART OF OPEN ̲EDC, MUST INFORM HOST */
INDEX2 = POP(STACK ̲OF ̲EMPTIES,CHANNO);
CALL QUEUE ̲STATUS(INCOMING ̲RESET,CHANNO);
ENDIF;
CLEAR PENDING ̲TABLE(CHANNO);
RSTATE(CHANNO) = READY ̲TO ̲RECEIVE;
CLEAR XSTATE5 ̲HEADER(CHANNO);
NAK ̲ADDR(CHANNO).NAK=ZERO;
NAK ̲ADDR(CHANNO). NAK#OUT = ZERO;
CLEAR NAK ̲AVAIL(CHANNO);
ACK ̲ADDR(CHANNO).ACK ̲IN=ZERO;
ACK ̲ADDR(CHANNO).ACK ̲OUT = ZERO;
CLEAR XSTATE4 ̲HEADER(CHANNO);
EOS ̲1(CHANNO) = NULL;
EOS ̲2(CHANNO) = NULL;
EOS ̲1C:=NULL;
EOS ̲2C:=NULL;
LDU1OCC:=FALSE;
LDU2OCC:=FALSE;
EOSCNT:=0;
REXOUT:=0;
REXIN:=0;
ACKONE:=NULL;
ACKTWO:=NULL;
NXTBID:=0;
BASE ̲BID(CHANNO) = J+1;
LAST ̲ACKED(CHANNO) = J;
NEXT ̲EXPECTED(CHANNO) = J+1;
RETURN;
END; /* CASE OF SETB */
/* TRANSMITTER PORTION OF RX DISPATCH */
/* BLOCK TYPE = ACK */
ACK: CASE OF (TSTATE(CHANNO))
TSTATE0: CALL DISCARD(INDEX,CHANNO);
TSTATE1: CALL DISCARD(INDEX,CHANNO);
TSTATE2: IF ACK(INDEX).BID = ACK ̲ONE(CHANNO) THEN
/* INITIATION IN PROGRESS */
/* IF THE RECEIVER IS UP */
IF NEXT ̲EXPECTED(CHANNO) .NE. (NULL ̲1 OR NULL ̲2)
THEN
CANCEL (ACKTO, CHANNO);
TSTATE(CHANNO) = TSTATE3;
CALL OPEN ̲COMPLETE(CHANNO);
CALL DISCARD (INDEX, CHANNO);
RETURN;
ELSE /* RECEIVER NOT UP YET */
DISABLE INTERRUPTS;
NEXT ̲EXPECTED(CHANNO) = NULL ̲2;
ENABLE INTERRUPTS;
CALL DISCARD(INDEX);
RETURN;
TSTATE3: /*CHANNEL IS RUNNING */
TSTATE4: IF ACK(INDEX).BID=ACK ̲TWO(CHANNO)THEN
LAST ̲ACKED=ACK ̲2 ̲INDEX(CHANNO);
TXCLACK:=ACK ̲TWO MOD TXCLEN;
ACK ̲ONE(CHANNO) = NULL;
ACK ̲TWO(CHANNO) = NULL;
TSTATE(CHANNO) = TSTATE3;
ELSE IF ACK(INDEX).BID=ACK ̲ONE(CHANNO)THEN
LAST ̲ACKED=ACK ̲1 ̲INDEX(CHANNO);
TXCLACK:=ACK ̲ONE MOD TXCLEN;
ACK ̲ONE(CHANNO) = ACK ̲TWO(CHANNO)
ACK ̲TWO(CHANNO) = NULL;
TSTATE(CHANNO) = TSTATE3;
CLEAR RCOUNT (CHANNO);
DISCARD(INDEX,CHANNO);
CANCEL (ACKTO,CHANNO);
TSTATE5: IF ACK(INDEX).BID = LAST ̲ACKED(CHANNO)THEN
IF ACK ̲TWO(CHANNO) .EQ.NULL THEN
TSTATE(CHANNO) = TSTATE3;
ELSE
TSTATE(CHANNO) = TSTATE4;
CLEAR RCOUNT (CHANNO);
DISCARD(INDEX,CHANNO);
IF ACKTOS(CHANNO) .EQ. PENDING THEN
CANCEL (ACKTO,CHANNO);
RETURN;
ELSE
GO TO CASE OF TSTATE4;
TSTATE6: CALL DISCARD(INDEX,CHANNO);
RETURN;
/* BLOCK TYPE = NAKI, NAKIJ, NAKF */
NAK ̲ FAMILY: IF ACKTOS(CHANNO) .EQ. PENDING THEN
CANCEL (ACKTO,CHANNO);
IF TSTATE(CHANNO) .EQ; TSTATE5 THEN
TSTATE(CHANNO) = TSTATE6;
CALL CLEANUP (CHANNO,NAK ̲1);
RETURN
ELSE
CLEAR RCOUNT(CHANNO);
CASE OF (NAK ̲TYPE)
NAKF: TRANS ̲INDEX ̲1=(NAK.BID1-TX ̲BID ̲BASE(CHANNO))
MOD THREE ̲TWO;
TRANS ̲INDEX ̲2=(NAK.BID.2-TX ̲BID ̲BASE(CHANNO))
MOD THREE ̲TWO;
GO TO NAK ̲PROC;
NAKIJ: TRAN ̲INDEX ̲1=(NAK.BID1-TX ̲BID ̲BASE(CHANNO)
MOD THREE ̲TWO;
TRAN ̲INDEX ̲2=(NAK.BID2-TX ̲BID ̲BASE(CHANNO)
MOD THREE ̲TWO;
GO TO NAK ̲PROC;
NAKI: TRAN ̲INDEX ̲1=(NAK.BID1-TX ̲BID ̲BASE(CHANNO))
MOD THREE ̲TWO;
TRAN ̲INDEX ̲2=TRAN ̲INDEX ̲1
NAK ̲PROC: IF TRAN ̲INDEX ̲1 .GE. LAST ̲ACKED(CHANNO) MOD
TRAN ̲CIRCLE ̲LEN .AND. TRAN ̲INDEX ̲2 .LT.
TRAN ̲NEXT(CHANNO) MOD TRAN ̲ CIRCLE ̲LEN
THEN
FOR TEMP ̲INDEX=TRAN ̲INDEX ̲1 TO TRAN ̲INDEX
̲2 IF TRAN ̲CIRCLE (TEMP ̲INDEX).NCOUNT .LT.
NCOUNT ̲MAX(CHANNO) THEN
INCREMENT TX ̲R ̲M ̲COUNT(CHANNO);
INDEX=TRAN ̲CIRCLE(TEMP ̲INDEX).INDEX;
RETRAN ̲CIRCLE(CHANNO;RETRAN ̲IN.) .LEN =
BUFFER ̲HEADER (INDEX).BYTECOUNT;
RETRAN ̲CIRCLE(CHANNO;RETRAN ̲IN).ADDR=
BUFFER ̲HEADER(INDEX).ADDR;
RETRAN ̲CIRCLE(CHANNO;RETRAN ̲IN).OFFSET =
TEMP ̲INDEX;
INCREMENT RETRAN ̲ADDR(CHANNO).RETRAN ̲IN MOD
RETRAN ̲CIRCLE ̲LEN;
INCREMENT TRAN ̲CIRCLE(TEMP ̲INDEX).NCOUNT;
ELSE
TSTATE(CHANNO) = TSTATE6;
CALL CLEANUP(CHANNO,NAK ̲2);
RETURN;
END; /* FOR STATEMENT */
SET XSTATE ̲HEADER(CHANNO);
SET ̲XMIT ̲PRIORITY(XSTATE3);
RETURN;
ELSE /* NAK OUT OF RANGE */
TSTATE(CHANNO) = TSTATE6;
CALL CLEANUP(CHANNO,NAK ̲3);
RETURN;
RETURN;
/* BLOCK TYPE = ACKL */
ACKL: IF BUFFER(INDEX).BID = LCB ̲BID THEN
/* VALID ACKL */
INCREMENT LCB ̲BID MOD THREE ̲TWO;
CLEAR LCB ̲IN ̲PROGRESS(CHANNO);
CANCEL(CHANNO,ACKLTO);
/* UPDATE CHANNEL STATISTICS */
INCREMENT TX ̲L ̲COUNT(CHANNO);
/* STATUS WILL BE RETURNED TO HOST BY HIF ̲TX ̲OUT */
ELSE /* INVALID ACKL, IGNORE */
PUSH (INDEX,STACK ̲OF ̲EMPTIES ̲RX,CHANNO);
RETURN;
END; /* ACKL */
END; /* RX ̲DISPATCHER */
7.51 P̲R̲O̲C̲E̲D̲U̲R̲E̲ ̲S̲C̲H̲E̲D̲U̲L̲E̲
F̲U̲N̲C̲T̲I̲O̲N̲
This procedure updates the monitor table used for scheduling.
The process ENABLE FLAG is set and if a TIMED WAIT
is involved that variable is set. The processes ACKTO
and ACKLTO use the EDC time out period for their TIMED
WAIT.
E̲N̲T̲R̲Y̲
Called from any task for the purpose of scheduling
another.
D̲E̲S̲C̲R̲I̲P̲T̲I̲O̲N̲
SCHEDULE (PROCESS ̲ID,CHANNO,TIME ̲INTERVAL):
SET SCHEDULING ̲TABLE(PROCESS ̲ID,CHANNO).ENABLE;
SCHEDULING ̲TABLE(PROCESS ̲ID,CHANNO).TIME ̲WAIT=
TIME ̲INTERVAL;
RETURN;
END; /* SCHEDULE */
PROCEDURE PERSCH
F̲U̲N̲C̲T̲I̲O̲N̲
Update scheduling table with delay for tasks that are
going to be scheduled periodically.
PROCEDURE CANCEL
F̲U̲N̲C̲T̲I̲O̲N̲
Cancels a task by updating appropriate entry in scheduling
table.
7.52 P̲R̲O̲C̲E̲D̲U̲R̲E̲ ̲S̲E̲G̲M̲E̲N̲T̲ ̲P̲R̲O̲C̲E̲S̲S̲O̲R̲
F̲U̲N̲C̲T̲I̲O̲N̲
To scan the PENDING ̲TABLE for complete segments which
have been received and may be transferred to the host.
This procedure will set EOS ̲1 ̲COMPLETED if the first
segment is found. It sets EOS ̲2 ̲COMPLETED if a second
segment is found. EOS ̲COUNT contains a count of the
segments which have been received but not deblocked.
D̲E̲S̲C̲R̲I̲P̲T̲I̲O̲N̲:̲
SEGMENT ̲PROCESSOR(CHANNO):
IF EOS ̲COUNT(CHANNO) .GT. ZERO THEN
FOR INDEX = COMPLETION ̲PTR(CHANNO) TO EOS ̲1 ̲INDEX
(CHANNO)
IF PENDING ̲TABLE(INDEX) .EQ. ZERO THEN
RETURN;
END; /* FOR STATEMENT */
POP(CURLDU,LDU);
POP(HRXSTK,INDEX);
Move data from GATHER to receive buffer
EOS ̲1:=EOS ̲2;
EOS ̲2:=NULL;
PUSHL(HOSTRQ,INDEX);
RETURN
END; /*SEGMENT ̲PROCESSOR*/
7.53 P̲R̲O̲C̲E̲D̲U̲R̲E̲ ̲S̲E̲R̲V̲I̲C̲E̲ ̲I̲N̲V̲A̲L̲I̲D̲ ̲R̲E̲T̲R̲A̲N̲S̲M̲I̲S̲S̲I̲O̲N̲S̲
F̲U̲N̲C̲T̲I̲O̲N̲
This procedure handles a buffer which arrived out of
sequence and was presumably retransmitted; but cannot
be accepted becuase of CRC error or other problem.
E̲N̲T̲R̲Y̲
Called from RX ̲DISPATCHER.
D̲E̲S̲C̲R̲I̲P̲T̲I̲O̲N̲
SERVICE ̲INVALID ̲RETRANSMISSIONS(INDEX,CHANNO):
/* CALCULATE ENTRY IN PENDING ̲TABLE(CHANNO) */
TEMP=(BID-BID ̲BASE(CHANNO)) MOD THREE ̲TWO;
IF PENDING ̲TABLE(CHANNO,TEMP) .EQ.EMPTY THEN
/* MISSING BLOCK HAS BEEN RECEIVED IN ERROR */
CALL QUEUE ̲NAK(BID,CHANNO);
PUSH(INDEX,CHANNO,STACK ̲OF ̲EMPTIES ̲RX);
RETURN;
ELSE /* DUPLICATE BLOCK */
PUSH(INDEX,CHANNO,STACK ̲OF ̲EMPTIES ̲RX);
RETURN;
END; /* SERVICE ̲INVALID ̲RETRANSMISSIONS */
7.54 P̲R̲O̲C̲E̲D̲U̲R̲E̲ ̲S̲E̲R̲V̲I̲C̲E̲ ̲N̲E̲X̲T̲ ̲E̲X̲P̲E̲C̲T̲E̲D̲
F̲U̲N̲C̲T̲I̲O̲N̲
To store in the pending table the buffer index of an
incoming block with a bid matching NEXT ̲EXPECTED.
E̲N̲T̲R̲Y̲
Called from RX ̲DISPATCHER.
D̲E̲S̲C̲R̲I̲P̲T̲I̲O̲N̲
SERVICE ̲NEXT ̲EXPECTED(CHANNO,INDEX):
CALL HRXDTA.
7.55 P̲R̲O̲C̲E̲D̲U̲R̲E̲ ̲S̲E̲R̲V̲I̲C̲E̲ ̲R̲E̲T̲R̲A̲N̲S̲M̲I̲S̲S̲I̲O̲N̲S̲
F̲U̲N̲C̲T̲I̲O̲N̲
To store a retransmitted block in the pending table.
E̲N̲T̲R̲Y̲
Called from RX ̲DISPATCHER.
D̲E̲S̲C̲R̲I̲P̲T̲I̲O̲N̲
SERVICE ̲RETRANSMISSIONS(INDEX,CHANNO):
/* CALCULATE ENTRY IN THE PENDING TABLE */
TEMP = (BID-BID ̲BASE(CHANNO)) MOD THREE ̲TWO;
IF PENDING ̲TABLE(CHANNO,TEMP) EQ EMPTY THEN
CALL HRXDTA.
RETURN;
END; /* SERVICE ̲RETRANSMISSIONS */
7.56 P̲R̲O̲C̲E̲D̲U̲R̲E̲ ̲S̲E̲T̲ ̲X̲M̲I̲T̲ ̲P̲R̲I̲O̲R̲I̲T̲Y̲
E̲N̲T̲R̲Y̲
Called from any procedure.
E̲N̲T̲R̲Y̲ ̲P̲a̲r̲a̲m̲e̲t̲e̲r̲s̲
PRIO - The priority level to which the XMITTER state,
XSTATE, is to be set.
Mandatory - indicates that XSTATE will be set to PRIO
in all cases.
F̲U̲N̲C̲T̲I̲O̲N̲
The XMITTER procedure begins transmission with the
highest priority frame available for transmission as
indicated by XSTATE. To set this variable and thus
raise the priority of the XMITTER, this procedure must
be called.
This procedure compares the value of PRIO to XSTATE.
If PRIO is higher, it raises the value of XSTATE to
PRIO. Additionally if XSTATE = 1 then the XMITTER was
idle so this routine schedules the XMITTER. The calling
procedure should have placed the frame to be sent in
the appropriate queue before calling this procedure.
D̲E̲S̲C̲R̲I̲P̲T̲I̲O̲N̲
SET ̲XMIT ̲PRIORITY(CHANNO,PRIO,MANDATORY);
IF MANDATORY .EQ. TRUE THEN
DISABLE INTERRUPTS;
XSTATE = PRIO;
ENABLE INTERRUPTS;
ELSE
IF XSTATE .NE. 1 THEN
IF XSTATE .LT.PRIO THEN
DISABLE INTERRUPTS;
XSTATE=PRIO
ENABLE INTERRUPTS
ELSE
XSTATE = PRIO;
SCHEDULE(XMITTER,CHANNO);
RETURN;
END; /* SET ̲XMIT ̲PRIORITY */
7.57 P̲R̲O̲C̲E̲D̲U̲R̲E̲ ̲S̲P̲E̲C̲ ̲I̲N̲T̲
F̲U̲N̲C̲T̲I̲O̲N̲
Special receive interrupt handling.
D̲E̲S̲C̲R̲I̲P̲T̲I̲O̲N̲
SPRX0(1):
save registers
CALL SPECR ̲O
restore registers
RETURN;
Special SIO interrupt service routine SPECR ̲O:
reset latched error condition
IF parity error THEN
IF parity error in header THEN
discard current block
ELSE
patch current data character with SUB character
ELSE
IF receiver overrun THEN
discard current block;
RETURN
END/* SPECR ̲O */
7.58 P̲R̲O̲C̲E̲D̲U̲R̲E̲ ̲S̲T̲O̲R̲E̲ ̲P̲R̲I̲M̲A̲R̲Y̲ ̲B̲U̲F̲F̲E̲R̲
F̲U̲N̲C̲T̲I̲O̲N̲
To place a buffer belonging to the host in TRAN ̲CIRCLE.
If the BLOCK ̲SIZE is less than 512 then the variable
BUFFER ̲EXHAUSTED is set FALSE if BYTECOUNT GT BLOCK
̲SIZE else BUFFER ̲EXHAUSTED is set TRUE. BUFFER ̲EXHAUSTED
is a flag used to signal that more blocks need to be
transmitted to cover the segment.
E̲N̲T̲R̲Y̲
Called by HIF ̲TX ̲IN.
D̲E̲S̲C̲R̲I̲P̲T̲I̲O̲N̲
STORE ̲PRIMARY ̲BUFFER(INDEX,CHANNO):
/* STORE BUFFER INDEX IN TRAN ̲CIRCLE TABLE */
TRAN ̲CIRCLE(CHANNO,HOST ̲IN(CHANNO)).INDEX = INDEX;
/* ZERO RETRANSMISSION COUNT */
TRAN ̲CIRCLE(CHANNO,HOST ̲IN(CHANNO)).NCOUNT = ZERO;
/* CLEAR OUTSTANDING I/O FLAG */
TRAN ̲CIRCLE(CHANNO,HOST ̲IN(CHANNO)).OUTSTANDING =
ZERO;
/* UPDATE TRAN ̲CIRCLE POINTER */
INCREMENT HOST ̲IN(CHANNO) MOD TRAN ̲CIRCLE ̲LEN;
IF BUFFER(INDEX).BYTECOUNT .LT. BLOCK ̲SIZE(CHANNO)
THEN
BUFFER ̲EXHAUSTED(CHANNO) = TRUE;
BUFFER(INDEX).TYPE = EOS;
ELSE
BUFFER(INDEX).BYTECOUNT = BLOCK ̲SIZE(CHANNO);
BUFFER ̲EXHAUSTED(CHANNO) = FALSE;
INCREMENT HIF ̲TX ̲BLOCK(CHANNO);
BUFFER(INDEX).TYPE = DATA;
T ̲BYTECOUNT = BUFFER(INDEX).BYTECOUNT-BLOCK ̲SIZE(CHANNO)
RETURN;
END; /* STORE ̲PRIMARY ̲BUFFER */
7.59 P̲R̲O̲C̲E̲D̲U̲R̲E̲ ̲S̲T̲O̲R̲E̲ ̲S̲E̲C̲ ̲B̲U̲F̲F̲E̲R̲
F̲U̲N̲C̲T̲I̲O̲N̲
This procedure continues the blocking function by moving
a block of data from the host segment buffer to an
LTU buffer. The varibale HIF ̲TX ̲BLOCK indicates which
block is to be transferred. If the data in the segment
is exhausted then the flag BUFFER ̲EXHAUSTED is set
true. This flags HIF ̲TX ̲IN to continue.
If a buffer cannot be allocated HIF ̲TX ̲IN is scheduled.
All exits from this procedure are by scheduling HIF
̲TX ̲IN.
Data is moved by calling MOVE ̲DATA. That procedure
will continue until the data is moved. It will exit
to this procedure. It will also reschedule itself so
as to allow other procedures to run.
This procedure files all LTU buffers in TRAN ̲CIRCLE,
sets owner to LTU and flags the last block of a segment
in the header.
D̲E̲S̲C̲R̲I̲P̲T̲I̲O̲N̲
STORE ̲SEC ̲BUFFER(CHANNO):
/* DETERMINE IF MOVE ̲DATA HAS FILLED A BUFFER */
IF MOVE ̲IN ̲PROGRESS(CHANNO) THEN
CLEAR MOVE ̲IN ̲PROGRESS(CHANNO);
/* PLACE FILLED BUFFER INDEX IN TRAN ̲CIRCLE */
TRAN ̲CIRCLE(CHANNO,HOST ̲IN(CHANNO)).INDEX = T ̲INDEX;
/* ZERO RETRY COUNT */
TRAN ̲CIRCLE(CHANNO,HOST ̲IN(CHANNO)),NCOUNT = ZERO;
/* CLEAR OUTSTANDING FLAG */
TRAN ̲CIRCLE(CHANNO,HOST ̲IN(CHANNO)).OUTSTANDING=ZERO;
/* UPDATE TRAN ̲CIRCLE POINTERS */
INCREMENT HOST ̲IN(CHANNO) MOD TRAN ̲CIRCLE ̲LEN;
/* UPDATE BLOCK POINTER */
INCREMENT HOST ̲TX ̲BLOCK(CHANNO);
/* DETERMINE IF LAST BLOCK OF SEGMENT */
IF BUFFER ̲EXHAUSTED(CHANNO) .EQ. TRUE THEN
BUFFER(TX ̲INDEX).TYPE = EOS;
CLEAR HIF ̲TX ̲IN ̲PROGRESS(CHANNO);
SCHEDULE(HOST ̲TX ̲IN,CHANNO);
RETURN;
/* PREPARE TO MOVE NEXT BLOCK */
MOVE ̲IN ̲PROGRESS(CHANNO) = TRUE;
/* ALLOCATE LTU BUFFER */
T ̲INDEX = POP(STACK ̲OF ̲EMPTIES,CHANNO)
IF STACK .EQ. EMPTY THEN
SCHEDULE(HIF ̲TX ̲IN,CHANNO);
RETURN;
ELSE
P ̲INDEX(CHANNO) = MIN(T ̲BYTECOUNT(CHANNO),BLOCK
̲SIZE(CHANNO));
IF P ̲INDEX(CHANNO) .LT. BLOCKSIZE(CHANNO) THEN
BUFFER ̲EXHAUSTED(CHANNO) .EQ. TRUE;
BUFFER(T ̲INDEX).TYPE = EOS;
ELSE
BUFFER(T ̲INDEX).TYPE = DATA;
DATA ̲DEST(CHANNO) = BUFFER(T ̲INDEX).DATA;
DATA ̲SRC(CHANNO) = BUFFER(INDEX).DATA+(HIF ̲TX
̲BLOCK(CHANNO)*
BLOCKSIZE(CHANNO));
CALL MOVE ̲DATA(CHANNO);
RETURN;
END; /* STORE ̲SEC ̲BUFFER */
7.60 P̲R̲O̲C̲E̲D̲U̲R̲E̲ ̲T̲R̲A̲N̲S̲M̲I̲T̲T̲E̲R̲(̲C̲H̲A̲N̲N̲O̲)̲
F̲U̲N̲C̲T̲I̲O̲N̲
This procedure attempts to begin transmission for a
particular channel. The actual transmission of the
block is handled by XMITTER. This procedure formats
the block and places it in the XMITTER queue.
Blocks to be transmitted were placed in TRAN ̲CIRCLE
by HIF ̲TX ̲IN. Transmitter determines the current state
of transmission and posts blocks until two segments
are outstanding. Control is returned to the scheduler
between blocks so as not to interfere with interrupt
service procedures.
TRANSMITTER)CHANNO):
DO CASE OF (TSTATE(CHANNO)):
TSTATE0: RETURN;
TSTATE1: RETURN;
TSTATE2: RETURN;
TSTATE3:
/* IF NO BUFFERS TO TRANSMIT, SET ACKTO */
IF TRAN ̲CIRCLE(CHANNO).HOST ̲IN .EQ. TRAN ̲CIRCLE(CHANNO).
NEXT ̲TRAN THEN
IF ACKTO(CHANNO) .NE. PENDING THEN
SCHEDULE(ACKTO,CHANNO);
RETURN;
ELSE /* TRANSMIT A BLOCK */
/* CANCEL ACKTO IF RUNNING */
IF ACKTOS(CHANNO) .EQ. PENDING THEN
CANCEL (ACKTO,CHANNO);
INDEX = TX ̲NEXT;
DETERMINE BUFFER ADDRESS FROM INDEX;
/* FORMAT BLOCK */
BUFFER(INDEX).C1 = BUFFER(INDEX).BYTECOUNT1;
BUFFER(INDEX).C2 = BUFFER(INDEX).BYTECOUNT2;
/* INITIALIZE XMITTER */
INC(NXT ̲BID)MOD MODBID;
BUFFER(INDEX).BID = NEXT ̲BID(CHANNO);
XMIT ̲CIRCLE(CHANNO,TRAN ̲IN).OFFSET = NEXT ̲TRAN(CHANNO);
INCREMENT TRAN ̲IN MODULO XMIT ̲CIRCLE ̲LEN,
SET XSTATE2 ̲HEADER(CHANNO);
IF BUFFER(INDEX).SEG ̲TYPE .EQ. (EOS.OR,EOM) THEN
IF ACK ̲ONE(CHANNO) .NE. NULL THEN
ACK ̲TWO(CHANNO) = BUFFER(INDEX).BID;
ACK ̲2INDEX(CHANNO) = NEXT ̲TRAN(CHANNO);
SET ̲XMIT ̲PRIORITY(XSTATE2);
INCREMENT NEXT ̲TRAN(CHANNO) MODULO TRAN ̲CIRCLE
̲LEN;
TSTATE = TSTATE4;
RETURN;
ELSE
ACK ̲ONE(CHANNO) = BUFFER(INDEX),BID;
ACK ̲1 ̲INDEN:=NEXT ̲TRAN;
TSTATE = TSTATE3;
SET ̲XMIT ̲PRIORITY(XSTATE2);
INCREMENT NEXT ̲TRAN(CHANNO) MODULO TRAN ̲CIRCLE
̲LEN;
RETURN;
END; /* STATE3 */
TSTATE4: IF ACKTO(CHANNO) .EQ. PENDING THEN
SCHEDULE(ACKTO),CHANNO);
RETURN
END; /* TSTATE4 */
TSTATE5: RETURN;
TSTATE6: RETURN;
END; /* TRANSMITTER */
7.61 P̲R̲O̲C̲E̲D̲U̲R̲E̲ ̲T̲X̲ ̲C̲A̲N̲C̲E̲L̲
F̲U̲N̲C̲T̲I̲O̲N̲
This procedure scans the TRAN ̲CIRCLE table for an LDU
which matches that cancelled by the host. Only those
LDU's which have not yet been transmitted may be cancelled.
If a match is found all buffers associated with that
LDU are released, and a status of cancelled is returned
to the host. If no match is found the request is ignored.
E̲N̲T̲R̲Y̲
Called from HIF ̲COMMAND with entry parameters equal
to channel No. and the index of the host command buffer.
D̲E̲S̲C̲R̲I̲P̲T̲I̲O̲N̲
TX ̲CANCEL(CHANNO;H ̲INDEX):
/* CHECK UNTRANSMITTED BUFFERS */
FOR STEP = NEXT ̲TRAN(CHANNO) TO HOST ̲IN(CHANNO)
INDEX = TRAN ̲CIRCLE(CHANNO,STEP).INDEX;
/* TO SEE IF THE LDU'S MATCH /*
IF BUFFER(INDEX).T ̲SEG ̲NO .EQ. BUFFER(H ̲INDEX).P1 THEN
/* RELEASE HOST BUFFER */
P ̲STEP = STEP;
CLEAR(INDEX);
PUSH(INDEX,CHANNO,HOST ̲EMPTIES);
/* RELEASE ANY LTU BUFFERS ASSOCIATED WITH THE LDU
*/
WHILE BUFFER(INDEX).OWNER .NE. HOST
INCREMENT P ̲STEP MOD TRAN ̲CIRCLE ̲LEN;
INDEX = TRAN ̲CIRCLE(CHANNO,P ̲STEP).INDEX;
PUSH(INDEX,CHANNO,STACK ̲OF ̲EMPTIES);
END: /* WHILE STATEMENT */
DELTA = 0;
/* REARRANGE TRAN ̲CIRCLE TO REMOVE THE GAP */
FOR TSTEP = STEP TO P ̲STEP
IF TRAN ̲CIRCLE(CHANNO;P ̲STEP+DELTA).INDEX .NE.
NULL
THEN
TRAN:CIRCLE(CHANNO,TSTEP.INDEX=
TRAN ̲CIRCLE(CHANNO,P ̲STEP+DELTA).INDEX;
INCREMENT DELTA MOD TRAN ̲CIRCLE ̲LEN;
ELSE
CLEAR(H ̲INDEX);
CALL TX ̲STATUS(BUFFER(H ̲INDEX).P1,CHANNO);
PUSH (H ̲INDEX,CHANNO,HOST ̲EMPTIES);
RETURN;
END; /* FOR STATEMENT */
END; /* FOR STATEMENT */
/* NN MATCH SO RETURN HOST COMMAND */
PUSH(H ̲INDEC,CHANNO,HOST ̲EMPTIES);
RETURN;
END; /* TX ̲CANCEL */
7.62 P̲R̲O̲C̲E̲D̲U̲R̲E̲ ̲T̲X̲ ̲E̲R̲R̲O̲R̲
F̲U̲N̲C̲T̲I̲O̲N̲:̲
To return an error status to the host for illegal transmission
buffers. A status buffer is allocated formatted and
returned to the host. The incoming transmission buffer
is returned empty to the host.
E̲N̲T̲R̲Y̲
Called by HIF ̲TX ̲IN.
D̲E̲S̲C̲R̲I̲P̲T̲I̲O̲N̲
TX ̲ERROR(CHANNO,TNDEC,ERR ̲CODE);
INDEX = POP(STACK ̲OF ̲EMPTIES ̲RX,CHANNO);
/* FORMAT STATUS BUFFER TO RETURN TO HOST */
BUFFER(INDEX).TYPE = SINGLE#LDU ̲STATUS;
BUFFER(INDEX).COMMAND = TRANSMISSION ̲STATUS;
BUFFER(INDEX).P1 = ERR ̲CODE;
BUFFER(INDEX).LDU ̲ID = BUFFER(TNDEC).LDU ̲ID;
PUSH(INDEX,CHANNO,STATUS ̲RETURN);
CLEAR(TNDEC);
PUSH(TNDEC,CHANNO,HOST ̲EMPTIES);
RETURN;
END; /* TX ̲ERROR */
7.63 P̲R̲O̲C̲E̲D̲U̲R̲E̲ ̲X̲M̲I̲T̲T̲E̲R̲
D̲E̲S̲C̲R̲I̲P̲T̲I̲O̲N̲
The Xmitter procedure performs the physical transmission
of blocks. These blocks are posted for transmission
by other procedures.
For each of the eight levels or states of transmission
associated with the Xmitter there exists a bit map
or circular buffer which contains information as to
which buffers have been posted for transmission at
this level. The first word of each such table is labelled
as XSTATEn ̲HEADER where n denotes the particular state
(8.GE.n.GE.1). XSTATE1 is the idle state, and there
is no table associated with it.
The XSTATES are prioritized with XSTATE8 being the
highest. The XSTATES are associated with the type of
block that is to be transmitted. The XSTATES are assigned
as follows:
XSTATE8 - SETB blocks are to be transmitted
XSTATE7 - RR response request blocks are to be transmitted
XSTATE6 - ACKL acknowledge LCB blocks are to be
transmitted
XSTATE5 - NAK non-acknowledgement blocks to to be
transmitted
XSTATE4 - ACK acknowledgment blocks are to be transmitted
XSTATE3 - RE-transmission blocks are to be transmitted
XSTATE2 - Transmission data blocks are to be transmitted
XSTATE1 - IDLE
Blocks for transmission may be posted by either receiver
or transmitter procedures. Each XSTATE table is accessed
by only one procedure so no contention exists (for
either input or output). The tables are sufficiently
large so that the inputting and outputting procedures
do not contend for table access and table overrun cannot
occur.
The current XSTATE is indicated by the variable XSTATE.
This variable is set by the procedure SET ̲XMIT ̲PRIORITY.
Procedures which wish to have blocks transmitted, place
the block in the appropriate XSTATE table and then
call SET ̲XMIT ̲PRIORITY with the XSTATE of the block
which they have just posted.
If the priority of the newly posted block is higher
than the current value of XSTATE, then SET ̲XMIT ̲PRIORITY
will increase the value of XSTATE to the level of the
newly posted block.
The XMITTER will begin or attempt to begin all new
transmissions at the level indicated by XSTATE. If
no blocks remain to be transmitted at that level then
XMITTER will lower the value of XSTATE until a posted
block is found or XSTATE = IDLE.
There exists an XSTATE variable for each channel. The
documentation indicates this by referring to XSTATE8(CHANNO).
Following is a pictorial description of the tables
associated with each XSTATE. In addition to XSTATEn
̲HEADER other tables are shown which contain buffer
information and are used by those procedures involved
in transmission.
All tables are shown with possible expansion to 4 channels.
CHANNEL 1
CHANNEL 2
XSTATE
XSTATE8 - SETB
XSTATE8 ̲HEADER: 1
2
The header consists of a channel BYTE MAP. If the BYTE
is TRUE a block has been posted. SETB blocks are fixed
in memory, 1 block per channel.
XSTATE7 - RR
XSTATE7 ̲HEADER: 1
2
The header consists of a channel BYTE MAP. If the BYTE
is TRUE a block has been posted. RR blocks are fixed
in memory, one block per channel.
XSTATE6 - ACKL
XSTATE6 ̲HEADER: 1
2
The header consists of a channel BYTE MAP. If the BYTE
is TRUE a block has been posted. ACKL blocks are fixed
in memory, 1 block per channel.
XSTATE5 - NAK
XSTATE5 ̲HEADER: 1
2
The header consists of a channel BYTE MAP. If the BYTE
is TRUE a block has been posted to that channel. Associated
with each channel is a circular array. With each circular
array is associated two pointers NAK ̲IN and NAK ̲OUT.
These indicate the next block to be assigned (NAK ̲IN)
and the next block to be released (NAK ̲OUT). The blocks
are fixed in memory and the address of each may be
determined as an offset from NAK ̲BASE. The index of
each block is fixed and is identical to the entry index
in the NAK ̲CIRCLE table. The NAK ̲CIRCLE contains the
type of the NAK posted. The type determine the length.
XMITTER will not transmit NAK blocks unless the corresponding
channel bit is set. This will be done when RR is received.
CH 1 NAK ̲IN index into
CH 2 NAK ̲CIRCLE(INPUT)
CH 1 NAK ̲OUT index into
CH 2 NAK ̲CIRCLE(OUTPUT)
In this documentation channel 1 is referred to as
NAK ̲ADDR(1).
NAK ̲IN and NAK ̲ADDR(1). NAK ̲OUT. Similarly channel
2 is
NAK ̲ADDR(2).NAK ̲IN and NAK ̲ADDR(2).NAK ̲OUT.
1 TYPE 1 TYPE
2 2
3 NAK ̲OUT 3 NAK ̲IN
4 4
5 5
6 6
NAK ̲IN
NAK ̲OUT
n n
CHANNEL 1 CHANNEL 2
n = NAK ̲TAB ̲LEN
TYPE = 1-NAKF, 2-NAKI, 3-NAKIJ
NAK ̲IN and NAK ̲OUT are INCREMENTED MODULO n.
In this documentation CHANNEL 1 is referred to as NAK
̲CIRCLE(1,INDEX) and CHANNEL 2 as NAK ̲CIRCLE(2,INDEX).
NAK BUFFER ADDRESSES are composed as
NAK ̲BASE+(NAK ̲IN*5) or NAK ̲BASE+(NAK ̲OUT*5)
XSTATE4 - ACK
XSTATE4 ̲HEADER: 1
2
The header consists of a channel BYTE MAP. If the BYTE
is TRUE a block has been posted to that channel. Associated
with each channel is a circular array. With each circular
array is associated two pointers ACK ̲IN and ACK ̲OUT.
These indicate the next block to be assigned (ACK ̲IN)
and the next block to be released (ACK ̲OUT).
The blocks are fixed in memory and the address of each
may be determined as an offset from ACK ̲BASE. The index
of each block is fixed and is identical to the entry
index in the ACK ̲CIRCLE table. The ACK ̲CIRCLE contains
the sequence number last acknowledged.
CH 1 ACK ̲IN index into
CH 2 ACK ̲CIRCLE (INPUT)
CH 1 ACK ̲OUT index into
CH 2 ACK ̲CIRCLE(OUTPUT)
In this documentation channel 1 is referred to as ACK
̲ADDR(1).ACK ̲IN and ACK ̲ADDR(1). ACK ̲OUT. Similarly
channel 2 is ACK ̲ADDR(2).ACK ̲IN and ACK ̲ADDR(2).ACK
̲OUT.
1 SEG NO 1
2 ACK ̲OUT 2
3 3
4
5
n-1 ACK ̲IN n-1
n n
CHANNEL 1 CHANNEL 2
ACK ̲CIRCLE
n = ACK ̲TAB ̲LEN
SEQ NO = 1 - 128 (BID)
ACK ̲IN and ACK ̲OUT are incremented MODULO ACK ̲TAB
̲LEN
In this documentation Channel 1 is referred to as ACK
̲CIRCLE(1,INDEX) and Channel 2 as ACK ̲CIRCLE(2,INDEX).
XSTATE3 - Retransmission Blocks.
XSTATE3 ̲HEADER: 1
2
The header consists of a channel BYTE MAP. If the BYTE
is TRUE a block has been posted to that channel. Associated
with each channel is a circular array. With each circular
array is associated two pointers RETRAN ̲IN and RETRAN
̲OUT.
These indicate the next block to be assigned (RETRAN
̲IN) and the next block to be released (RETRAN ̲OUT).
The data entries in RETRAN ̲CIRCLE contain the information
necessary to release blocks after transmission and
to initiate transmission.
In this documentation channel 1 is referred to as RETRAN
̲ADDR(1). RETRAN ̲IN and RETRAN ̲ADDR(1).RETRAN ̲OUT. Similarly
channel 2 is referred to as RETRAN ̲ADDR(2).RETRAN ̲IN
and RETRAN ̲ADDR(2).RETRAN ̲OUT.
CH 1 RETRAN ̲IN index into
CH 2 RETRAN ̲TABLE(INPUT)
CH 1 RETRAN ̲OUT index into
CH 2 RETRAN ̲TABLE(OUTPUT)
1
2
3
4 RETRAN ̲OUT
5
W-2 RETRAN ̲IN
W-1
W
CH1 or CH2
RETRAN ̲TABLE
W=length of RETRAN ̲TABLE
The table contains indices into TRANSMIT ̲CIRCLE
XSTATE2 -TRANSMISSION DATA BLOCKS
XSTATE2 ̲HEADER: 1
2
The header consists of a channel BYTE MAP. If the BYTE
is TRUE a block has been posted to that channel. Associated
with that channel is a circular array XMIT ̲CIRCLE.
With each circular array is associated two pointers
TRAN ̲IN and TRAN ̲OUT.
These indicate the next block to be assigned and the
next block to be released, respectively. The data entries
in XMIT ̲CIRCLE contain information necessary to initiate
transmission and to release the block when transmission
has completed.
CH 1 XMT ̲IN index into
CH 2 XMITER ̲TABLE (INPUT)
CH 1 XMT ̲OUT index into
CH 2 XMITER ̲TABLE(OUTPUT)
1
2 XMT ̲OUT
3
W-1 XMT ̲IN
W
CH1 or CH 2
XMITER ̲TABLE
W = length of XMITER ̲TABLE
The table contains indices of the buffers to be transmitted.
E̲N̲T̲R̲Y̲
This procedure is scheduled by SET.XMIT ̲PRIORITY if
XMITTER were previously in IDLE state, i.e. XSTATE1
or by the SIO transmission complete interrupt.
E̲N̲T̲R̲Y̲ ̲P̲o̲i̲n̲t̲s̲
- XMITTER via the scheduler,
- XMIT ̲2 via TX interrupt handler.
F̲U̲N̲C̲T̲I̲O̲N̲
The XMITTER handles all external transmissions. It
handles two channels. For each channel, XMITTER maintains
eight levels or priority. The lowest level XSTATE1
is the IDLE level. With each level is associated a
BIT MAP or CIRCULAR LIST which contains information
as to the buffer to be transmitted.
The XMITTER stores the current XSTATE in CURRENT ̲TRANSMISSION
when it begins transmission. XMITTER will attempt to
begin transmission for all inactive channels.
XMITTER:
/* SCHEDULER ENTRY POINT */
IF LEV1 ̲STATE .EQ. SYN4 THEN
FOR EACH CHANNEL
XMIT ̲2:
IF XMIT ̲IN ̲PROGRESS(CHANNO) .EQ.IDLE THEN
CALL RELEASE ̲BUFFER(CHANNO);
IF XMIT ̲IN ̲PROGRESS(CHANNO) .EQ.RESET THEN
DO CASE OF (XSTATE(CHANNO))
XSTATE8: /* HANDLE SETB */
IF XSTATE8 ̲HEADER(CHANNO) .NE. ZERO THEN
SET CURRENT ̲TRANSMISSION(CHANNO) = XSTATE8;
CALL INITIATE ̲TRANSMISSION(CHANNO,SETB ̲ADDR(CHANNO),
SETB
̲LEN;
RETURN
ELSE
CALL SETXMIT ̲PRIORITY(CHANNO,XSTATE7,MANDATORY);
END /* XSTATE8 */
XSTATE7: /* HANDLE RR */
IF XSTATE7 ̲HEADER(CHANNO) .NE. ZERO THEN
SET CURRENT ̲TRANSMISSION(CHANNO) = XSTATE7;
CALL INITIATE ̲TRANSMISSION(CHANNO,RR ̲ADDR(CHANNO),
RR ̲LEN);
RETURN
ELSE
CALL SET ̲XMIT ̲PRIORITY(CHANNO,XSTATE6,MANDATORY);
END /* XSTATE7 */
XSTATE6: /* HANDLE ACKL */
IF XSTATE6 ̲HEADER(CHANNO) .NE. ZERO THEN
SET CURRENT ̲TRANSMISSION(CHANNO) = XSTATE6;
CALL INITIATE ̲TRANSMISSION(CHANNO,ACKL ̲ADDR(CHANNO),
ACK
̲LEN;
RETURN;
ELSE
CALL SET ̲XMIT ̲PRIORITY(CHANNO,XSTATE5,MANDATORY);
END / * XSTATE6 */
XSTATE5: /* HANDLE NAK */
IF XSTATE5 ̲HEADER(CHANNO) .NE. ZERO THEN
SET CURRENT ̲TRANSMISSION = XSTATE5;
TEMP = NAK ̲ADDR(CHANNO).NAK ̲OUT;
CALL INITIATE ̲TRANSMISSION(CHANNO,NAK ̲BASE+
TEMP*5,NAK ̲CIRCLE(TEMP)+4);
RETURN;
ELSE
CALL SET ̲XMIT ̲PRIORITY(CHANNO,XSTATE4,MANDATORY);
END; /* XSTATE5 */
XSTATE4: /* HANDLE ACK */
IF XSTATE4 ̲HEADER(CHANNO) .NE. ZERO THEN
SET CURRENT ̲TRANSMISSION = XSTATE4
TEMP = ACK ̲ADDR(CHANNO).ACK ̲OUT;
CALL INITIATE ̲TRANSMISSION(CHANNO,ACK ̲BASE+TEMP*4,
ACK ̲LEN);
RETURN;
ELSE
CAL SET ̲XMIT ̲PRIORITY(CHANNO,XSTATE3,MANDATORY);
END; /* XSTATE4 */
XSTATE3: /* HANDLE RE-TRANSMISSION BLOCKS */
IF XSTATE3 ̲HEADER(CHANNO) .NE. ZERO THEN
SET CURRENT ̲TRANSMISSION = XSTATE3;
TEMP = RETRAN ̲ADDR(CHANNO).RETRAN ̲OUT;
CALL INITIATE ̲TRANSMISSION(CHANNO,RETRAN ̲CIRCLE(TEMP).
ADDR,RETRAN ̲CIRCLE(TEMP).LEN);
RETURN;
ELSE
CALL SET ̲XMIT ̲PRIORITY(CHANNO,XSTATE2,MANDATORY);
END; /* XSTATE3 */
XSTATE2: /* HANDLE INITIAL TRANSMISSION */
IF XSTATE2 ̲HEADER(CHANNO) .NE. ZERO THEN
SET CURRENT ̲TRANSMISSION = XSTATE2;
TEMP = TRAN ̲ADDR(CHANNO).TRAN ̲OUT;
CALL INITIATE ̲TRANSMISSION(CHANNO,XMIT ̲CIRCLE(TEMP).
ADDR,XMIT ̲CIRCLE(TEMP).LEN);
RETURN;
ELSE
SET ̲XMIT ̲PRIORITY(CHANNO,XSTATE1,MANDATORY);
END; /* XSTATE2 */
XSTATE1: /* IDLE */
RETURN
ELSE
SCHEDULE XMITTER(CHANNO,XDELTA);
RETURN;
END; /* XMITTER */
7.64 P̲R̲O̲G̲R̲A̲M̲ ̲D̲E̲F̲I̲N̲I̲T̲I̲O̲N̲S̲
CANCELLED ̲LDU FIFO queue used to store LDU's
which have been cancelled by
the HOST.
CURRENT ̲LDU FIFO queue used to store LDU
received from the HOST.
CUR ̲LDU Pointer to CURREN ̲LDU
EOS ̲COMPLETION ̲COUNT Number of segments completely
received.
EOS ̲COUNT Number of EOS blocks detected.
EOS ̲1 ̲INDEX Index of first EOS block received.
EOS ̲2 ̲INDEX Index of second EOS block received.
HIF ̲TX ̲BLOCK Current transmission block
within a segment.
HOST ̲EMPTIES Stack used to store empty transmission
blocks which are to be returned
to the HOST.
INDEX ̲1 Index of first block to be
re-transmitted
INDEX ̲2 Index of second block to be
re-transmitted.
STACK ̲OF ̲EMPTIES Stack used to store empty LTU
transmission blocks.
STACK ̲OF ̲EMPTIES ̲RX Stack used to store empty LTU
buffers used for reception
of data or to give status to
the HOST.
STATUS ̲RETURN FIFO queue used to store status
blocks which are to be returned
to the HOST
8̲ ̲ ̲T̲E̲S̲T̲I̲N̲G̲
Testing will be divided into three phases: Phase I,
Phase II, and Phase III. Phase I will consist of protocol
verification, Phase II will consist of testing against
a NICS-TARE configuration, and Phase III will consist
of CR80D (NICS-TARE Handler) interface verification
and acceptance testing.
Phase I consists of fifty tests designed to verify
that the protocol is functioning. The tests will be
run in an LTU using a Z-80 In-Circuit Emulator to initialize
the shared data areas and other data areas. A small
HOST Emulation routine will execute in the LTU to emulate
release of buffers and host acknowledgements.
Phase I testing will take place in Thousand Oaks with
a final demonstration given in Denmark.
Phase III will consist of interfacing an LTU to a CR80D
running the NICS-TARE Handler. Data will be looped
back from channel A to channel B. CR A/S will be responsible
for the test programs necessary to stimulate the NICS-TARE
Handler. The test programs should transmit and receive
messages and compare transmitted data with received
data. A datascope will be used to verify the link protocol.
Phase III testing will take place in Denmark.
Phase II will consist of running the test protocol
against an existing NICS-TARE configuration.
8.1 P̲H̲A̲S̲E̲ ̲1̲
T̲e̲s̲t̲ ̲1̲.̲ ̲S̲E̲T̲B̲ ̲P̲R̲O̲C̲E̲S̲S̲I̲N̲G̲
Purpose: 1) Verify that SETB is properly transmitted
when HOST request is entered in HOST
interface area.
2) Verify Receiver's response to SETB.
Test De- LTU will have been placed in opened state.
scription: HOST Emulation routine will place OPEN
̲EDC command in HOST interface area.
Results: 1) Transmitter should send SETB and RR
2) Receiver should respond with ACK
3) All transmitter and receiver variables
should reflect that the line is up
and ready for transmission.
T̲e̲s̲t̲ ̲2̲.̲ ̲D̲A̲T̲A̲ ̲B̲L̲O̲C̲K̲ ̲P̲R̲O̲C̲E̲S̲S̲I̲N̲G̲
Purpose: 1) Verify that data block is transmitted
2) Verify receiver's response
Test De- HOST Emulation routine will place data
buffer
scription: address in HOST interface area.
Results: 1) Transmitter should send properly framed
data block.
2) Receiver should accept data block
3) All transmitter and receiver tables
should reflect that a data block was
sent and received.
T̲e̲s̲t̲ ̲3̲.̲ ̲D̲A̲T̲A̲ ̲B̲L̲O̲C̲K̲ ̲A̲C̲K̲N̲O̲W̲L̲E̲D̲G̲E̲
Purpose: 1) Verify that Receiver responds to data
block with ACK
2) Verify that Transmitter accepts ACK
Test De- HOST Emulation routine will place input
scription: enabled in HOST interface area. Emulation
routine will scan interface area for received
data and respond with acknowledgement command.
Results: 1) Receiver will send back ACK
2) Transmitter will accept ACK and release
buffer to HOST.
T̲e̲s̲t̲ ̲4̲.̲ ̲A̲C̲K̲T̲O̲
Purpose: 1) Verify that transmitter sets ACKTO
2) Verify that ACKTO routine is functioning
3) Verify that RR is transmitted
4) Verify that Receiver responds with
ACK.
Test De- HOST Emulation routine will place data
buffer
scription: address in HOST interface area. After ACKTO
the HOST Emulation routine will respond
with acknowledge command.
Results: 1) The Transmitter will send data block
2) ACKTO will expire
3) Transmitter will send RR
4) Receiver will respond with ACK
T̲e̲s̲t̲ ̲5̲.̲ ̲N̲O̲ ̲R̲E̲C̲E̲I̲V̲E̲R̲ ̲R̲E̲S̲P̲O̲N̲S̲E̲
Purpose: 1) Verify ACKTO
2) Verify that Transmitter correctly handles
multiple ACKTO
3) Verify that Transmitter responds to
HOST with line status.
Test De- HOST Emulation routine will place data
scription: buffer address in HOST interface area (TX).
Results: 1) Transmitter will send data block
2) ACKTO will expire 4 times
3) Transmitter will send RR four times
4) Transmitter will close down the line
with fatal error and report condition
to the HOST.
T̲e̲s̲t̲ ̲6̲.̲ ̲L̲I̲N̲E̲ ̲R̲E̲-̲E̲S̲T̲A̲B̲L̲I̲S̲H̲M̲E̲N̲T̲
Purpose: 1) Verify that Transmitter can re-establish
link after failure
Test De- HOST Emulation routine will place data
buffer
scription: address in HOST interface area (TX), scan
for status showing line status to be "down"
and respond with command to OPEN ̲EDC.
Results: 1) Transmitter will send segment block
2) ACKTO will expire 4 times
3) Transmitter will close down the line
and report status to HOST
4) HOST will request SETB
5) Transmitter will send SETB, RR
6) Receiver will respond with ACK
7) All receive buffers will be released.
T̲e̲s̲t̲ ̲7̲.̲ ̲B̲L̲O̲C̲K̲ ̲R̲E̲-̲T̲R̲A̲N̲S̲M̲I̲S̲S̲I̲O̲N̲ ̲-̲ ̲S̲I̲N̲G̲L̲E̲
Purpose: Verify Transmitter's ability to re-transmit
a single data block
Test De- Transmitter will increment the block sequence
scription: number placed in the BID. This will cause
the receiver to believe that a block is
missing. HOST Emulator will accept all
received blocks.
Results: 1) Transmitter will send SETB (J)
2) Transmitter will send segment data
block with BID = J+2
3) Transmitter will send RR (J+2)
4) Receiver will respond with NAK (J+1)
5) Transmitter will send segment data
block with BID = J+1
6) Receiver will respond with ACK (J+1),
ACK (J=2)
T̲e̲s̲t̲ ̲8̲.̲ ̲B̲L̲O̲C̲K̲ ̲R̲E̲-̲T̲R̲A̲N̲S̲M̲I̲S̲S̲I̲O̲N̲ ̲-̲ ̲T̲W̲O̲
Purpose: Verify Transmitter's ability to re-transmit
two consecutive data blocks.
Test De- Transmitter will increment the block sequence
scription: number placed in the BID by 2. This will
cause the Receiver to believe that two
blocks are missing. The HOST Emulator will
accept all received blocks.
Results: 1) Transmitter will send SETB (J)
2) Transmitter will send segment data
block with BID = J+3
3) Transmitter will send RR (J+3)
4) Receiver will respond with NAK (J+1
, J+2)
5) Transmitter will send data blocks (not
EOS) with sequence numbers = J+1, J+2
6) Receiver will respond with ACK (J+3)
T̲e̲s̲t̲ ̲9̲.̲ ̲B̲L̲O̲C̲K̲ ̲R̲E̲-̲T̲R̲A̲N̲S̲M̲I̲S̲S̲I̲O̲N̲-̲ ̲T̲H̲R̲E̲E̲
Purpose: Verify Transmitter's ability to re-transmit
three consecutive data blocks, and Receiver's
ability to format NAK.
Test De- Transmitter will increment sequence number
scription: placed in the BID by 3. This will cause
the Receiver to believe that three blocks
are missing. The HOST Emulator will accept
all received blocks.
Results: 1) Transmitter will send SETB (J)
2) Transmitter will send data segment
block with BID = J+4
3) Transmitter will send RR (J+4)
4) Receiver will respond with NAK (J+1,
J+3)
5) Transmitter will send data blocks (not
EOS) with BID = J+1, BID = J+2, and
BID = J+3.
6) Receiver will respond with ACK (J+4).
T̲e̲s̲t̲ ̲1̲0̲.̲ ̲B̲L̲O̲C̲K̲ ̲R̲E̲-̲T̲R̲A̲N̲S̲M̲I̲S̲S̲I̲O̲N̲ ̲-̲ ̲F̲O̲U̲R̲
Purpose: Verify Transmitter's ability to re-transmit
four consecutive data blocks, and Receiver's
ability to format NAK.
Test De- Transmitter will increment sequence number
scription: placed in the BID by 4. This will cause
the Receiver to believe that four blocks
are missing. The HOST Emulator will accept
all received blocks.
Results: 1) Transmitter will send SETB (J)
2) Transmitter will send data segment
block with BID = J+5
3) Transmitter will send RR (J+5)
4) Receiver will respond with NAK (J+1,
J+4)
5) Transmitter will send data blocks (not
EOS) with BID = J+1, BID = J+3, BID
= J+4
6) Receiver will respond with ACK (J+5)
T̲e̲s̲t̲ ̲1̲1̲.̲ ̲B̲L̲O̲C̲K̲ ̲R̲E̲-̲T̲R̲A̲N̲S̲M̲I̲S̲S̲I̲O̲N̲ ̲-̲ ̲N̲A̲K̲F̲
Purpose: 1) Verify Transmitter's ability to retransmit
five data blocks
2) Verify that Receiver sends NAKF.
Test De- Transmitter will increment sequence number
scription: placed in BID by 5. This will cause the
Receiver to believe that five blocks are
missing. HOST Emulator will acknowledge
all received blocks.
Results: 1) Transmitter will send SETB (J)
2) Transmitter will send data segment
block with BID = J+6
3) Transmitter will send RR (J+6)
4) Receiver will respond with NAKF (J+1)
5) Transmitter will send data blocks (not
EOS) with BID = J+1, BID = J+2, BID
= J+3, BID = J+4, BID = J+5, BID =
J+6
6) Receiver will respond with ACK (J+6)
Test 12. B̲L̲O̲C̲K̲ ̲R̲E̲-̲T̲R̲A̲N̲S̲M̲I̲S̲S̲I̲O̲N̲ ̲-̲ ̲D̲A̲T̲A̲ ̲V̲E̲R̲I̲F̲I̲C̲A̲T̲I̲O̲N̲
Purpose: Verify that receiver correctly constructs
message with missing blocks
Test De- Transmitter will send one segment, then
the
scription: first block of the next segment and skip
two blocks, sending the next (with EOS).
Results: 1) Transmitter will send segment data
block, BID = J
2) Receiver will respond with ACK (J)
3) Transmitter will send data block, BID
= J+1
4) Transmitter will send segment data
block, BID = J+4
5) Transmitter will send RR (J+4)
6) Receiver will send NAK (J+2, J+3)
7) Transmitter will send data blocks with
BID = J+2, BID = J+3
8) Receiver will respond with ACK (J+4)
9) Received message will be verified to
be complete.
Test 13. B̲L̲O̲C̲K̲ ̲R̲E̲-̲T̲R̲A̲N̲S̲M̲I̲S̲S̲I̲O̲N̲ ̲-̲ ̲A̲L̲T̲E̲R̲N̲A̲T̲E̲ ̲B̲L̲O̲C̲K̲S̲:̲
̲S̲I̲N̲G̲L̲E̲
Purpose: Exercise transmitter and receiver for block
re-transmission
Test De- Transmitter will transmit data blocks with
scription: alternating sequential BID's, i.e. J, J+2,
J+4, J+6, ending with EOS. HOST Emulator
will accept all received blocks.
Results: 1) Transmitter will send data blocks with
BID = J, J+2, J+4 and EOS block with
BID = J+6
2) Transmitter will send RR (J+6)
3) Receiver will respond with NAK (J+1),
NAK (J+3) NAK (J+5)
4) Transmitter will send data blocks with
BID = J+1, BID = J+3 and BID = J+5.
5) Receiver will respond with ACR (J+6).
T̲e̲s̲t̲ ̲1̲4̲.̲ ̲B̲L̲O̲C̲K̲ ̲R̲E̲-̲T̲R̲A̲N̲S̲M̲I̲S̲S̲I̲O̲N̲ ̲-̲ ̲A̲L̲T̲E̲R̲N̲A̲T̲E̲ ̲B̲L̲O̲C̲K̲S̲:̲
̲D̲O̲U̲B̲L̲E̲
Purpose: Exercise transmitter and receiver for multiple
block re-transmission.
Test De-
scription: Transmitter will transmit data blocks with
two missing for each block sent. HOST Emulator
will accept all blocks received.
Results: 1) Transmitter will send data blocks with
two blocks missing for each block sent,
i.e. BID = J, BID = J+3, BID = J+6
2) Transmitter will send RR (J+6)
3 Receiver will respond with NAK (J+1,
J+2), NAK (J+4, J+5)
4) Transmitter will send BID = J+1, BID
= J+2, BID = J+4, BID = J+5
5) Receiver will respond with ACK (J+6)
T̲e̲s̲t̲ ̲1̲5̲.̲ ̲B̲L̲O̲C̲K̲ ̲O̲U̲T̲ ̲O̲F̲ ̲R̲A̲N̲G̲E̲ ̲-̲ ̲N̲O̲ ̲S̲E̲G̲M̲E̲N̲T̲S̲ ̲O̲U̲T̲S̲T̲A̲N̲D̲I̲N̲G̲
Purpose: Verify that Receiver recognizes that a
block with BID greater than last acknowledged
+ 32 is out of range
Test De-
scription: Transmitter will send an out of range block,
with no data segments outstending, i.e.
which have not been acknowledged.
Results: 1) Transmitter will send SETB (J)
2) Transmitter will send data block with
BID = J+32
3) Receiver will ignore the data block
4) Transmitter will send RR (J+32)
5) Receiver will send NAKF (J+1)
T̲e̲s̲t̲ ̲1̲6̲.̲ ̲B̲L̲O̲C̲K̲ ̲O̲U̲T̲ ̲O̲F̲ ̲R̲A̲N̲G̲E̲ ̲-̲ ̲O̲N̲E̲ ̲S̲E̲G̲M̲E̲N̲T̲ ̲O̲U̲T̲S̲T̲A̲N̲D̲I̲N̲G̲
Purpose: Verify that Receiver recognizes that a
block with BID greater than last received
EOS + 16 is out of range.
Test De-
scription: Transmitter will send an EOS block followed
by a block which is out of range.
Results: 1) Transmitter will send SETB (J)
2) Transmitter will send EOS block, BID
= J+1
3) Transmitter will send data block with
BID = J+18
4) Transmitter will send RR (J+18)
5) Receiver will send NAKF (J+2)
T̲e̲s̲t̲ ̲1̲7̲.̲ ̲B̲L̲O̲C̲K̲ ̲O̲U̲T̲ ̲O̲F̲ ̲R̲A̲N̲G̲E̲ ̲-̲ ̲T̲W̲O̲ ̲S̲E̲G̲M̲E̲N̲T̲S̲ ̲O̲U̲T̲S̲T̲A̲N̲D̲I̲N̲G̲
Purpose: Verify that Receiver recognizes that a
block with BID greater than last received
EOS is out of range.
Test De-
scription: Transmitter will send two EOS block followed
by a block which is out of range i.e. any
block.
Results: 1) Transmitter will send EOS with BID
= J
2) Transmitter will send EOS with BID
= J+1
3) Transmitter will send data block with
BID = J+2
4) Transmitter will send RR (J+2)
5) Receiver will send NAKF (J+2)
T̲e̲s̲t̲ ̲1̲8̲.̲ ̲T̲R̲A̲N̲S̲M̲I̲T̲T̲E̲R̲ ̲W̲I̲L̲L̲ ̲S̲E̲N̲D̲ ̲A̲ ̲M̲A̲X̲I̲M̲U̲M̲ ̲O̲F̲ ̲T̲W̲O̲ ̲S̲E̲G̲M̲E̲N̲T̲S̲
Purpose: Verify that Transmitter sends at most two
outstanding or unacknowledged segments.
Test De-
scription Receiver will not respond, but Transmitter's
table contains at least three segments
of data. Each segment will contain 4 blocks.
Results: 1) Transmitter will transmit 8 blocks
including 2 EOS
2) Transmitter will send RR (J+8)
3) Receiver will respond with ACK (J)
T̲e̲s̲t̲ ̲1̲9̲.̲C̲O̲N̲T̲I̲N̲U̲O̲U̲S̲ ̲T̲R̲A̲N̲S̲M̲I̲S̲S̲I̲O̲N̲ ̲W̲I̲T̲H̲ ̲O̲N̲E̲ ̲B̲L̲O̲C̲K̲ ̲O̲U̲T̲S̲T̲A̲N̲D̲I̲N̲G̲
Purpose: To verify that the transmitter can sustain
transmission if at most one data block
at a time remains outstanding.
Test De-
scription: Transmit table will be filled with buffers
to send. HOST Emulator acknowledges received
blocks in such a manner that at no time
will two blocks remain outstanding.
Results: Data flow will remain continuous with each
transmitted block acknowledged while the
next one is being transmitted.
T̲e̲s̲t̲ ̲2̲0̲.̲ ̲C̲E̲S̲S̲A̲T̲I̲O̲N̲ ̲O̲F̲ ̲T̲R̲A̲N̲S̲M̲I̲S̲S̲I̲O̲N̲ ̲W̲H̲I̲L̲E̲ ̲R̲R̲ ̲I̲N̲ ̲P̲R̲O̲G̲R̲E̲S̲S̲
Prupose: To verify that the Transmitter does not
send data blocks following an RR block
until ACK is received to RR.
Test De-
scription: Transmitter will send an RR block and the
transmit table will be filled with data
buffers to be sent.
Results: The transmitter will send no data blocks
until an ACK is received from the receiver.
When this occurs transmission will be continuous.
T̲e̲s̲t̲ ̲2̲1̲.̲ ̲R̲E̲S̲U̲M̲P̲T̲I̲O̲N̲ ̲O̲F̲ ̲T̲R̲A̲N̲S̲M̲I̲S̲S̲I̲O̲N̲ ̲W̲H̲E̲N̲ ̲D̲A̲T̲A̲ ̲A̲V̲A̲I̲L̲A̲B̲L̲E̲
F̲R̲O̲M̲ ̲H̲O̲S̲T̲
Purpose: To verify that the transmitter will immediately
resume transmission after an idle state
caused by lack of available transmission
data.
Test De-
scription: The HOST Emulator will make a transmission
block available, wait until transmission
has been completed (but not acknowledged)
and then make another block available.
Results: 1) Transmitter will send a block
2) Transmitter will send another block
3) Transmitter will send RR for both blocks
T̲e̲s̲t̲ ̲2̲2̲.̲ ̲I̲D̲L̲E̲ ̲T̲I̲M̲E̲ ̲H̲A̲N̲D̲S̲H̲A̲K̲I̲N̲G̲
Purpose: To verify that the transmitter and receiver
exchange protocol blocks when no data is
queued for transmission.
Test De-
scription: The HOST Emulator will request that the
link be established.
Results: 1) The Trnasmitter will periodically send
RR (J) blocks.
2) The Receiver will respond with ACK
(J) blocks.
T̲e̲s̲t̲ ̲2̲3̲ ̲E̲O̲M̲ ̲R̲E̲C̲E̲P̲T̲I̲O̲N̲
Purpose: To verify EOM block handling.
Test De-
scription: The Transmitter will send an EOM data block.
The HOST Emulator will acknowledge all
blocks received.
Results: 1) The Transmitter will send an EOM block
with BID = J.
2) The Receiver will respond with ACK
(J).
T̲e̲s̲t̲ ̲2̲4̲.̲ ̲V̲A̲R̲Y̲I̲N̲G̲ ̲B̲L̲O̲C̲K̲S̲I̲Z̲E̲
Purpose: To verify that the transmitter can handle
varying blocksize.
Test De-
scription: The HOST Emulator will request data blocks
of differing block size.
Results: Transmission will continue without interruption.
Block size will wary according to command.
T̲e̲s̲t̲ ̲2̲5̲.̲ ̲D̲U̲A̲L̲ ̲C̲H̲A̲N̲N̲E̲L̲
Purpose: To verify that LTU can sustain two channels
simultaneously.
Test De-
scription: The HOST Emulator will request that two
lines be established and will queue data
blocks for each.
T̲e̲s̲t̲ ̲2̲6̲.̲ ̲L̲C̲B̲ ̲P̲R̲O̲C̲E̲S̲S̲I̲N̲G̲
Purpose: To verify that proper processing of line
control blocks occurs.
Test De-
scription: HOST Emulation routine will post a LCB
to be transmitted.
Results: 1) The Transmitter will send the LCB.
2) The Receiver will respond with ACKL.
T̲e̲s̲t̲ ̲2̲7̲.̲ ̲L̲C̲B̲ ̲P̲R̲O̲C̲E̲S̲S̲I̲N̲G̲ ̲-̲ ̲H̲O̲S̲T̲ ̲E̲R̲R̲O̲R̲
Purpose: To verify that LTU will handle only one
LCB at a time.
Test De-
scription: HOST Emulation routine will post an LCB
for transmission. Before transmission complete
for the LCB occurs the HOST Emulator will
post another LCB for transmission.
Results: 1) The Transmitter will send the first
LCB
2) The transmitter will return the second
LCB to the HOST with error status set.
3) THE Receiver will send ACKL.
T̲e̲s̲t̲ ̲2̲8̲.̲ ̲L̲C̲B̲ ̲R̲P̲O̲C̲E̲S̲S̲I̲N̲G̲ ̲-̲ ̲T̲X̲ ̲E̲R̲R̲O̲R̲
Purpose: Verify that the Receiver will accept only
one LCB at a time.
Test De-
scription: The Transmitter will send two line control
blocks with different sequence numbers.
The HOST Emulator will accept the first
LCB.
Results: 1) The Transmitter will send two LCB's
with different sequence numbers.
2) The Receiver will accept the first
and post LCB to HOST.
3) The Receiver will ignore the second
LCB.
4) The HOST will accept the LCB.
5) The Receiver will respond with ACKL
for the first LCB.
T̲e̲s̲t̲ ̲2̲9̲.̲ ̲L̲C̲B̲ ̲P̲R̲O̲C̲E̲S̲S̲I̲N̲G̲ ̲-̲ ̲R̲E̲-̲T̲R̲A̲N̲S̲M̲I̲S̲S̲I̲O̲N̲/̲T̲E̲R̲M̲I̲N̲A̲T̲I̲O̲N̲
Purpose: To verify that the Transmitter will re-transmit
an unacknowledged LCB when the ACKLTO expires,
for a maximum of 4 tries.
Test De-
scription: The HOST Emulator will post an LCB for
transmission. The HOST Emulator will not
acknowledge the received LCB.
Results: 1) The Transmitter will send the LCB.
2) ACKLTO will expire.
3) The Transmitter will send the LCB.
4) The scenario will repeat 4 times.
5) The Transmitter will return a transmission
completed with error status to the
HOST.
T̲e̲s̲t̲ ̲3̲0̲.̲ ̲L̲C̲B̲ ̲P̲R̲O̲C̲E̲S̲S̲I̲N̲G̲ ̲-̲ ̲R̲E̲-̲T̲R̲A̲N̲S̲M̲I̲S̲S̲I̲O̲N̲/̲A̲C̲C̲E̲P̲T̲A̲N̲C̲E̲
Purpose: To verify that the Transmitter will re-transmit
an unacknowledged LCB when ACKLTO expires.
Test De-
scription: The HOST Emulator will post an LCB for
transmission. The HOST Emulator will acknowledge
the received LCB after ACKLTO expires.
Results: 1) The Transmitter will send for LCB
2) ACKLTO will expire
3) The Transmitter will re-transmit the
LCB
4) The Receiver will respond with ACKL
5) The Transmitter will return the LCB
buffer with good status to the HOST.
T̲e̲s̲t̲ ̲3̲1̲.̲ ̲M̲O̲D̲E̲M̲ ̲S̲Y̲N̲C̲H̲R̲O̲N̲I̲Z̲A̲T̲I̲O̲N̲ ̲(̲R̲E̲M̲O̲T̲E̲)̲
Purpose: To verify that modem/crypto processing
is correct for the remote mode.
Test De-
scription: The HOST Emulator will request link establishment.
Necessary reponse pulses will be applied
to the SIO to emulate modem/crypto.
Results: The correct pattern of synchronizing signals
will be observed using an oscilliscope.
T̲e̲s̲t̲ ̲3̲2̲.̲ ̲M̲O̲D̲E̲M̲ ̲R̲E̲S̲Y̲N̲C̲H̲R̲O̲N̲I̲Z̲A̲T̲I̲O̲N̲ ̲(̲R̲E̲M̲O̲T̲E̲)̲
Purpose: To verify that the modem resynchronization
process is executed correctly when 109
signal is lost.
Test De-
scription The 109 signal will be re-set.
Results: The LTU will clear the link and begin the
modem/crypto re-synchronization procedure.
T̲e̲s̲t̲.̲ ̲3̲3̲ ̲L̲I̲N̲E̲ ̲S̲Y̲N̲C̲H̲R̲O̲N̲I̲Z̲A̲T̲I̲O̲N̲ ̲-̲ ̲L̲O̲C̲A̲L̲ ̲M̲O̲D̲E̲
Purpose: To verify that line establishment is correct
for local mode.
Test De-
scription The HOST Emulator will request link establishment.
Necessary pulses will be applied to SIO
to emulate TARE.
Results: The correct pattern of synchronizing signals
will be observed using an oscilliscope.
T̲e̲s̲t̲ ̲3̲4̲.̲ ̲T̲R̲A̲N̲S̲M̲I̲S̲S̲I̲O̲N̲ ̲E̲R̲R̲O̲R̲ ̲-̲ ̲B̲A̲D̲ ̲C̲R̲C̲
Pupose: To verify that Receiver can detect CRC
error and NAK the block.
Test De-
scription: An incorrect length will be placed in the
block header causing the Receiver to calculate
bad CRC. BID = Next expected.
Results: 1) Transmitter will send data block with
invalid length.
2) Receiver will send NAK.
3) Transmitter will send data block with
valid length.
4) Receiver will send ACK.
T̲e̲s̲t̲ ̲3̲5̲.̲ ̲C̲R̲C̲ ̲E̲R̲R̲O̲R̲ ̲-̲ ̲N̲O̲T̲ ̲N̲E̲X̲T̲ ̲B̲L̲O̲C̲K̲ ̲E̲X̲P̲E̲C̲T̲E̲D̲
Purpose: To verify that the Receiver can detect
bad CRC and will ignore the block if BID
does not equal next expected.
Test De-
scription: The Transmitter will send SETB followed
by block with a BID = J+2 and invalid CRC.
The invalid length will cause the Receiver
to detect a CRC error.
Resutls: 1) Transmitter sends SETB (J).
2) Transmitter sends RR (J).
3) Receiver sends ACK (J).
4) Transmitter sends segment data block,
BID = J+2 (Invalid length).
5) Receiver sees CRC error and ignores
the block.
6) ACKTO expires.
7) Transmitter sends RR (J+2).
8) Receiver sends NAKF (J+1).
T̲e̲s̲t̲ ̲3̲6̲.̲ ̲T̲R̲A̲N̲S̲M̲I̲S̲S̲I̲O̲N̲ ̲E̲R̲R̲O̲R̲ ̲-̲ ̲D̲U̲P̲L̲I̲C̲A̲T̲E̲ ̲B̲L̲O̲C̲K̲S̲ ̲-̲ ̲E̲O̲S̲
Purpose: To verify that Receiver will ignore the
duplicata EOS block.
Test De-
scription: Transmitter will send two segment blocks.
Results: The Receiver will ACK the first and ignore
the second.
T̲e̲s̲t̲ ̲3̲7̲.̲ ̲T̲R̲A̲N̲S̲M̲I̲S̲S̲I̲O̲N̲ ̲E̲R̲R̲O̲R̲ ̲-̲ ̲D̲U̲P̲L̲I̲C̲A̲T̲A̲ ̲B̲L̲O̲C̲K̲S̲ ̲-̲ ̲D̲A̲T̲A̲
B̲L̲O̲C̲K̲S̲
Purpose: To verify that Receiver will ignore the
duplicata block, but accept all valid blocks.
Test De- The Transmitter will send one block twice
and
scription: then send valid data blocks culminating
with EOS block.
Results: 1) The Transmitter will send blocks with
BID = J, BID = J, BID = J+1, BID =
J+2, and EOS block with BID = J+3.
2) Receiver will respond with ACK (J+3).
3) Correct message will be returned to
HOST.
T̲e̲s̲t̲ ̲3̲8̲.̲ ̲T̲R̲A̲N̲S̲M̲I̲S̲S̲I̲O̲N̲ ̲E̲R̲R̲O̲R̲ ̲-̲ ̲P̲A̲R̲I̲T̲Y̲ ̲E̲R̲R̲O̲R̲ ̲I̲N̲ ̲B̲I̲D̲
Purpose: To verify that the Receiver will ignore
a block with parity error in BID field.
Test De-
scription Transmitter will send out segment block
with even parity BID. Later the Transmitter
will send the block with odd parity BID.
Results: 1) Transmitter will send data segment
block with even parity BID.
2) Receiver will ignore the data block.
3) Transmitter will send RR (J+1).
4) Receiver will respond with NAKF (J).
5) Transmtitter will re-transmit data
segment block with odd parity BID.
6) Receiver will respond with ACK (J+1).
T̲e̲s̲t̲ ̲3̲9̲.̲ ̲T̲R̲A̲N̲S̲M̲I̲S̲S̲I̲O̲N̲ ̲E̲R̲R̲O̲R̲ ̲-̲ ̲P̲A̲R̲I̲T̲Y̲ ̲E̲R̲R̲O̲R̲ ̲I̲N̲ ̲C̲H̲A̲R̲A̲C̲T̲E̲R̲
C̲O̲U̲N̲T̲
Purpose: To verify that Receiver will ignore a block
with parity error in CC field.
Test De- Transmitter will send out segment data
block
scription: with even parity Character Count, later,
the Transmitter will resend the block with
odd parity CC.
Results: 1) Transmitter will send data segment
block with even parity CC.
2) Receiver will ignore data block.
3) Transmitter will send RR (J+1).
4) Receiver will respond with NAKF (J).
5) Transmitter will re-transmit data segment
block with odd parity CC.
6) Receiver will respond with ACK (J+1).
T̲e̲s̲t̲ ̲4̲0̲.̲ ̲T̲R̲A̲N̲S̲M̲I̲S̲S̲I̲O̲N̲ ̲E̲R̲R̲O̲R̲ ̲-̲ ̲P̲A̲R̲I̲T̲Y̲ ̲E̲R̲R̲O̲R̲ ̲I̲N̲ ̲T̲Y̲P̲E̲
Purpose: To verify that Receiver will ignore a block
with parity error in TYPE field.
Test De-
scription: Transmitter will send out segment data
block with even parity TYPE. Later, the
Transmitter will resend the block with
odd parity TYPE.
Results: 1) Transmitter will send data segment
block with even parity TYPE.
2) Receiver will ignore data block.
3) Transmitter will send RR (J+1).
4) Receiver will respond with NAKF (J).
5) Transmitter will re-transmit data segment
block with odd parity TYPE.
6) Receiver will respond with ACK (J+1).
T̲e̲s̲t̲ ̲4̲1̲.̲ ̲L̲O̲S̲T̲ ̲N̲A̲K̲
Purpose: To verify that Transmitter recovers form
the situation in which a NAK is lost.
Test De-
scription: The Receiver will ignore the first block
and not post NAK.
Results: 1) Transmitter will send data block, BID
= J.
2) Receiver will ignore the block and
not post NAK.
3) Transmitter will send RR (J).
4) Receiver will not respond.
5) Transmitter will send RR (J)
6) Receiver will respond with NAKF (J).
7) Transmitter will resend data block.
8) Receiver will respond with ACK (J).
T̲e̲s̲t̲ ̲4̲2̲.̲ ̲L̲O̲S̲T̲ ̲A̲C̲K̲
Purpose: To verify that Transmitter can recover
after ACK is lost.
Test De-
scription: The Receiver will not post ACK for first
valid data block received.
Results: 1) Transmitter will send valid data block
(EOS).
2) Receiver will accept block but not
post ACK in return.
3) Trnasmitter will send RR.
4) Receiver will respond with ACK.
T̲e̲s̲t̲ ̲4̲3̲.̲ ̲L̲O̲S̲T̲ ̲R̲R̲
Purpose: To verify that Transmitter can recover
after RR is lost.
Test De-
scription: The Receiver will ignore the first RR received.
Results: 1) Transmitter will send SETB.
2) Transmitter will send RR.
3) Receiver will ignore RR.
4) ACKTO will expire.
5) Transmitter will send RR.
6) Receiver will respond with ACK
T̲e̲s̲t̲ ̲4̲4̲.̲ ̲S̲E̲T̲B̲ ̲W̲I̲T̲H̲ ̲T̲R̲A̲N̲S̲M̲I̲S̲S̲I̲O̲N̲ ̲I̲N̲ ̲P̲R̲O̲G̲R̲E̲S̲S̲
Purpose: To verify that Receiver and Transmitter
can properly handle SETB when transmission
is in progress:
Test De
scription: The HOST Emulator will post 4 data
blocks for transmission: Then it will
post a SETB. CLOSE followed by OPEN
command.
Results: 1) The Transmitter will send the 4 data
blocks.
2) The Transmitter will send the SETB
block and RR block.
3) The 4 outstanding blocks will be returned
to the HOST with a status of cancelled.
4) The Receiver will release all filled
data buffers and respond with ACK.
T̲e̲s̲t̲ ̲4̲5̲.̲ ̲R̲E̲C̲E̲I̲V̲E̲R̲ ̲D̲O̲W̲N̲
Purpose: To verify that Transmitter downs the line
if the Receiver fails to respond.
Test De-
scription: The Receiver will cease to function in
mid-stream.
Results: 1) The Transmitter will send out EOS.
2) Receiver will respond with ACK.
3) Transmitter will send out 4 data blocks
and EOS.
4) The Receiver will cease to respond.
5) The Transmitter will send RR.
6) No response.
7) The Transmitter will send 4 RR's and
then return a line down status to HOST.
The 4 outstanding line blocks will
be returned to the HOST with an error
status:
T̲e̲s̲t̲ ̲4̲6̲.̲ ̲S̲I̲X̲T̲E̲E̲N̲ ̲B̲L̲O̲C̲K̲S̲ ̲P̲E̲R̲ ̲S̲E̲G̲M̲E̲N̲T̲ ̲-̲ ̲T̲W̲O̲ ̲S̲E̲G̲M̲E̲N̲T̲S̲
Purpose: To verify that both Transmitter and Receiver
can handle sixteen blocks per segment (32
bytes/block).
Test De-
scription: The HOST Emulator will post 15 data blocks
and 1 EOS to the Transmitter. Then the
HOST Emulator will repeat the process.
This constitutes two segments:
Results: 1) The Transmitter will send all 16 blocks.
2) The Receiver will respond with ACK.
3) The Transmitter will release the buffers
to the HOST with a status of success.
4) The Receiver will release the message
segment to the HOST with status of
success.
5) Steps 1 through 4 will be repeated.
T̲e̲s̲t̲ ̲4̲7̲.̲ ̲E̲I̲G̲H̲T̲ ̲B̲L̲O̲C̲K̲S̲ ̲P̲E̲R̲ ̲S̲E̲G̲M̲E̲N̲T̲ ̲-̲ ̲T̲W̲O̲ ̲S̲E̲G̲M̲E̲N̲T̲S̲
Purpose: To verify that both Transmitter and Receiver
can handle eight blocks per segment (64
bytes/block).
Test De-
scription: The HOST Emulator will post 7 data blocks
and 1 EOS to the transmitter: Then the
HOST Emulator will repeat the process.
This constitutes two segments.
Results: 1) The Transmitter will send 8 data blocks.
2) The Receiver will respond with ACK.
3) The Transmitter will release the buffer
to the HOST with a status of success.
4) The Receiver will release the message
segment to the HOST with a status of
success.
5) Steps 1 Through 4 will be repeated.
T̲e̲s̲t̲ ̲4̲8̲.̲ ̲F̲O̲U̲R̲ ̲B̲L̲O̲C̲K̲S̲ ̲P̲E̲R̲ ̲S̲E̲G̲M̲E̲N̲T̲ ̲-̲ ̲T̲W̲O̲ ̲S̲E̲G̲M̲E̲N̲T̲S̲
Purpose: To verify that both Transmitter and Receiver
can handle four blocks per segment (128
bytes/block).
Test De-
scription: The HOST Emulator will post 3 data blocks
and 1 EOS to the Transmitter. Then the
HOST Emulator will repeat the process.
This constitutes two segments.
Results: 1) Transmitter will send 4 data blocks.
2) Receiver will respond with ACK.
3) Transmitter will release the 4 data
buffers to the HOST with a status of
success.
4) Receiver will release message segment
to HOST with status of success.
5) Steps 1 through 4 will be repeated.
T̲e̲s̲t̲ ̲4̲9̲.̲ ̲T̲W̲O̲ ̲B̲L̲O̲C̲K̲S̲ ̲P̲E̲R̲ ̲S̲E̲G̲M̲E̲N̲T̲ ̲-̲ ̲T̲W̲O̲ ̲S̲E̲G̲M̲E̲N̲T̲S̲
Purpose: To verify that both Transmitter and Receiver
can handle two blocks per segment (256
bytes/block).
Test De-
scription: The HOST Emulator will post a data block
followed by an EOS block. Then the HOST
Emulator will repeat the process. This
constitutes two data segments.
Results: 1) Transmitter will send two data blocks.
2) Receiver will respond with ACK.
3) Transmitter will release the 4 data
buffers to the HOST with a status of
success.
4) The Receiver will release the message
segment to the HOST with a status of
success.
5) Steps 1 through 4 will be repeated.
T̲e̲s̲t̲ ̲5̲0̲.̲ ̲O̲N̲E̲ ̲B̲L̲O̲C̲K̲ ̲P̲E̲R̲ ̲S̲E̲G̲M̲E̲N̲T̲ ̲-̲ ̲T̲W̲O̲ ̲S̲E̲G̲M̲E̲N̲T̲S̲
Purpose: To verify that both Transmitter and Receiver
can handle one block per segment (512 bytes/block).
Test De-
scription: The HOST Emulator will post two EOS blocks
to the Transmitter.
Results: 1) Transmitter will send two data blocks.
2) Receiver will send two ACK's.
3) Transmitter will release two data buffers
to HOST with status of success.
4) Receiver will release two message segments
to the HOST with status of success.
A̲P̲P̲E̲N̲D̲I̲X̲ ̲A̲1̲
̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲
0
I̲N̲D̲E̲X̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲
O̲W̲N̲E̲R̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ 1 BUFFER (INDEX) .OWNER
T̲E̲M̲P̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ 2
̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ 3
4
B̲Y̲T̲E̲C̲O̲U̲N̲T̲ ̲ ̲ ̲ 5 BUFFER (INDEX) .BYTECOUNT
ADDRESS OF 6
D̲A̲T̲A̲ ̲B̲U̲F̲F̲E̲R̲ ̲ 7 BUFFER (INDEX) .ADDR
T̲ ̲T̲Y̲P̲E̲ ̲ ̲ ̲ ̲ ̲ ̲ 8 BUFFER (INDEX) .T ̲TYPE (TEMP STORAGE)
T̲ ̲S̲E̲Q̲ ̲N̲O̲ ̲ ̲ ̲ ̲ 9 BUFFER (INDEX) .T ̲SEQ ̲NO (TEMP STORAGE)
T̲#̲S̲E̲G̲ ̲T̲Y̲P̲E̲ ̲ ̲ 10 BUFFER (INDEX) .T ̲SEG ̲TYPE (TEMP STORAGE)
̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ 11
C̲1̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ 12 BUFFER (INDEX) .C1
C̲O̲D̲E̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ 13 BUFFER (INDEX) .CODE
DATA- L̲D̲U̲-̲I̲D̲ ̲ ̲ ̲ ̲ ̲ ̲ 14 BUFFER (INDEX) LDU-ID
BUFFER
B̲I̲D̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ 15 BUFFER (INDEX) .BID
16 BUFFER (INDEX) .DATA
DATA
SEGMENT
̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ 517
All Buffers are identified by a Buffer index (BYTE0).
Fields within the Buffer are referenced in the documentation
as shown above. All HOST references are to buffer address.
Most LTU references are to buffer index.
A̲P̲P̲E̲N̲D̲I̲X̲ ̲A̲2̲,̲ ̲H̲O̲S̲T̲ ̲C̲O̲M̲M̲A̲N̲D̲S̲
1. INPUT REQUEST An input request signals
to the LTU that the handler
is ready to receive an LDU
of data.
2. CANCEL INPUT REQUEST Cancel specified input requests
of data if pending.
3. CANCEL OUTPUT If a data buffer is still
queued for the protocol and
transmission has not yet
been started a cancel shall
be as if the data buffer
was never queued.
4. REPORT STATUS HOST commands used for controlling
the protocol.
1) ENABLE
2) OPEN EDC
3) CLOSE EDC
4) REDEFINE EDC PARAMETERS
5) COLLECT STATISTICS
6) PROTOCOL STATUS + LEVEL 1 STATUS (EDC STATE)
7) ACKNOWLEDGE
5. OPEN CHANNEL Used to enable the CR80-LTU
interface.
6. CLOSE CHANNEL Used to disable the CR80-LTU
interface.
A̲P̲P̲E̲N̲D̲I̲X̲ ̲A̲3̲
Setup Parameters Specified by the HOST in ENABLE Command
H̲O̲S̲T̲ ̲P̲a̲r̲a̲m̲e̲t̲e̲r̲: L̲T̲U̲ ̲V̲a̲r̲i̲a̲b̲l̲e̲
1. Definition REMOTE/LOCAL TARE IF ̲STATE
2. Baudrate BAUD ̲RATE
3. LEVEL 1 Timeout (remote TARE) LEVEL#1
̲STO
4. Retry Count LEVEL 1 (Remote TARE) SYN ̲RETRY
̲MAX
5. Block Size BLOCK ̲SIZE
6. ACKTO Timeout in Steps of 100 ms ACKTO ̲DELTA
7. ACKLTO Timeout in Steps of 100 ms ACKLTO ̲DELTA
8. MAX N Count NCOUNT ̲MAX
9. MSX L Count LCONT ̲MAX
10. MAX R Count RCOUNT ̲MAX
A̲P̲P̲E̲N̲D̲I̲X̲ ̲A̲4̲,̲ ̲B̲U̲F̲F̲E̲R̲ ̲U̲T̲I̲L̲I̲Z̲A̲T̲I̲O̲N̲
Each channel has its own buffers allocated to it. The
buffers are further divided into transmit and receive.
The HOST I/F area is formatted as follows:
Bytes 2-3 TX.OUT: Empty buffers returned to the
HOST for the purpose of being
used as command or data transmission
buffers.
Bytes 6-7 TX-.IN: Command and data transmission
buffers filled by the HOST.
Bytes 10-11 RX.OUT: Data reception and status buffers
filled by the LTU.
Bytes 14-15 RX.IN: Empty data reception and status
buffer returned by the HOST.
The HOST must return all buffers received in TX.OUT
to TX.IN, and all buffers received in RX.OUT to RX.IN.
The LTU will initially furnish the HOST with 3 empty
buffers via TX.OUT. Thereafter all transmission and
command buffers will be returned as empty.
The LTU will allocate status buffers and data reception
buffers from its internal pool. Those must be returned
by the HOST as empty.
A̲P̲P̲E̲N̲D̲I̲X̲ ̲A̲5̲
Variables used in statistics collection
TX ̲M ̲COUNT Number of successfully transmitted
message blocks
TX ̲L ̲COUNT Number of successfully transmitted
LCB'S
RX ̲M ̲COUNT Number of received message blocks
RX ̲L ̲COUNT Number of received LCB'S
TX ̲R ̲RR ̲COUNT Number of transmitted RR blocks
RX ̲RR ̲COUNT Number of correctly received RR
blocks
SYN ̲RETRY ̲COUNT Number of SYNC retries on LEVEL
1 (REMOTE TARE)
A̲P̲P̲E̲N̲D̲I̲X̲ ̲B̲1̲
INTERNAL TABLES
̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲
̲ ̲ ̲ ̲ ̲ ̲
TRAN ̲CIRCLE ̲LEN
̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲
̲ ̲ ̲ ̲ ̲ ̲
̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ LAST ̲ACKED
̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲
̲ ̲ ̲ ̲ ̲ ̲
INDEX ENTRY
̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ NEXT ̲TRAN
̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲
̲ ̲ ̲ ̲ ̲ ̲
TRAN ̲CIRCLE
TRAN ̲BID ̲BASE
̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲
̲ ̲ ̲ ̲ ̲ ̲
TABLE POINTERS
DIAGRAM OF TRANSMITTER TABLES
A̲P̲P̲E̲N̲D̲I̲X̲ ̲B̲1̲
̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲
CHANNEL 1
̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲
CHANNEL 2
̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲
LAST ̲ACKED
ACK ̲ONE CHANNEL 1
A̲C̲K̲ ̲T̲W̲O̲ ̲ ̲ ̲ ̲ ̲ ̲
LAST ̲ACKED
ACK ̲ONE CHANNEL 2
A̲C̲K̲ ̲T̲W̲O̲ ̲ ̲ ̲ ̲ ̲ ̲
T̲R̲A̲N̲ ̲B̲I̲D̲ ̲B̲A̲S̲E̲ CH 1
T̲R̲A̲N̲ ̲B̲I̲D̲ ̲B̲A̲S̲E̲ CH 2
LAST ̲ACKED Contains BID of FRAME, which was last
acknowledged.
ACK ̲ONE Contains the BID of an END OF SEGMENT
or END OF MESSAGE block which requires
acknowledgement.
ACK ̲TWO Contains the BID of an END OF SEGMENT
or END OF message block which requires
acknowledgement.
TRAN ̲BID ̲BASE Contains BID of first entry in TRAN
̲CIRCLE.
A̲P̲P̲E̲N̲D̲I̲X̲ ̲B̲2̲
DATA FRAME FORMAT: FORMAT 1
̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲
S S B C
Y Y C C T I VARIABLE DATA FIELD R
N N 1 2 D C
1̲ ̲2̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲
C1, C2 = FRAME LENGTH
T = DATA TYPE = D,EOS,EOM
BID = SEQUENCE NUMBER MODULO 128
CRC = 16 BIT POLYNOMINAL x16 + x12 + x + 1 (INCLUDES
SYN1, SYN2)
FORMAT 2: ACK (J), ACKL (J), NAK (J), RR (J), SETB
(J)
̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲
S S B C
Y Y C C T I R
N N 1 2 D C
1̲ ̲2̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲
T = FRAME TYPE = ACK,ACKL,NAK,RR,SETB
FORMAT 3: NAK (i,j)
̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲
S S B B C
Y Y C C T I I R
N N 1 2 D D C
1̲ ̲2̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲1̲ ̲2̲ ̲ ̲ ̲ ̲ ̲ ̲
BID 1 = i
BID 2 = j
FORMAT 4: LCB (J)
̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲
S S B C
Y Y C C T I DATA R
N N 1 2 D C
1̲ ̲2̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲
DATA: MAX. 32 CHARACTERS
A̲P̲P̲E̲N̲D̲I̲X̲ ̲B̲3̲
PENDING ̲TABLE ENTRY CH 1 or CH 2
̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲
̲G̲O̲T̲I̲T̲ ̲ ̲ = TRUE, if a packet i received
̲P̲T̲Y̲P̲E̲ ̲ ̲ = packet type (EOS,EOM,DATA)
̲L̲E̲N̲1̲ ̲ ̲ ̲ length received so far
̲L̲E̲N̲2̲ ̲ ̲ ̲ =
̲ ̲1̲ ̲ ̲ ̲ ̲ ̲
̲ ̲2̲ ̲ ̲ ̲ ̲ ̲
= offset into GATHER of
̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ relevant 32 byte piece
̲1̲6̲ ̲ ̲ ̲ ̲ ̲
Each entry in PENDING ̲TABLE corresponds to a BID.
To cope with MXSEGS unacknowledged segments of minimum
blocksize and maximum segment length, the number of
entries should be:
(B ̲MAX/B ̲MIN) * MXSEGS
A̲P̲P̲E̲N̲D̲I̲X̲ ̲C̲1̲
DIAGRAM OF LTU STATES
DISABLED OPEN ̲CHANNEL
CLOSE ̲CHANNEL
CLOSE
CHANNEL
CLOSE ̲ ENABLED
CHANNEL
ENABLE
CLOSE INITIA-
LISED
CLOSE ̲EDC/FAILURE
OPEN
̲EDC
OPENING
ERROR CLOSE ̲EDC
level 1
or EDC RUNNING LEVEL 1 ̲STATE =
SYN4
TSTATE = TSTATE3
DISABLED - LTU is passive; I/F area disabled
ENABLED - LTU has received open channel command
but no EDC PARAMETERS; I/F area enabled:
LEVEL 1 disabled
INITIALIZED - LTU has received EDC PARAMETERS; LEVEL
1 enabled
OPENING* - OPEN ̲EDC COMMAND has been received
RUNNING - LEVEL 1 is functioning and EDC has opened
FULL-DUPLEX CHANNEL
ERROR* - LEVEL 1 OR EDC FATAL ERROR
CLOSE* - Either a FATAL ERROR has occured or
a close EDC COMMAND has been received
* TRANSITION STATES
A̲P̲P̲E̲N̲D̲I̲X̲ ̲C̲1̲
RUNNING LTU ̲STATE ENABLED INITIALIZED
DISABLED
̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲
̲ ̲ ̲ ̲ ̲
INPUT ̲REQUEST OPEN ̲CHANNEL CLOSE ̲CHANNEL CLOSE ̲CHANNEL
CANCEL ̲INPUT ̲
REQUEST ENABLE OPEN ̲EDC
VALID
HOST CANCEL ̲OUTPUT
COMMANDS
CLOSE ̲EDC
REDEFINE ̲EDC
STATISTICS
PROTOCOL ̲STATUS
ACKNOWLEDGE
TRANS REQ.
CLOSE ̲CHANNEL
̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲
̲ ̲ ̲ ̲ ̲
LTU STATE MATRIX OF VALID HOST COMMANDS
DIAGRAM SHOWING WHICH HOST COMMANDS WILL BE
ACCEPTED BY THE LTU DEPENDING UPON LTU
STATE FOR THAT CHANNEL.
A̲P̲P̲E̲N̲D̲I̲X̲ ̲C̲2̲
A̲P̲P̲E̲N̲D̲I̲X̲ ̲C̲2̲
LEV1 STATES
SYN0: OPEN ̲EDC COMMAND HAS BEEN RECEIVED
SYN1: 107 OFF
SYN2: 107 ON
SYN3: TEMPORARY STATE TO CHECK 106 & 109
SYN4: NORMAL RUNNING STATE
SYN5: ERROR STATE
SYN6: ENABLED STATE
SYN7: MANUAL SYNC
SYN8: CIR 107 ON
SYN9: DISABLED
A̲P̲P̲E̲N̲D̲I̲X̲ ̲C̲3̲
TRANSMITTER STATE TRANSITIONS
TSTATE0: TRANSMITTERR has been initialized with
EDC PARAMETERS. Line is down
TSTATE1: OPEN ̲EDC COMMAND has been received from
HOST
TSTATE2: SETB BLOCK has been transmitted. LTU is
awaiting ACK
TSTATE3: Line is up. Less than two SEGMENTS have
been transmitted
TSTATE4: Line is up. Two SEGMENTS have been transmitted
TSTATE5: RR has been transmitted. LTU is awaiting
response
TSTATE6: Cleanup is in PROGRESS. This could be caused
by LEVEL1 ERROR, FATAL EDC ERROR OR CLOSE
̲EDC COMMAND from HOST.
A̲P̲P̲E̲N̲D̲I̲X̲ ̲C̲4̲
DIAGRAM OF RECEIVER STATE, R ̲STATE
READY ̲TO ̲RECIEVE - RECEIVER has buffer space and is
not in error condition. If EOS ̲1
.NE. ZERO then one SEGMENT has been
received.
NAKF: An IN-RANGE but not acceptable BID
was received. A NAKF has been sent.
Now the next expected BID must be
seen before new BID will be accepted.
Old BIDS (re-transmission will be
accepted).
MAX ̲SEG: Two SEGMENTS have been received
but not acknowledged. Only re-transmission
will be accepted.
ALL R ̲STATES ARE SUB-STATES OF LTU ̲STATE = RUNNING.
A̲P̲P̲E̲N̲D̲I̲X̲ ̲C̲5̲
DIAGRAM OF RECEIVER LCB STATE, R ̲L ̲STATE
LCB'S will only be accepted if R ̲L ̲STATE .EQ. accept
and the SEQ. number of the LCB does not match that
of the last LCB received.
BUSY indicates that the RECEIVER has received one LCB.
PENDING indicates that the LCB has been transferred
to the HOST and the LTU is waiting for an ACKNOWLEDGE
STATUS BLOCK from the HOST.
Variables associated with LCB processing are:
1) LDU ̲LCB = LDU of BLOCK transferred to the
HOST
2) LCB ̲INDEX = BUFFER INDEX of received LCB
3) LCB ̲SEQ = SEQUENCE NUMBER of LCB received.
used in acknowledgement.
R ̲L ̲STATE is SUBSTATE of LTU ̲STATE RUNNING.
A̲P̲P̲E̲N̲D̲I̲X̲ ̲D̲
1̲ ̲ ̲M̲o̲n̲i̲t̲o̲r̲ ̲D̲a̲t̲a̲s̲t̲r̲u̲c̲t̲u̲r̲e̲
Placed in PHYCONS:
1. Schedule table (SCH ̲TAB):
One byte for each TASK. If bit 7 is SET then the
TASK is cancelled. Else the byte indicate the time
(in TICKS) the TASK may wait before it will be
activated.
2. TASK Jump Table:
Contain "Jumps" to entrypoints to each TASK.
3. Delay Table (DEL ̲TAB):
One byte for each TASK (2 channels). The byte contain
the periode by which the TASK shall be activated.
Zero means that the TASK not shall be activated
periodic.
2̲ ̲ ̲I̲d̲e̲n̲t̲i̲f̲i̲c̲a̲t̲i̲o̲n̲ ̲o̲f̲ ̲D̲a̲t̲a̲m̲o̲d̲u̲l̲e̲s̲
AAAC ̲DAT LCLZ ̲DAT S ̲DAT
ACAZ ̲DAT M ̲DAT TATX ̲DAT
B ̲DAT N ̲DAT TXTZ ̲DAT
C ̲DAT OP ̲DAT TZTZ ̲DAT
DE ̲DAT PHYCONS XAXM ̲DAT
G ̲DAT RARL ̲DAT XMXZ ̲DAT
HI ̲DAT RRRZ ̲DAT
LALC ̲DAT STACK
Finally there are some data in:
HIFCANCEL
HIFTXOUT
TXCANCEL
3̲ ̲ ̲M̲o̲d̲u̲l̲e̲s̲ ̲C̲o̲n̲t̲a̲i̲n̲i̲n̲g̲ ̲C̲R̲8̲0̲ ̲I̲n̲t̲e̲r̲f̲a̲s̲e̲ ̲P̲r̲o̲g̲r̲a̲m̲s̲
HIFRXIN HIFTXRTN
HIFRXOUT STORSBUF
HIFTXIN
4̲ ̲ ̲C̲o̲n̲t̲r̲o̲l̲ ̲I̲n̲t̲e̲r̲c̲h̲a̲n̲g̲e̲ ̲B̲e̲t̲w̲e̲e̲n̲ ̲M̲o̲d̲u̲l̲e̲s̲
a) T̲r̲a̲n̲s̲m̲i̲s̲s̲i̲o̲n̲ ̲o̲f̲ ̲a̲ ̲S̲e̲g̲m̲e̲n̲t̲
b) R̲e̲c̲e̲i̲v̲i̲n̲g̲ ̲a̲ ̲S̲e̲g̲m̲e̲n̲t̲
c) T̲r̲a̲n̲s̲m̲i̲s̲s̲i̲o̲n̲ ̲o̲f̲ ̲A̲c̲k̲n̲o̲w̲l̲e̲d̲g̲e̲
d) R̲e̲c̲e̲i̲v̲i̲n̲g̲ ̲o̲f̲ ̲A̲c̲k̲n̲o̲w̲l̲e̲d̲g̲e̲
A̲P̲P̲E̲N̲D̲I̲X̲ ̲E̲
D̲a̲t̲a̲ ̲D̲e̲s̲c̲r̲i̲p̲t̲i̲o̲n̲
ACK's between ACKOUT and ACKIN are those which are
queued but not yet frame.
NAKBAS, NAKCIR, NAKIN and NAKOUT correspond directly
to ACKBAS, ACKCIR, ACKIN and ACKOUT, except that NAKCIR
contains the size of the relevant NAK frame.
For a description of PNDTBL and GATHER, refer Appendix
B3.
RRASSR contains RR frames (1 for each channel).
SETB-A contains SETB frames (1 for each channel).
"entry" contains index of transmission buffer.
TXCOUT points to next buffer to be released.
TXCLACK points to next buffer requiring ACK.
TXNEXT points to next buffer to be transmitted.
TXCIN points to next place for insertion of transmission
buffer.
HIFTXOUT has work to do as long as TXCOUT LT TXCLACK.
TRANS has work to do as long as TXNEXT LT TXCIN.
NCOUNT corresponds directly to TXCIR and contains the
number of times that entry has been transmitted.
XMTTBL, XMTIN and XMTOUT work exactly as TXCIR, TXCIN
and TXNEXT.
Q̲u̲e̲u̲e̲s̲ ̲(̲F̲I̲F̲O̲ ̲s̲t̲a̲c̲k̲s̲)̲
a) CANLDU = LDU's cancelled by HOST
b) CURLDU = LDU's corresponding to input requests
issued by HOST.
c) HOSTRQ = queue for returning segments to HOST.
d) INQUE = queue for incoming data frames.
S̲t̲a̲c̲k̲s̲,̲ ̲P̲o̲o̲l̲s̲ ̲(̲F̲I̲L̲O̲)̲
General layout:
a) HRXSTK = pool of receive buffers
b) HSTEMP = stack of transmission buffers going to
be returned to HOST.
c) STKEMP = pool of receive buffer for sending fatal
error reports (HRXSTK may be empty).
d) STKRXE = pool of LTU receive buffers (for receiving
frames from line).
e) STKTXE = pool of LTU transmission buffers.
f) STSRET = stack for returning status to HOST.
