OctetView
0x00000…00100 (0, 0, 0) Sector 00884130303838 ┆ A0088A ┆
0x00100…00200 (0, 0, 1) Sector 00000000000000 ┆ ┆
0x00200…00300 (0, 0, 2) Sector ff00c080ffffff ┆ @ ~ ┆
0x00300…00306 (0, 0, 3) WangDocument {d00=0x13, d01=0x57, d02=0x41, ptr=(49,0, 8), d05=0x00}
0x00306…0030c WangDocument {d00=0x13, d01=0x58, d02=0x41, ptr=(49,0, 0), d05=0x00}
0x0030c…00312 WangDocument {d00=0x13, d01=0x59, d02=0x41, ptr=(15,0, 8), d05=0x00}
0x00312…00318 WangDocument {d00=0x13, d01=0x60, d02=0x41, ptr=(24,0, 0), d05=0x00}
0x00318…0031e WangDocument {d00=0x13, d01=0x61, d02=0x41, ptr=(32,0, 0), d05=0x00}
0x0031e…00324 WangDocument {d00=0x13, d01=0x62, d02=0x41, ptr=(39,0, 8), d05=0x00}
0x00324…0032a WangDocument {d00=0x13, d01=0x63, d02=0x41, ptr=(48,0, 0), d05=0x00}
0x0032a…00340 13 66 41 42 00 49 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ┆ fAB I ┆
0x00340…00360 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ┆ ┆
[…0x4…]
0x003e0…00400 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 2a ┆ *┆
0x00400…00500 (0, 0, 4) Sector 00000000000000 ┆ ┆
0x00500…00600 (0, 0, 5) Sector 86312020202020 ┆ 1 8 7 Q? > 7 J N | | d N ~<) 0uH &4'>( 1c5 & & ┆
0x00600…00700 (0, 0, 6) Sector 421c402600415b ┆B @& A[' N X% % PO P ; XA L C g x g V WD O 8 :h Ip R 1358A g H < {C < { ; 8 hA b bI > P 9 8 : o V! H Iy :- ┆
0x00700…00800 (0, 0, 7) Sector 00000000000000 ┆ ┆
[…0x8…]
0x01000…01100 (1, 0, 0) WangDocumentBody
[…0x1…]
0x01200…01300 (1, 0, 2) Sector 0103ff00135741 ┆ WA0001. Print lay-out refer CPS/230/ICD/0002. c) A terminal position (VDU) has always associated a printer, which may be shared with other VDUs. The user may command a print-out of the information of which a part is currently displayed at the VDU┆
0x01300…01400 (1, 0, 3) Sector 0104ff00135741 ┆ WA, on the associated printer. For details refer to CPS/210/SYS/0001 and CPS/230/ICD/0001. Print lay out refer CPS/230/ICD/0001. 4.4.4 Use of Supervisor VDU The use of the Supervisor VDU is as described in section 4.4.2 with the following e┆
0x01400…01500 (1, 0, 4) Sector 00009600135741 ┆ WAxception. Only one supervisor VDU is active at one time. The active supervisor VDU will be the one where the ASSIGN command was issued last. al Function, i.e. transaction in course - Classification of current screen contents - Time (Day, ┆
0x01500…01600 (1, 0, 5) Sector 00000000000000 ┆ ┆
[…0x2…]
0x01800…01900 (1, 0, 8) WangDocumentBody
0x01900…01a00 (1, 0, 9) Sector 010aff00135741 ┆ WAto the Supervisor printers are controlled by the supervisor using the appropriate commands. For details refer CPS/210/SYS/0001. Print lay-out for supervisor print types refer CPS/230/ICD/0002. b) Supervisor assistant printers refer CPS/210/SYS/┆
0x01a00…01b00 (1, 0, 10) Sector 010bff00135741 ┆ WA0001. Print lay-out refer CPS/230/ICD/0002. c) A terminal position (VDU) has always associated a printer, which may be shared with other VDUs. The user may command a print-out of the information of which a part is currently displayed at the VDU┆
0x01b00…01c00 (1, 0, 11) Sector 010cff00135741 ┆ WA, on the associated printer. For details refer to CPS/210/SYS/0001 and CPS/230/ICD/0001. Print lay out refer CPS/230/ICD/0001. d) Stand alone printers, i.e. Receive Only Printers that are separately addressable without any special attachment┆
0x01c00…01d00 (1, 0, 12) Sector 010dff00135741 ┆ WA to a VDU. To such printers, messages/comments may be subject to distribution based on the same criteria as for distribution to VDUs. A stand alone printer of this kind may at the same time act as a shared printer refer c) above. This means┆
0x01d00…01e00 (1, 0, 13) Sector 010e8f00135741 ┆ WA that it may be addressable in two ways: Via its own SCD(s) and via an SCD of a related VDU. Print lay out refer CPS/230/ICD/0001. = inverse video field = unprotected data entry field Line Descriptors R = Repeating S = Select┆
0x01e00…01f00 (1, 0, 14) Sector 010fbb00135741 ┆ ; WA 1 4.4.4 Use of Supervisor VDU The use of the Supervisor VDU is as described in section 4.4.2 with the following e Optional alphanumeric Figure 4.4.2-3 Symbols Used on VDU La┆
0x01f00…02000 (1, 0, 15) Sector 00009600135741 ┆ WAxception. Only one supervisor VDU is active at one time. The active supervisor VDU will be the one where the ASSIGN command was issued last. 1 The user area consists of the ri┆
0x02000…02100 (2, 0, 0) WangDocumentBody
[…0x2e…]
0x04f00…05000 (4, 0, 15) Sector 00000000000000 ┆ ┆
0x05000…05100 (5, 0, 0) WangDocumentBody
[…0xf…]
0x06000…06100 (6, 0, 0) Sector 0601ff00135841 ┆ XA 1 This structure allows to - Use the same TESTER in various tests with the same or with different test data - Specify dynamic load and execution of TESTERS - Execute in paralle┆
0x06100…06200 (6, 0, 1) Sector 0602ff00135841 ┆ XAl TESTERS with internal synchronization - Record output data from each pass (to be deleted after proper verification) The Test Monitor controls only the configuration and execution of tests, the logical contents of the tests resides fully within┆
0x06200…06300 (6, 0, 2) Sector 0603ff00135841 ┆ XA the TESTERS and the test data. The Test Monitor controls the tests in this rather rigid manner in order to be able to trace the result after execution of a test. Tests may be fully automatic or interactive/automatic. It is possible interactiv┆
0x06300…06400 (6, 0, 3) Sector 0604ff00135841 ┆ XAely to specify test steps to be executed and it is possible to select parts of the automatic sequences. Tests may run on disk-file input/output only or may include interactive input and operator verification of output. In order to allow complete┆
0x06400…06500 (6, 0, 4) Sector 0605ff00135841 ┆ XA documentation of tests desired input, expected output is presented for the operator by the TESTERS when interactive tests are conducted. The TESTDEFinition consists of control commands for sequences. This includes commands for load of testers and┆
0x06500…06600 (6, 0, 5) Sector 0606fe00135841 ┆ ~ XA execution of sequences (parallel or in chain). Sequences define execution of steps for one Tester (each Tester is subdivided into subtests executed in steps) and synchronization of sequences (signal to other sequence, wait for other sequence). a┆
0x06600…06700 (6, 0, 6) Sector 0607ff00135841 ┆ XA 1 Testers, test data, and test results are kept in 3 levels of libraries corresponding to individual responsibility, development team responsibility and under configuration control. ┆
0x06700…06800 (6, 0, 7) Sector 0000d300135841 ┆ S XAThis corresponds to the levels of control on the software (figure 4.5.2.1-2) and allows a controlled execution of operational test, because the test procedure is approved and under configuration control. The off-line utility configuration is simil┆
0x06800…06900 (6, 0, 8) WangDocumentBody
[…0x8f…]
0x0f800…0f900 (15, 0, 8) WangDocumentHead {hdr=WangSectHead {next=(15,0, 9), len=0xff, h3=41135941}, f00=»1359A «, f01=»CPS/SDS/001 «, f02=»vhn «, f03=»KR «, f04=»Kapitel 4.6 «, f05=09-10-81 06:35, f06=» «, f07=»05 «, f08=» 130 «, f09=21-02-84 14:20, f10=» «, f11=»00 «, f12=» 2 «, f13=15-10-81 15:54, f14=21-02-84 14:20, f15=»0088A «, f16=» 24 «, f17=» «, f18=»05 «, f19=» 340 «, f20=» 132 «, f21=» «, f22=» «, f99=810010000110066610110480aaca15050000000000000037036f00df}
0x0f900…0fa00 (15, 0, 9) WangDocumentBody
[…0x86…]
0x18000…18100 (24, 0, 0) WangDocumentHead {hdr=WangSectHead {next=(24,0, 1), len=0xff, h3=41136041}, f00=»1360A «, f01=»CPS/SDS/001 «, f02=»vhn «, f03=»BBC «, f04=»Kapitel 4.7 «, f05=09-10-81 06:36, f06=» «, f07=»31 «, f08=» 205 «, f09=18-05-83 22:50, f10=» «, f11=»02 «, f12=» 83 «, f13=16-10-81 14:41, f14=19-05-83 02:21, f15=»0088A «, f16=» 25 «, f17=» «, f18=»36 «, f19=» 412 «, f20=» 345 «, f21=» «, f22=» «, f99=120010000110066610110480aaca15050000000000000037038200df}
0x18100…18200 (24, 0, 1) WangDocumentBody
[…0x7…]
0x18900…18a00 (24, 0, 9) Sector 180a1900136041 ┆ `A DOKUMENTOVERSIGT Dokument nr: Dokumentnavn: Operat]r: Forfatter: Kommentarer: STATISTIK AKTIVITET DATO TID ANV.TID ANSLAG Oprettet / / : : S┆
0x18a00…18b00 (24, 0, 10) Sector 180ba500136041 ┆ % `A 1 CPS/SDS/001 BBC/811020 CAMPS SYSTEM DESIGN SPECIFICATION ISSUE 1.1 CAMPS /=6)M2&*/=MM, > I!e=6 !Z="(=e*$<kas#r 9x2"<! <6 M8)I:^=~ B#.!#<6 ! <6 M&&:!<~ J#.:!<2.=M2┆
0x18b00…18c00 (24, 0, 11) Sector 180cff00136041 ┆ `A 1 1 TABLE OF CONTENTS 4.7 RECOVERY .............................. 255 4.7.1 Requirements and General Concepts ┆
0x18c00…18d00 (24, 0, 12) Sector 180dff00136041 ┆ `A... 255 4.7.1.1 Queue Control at Restart ........ 255 4.7.1.2 Recovery Situations ............. 255 4.7.1.3 Recovery/Restart from Total System Failure .................. 256 4.7.1.4 Recovery after Switch-over ...... 257 4.7.1.┆
0x18d00…18e00 (24, 0, 13) Sector 180eff00136041 ┆ `A5 Withdrawal of Redundant Items ... 257 4.7.2 Failure Types ....................... 258 4.7.2.1 Minor Errors .................... 258 4.7.2.1.1 Process Failure ............. 258 4.7.2.1.2 Process Detected Failure .... 258 4.7.2.2 S┆
0x18e00…18f00 (24, 0, 14) Sector 180fff00136041 ┆ `Aingle System Failures .......... 259 4.7.2.3 Total System Failures ........... 259 4.7.2.4 Software System Errors .......... 259 4.7.2.5 Disastrous Errors ............... 259 4.7.3 Recovery Actions .................... 259 4.7.4 Centr┆
0x18f00…19000 (24, 0, 15) Sector 1800ff00136041 ┆ `Aal Recovery Functions .......... 260 4.7.4.1 Checkpoint Function ............. 260 4.7.4.2 Consistent Checkpoints .......... 261 4.7.4.3 Checkpoint Generation ........... 261 4.7.4.4 Checkpoint Reception ............ 261 4.7.4.5 Check┆
0x19000…19100 (25, 0, 0) WangDocumentBody
[…0x6f…]
0x20000…20100 (32, 0, 0) WangDocumentHead {hdr=WangSectHead {next=(32,0, 1), len=0xff, h3=41136141}, f00=»1361A «, f01=»CPS/SDS/001 «, f02=»vhn «, f03=»OKH «, f04=»Kapitel 4.8 «, f05=09-10-81 07:02, f06=» «, f07=»05 «, f08=» 143 «, f09= - - : , f10=» «, f11=» «, f12=» «, f13=15-10-81 14:44, f14=24-03-86 11:15, f15=»0088A «, f16=» 33 «, f17=» «, f18=»05 «, f19=» 348 «, f20=» 143 «, f21=» «, f22=» «, f99=420010000110066610110480aaca15050000000000000037037900df}
0x20100…20200 (32, 0, 1) WangDocumentBody
[…0x76…]
0x27800…27900 (39, 0, 8) WangDocumentHead {hdr=WangSectHead {next=(39,0, 9), len=0xff, h3=41136241}, f00=»1362A «, f01=»CPS/SDS/001 «, f02=»vhn «, f03=»OKH «, f04=»kapitel 4.9 «, f05=09-10-81 07:04, f06=» «, f07=»03 «, f08=» 108 «, f09=21-02-84 13:57, f10=» «, f11=»00 «, f12=» 6 «, f13=15-10-81 14:47, f14=21-02-84 13:57, f15=»0088A «, f16=» 22 «, f17=» «, f18=»03 «, f19=» 388 «, f20=» 114 «, f21=» «, f22=» «, f99=510010000110066610110480aaca15050000000000000037037900df}
0x27900…27a00 (39, 0, 9) WangDocumentBody
[…0x7…]
0x28100…28200 (40, 0, 1) Sector 28021600136241 ┆( bA ( ( ' ' ' & & & % % % $ $ $ $ # # " " " ! ! ! DOKUMENTOVERSIGT Dokument nr: Dokumentnavn: Operat]r: Forfatter: Kommentarer: STATISTIK AKTIVITET DATO TID ANV.TID ANSLAG Oprettet / / : : S┆
0x28200…28300 (40, 0, 2) Sector 2803a600136241 ┆( & bA 1 CPS/SDS/001 OKH/811020 CAMPS SYSTEM DESIGN SPECIFICATION ISSUE 1.1 CAMPS =6)M2&*/=MM, > I!e=6 !Z="(=e*$<kas#r 9x2"<! <6 M8)I:^=~ B#.!#<6 ! <6 M&&:!<~ J#.:!<2.=M2┆
0x28300…28400 (40, 0, 3) Sector 2804ff00136241 ┆( bA 1 TABLE OF CONTENTS 1 4.9 SECURITY ................................... 312 4.9.1 Introduction ..............┆
0x28400…28500 (40, 0, 4) Sector 2805ff00136241 ┆( bA............... 312 4.9.2 Security and Access Control .............. 313 4.9.2.1 General Concepts ..................... 313 4.9.2.1.1 Classification of Data ............. 313 4.9.2.1.2 External Interface Points .......... 314 4.9.2.1.┆
0x28500…28600 (40, 0, 5) Sector 2806ff00136241 ┆( bA3 Classification of Control Functions 314 4.9.2.1.4 User Processes ..................... 317 4.9.2.2 Security Profile ..................... 319 4.9.2.3 Security and Access Control Mechanisms 321 4.9.2.3.1 CAMPS Modules Involved in Sec┆
0x28600…28700 (40, 0, 6) Sector 2807ff00136241 ┆( bAurity 322 4.9.2.3.2 Security Control on User Processes 325 4.9.2.3.3 Access Control on User Processes . 325 4.9.2.3.3.1 Access to Messages ........... 325 4.9.2.3.3.2 Access to System Control Data 326 4.9.2.3.4 Message Securi┆
0x28700…28800 (40, 0, 7) Sector 2708ff00136241 ┆' bAty Profile ......... 326 4.9.2.3.5 User Process Security Profile .... 327 4.9.2.3.6 Message Distribution Decisions ... 328 4.9.2.3.7 Management of Profiles ........... 329 4.9.2.3.8 User Verification ................ 330 4.9.2.3.┆
0x28800…28900 (40, 0, 8) WangDocumentBody
[…0x77…]
0x30000…30100 (48, 0, 0) WangDocumentHead {hdr=WangSectHead {next=(48,0, 1), len=0xff, h3=41136341}, f00=»1363A «, f01=»CPS/SDS/001 «, f02=»vhn «, f03=»FH «, f04=»Kapitel 4.10 «, f05=09-10-81 07:05, f06=» «, f07=»05 «, f08=» 184 «, f09= - - : , f10=» «, f11=» «, f12=» «, f13=15-10-81 15:02, f14=21-02-84 14:47, f15=»0088A «, f16=» 23 «, f17=» «, f18=»05 «, f19=» 384 «, f20=» 184 «, f21=» «, f22=» «, f99=410010000110066610110480aaca15050000000000000037037900df}
0x30100…30200 (48, 0, 1) WangDocumentBody
[…0xe…]
0x31000…31100 (49, 0, 0) WangDocumentHead {hdr=WangSectHead {next=(49,0, 1), len=0xff, h3=41135841}, f00=»1358A «, f01=»CPS/SDS/001 «, f02=»vhn «, f03=»KR «, f04=»Kapitel 4.5 «, f05=09-10-81 06:34, f06=» «, f07=»00 «, f08=» 18 «, f09= - - : , f10=» «, f11=» «, f12=» «, f13= - - : , f14=24-03-86 11:15, f15=»0088A «, f16=» 32 «, f17=» «, f18=»00 «, f19=» 216 «, f20=» 18 «, f21=» «, f22=» «, f99=020010000110066610a10a80aaca15050000000000000037035800df}
0x31100…31200 (49, 0, 1) WangDocumentBody
[…0x6…]
0x31800…31900 (49, 0, 8) WangDocumentHead {hdr=WangSectHead {next=(49,0, 9), len=0xff, h3=41135741}, f00=»1357A «, f01=»CPS/SDS/001 «, f02=»vhn «, f03=» «, f04=»Kapitel 4.4 «, f05=09-10-81 06:31, f06=» «, f07=»07 «, f08=» 105 «, f09=21-02-84 14:50, f10=» «, f11=»00 «, f12=» 2 «, f13=19-04-82 15:32, f14=21-02-84 14:50, f15=»0088A «, f16=» 16 «, f17=» «, f18=»23 «, f19=» 152 «, f20=» 953 «, f21=» «, f22=» «, f99=510010000110066610110480aaca15050000000000000037033800df}
0x31900…31a00 (49, 0, 9) WangDocumentBody
[…0x6…]
0x32000…32100 (50, 0, 0) Sector 3201ff00136641 ┆2 fA 0 DISK CH 0 Disk Change, Drive 0 1 DISK CH 1 Disk Change, Drive 1 2 DISK CH 2 Disk Change, Drive 2 (N/A) 3 DISK CH 3 Disk Change, Drive 3 (N/A) 4 DEL REC DELETED RECORD, i.e. an F8 address mark found during a┆
0x32100…32200 (50, 0, 1) Sector 3202ff00136641 ┆2 fA read operation. 5 OVERRUN HANDSHAKE ERROR, transfer between floppy disk drive and sector buffer failed. 6 BUSY The formatter is executing a command. 7 TWO SIDED The selected drive contains a two sided diskette. (N/A) ┆
0x32200…32300 (50, 0, 2) Sector 32034d00136641 ┆2 M fA8 - 15 UNDEFINED Table 5.1.5.1.4.1-6 Additional Status Code ful termination of either of the system commands: Read, Write, and Write Deleted. 5) Write Data to Buffer Transfers a 16 bit data word into the sector buffer (64 words of R┆
0x32300…32400 (50, 0, 3) Sector 3204ff00136641 ┆2 fA 1 5.1.5.1.4.2 Mechanical & Electrical Specifications Mechanical Specification for the Floppy Disk Controller Height: 412,6 mm ( 10 U crate) Width: 17,1 mm ( 1 Module) Dept┆
0x32400…32500 (50, 0, 4) Sector 3205ff00136641 ┆2 fAh: 305 mm The Floppy Disk Controller is a front crate mounted module. Power Consumption for the Floppy Disk Controller + 5V: 3,5 A +12V: 25 mA -12V: N/A Mechanical Specification for the Adapter Height: 412,6 mm ( 10 U crate) Width: 1┆
0x32500…32600 (50, 0, 5) Sector 3206ff00136641 ┆2 fA7,1 mm ( 1 Module) Depth: 160 mm Power Consumption for the Adapter Not applicable. Electrical Specifications for the Floppy Disk Controller/Adapter Flatcable Bus All specifications apply to drivers/receivers on the SFDC. Drivers: thes┆
0x32600…32700 (50, 0, 6) Sector 3207ff00136641 ┆2 fAe are open collector drivers with the pull up resistor placed in the FDDs. (the far end) V 0H - 5,5V 0V - V OL - 0,4V I OL : N/A I OL - 48 mA Receivers: A pull up resistor is provi┆
0x32700…32800 (50, 0, 7) Sector 31089d00136641 ┆1 fAded at each input. 2V - V IH - 5V V IL - 0,8V I IH - 20 micro A I IL - 35 mA ette with data tracks on both sides is installed (Not applicable to CAMPS). b) Seek The trac┆
0x32800…32900 (50, 0, 8) Sector 3209ff00136641 ┆2 fA 1 b) SFDC provided status information After the completion of an operation, the SFDC utilizes two types of status information, the auto status (table 5.1.5.1.4.1-5) and the addi┆
0x32900…32a00 (50, 0, 9) Sector 320a8e00136641 ┆2 fAtional status (table 5.1.5.1.4.1-6), both loaded during operation and upon completion (successfully or due to errors) of an operation. ack address is maintained for each drive at all times. c) Restore The RESTORE command causes the drive to s┆
0x32a00…32b00 (50, 0, 10) Sector 320bff00136641 ┆2 fA 1 Bit Position Description Definition ┆
0x32b00…32c00 (50, 0, 11) Sector 320cff00136641 ┆2 fA 0 Seek Complete Seek command was executed successfully. 1 ID DATA CHECK CRC failed to compare in the ID field. 2 PROGRAM ERROR Invalid command. 3 NOT USED 4 DATA CHECK CRC check failed on the data field. ┆
0x32c00…32d00 (50, 0, 12) Sector 320dff00136641 ┆2 fA 5 ID NOT FOUND Search of the ID field was not successful after 4 re- volutions. 6 EQUIPMENT CHECK Resident Microdiagnostics failed. 7 ADD. STATUS One or more bits in the NOT ZERO additional status are set. 8 WRITE PRO┆
0x32d00…32e00 (50, 0, 13) Sector 320eff00136641 ┆2 fATECT selected drive is write pro- tected. 9 NOT USED 10 NOT USED 11 DRIVE NOT READY Selected drive is not ready. 12 SEEK ERROR Upon completion of the SEEK or RESTORE command, the track address does not compare. 13 RECALIBR┆
0x32e00…32f00 (50, 0, 14) Sector 320f8b00136641 ┆2 fAATE Track 00 was not detected in ERROR response to a RESTORE command. 14-15 NOT USED Table 5.1.5.1.4.1-5 Auto Status Code to precede the record data field. The write operation continues until one of the following occurs: 1. A full s┆
0x32f00…33000 (50, 0, 15) Sector 3200ff00136641 ┆2 fA 1 Bit Position Description Definition ┆
0x33000…33100 (51, 0, 0) Sector 3301a600136641 ┆3 & fA status is set. f) Write Deleted Record Identical to the WRITE command except that an F8 hex (11111000 binary) address mark is written instead of an FB. Data Word, byte position 15 ┆
0x33100…33200 (51, 0, 1) Sector 3302ff00136641 ┆3 fA 1 4) Reset RAM Pointer This command is used to reset the pointer used to indicate the sector buffer RAM location where transfer of data takes place. The address pointer of the ┆
0x33200…33300 (51, 0, 2) Sector 3303ff00136641 ┆3 fAsector buffer RAM is automatically reset at the start of and at successful termination of either of the system commands: Read, Write, and Write Deleted. 5) Write Data to Buffer Transfers a 16 bit data word into the sector buffer (64 words of R┆
0x33300…33400 (51, 0, 3) Sector 3304ff00136641 ┆3 fAAM). The address of the RAM is automatically incremented after each "Write data to buffer" command. Note: Before filling the sector buffer, the RAM Buffer pointer should be reset, by issuing a Reset RAM Pointer System Command. "Write data t┆
0x33400…33500 (51, 0, 4) Sector 3305ff00136641 ┆3 fAo buffer" command is used (typ. 64 times) before giving a WRITE system command. 6) Read Auto Status When this command is sued, the SFDC will put the auto status, the format of which is shown in table 5.1.5.1.4.1-5, onto the I/O Bus data lines. ┆
0x33500…33600 (51, 0, 5) Sector 3306ff00136641 ┆3 fA 7) Read Additional Status Equivalent to Read auto status. Though it will be the additional status, the format of which is shown in table 5.1.5.1.4.1-6, that is presented on the I/O Bus datalines. 8) Read Data from Buffer This command tran┆
0x33600…33700 (51, 0, 6) Sector 3307ff00136641 ┆3 fAsfers one 16 bit data word from the sector buffer (RAM). The address of the RAM is automatically incremented after each command. When the command is used after a READ System command, the sector buffer contains the addressed sector, even if the s┆
0x33700…33800 (51, 0, 7) Sector 32083600136641 ┆2 6 fAtatus bit DATA CHECK or DELETED RECORD was set. TE PROTECT status indicates that the diskette may only be read. TWO SIDED status indicates that a diskette with data tracks on both sides is installed (Not applicable to CAMPS). b) Seek The trac┆
0x33800…33900 (51, 0, 8) Sector 3309ff00136641 ┆3 fAk number passed within the SEEK command is located and verified automatically. If the verify does not succeed within 4 revolutions of the diskette, a SEEK ERROR status is presented. A successful completion of a seek indicated by track address comp┆
0x33900…33a00 (51, 0, 9) Sector 330aff00136641 ┆3 fAarison and CRC check would set SEEK COMPLETE status. A CRC error would set ID DATA CHECK status after four verify attempts. Present track address is maintained for each drive at all times. c) Restore The RESTORE command causes the drive to s┆
0x33a00…33b00 (51, 0, 10) Sector 330be600136641 ┆3 f fAtep out max. 256 times and tests for a TRACK 00 signal. Upon issuing 256 steps, if TRACK 00 fails to be detected, a RECALIBRATE ERROR status is set. When the TRACK 00 signal is detected, a verify is performed as for SEEK. fy the command type Mod┆
0x33b00…33c00 (51, 0, 11) Sector 330cff00136641 ┆3 fA 1 d) Read The READ command is initiated after a SEEK or RESTORE command. The drive orients to the sector number within the command. Data is read from that sector until one of ┆
0x33c00…33d00 (51, 0, 12) Sector 330dff00136641 ┆3 fAthe following occurs: 1. A full sector (128 bytes) has been read and stored in the sector buffer RAM on the SFDC. 2. An error is detected. If the record ID fails to compare without an ID DATA CHECK error after 4 disk revolutions, the REA┆
0x33d00…33e00 (51, 0, 13) Sector 330eff00136641 ┆3 fAD operation is terminated and an ID NOT FOUND status will be presented. If the data field CRC check fails, the status DATA CHECK will be presented. e) Write The WRITE command is initiated after a SEEK or RESTORE command. The drive orient┆
0x33e00…33f00 (51, 0, 14) Sector 330fff00136641 ┆3 fAs to the sector number within the command and the FB hex (11111011 binary) data pattern indicating the record address mark is written to precede the record data field. The write operation continues until one of the following occurs: 1. A full s┆
0x33f00…34000 (51, 0, 15) Sector 3300ff00136641 ┆3 fAector (128 bytes) has been written from the sector buffer RAM on the SFDC. 2. An error is detected. If the record ID fails to compare without ID DATA CHECK error after 4 disk revolutions, the WRITE operation is terminated and an ID NOT FOUND┆
0x34000…34100 (52, 0, 0) Sector 3401ff00136641 ┆4 fAe 5.1.5.1.4.1-4. Each system command is given a detailed explanation. 1 Data Word, byte position 15 ┆
0x34100…34200 (52, 0, 1) Sector 3402ff00136641 ┆4 fA14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 D D X X X X X X X X select drive 0 0 1 0 0 0 D D T T T T T T T T seek track 0 1 0 0 0 0 D D X X X X X X X X restor┆
0x34200…34300 (52, 0, 2) Sector 3403ff00136641 ┆4 fAe head 0 0 0 1 0 0 D D R R R R R R R R read initial record 0 0 0 1 0 0 D D R R R R R R R R write initial record 0 0 1 0 1 0 D D R R R R R R R R write deleted reco┆
0x34300…34400 (52, 0, 3) Sector 3404ff00136641 ┆4 fArd T Track number (0:76) R Record (sector) number (1-26) D Drive number (0;1) X Don't care condition Table 5.1.5.1.4.1-4 Normal System Command, Data Word 1 ┆
0x34400…34500 (52, 0, 4) Sector 3405da00136641 ┆4 Z fA When a system command is given, transfer between the formatter and the disk drives takes place, and it is necessary to wait for the completion of the command. SFDC is considered busy. This is ind┆
0x34500…34600 (52, 0, 5) Sector 3406ff00136641 ┆4 fA 1 The completion of the command is indicated in two ways: 1. An additional status bit changes from a BUSY to a NOT BUSY indication. 2. An interrupt is generated a) Select ┆
0x34600…34700 (52, 0, 6) Sector 3407ff00136641 ┆4 fAThis command performs drive selection and presents the following status (if the status condition exists): 1. DRIVE NOT READY 2. WRITE PROTECT 3. TWO SIDED The selected drive would not be ready if a diskette is not properly installed o┆
0x34700…34800 (52, 0, 7) Sector 3308ff00136641 ┆3 fAr the drive is not up to operational speed. WRITE PROTECT status indicates that the diskette may only be read. TWO SIDED status indicates that a diskette with data tracks on both sides is installed (Not applicable to CAMPS). b) Seek The trac┆
0x34800…34900 (52, 0, 8) Sector 3409ff00136641 ┆4 fAule, reset By this command the floppy disk controller is disabled from both main buses and the module is reset to a well defined state. 2) Enable Switch, reset By this command the floppy disk controller is enabled onto the bus, which is s┆
0x34900…34a00 (52, 0, 9) Sector 340a7100136641 ┆4 q fAourcing the command and disabled from the other bus. Transfer on the other bus if any will be destroyed. 2-bit interrupt priority setting. The only requirement to the switch setting is that the controller must be assigned a controller number dist┆
0x34a00…34b00 (52, 0, 10) Sector 340bff00136641 ┆4 fA 1 R/W: "0" transfer from SFDC to PU "1" transfer from PU to SFDC LS1 = LS0 = "0" I/O operation Command code: These 6 bits specify the command type Mod┆
0x34b00…34c00 (52, 0, 11) Sector 340cce00136641 ┆4 N fAule address: These 6 bits specify the I/O module address. This address is selectable by means of switches on the module. Fig. 5.1.5.1.4.1-2 Address Format d. The output of the Power On detection circuit ┆
0x34c00…34d00 (52, 0, 12) Sector 340dff00136641 ┆4 fA 1 R/W ADDR 6-11 COMMAND 11 10 9 8 7 6 1 1 0 0 X 0 1 Disable module, r┆
0x34d00…34e00 (52, 0, 13) Sector 340eff00136641 ┆4 fAeset 1 1 0 1 X 0 1 Enable module, reset 1 0 X X X 0 0 Normal system command 1 0 X X X 0 1 Reset RAM Pointer 1 0 X X X 1 0 Write data to buffer 0 0 X X X 0 0 Read auto status 0 0 X X X 0 1 Read additional status 0 0 ┆
0x34e00…34f00 (52, 0, 14) Sector 340f7700136641 ┆4 w fA X X X 1 0 Read data from buffer X = "don't care condition". Table 5.1.5.1.4.1-3 Command Interpretation nership" bit associated with each port which indicates whether it is the primary port or the alternate. Ownership is changed only by a ┆
0x34f00…35000 (52, 0, 15) Sector 3400ff00136641 ┆4 fA 1 3) Normal System Command This command is actually a set of different commands. The command to be performed must be specified simultaneously in the data word as shown in tabl┆
0x35000…35100 (53, 0, 0) Sector 3501ff00136641 ┆5 fAessor Unit will result in an ownership violation. If a Processor Unit determines that the controller is malfunctioning on its Data Channel it can issue a DISABLE PORT command which logically disconnects the port from the controller. However, this ┆
0x35100…35200 (53, 0, 1) Sector 3502e500136641 ┆5 e fAdoes not affect the ownership status. If the problem is within the port, the alternate path can be used, but if the problem is in the common part of the controller, ownership is not forced upon the other Processor Unit. B(P+1) Fetch word B(P+┆
0x35200…35300 (53, 0, 2) Sector 3503a900136641 ┆5 ) fA 1 Fig. 5.1.5.1.4.1-1 The Floppy Disk Controller B(P), P = P+1 1 0 0 0 0 1 0 Write upper byte B(P) P=P+1 0 0 0 ┆
0x35300…35400 (53, 0, 3) Sector 3504ff00136641 ┆5 fA 1 The SFDC is a standard I/O module which only, with the exception of Bus-switch commands, responds to I/O commands from the currently selected I/O Bus. Operation of the floppy dis┆
0x35400…35500 (53, 0, 4) Sector 3505ff00136641 ┆5 fAk system is performed via a set of I/O commands. An operation may include for instance reading or writing data from/to a Floppy Disk or initiation of a seek (move of read/write head). During an operation, the SFDC is considered busy. This is ind┆
0x35500…35600 (53, 0, 5) Sector 3506ff00136641 ┆5 fAicated by setting the BUSY bit contained in a status word called the additional status code. When the operation is terminated (successfully or due to an error), the BUSY bit is reset and the SFDC as a result of this generates a non maskable interru┆
0x35600…35700 (53, 0, 6) Sector 3507ff00136641 ┆5 fApt. Information about the completed operation will be available in two different status words, the Auto status and the Additional status (the content of these status words will be explained in sec. 5.1.5.1.4.1 b). a) SFDC commands The addressi┆
0x35700…35800 (53, 0, 7) Sector 3408ff00136641 ┆4 fAng format when addressing the SFDC is shown in fig. 5.1.5.1.4.1-2. Part of the address (Bits 6-11 incl.) is decoded by the SFDC as a command as shown in table 5.1.5.1.4.1-3. In the following the possible commands are explained: 1) Disable Mod┆
0x35800…35900 (53, 0, 8) Sector 3509ff00136641 ┆5 fAa bus switch logic is included providing dynamical switching between the two I/O buses. The bus switch logic controls two independent I/O bus ports implemented by physically separate IC packages. Thus no interface chip can simultaneously cause fa┆
0x35900…35a00 (53, 0, 9) Sector 350aff00136641 ┆5 fAilure of both ports. Each port of the controller has a 6-bit configurable controller number, as well as a 2-bit interrupt priority setting. The only requirement to the switch setting is that the controller must be assigned a controller number dist┆
0x35a00…35b00 (53, 0, 10) Sector 350b4900136641 ┆5 I fAinct from controller numbers located within the same Channel Unit. 10) Write Lower Byte B(B), P=P+1 This command writes the lower byte of the I/O bus data lines into the shared RAM location addressed by the pointer. Data is latched to give f┆
0x35b00…35c00 (53, 0, 11) Sector 350cff00136641 ┆5 fA 1 A power-on condition causes a controller reset and also gives an interrupt to one of the two Processor Units to which it is attached. The output of the Power On detection circuit ┆
0x35c00…35d00 (53, 0, 12) Sector 350dff00136641 ┆5 fAis also used to control all the Data bus transceivers so that a controller being powered down will not cause interference on the I/O buses during the power transient. This is possible because the power circuit operates with very low supply voltage ┆
0x35d00…35e00 (53, 0, 13) Sector 350eff00136641 ┆5 fAand special transceivers are used which correctly stay in a high impedance state as long as the supply voltage is too low for correct functioning of the board logic circuitry. Logically only one of the two ports of the controller is active, while ┆
0x35e00…35f00 (53, 0, 14) Sector 350fff00136641 ┆5 fAthe other port, the alternative, is utilized in the event of a path failure of the primary port. There is an "ownership" bit associated with each port which indicates whether it is the primary port or the alternate. Ownership is changed only by a ┆
0x35f00…36000 (53, 0, 15) Sector 3500ff00136641 ┆5 fAPU issuing a TAKE OWNERSHIP I/O command. Executing this special command will cause the controller to define its primary and alternate port designation and to do a controller reset. Any attempt to use a controller which is not owned by a given Proc┆
0x36000…36100 (54, 0, 0) Sector 3601ff00136641 ┆6 fAle. Power Consumption of the Adapter + 5V: N/A +12V: 0,1 A -12V: 0,1 A Electrical Specification of the LTU/Adapter Flatcable Connection Bus Fig. 5.1.5.1.3.3-1 shows the signals transferred on the flatcable bus. The circuits used for┆
0x36100…36200 (54, 0, 1) Sector 36027b00136641 ┆6 { fA each circuitry, with the exception of CALL, are in accordance with CCITT's V24 - and EIA's RS-232C Recommendation. nter 0 0 0 0 0 0 0 Read Status Word B(0), B(1), P=2 0 0 0 0 1 0 0 Read word B(P), B(P+1) Fetch word B(P+┆
0x36200…36300 (54, 0, 2) Sector 3603aa00136641 ┆6 * fA 1 Fig. 5.1.5.1.3.3-1 LTU Flatcable I/O Connector B(P), P = P+1 1 0 0 0 0 1 0 Write upper byte B(P) P=P+1 0 0 0 ┆
0x36300…36400 (54, 0, 3) Sector 3604ff00136641 ┆6 fA 1 5.1.5.1.4 The Floppy Disk Controller & Adapter The Standard Floppy Disk Controller (SFDC) and the Standard Floppy Disk Controller Adapter (SFA) constitute the complete interface ┆
0x36400…36500 (54, 0, 4) Sector 3605ff00136641 ┆6 fAbetween the CR80D I/O buses and up to 4 Floppy disk drives (FDDs) of the type Shuggart SA 800/850. Only two of the four possible drives are provided within CAMPS. The CAMPS FDDs are Shuggart SA 800, or equivalent, characterized by: - Single den┆
0x36500…36600 (54, 0, 5) Sector 3606ff00136641 ┆6 fAsity disk (IBM 3740 compatible) - Single sided disk - Soft Sector - 77 tracks/disk - 26 sectors/track The FDDs are connected to the SFA (rear crate module) via a flatcable. The SFA is in turn connected to the SFDC (front crate module) via a f┆
0x36600…36700 (54, 0, 6) Sector 3607ff00136641 ┆6 fAlatcable. The SFA only acts as an extension board between the SFDC flatcable connector and the FDD flatcable connector. The SFA contains neither active nor passive circuitry. CAMPS configuration of the Floppy Disk system is shown in fig. 5.1.5.1┆
0x36700…36800 (54, 0, 7) Sector 3508ff00136641 ┆5 fA.4-1. 5.1.5.1.4.1 The Floppy Disk Controller The SDFC module (ref. fig. 5.1.5.1.4.1-1) provides all necessary timing, buffering and signal conversion between the CR80D I/O buses and 2 FDDs. To adapt the SDFC to the dualized I/O bus structure ┆
0x36800…36900 (54, 0, 8) Sector 3609ff00136641 ┆6 fAhis command reads 1 byte from the shared RAM location to which the pointer points. The result is placed in the lower part of the I/O bus data lines. The pointer is incremented by one. 9) Write Word B(P), B(P+1), P=P+2 This command writes a ┆
0x36900…36a00 (54, 0, 9) Sector 360ae000136641 ┆6 ` fAword (2 bytes) to the shared RAM location to which the pointer points. To give faster response, the data is latched and response sent to the PU. Then the data is stored in the RAM. The pointer is incremented by 2. ocessor part. Access to this R┆
0x36a00…36b00 (54, 0, 10) Sector 360bff00136641 ┆6 fA 1 10) Write Lower Byte B(B), P=P+1 This command writes the lower byte of the I/O bus data lines into the shared RAM location addressed by the pointer. Data is latched to give f┆
0x36b00…36c00 (54, 0, 11) Sector 360cff00136641 ┆6 fAaster response. The pointer is incremented by one. 11) Write Upper Byte B(P), P=P+1 This command writes the upper byte of the I/O bus data lines into the shared RAM location to which the pointer points. Data is latched to give faster respon┆
0x36c00…36d00 (54, 0, 12) Sector 360dff00136641 ┆6 fAse. The pointer is incremented by one. 12) Read Parity Status This command reads the parity status. If there has been a parity error in any of the two RAM areas, the status word will be 01 Hex. If no error the status word will be 00 Hex. ┆
0x36d00…36e00 (54, 0, 13) Sector 360eff00136641 ┆6 fA 5.1.5.1.3.2 The V24/V28(L) Adapter The functions of the Low Level adapter is explained in sec 5.3.2.4. 5.1.5.1.3.3 Mechanical & Electrical Specifications Mechanical Dimensions of the LTU Height: 412,6 mm ( 10 U crate) Width: 17,1┆
0x36e00…36f00 (54, 0, 14) Sector 360fb000136641 ┆6 0 fA mm ( 1 Module) Depth: 305 mm The LTU is a front crate mounted module. Power Consumption of the LTU + 5V: 4,2 A +12V: 0,25 A -12V: 0,15 A e system RAM. The microprocessor now executes the programs resident in the PRO┆
0x36f00…37000 (54, 0, 15) Sector 3600ff00136641 ┆6 fA 1 Mechanical Dimensions of the V24/V28(L) Adapter Height: 412,6 mm ( 10 U crate) Width: 17,1 mm ( 1 Module) Depth: 160 mm The Adapter is a rear crate mounted modu┆
0x37000…37100 (55, 0, 0) Sector 3701ff00136641 ┆7 fA8 7 6 Command 0 l 0 0 0 0 0 Disable LTU, Programmed clear 0 1 0 1 0 0 0 Enable LTU, Programmed clear 0 1 1 1 0 0 0 Enable LTU, Set LTU in Bootl┆
0x37100…37200 (55, 0, 1) Sector 3702ff00136641 ┆7 fAoad mode 0 0 1 0 0 0 0 Interrupt request to micro- processor. 1 0 0 0 0 1 1 Load Address Counter 0 0 0 0 0 0 0 Read Status Word B(0), B(1), P=2 0 0 0 0 1 0 0 Read word B(P), B(P+1) Fetch word B(P+┆
0x37200…37300 (55, 0, 2) Sector 3703ff00136641 ┆7 fA2), B(P+3) 0 0 0 0 1 0 1 Read Lower Byte B(P) P=P+1 1 0 0 1 0 0 0 Write word B(P), B(P+1) P = P+2 1 0 0 0 0 0 1 Write lower byte B(P), P = P+1 1 0 0 0 0 1 0 Write upper byte B(P) P=P+1 0 0 0 ┆
0x37300…37400 (55, 0, 3) Sector 37049b00136641 ┆7 fA1 0 1 1 Read Parity Status Table 5.1.5.1.3.1-3 COMMAND INTERPRETATION ud rates are under Software control. - Parallel I/O circuitry giving an extended set of control si┆
0x37400…37500 (55, 0, 4) Sector 3705ff00136641 ┆7 fA 1 5) Load Address Counter Before an access, read or write, to the shared RAM can be performed by a PU, it is necessary to load the Address Counter with an address pointing to th┆
0x37500…37600 (55, 0, 5) Sector 3706ff00136641 ┆7 fAe location in shared RAM where the access is to take place. The address loaded by this command is the contents of the I/O bus Data lines. Since the size of the Shared RAM is 16K bytes, the "pointer" must have a value: 0 - pointer - 3FFF H┆
0x37600…37700 (55, 0, 6) Sector 3707ff00136641 ┆7 fAex. 6) Read Status Word B(0), B(1), P=2 This command resets the pointer (P) (held in Address counter) and reads the Status word contained in the bytes B(0) and B(1). The pointer is auto incremented to 2. 7) Read Word B(P), B(P+1), Fetch B┆
0x37700…37800 (55, 0, 7) Sector 3608ff00136641 ┆6 fA(P+2), B(P+3) This command reads a word (two bytes) from the shared RAM location addressed by the pointer. To give faster response to the PU, the next word is fetched and kept ready for the next transfer. 8) Read Lower Byte B(P), P=P+1 T┆
0x37800…37900 (55, 0, 8) Sector 3709ff00136641 ┆7 fArammed clear similar to that of the Disable LTU Programmed Clear is performed. 3) Enable LTU, Set LTU in Boot Load Mode This command enables the LTU towards the I/O Bus transferring the command. The LTU is disabled from the opposite I/O Bus. ┆
0x37900…37a00 (55, 0, 9) Sector 370a5100136641 ┆7 Q fAThen the clear routine is performed and the LTU is set in boot load mode. ared Ram area is a 16K x 9 bits (8 bit data + 1 parity bit) dynamic RAM. It is the data exchange interface between I/O bus and the LTU microprocessor part. Access to this R┆
0x37a00…37b00 (55, 0, 10) Sector 370bff00136641 ┆7 fA 1 Before the bootload operation takes place, the bootloader performs an off line diagnostic self test to ensure that there is no failure in the module. 4) Interrupt Request ┆
0x37b00…37c00 (55, 0, 11) Sector 370c5500136641 ┆7 U fAThe result of this command is an interrupt issued to the LTU microprocessor. /O bus and controlled by the Sequencer. After finishing the access, the RAM bus is returned to the microprocessor part. The microprocessor part of the LTU runs the V24┆
0x37c00…37d00 (55, 0, 12) Sector 370dff00136641 ┆7 fA 1 R/W: "0" data transfer LTU to PU "1" data transfer PU to LTU Module type: LS1 "0" I/O Module LS0 "0" Command Code: These 6 bits together wi┆
0x37d00…37e00 (55, 0, 13) Sector 370eff00136641 ┆7 fAth R/W specify the actual command to the LTU. Module address: The 6 bits together with LS1 and LS0 is the module address. The module address is selectable by means of switches. Fig. 5.1.5.1.3.1-2 ADDR┆
0x37e00…37f00 (55, 0, 14) Sector 370f1300136641 ┆7 fAESS FORMAT done to the System RAM. The bootload PROM is a "shadow PROM" because the PROM in the bootload mode during read operations occupies the 8K lower bytes of the system RAM. The microprocessor now executes the programs resident in the PRO┆
0x37f00…38000 (55, 0, 15) Sector 3700ff00136641 ┆7 fA 1 1 ADDR. 6-11 R/W 11 10 9 ┆
0x38000…38100 (56, 0, 0) Sector 3801ff00136641 ┆8 fAU firmware from the Shared RAM, to which it has been loaded from a PU, to the System RAM. Handshaking between a PU and the microprocessor part during bootload is performed via a status word in the shared RAM. When the bootload has finished, the LT┆
0x38100…38200 (56, 0, 1) Sector 3802ff00136641 ┆8 fAU is set in normal mode by a "programmed clear" command from the PU, and the LTU starts executing the firmware program. The microprocessor section contains hardware necessary to serve the serial communication channels: - Serial input/output circ┆
0x38200…38300 (56, 0, 2) Sector 3803c800136641 ┆8 H fAuitry, which converts parallel data to serial data for transmission and vice versa for reception. - DMA circuitry for fast data transfer between serial input/output circuitry and shared RAM. Select circuitry are equal to the dual port descriptio┆
0x38300…38400 (56, 0, 3) Sector 3804ff00136641 ┆8 fA 1 - Timer circuitry for generating the different baud clocks for each channel. Baud rates are under Software control. - Parallel I/O circuitry giving an extended set of control si┆
0x38400…38500 (56, 0, 4) Sector 3805ff00136641 ┆8 fAgnals on the V24/V28 communication lines. Via the Transceiver block, the electrical conversion between TTL level signals and line level signals and vice versa is performed. These Transceivers are standard circuitry in accordance with CCITT's V24/┆
0x38500…38600 (56, 0, 5) Sector 3806ff00136641 ┆8 fAV28 and EIA's RS-232C recommendations. In the following, a short description of the commands issued from a PU to control the LTU is given. Fig. 5.1.5.1.3.1-2 shows the Address format on the I/O bus when addressing a LTU, and table 5.1.5.1.3.1-3 ┆
0x38600…38700 (56, 0, 6) Sector 3807ff00136641 ┆8 fAgives the different command interpretations. a) LTU Commands 1) Disable LTU, Programmed Clear This command disables the LTU from both I/O Buses, and makes the LTU go through an overall clear routine. This clear does not affect the RAM conte┆
0x38700…38800 (56, 0, 7) Sector 3708ff00136641 ┆7 fAnts. The address counter will be reset and point to location 0 in the shared RAM. 2) Enable LTU, Programmed Clear This command enables the LTU towards the I/O bus transferring the command. The LTU is disabled from the opposite I/O Bus. A prog┆
0x38800…38900 (56, 0, 8) Sector 38090a00136641 ┆8 fAs. GND 6 XC0 GND 7 XC1 GND 8 XC2 GND 9 XC3 XLU 10 ZLU XCK 11 ZCK XRD 12 ZRD XWC 13 ZWC XWD 14 ZWD XMC 15 ZMC XLD 16 ZLD XRU 17 ZRU XFM 18 ZFM GND 19 XSO GND 20 XS1 GND 21 XS2 GND 22 XS3 GND 23 XIN GND 24 XSC GND 25 XOC GND ┆
0x38900…38a00 (56, 0, 9) Sector 380aff00136641 ┆8 fA 1 The Shared Ram area is a 16K x 9 bits (8 bit data + 1 parity bit) dynamic RAM. It is the data exchange interface between I/O bus and the LTU microprocessor part. Access to this R┆
0x38a00…38b00 (56, 0, 10) Sector 380bff00136641 ┆8 fAAM is controlled by the Shared RAM Control Logic. Normally, the microprocessor part has direct access to the Shared RAM, but if a PU wants to access this area, a bus request signal is sent from the Sequencer. As soon as the microprocessor part has┆
0x38b00…38c00 (56, 0, 11) Sector 380cff00136641 ┆8 fA finished a possible access to the shared RAM, the bus is shifted over to the I/O bus and controlled by the Sequencer. After finishing the access, the RAM bus is returned to the microprocessor part. The microprocessor part of the LTU runs the V24┆
0x38c00…38d00 (56, 0, 12) Sector 380dff00136641 ┆8 fA/V28 communication ports transferring data to/from the Shared Ram area. The firmware programs controlling the microprocessor are resident in the System RAM which is a 16K x 9 bit (8 bit data + 1 bit parity) dynamic RAM. The firmware is loaded to ┆
0x38d00…38e00 (56, 0, 13) Sector 380eff00136641 ┆8 fAthe system RAM by a multi step bootload procedure. The PU issues a "boot load" command to the LTU. This puts the LTU in bootload mode, having the effect that all microprocessor section reads are performed in the bootload PROM ("shadow" PROM) and a┆
0x38e00…38f00 (56, 0, 14) Sector 380fff00136641 ┆8 fAll writes are done to the System RAM. The bootload PROM is a "shadow PROM" because the PROM in the bootload mode during read operations occupies the 8K lower bytes of the system RAM. The microprocessor now executes the programs resident in the PRO┆
0x38f00…39000 (56, 0, 15) Sector 3800ff00136641 ┆8 fAM starting with an offline diagnostic test program. If the test reveals no failures then the PROM resident bootload program is executed. If the test detects a failure, no bootloading is performed. The bootload program takes care of loading the LT┆
0x39000…39100 (57, 0, 0) Sector 3901ff00136641 ┆9 fA 1 Communication between the I/O bus interface and the microprocessor section is done via a RAM area, called the shared RAM, on the LTU. The I/O bus interface contains two independe┆
0x39100…39200 (57, 0, 1) Sector 3902ff00136641 ┆9 fAnt I/O bus ports implemented by physically separate IC packages. Thus no interface chip can simultaneously cause failure of both ports. Each port of the LTU has a 6-bit configurable controller number, as well as an interrupt priority setting. The┆
0x39200…39300 (57, 0, 2) Sector 3903ff00136641 ┆9 fA only requirement is that the LTU must be assigned an I/O number distinct from I/O controller numbers located within the same channel unit. The functions of the dual I/O bus ports plus the Bus Select circuitry are equal to the dual port descriptio┆
0x39300…39400 (57, 0, 3) Sector 3904ff00136641 ┆9 fAn given in sec. 5.1.5.1.2.1 (The Disk Controller). Furthermore, the I/O interface circuitry contains: - An Interface Control (including Interrupt Logic) - An Address Counter - A Sequencer (micro programmed) The microprocessor part contains: ┆
0x39400…39500 (57, 0, 4) Sector 3905ff00136641 ┆9 fA - A system RAM - A Bootload PROM - A microprocessor section When a LTU is addressed the Interface Control takes over the control of the LTU. It handles all accesses from a PU, and ensures that no new access is started before the current is f┆
0x39500…39600 (57, 0, 5) Sector 3906ff00136641 ┆9 fAinished. Upon address recognition, the Interface Control gives a start signal to the Sequencer. The Sequencer is controlled by a microprogram. This program handles the access to the shared RAM, Loading of the Address Counter, parity control and ┆
0x39600…39700 (57, 0, 6) Sector 3907ff00136641 ┆9 fAthe hand shaking between a PU and the microprocessor section when sharing the shared RAM area. Part of the addressing bits (bit 6-11) are by the Sequencer decoded as an instruction to the LTU. The Address Counter is a 16 bit up/down counter which┆
0x39700…39800 (57, 0, 7) Sector 3808ff00136641 ┆8 fA holds the next address in shared RAM to be accessed from a PU. The loading is as mentioned controlled by the Sequencer which when it detects a "Load Address counter" instruction, loads the Address Counter with the contents of the I/O bus Data line┆
0x39800…39900 (57, 0, 8) Sector 3909ff00136641 ┆9 fAXC7 GND 6 XC0 GND 7 XC1 GND 8 XC2 GND 9 XC3 XLU 10 ZLU XCK 11 ZCK XRD 12 ZRD XWC 13 ZWC XWD 14 ZWD XMC 15 ZMC XLD 16 ZLD XRU 17 ZRU XFM 18 ZFM GND 19 XSO GND 20 XS1 GND 21 XS2 GND 22 XS3 GND 23 XIN GND 24 XSC GND 25 XOC GND ┆
0x39900…39a00 (57, 0, 9) Sector 390aff00136641 ┆9 fA26 XUF0 GND 27 XUF1 GND 28 XUF2 GND 29 XUF3 GND 30 XVOK +5V 31 +5V +5V 32 +5V -12V 33 -12V not used 34 not used not used 35 not used FIGURE 5.1.5.1.2.3-1 DISK CTRL. - Adapter Connector Pi┆
0x39a00…39b00 (57, 0, 10) Sector 390b1000136641 ┆9 fAn Lay-Out k multiplexer and the status multiplexer the B cable connected to the selected drive. The B cable transfers serial data & clock signals to/from the selected drive plus status signals such as "seek end" and "unit selected" from the selecte┆
0x39b00…39c00 (57, 0, 11) Sector 390cff00136641 ┆9 fA 1 5.1.5.1.3 The Line Termination Unit (LTU) and the V24/V28(L) Adapter The LTU and the V24/V28(L) Adapter constitutes the heavy protocol driving interface between the CR80D I/O buse┆
0x39c00…39d00 (57, 0, 12) Sector 390dff00136641 ┆9 fAs and up to 4 external V24/V28 communication lines, which can be served with a speed of up to 9,6 KBaud full duplex on each channel, dependent on protocol. For CAMPS Connectivity refer to sec. 5.3. 5.1.5.1.3.1 The LTU Module The LTU is a stan┆
0x39d00…39e00 (57, 0, 13) Sector 390eff00136641 ┆9 fAdard CR80D I/O module occupying 1 of 62 possible in-crate module addresses. It communicates with the Processor Unit CPUs via FIFO oriented block transfers. A block diagram of the LTU is shown on fig. 5.1.5.1.3.1-1. The LTU is divided into two ma┆
0x39e00…39f00 (57, 0, 14) Sector 390f8200136641 ┆9 fAjor parts: - The interface circuitry towards the I/O bus. - The V24/V28 communication controlling microprocessor part. .5.1.2.2-1 The DCA Module is sent when the DIF is ready. If this command is issued while the DIF is busy, it will be ig┆
0x39f00…3a000 (57, 0, 15) Sector 39009c00136641 ┆9 fA 1 Fig. 5.1.5.1.3.1-1 The LTU Module Disk Controller Height: 412,6 mm ( 10 U crate) Width: 17,1 mm ( 1 Module) Depth: 305 m┆
0x3a000…3a100 (58, 0, 0) Sector 3a01ff00136641 ┆: fAm The Disk Controller is a front crate mounted module. Power Consumption of the Disk Controller + 5V: 8 A +12U: 0.5 A Mechanical dimensions of the DCA Height: 412,6 mm ( 10 U crate) Width: 17,1 mm ( 1 Module) Depth: 160 mm ┆
0x3a100…3a200 (58, 0, 1) Sector 3a02ff00136641 ┆: fA The DCA is a rear crate mounted module. Power consumption of the DCA + 5V: 1,5 A -12V: 0,3 A Electrical specification of the Disk Controller/DCA Flat Cable Connection Bus The adapter is connected through the 86-pin I/O connector of th┆
0x3a200…3a300 (58, 0, 2) Sector 3a03ff00136641 ┆: fAe controller. Only 64 pins are used, thus allowing 64 pole twisted pair flat cable to be used. The pin assignment is shown in fig. 5.1.5.1.2.3-1. The electrical specifications apply to the disk controller. That is, driver specifications are for si┆
0x3a300…3a400 (58, 0, 3) Sector 3a04ff00136641 ┆: fAgnals originated in the controller, and receiver specifications are for signals originated in the adapter. 1 DRIVER SPECS. V OH MIN V OL MAX I OH MIN I OL MIN B2-9 2.4V 0┆
0x3a400…3a500 (58, 0, 4) Sector 3a055700136641 ┆: W fA.5V 2.6 mA 24 mA AB11-18 2.5V 0.5V 20 mA 20 mA B30 2.4V 0.5V 5 mA 30 mA Disk Controller is then initialized. If an enable command is received and the Disk Controller is already enabled towards the transferring I/O Bus then the Disk Control┆
0x3a500…3a600 (58, 0, 5) Sector 3a06ff00136641 ┆: fA 1 RECEIVER SPECS V IH MIN V IL MAX I IH MAX I IL MAX A10 2.0V 0.8V 20 micro A 0.36 mA B19-22 2.0V 0.8V 20 micro A 0.40 mA B 23-29 2.0V 0.8V 20 micro A 0.20 mA B30 1.0V ┆
0x3a600…3a700 (58, 0, 6) Sector 3a071f00136641 ┆: fA1.0V 20 micro A 0.40 mA mum of 5 flatcables (4 disks connected). One flatcable (the A cable), is a common bus (daisy chain) for all connected drives. t (R/W = 1) - except RESET - this bit is interpreted as the mask bit for OPC┆
0x3a700…3a800 (58, 0, 7) Sector 3908ff00136641 ┆9 fA 1 1 A B not used 1 not used GND 2 XC4 GND 2 XC5 GND 4 XC6 GND 5 ┆
0x3a800…3a900 (58, 0, 8) Sector 3a09ff00136641 ┆: fAith ground plane and drain wire. A disk operation performed by the Disk Controller has to contain information about: - The disk drive to be used (1 of 4). - The disk cylinder number (head position) - The Head number and - The disk sector num┆
0x3a900…3aa00 (58, 0, 9) Sector 3a0aff00136641 ┆: fAber. These control signals, of which not all have to be used in every operation, are forwarded to the connected drive(s) via the DCA control register and the common A cable. The disk drive number latched in the control register selects via the D┆
0x3aa00…3ab00 (58, 0, 10) Sector 3a0bff00136641 ┆: fAata & Clock multiplexer and the status multiplexer the B cable connected to the selected drive. The B cable transfers serial data & clock signals to/from the selected drive plus status signals such as "seek end" and "unit selected" from the selecte┆
0x3ab00…3ac00 (58, 0, 11) Sector 3a0cff00136641 ┆: fAd drive. The "seek end" status signal from all connected drives is, via the Drive interrupt circuitry, sent to the Controller as an interrupt condition (if not masked) for a Processor Unit. Another status signal which causes an interrupt (if not ┆
0x3ac00…3ad00 (58, 0, 12) Sector 3a0dff00136641 ┆: fAmasked) to a Processor Unit is the "Unit Ready" signal transferred via the A cable (only accessed from the selected drive). The DCA furthermore contains circuitry to monitor supply voltages and clock signals. If a power or clock failure in the co┆
0x3ad00…3ae00 (58, 0, 13) Sector 3a0e5600136641 ┆: V fAntroller or the DCA is detected then the connected drive(s) is (are) disabled. upt or not. 7) Load Instruction Pointer, Initiate Operation The I/O bus datalines DA15 - DAO are interpreted as the start address of an instruction field in the m┆
0x3ae00…3af00 (58, 0, 14) Sector 3a0f9d00136641 ┆: fA 1 Fig. 5.1.5.1.2.2-1 The DCA Module is sent when the DIF is ready. If this command is issued while the DIF is busy, it will be ig┆
0x3af00…3b000 (58, 0, 15) Sector 3a00ff00136641 ┆: fA 1 5.1.5.1.2.3 Mechanical & Electrical Specifications Mechanical dimensions of the Disk Controller Height: 412,6 mm ( 10 U crate) Width: 17,1 mm ( 1 Module) Depth: 305 m┆
0x3b000…3b100 (59, 0, 0) Sector 3b01ff00136641 ┆; fA 1 8) Terminate operation An internal termination flag is set, and the current operation will be terminated when allowed. Depending on the kind and progress of the current opera┆
0x3b100…3b200 (59, 0, 1) Sector 3b02ff00136641 ┆; fAtion, this may be completed in a normal way regardless of the terminate command. When the DIF is ready (i.e. operation is over), a bit in the status word tells, if the operation has been terminated by the terminate command. Also in this case an OP┆
0x3b200…3b300 (59, 0, 2) Sector 3b03ff00136641 ┆; fAC interrupt is sent if enabled. 9) Disable Disk Controler, Reset By this command the Disk Controller is disabled from both I/O buses and reset to a well defined state. 10) Enable Disk Controller, Reset By this command the Disk Controll┆
0x3b300…3b400 (59, 0, 3) Sector 3b04ff00136641 ┆; fAer is enabled towards the I/O Bus that transferred the command, and disabled from the other I/O Bus. In case a transfer between an I/O Bus and the Disk Controller RAM area is ative at the time of an enable command received from the opposite I/O bus,┆
0x3b400…3b500 (59, 0, 4) Sector 3b05ff00136641 ┆; fA the bus switch is delayed to guarantee correct contents of the RAM area. The Disk Controller is then initialized. If an enable command is received and the Disk Controller is already enabled towards the transferring I/O Bus then the Disk Control┆
0x3b500…3b600 (59, 0, 5) Sector 3b06ff00136641 ┆; fAler is initialized. 5.1.5.1.2.2 The DCA The DCA (Disk Controller Adapter) is the interface between the Disk Controller and one or more (max. 4) disk drives, as shown on fig. 5.1.5.1.2.1-2. The DCA is connected to the disk drive(s) via at leas┆
0x3b600…3b700 (59, 0, 6) Sector 3b079f00136641 ┆; fAt 2 flatcables and a maximum of 5 flatcables (4 disks connected). One flatcable (the A cable), is a common bus (daisy chain) for all connected drives. t (R/W = 1) - except RESET - this bit is interpreted as the mask bit for OPC┆
0x3b700…3b800 (59, 0, 7) Sector 3a08ff00136641 ┆: fA 1 Furthermore, each drive is connected to the DCA via an individual flatcable (the B cable). The A cable is a 30 twisted pair flatcable. Each B cable is a 26 conductor flatcable w┆
0x3b800…3b900 (59, 0, 8) Sector 3b09ff00136641 ┆; fA related. The module address is selected by means of switches in the DIF. BUS SWITCH AD 11 10 9 COMMANDS: 1 0 0 DISABLE DISK CTRL, RESET ┆
0x3b900…3ba00 (59, 0, 9) Sector 3b0a6c00136641 ┆; l fA 1 0 1 ENABLE DISK CTRL, RESET Fig. 5.1.5.1.2.1-4 ADDRESS FORMAT 5.1.2.1-1. The RAM Control switches via the multiplexers the access over between the disk controller and the internal I/O bus in turn. For this┆
0x3ba00…3bb00 (59, 0, 10) Sector 3b0bff00136641 ┆; fA 1 1 R/W Command Code Command 0 0 0 read status wor┆
0x3bb00…3bc00 (59, 0, 11) Sector 3b0cff00136641 ┆; fAd. 0 0 1 read status word, clear interrupt. 0 0 0 read unit flags. 0 1 1 read unit flags, clear interrupt. 1 0 0 reset. 1 0 1 load unit interrupt mask 1 1 0 load instruction pointer, initiate operation. 1 1 ┆
0x3bc00…3bd00 (59, 0, 12) Sector 3b0dff00136641 ┆; fA1 terminate operation. Table 5.1.5.1.2.1-5 COMMAND INTERPRETATION 1 6) Load Unit Interrupt Mask The I/O bus datalines DA3-DAO are loaded into the unit interrupt mask (UI┆
0x3bd00…3be00 (59, 0, 13) Sector 3b0eff00136641 ┆; fAM) register. This register determines, which of the unit flags may cause interrupt or not. 7) Load Instruction Pointer, Initiate Operation The I/O bus datalines DA15 - DAO are interpreted as the start address of an instruction field in the m┆
0x3be00…3bf00 (59, 0, 14) Sector 3b0fff00136641 ┆; fAemory. The operation specified here is then carried out. The DIF will be busy until the operation has been completed, and if enabled an OPC interrupt is sent when the DIF is ready. If this command is issued while the DIF is busy, it will be ig┆
0x3bf00…3c000 (59, 0, 15) Sector 3b008200136641 ┆; fAnored, except that the ICM bit of the status word is set and an interrupt is sent. The current operation is not affected. = 0: max. 900 ns typ. 450 ns (These signals are described in sec. 5.1.3.1.1). 1 ┆
0x3c000…3c100 (60, 0, 0) Sector 3c01ff00136641 ┆< fA 2) Disk Controller Port The RAM will always respond to the controller port. For 16K version, the lower 14 address bits are used, and for 32K version, the lower 15 address bits are used as ad┆
0x3c100…3c200 (60, 0, 1) Sector 3c02ff00136641 ┆< fAdress relative to the start of the RAM space included. A brief description of the commands issued from a PU to the Disk Controller is given on the following pages. The Address/Command format is shown in fig. 5.1.5.1.2.1-4, and the Command Co┆
0x3c200…3c300 (60, 0, 2) Sector 3c03ff00136641 ┆< fAde interpretation is shown in table 5.1.5.1.2.1-5. c) Disk Controller Commands 1) Read Status Word The DIF puts its status word on the I/O bus data lines DA15 - DA0. 2) Read Status Word, Clear Interrupt As "Read Status Word" except t┆
0x3c300…3c400 (60, 0, 3) Sector 3c04ff00136641 ┆< fAhat the interrupt flag internal in the DIF is cleared, thus enabling the DIF to send further interrupts. This is a message to the DIF, that an interrupt is received. 3) Read Unit Flags The DIF puts the unit flag (4 bit) on the I/O bus data l┆
0x3c400…3c500 (60, 0, 4) Sector 3c051500136641 ┆< fAines DA3-DA0. checker, byte synchronizer and sequencer for the serial data and clock. The drive control transmits control signals as well as cylinder, head, and sector numbers from the control processor. The status of the drive(s) is received a┆
0x3c500…3c600 (60, 0, 5) Sector 3c06ff00136641 ┆< fA 1 4) Read Unit Flags, Clear Interrupt As "Read Unit Flags" except that the interrupt flag internal in the DIF is cleared. 5) Reset This command immediately forces the DIF┆
0x3c600…3c700 (60, 0, 6) Sector 3c07ff00136641 ┆< fA to execute the start up routine. R/W: '0' = input (DIF to PU) '1' = output (PU to DIF) OPC interrupt: During output (R/W = 1) - except RESET - this bit is interpreted as the mask bit for OPC┆
0x3c700…3c800 (60, 0, 7) Sector 3b08ff00136641 ┆; fA - interrupt: '0' = enable '1' = disable AD10 is ignored if R/W = 0 Command code: These two bits specify together with R/W the command. Module address: Specifies the module to which the I/O is┆
0x3c800…3c900 (60, 0, 8) Sector 3c09ff00136641 ┆< fA Disk Controller module forms 16 K or 32 K words (type dependent) of the memory space connected to the currently selected bus. Each word consists of 16 bit data and 2 bit parity in accordance with CR80D standard. The RAM is dual ported. One por┆
0x3c900…3ca00 (60, 0, 9) Sector 3c0aff00136641 ┆< fAt is connected to the current I/O bus, and one port is connected to the disk controller, cf. fig. 5.1.5.1.2.1-1. The RAM Control switches via the multiplexers the access over between the disk controller and the internal I/O bus in turn. For this┆
0x3ca00…3cb00 (60, 0, 10) Sector 3c0bff00136641 ┆< fA purpose the RAM Control receives requests from the bus control logic (RAM) and the disk control processor. The bus control logic (RAM) transfers data and address between the internal I/O bus and the RAM. Memory transfer rate: From/to a disk:┆
0x3cb00…3cc00 (60, 0, 11) Sector 3c0cb900136641 ┆< 9 fA 625 Kwords/second From/to I/O Bus: 2 Mwords/second The actual address space covered by the RAM is set by switches on the printed circuit board (fig. 5.1.5.1.2.1-3): interrupt). Return information to the CPU primarily consists of: ┆
0x3cc00…3cd00 (60, 0, 12) Sector 3c0dff00136641 ┆< fA 1 switch no: 1 2 3 4 5 6 bank select, AD19-AD18 (switch 6 = MSB) 32K section within selected bank: ┆
0x3cd00…3ce00 (60, 0, 13) Sector 3c0ecd00136641 ┆< M fA SW4 = AD17 SW3 = AD16 SW2 = AD15 For 16K version: SW 1 = AD14 For 32K version: SW 1 = "don't care" Fig. 5.1.5.1.2.1-3 RAM ADDRESS SWITCH (unit interrupt). Unit interrupts and OPC interr┆
0x3ce00…3cf00 (60, 0, 14) Sector 3c0fff00136641 ┆< fA 1 1) I/O Bus Port The RAM will respond to the bus, only if AD 19-18 and AD17-14 (for 32K version: AD17-15) match the switch settings and LS1-0 = 00 (indicating I/O) 1 ┆
0x3cf00…3d000 (60, 0, 15) Sector 3c00ff00136641 ┆< fA Response time from TRQ(L) = 0 and AE(L) = 0 to RS(L) = 0: max. 900 ns typ. 450 ns (These signals are described in sec. 5.1.3.1.1). 1 ┆
0x3d000…3d100 (61, 0, 0) Sector 3d01a400136641 ┆= $ fA 1 Fig. 5.1.5.1.2.1-2 Max. Disk Drive Configuration ports of the controller is active, while the other port, the alternative, is utilized in t┆
0x3d100…3d200 (61, 0, 1) Sector 3d02ff00136641 ┆= fA 1 The DIF consists of: - a micro-programmed disk control processor - a data synchronizer and serial/parallel converter - drive control logics and - bus control logics Th┆
0x3d200…3d300 (61, 0, 2) Sector 3d03ff00136641 ┆= fAe control processor interprets instructions stored in the RAM memory, controls and monitors the drives, performs word and byte oriented formatting and data transfers, and does all the sequencing of operations. The processor includes an ALU (Arithme┆
0x3d300…3d400 (61, 0, 3) Sector 3d04ff00136641 ┆= fAtic & Logic Unit) and 16 registers for handling memory addresses and disk parameters such as: - cylinder number - head number - sector number - drive status etc. The data synchronizer and serial/parallel converter include shift register,┆
0x3d400…3d500 (61, 0, 4) Sector 3d05ff00136641 ┆= fA CRC generator/checker, byte synchronizer and sequencer for the serial data and clock. The drive control transmits control signals as well as cylinder, head, and sector numbers from the control processor. The status of the drive(s) is received a┆
0x3d500…3d600 (61, 0, 5) Sector 3d06ff00136641 ┆= fAnd transferred to the control processor. Furthermore, the drive control transfers "seek complete" and "drive not busy" conditions to the bus control. The bus control logic (disk) interprets commands from the internal I/O bus. It puts drive and ┆
0x3d600…3d700 (61, 0, 6) Sector 3d07c600136641 ┆= F fAcontroller status on the internal I/O bus, requests the control processor for operations, sets interrupt masks etc. Furthermore, it generates interrupts in accordance with status and masks. ons for the disk drives connected. When a daisy chain co┆
0x3d700…3d800 (61, 0, 7) Sector 3c08ff00136641 ┆< fA 1 b) RAM Memory Section The RAM memory part consists of: - a RAM - RAM control - address and data multiplexers - bus control logic - switch array The RAM part of the┆
0x3d800…3d900 (61, 0, 8) Sector 3d09ff00136641 ┆= fA Unit is carried out via the I/O bus (I/O-commands), while memory is accessed via the internal micro-bus. The memory is used for data transfer to and from disk and for information between a Processor Unit and the DIF. An operation is defined as ┆
0x3d900…3da00 (61, 0, 9) Sector 3d0aff00136641 ┆= fAa task for the DIF concerning a specified drive. An operation may include for instance reading or writing data or initiation of a seek (move of recording heads). During an operation, the DIF is considered busy. When the DIF is not busy, a Proce┆
0x3da00…3db00 (61, 0, 10) Sector 3d0bff00136641 ┆= fAssor Unit CPU may initiate an operation by an I/O-command. Information about the desired operation must have been stored in the memory by the CPU. As long as the DIF is busy with the operation, it will not receive requests for more operations. Th┆
0x3db00…3dc00 (61, 0, 11) Sector 3d0cff00136641 ┆= fAe DIF indicates by a bit in its status word whether it is busy or not. If enabled, an interrupt is sent to the CPU when the operation has been completed (Operation Complete (OPC) interrupt). Return information to the CPU primarily consists of: ┆
0x3dc00…3dd00 (61, 0, 12) Sector 3d0d7e00136641 ┆= ~ fA 1) A status word concerning the DIF and the latest operation, and 2) A unit flag word concerning the disk drives. ts implemented by physically separate IC packages. Thus no interface chip can simultaneously cause failure of both ports. Each ┆
0x3dd00…3de00 (61, 0, 13) Sector 3d0eff00136641 ┆= fA 1 Interrupts may be caused by certain changes in the status word (OPC - and ICM (Illegal Command Interrupts)) and by the unit flags (unit interrupt). Unit interrupts and OPC interr┆
0x3de00…3df00 (61, 0, 14) Sector 3d0fff00136641 ┆= fAupt may be masked off. The DIF provides generation and checking of a 2 byte CRC code added to the address field as well as to the data field of each sector. During an operation, various checks are carried out considering the status lines of th┆
0x3df00…3e000 (61, 0, 15) Sector 3d004900136641 ┆= I fAe drive, memory parity, CRC check, validity of address field etc. rence on the I/O buses during the power transient. This is possible because the power circuit operates with very low supply voltage and special transceivers are used which correctly┆
0x3e000…3e100 (62, 0, 0) Sector 3e01ff00136641 ┆> fA stay in a high impedance state as long as the supply voltage is too low for correct functioning of the board logic circuitry. Logically only one of the two ports of the controller is active, while the other port, the alternative, is utilized in t┆
0x3e100…3e200 (62, 0, 1) Sector 3e02ff00136641 ┆> fAhe event of a path failure of the primary port. There is an "ownership" bit associated with each port which indicates whether it is the primary port or the alternate. Ownership is changed only by a PU issuing a TAKE OWNERSHIP I/O command. Executi┆
0x3e200…3e300 (62, 0, 2) Sector 3e03ff00136641 ┆> fAng this special command will cause the controller to define its primary and alternate port designation and to do a controller reset. Any attempt to use a controller which is not owned by a given Processor Unit will result in an ownership violation.┆
0x3e300…3e400 (62, 0, 3) Sector 3e04ff00136641 ┆> fA If a Processor Unit determines that a controller is malfunctioning on its Data Channel it can issue a DISABLE PORT command which logically disconnects the port from that I/O controller. However, this does not affect the ownership status. If the┆
0x3e400…3e500 (62, 0, 4) Sector 3e05b700136641 ┆> 7 fA problem is within the port, the alternate path can be used, but if the problem is in the common part of the controller, ownership is not forced upon the other Processor Unit. a Channel Signals The Data Channel signals are pulsed with a nominal p┆
0x3e500…3e600 (62, 0, 5) Sector 3e06ff00136641 ┆> fA 1 a) Disk Controller Section The disk controller part is a standard I/O module, called DIF (Disk I/F and Formatter), which responds to I/O commands from the currently selected I/O┆
0x3e600…3e700 (62, 0, 6) Sector 3e07ff00136641 ┆> fA bus. The controller interfaces to the disk adaptor (DCA) for connection of max. 4 disk drives in daisy chain. The DIF (Disk I/F and formatter) provides all controller and formatter functions for the disk drives connected. When a daisy chain co┆
0x3e700…3e800 (62, 0, 7) Sector 3d08ff00136641 ┆= fAnfiguration is used (Fig. 5.1.5.1.2.1-2), only one drive may be written to or read from at a time. However, overlapped seeks are possible, since all drives are at all times monitored for "seek over" conditions. The communication with a Processor┆
0x3e800…3e900 (62, 0, 8) Sector 3e093a00136641 ┆> : fAng 1 of the possible 62 in-crate module addresses. two modules interrupt simultaneously, the one with the highest priority and address is chosen. When an interrupt address has been shifted into the interrupt register, further interrupts are disa┆
0x3e900…3ea00 (62, 0, 9) Sector 3e0aff00136641 ┆> fA 1 - a RAM module forming 16K (32K) of the possible 1M words of in-crate memory. The controller receives commands and delivers status via its own bus control logic, whereas instruct┆
0x3ea00…3eb00 (62, 0, 10) Sector 3e0b7100136641 ┆> q fAions concerning disk operations, are fetched from the RAM. The RAM is furthermore used as a data buffer. l through the interrupt transmit register. If the interrupt register is empty or if a parity error has been detected in the fetch command, th┆
0x3eb00…3ec00 (62, 0, 11) Sector 3e0ca100136641 ┆> ! fA 1 Fig. 5.1.5.1.2.1-1 The Disk Controller iminates the need for bus arbitration. The remaining support functions are described in the f┆
0x3ec00…3ed00 (62, 0, 12) Sector 3e0dff00136641 ┆> fA 1 The controller contains two independent I/O bus ports implemented by physically separate IC packages. Thus no interface chip can simultaneously cause failure of both ports. Each ┆
0x3ed00…3ee00 (62, 0, 13) Sector 3e0eff00136641 ┆> fAport of the controller has a 6-bit configurable controller number, as well as a 2-bit interrupt priority setting. The only requirement is that the controller must be assigned a controller number distinct from controller numbers located within the s┆
0x3ee00…3ef00 (62, 0, 14) Sector 3e0fff00136641 ┆> fAame Channel Unit. A power-on condition causes a controller reset and also gives an interrupt to one of the two Processor Units to which it is attached. The output of the Power On detection circuit is also used to control all the Data bus transcei┆
0x3ef00…3f000 (62, 0, 15) Sector 3e00ff00136641 ┆> fAvers so that a controller being powered down will not cause interference on the I/O buses during the power transient. This is possible because the power circuit operates with very low supply voltage and special transceivers are used which correctly┆
0x3f000…3f100 (63, 0, 0) Sector 3f01ff00136641 ┆? fAIA is activated. A special interrupt fetch command is used to reset the PFF. 3) Power up Reset CR80D-modules connected to a dual bus structure generate power up reset on their own. The CIA, however, can also be used as interface towards ┆
0x3f100…3f200 (63, 0, 1) Sector 3f02ff00136641 ┆? fAa single I/O bus structure, and therefore a power up reset (not used in this system) is carried to the I/O Bus. The power up reset observes the Master Clear specifications of the CR80D Main Bus (sec. 5.1.3.1.1). 4) I/O Bus Termination The┆
0x3f200…3f300 (63, 0, 2) Sector 3f03ff00136641 ┆? fA physical appearance of the I/O Bus is a motherboard (DMB) and the signals are electrically terminated on one end by the CIA and on the other by a terminating board, the MBT. 5.1.5.1.1.1 Mechanical & Electrical Specifications Mechanical Dimensi┆
0x3f300…3f400 (63, 0, 3) Sector 3f045600136641 ┆? V fAons of the CIA Height: 263 mm Width: 17,1 mm ( l Module) Depth: 280 mm detected by parity The termination phase is characterized by an acknowledge on the DA-line of the Data Channel. Normally the CIA issues the DA-signal when the t┆
0x3f400…3f500 (63, 0, 4) Sector 3f05ff00136641 ┆? fA 1 Electrical Specifications for the CIA Power Consumption + 5V: 3 A + 12V: 80 mA - 12V: 80 mA CIA/Data Channel Signals The Data Channel signals are pulsed with a nominal p┆
0x3f500…3f600 (63, 0, 5) Sector 3f06ff00136641 ┆? fAulse width of 62.5 ns. Transformer driver specifications: I OL max - 100 mA V O max - 10 V Receiver specification: Sensitivity: 0.2 V Hysteresis: 30 mV The signals are terminated in the PU-end and in the CU end by a 120 Ohm shunt┆
0x3f600…3f700 (63, 0, 6) Sector 3f07ff00136641 ┆? fA resistor. 5.1.5.1.2 The Disk Controller and the Disk Controller Adapter (DCA) The Disk Controller and the DCA constitute the complete interface between the CR80D I/O buses and up to 4 disk drives. Any combination of drives from Control Data C┆
0x3f700…3f800 (63, 0, 7) Sector 3e08ff00136641 ┆> fAorporation's (CDC) SMD, MMD, and CMD families is possible. 5.1.5.1.2.1 The Disk Controller Module The Disk Controller module consists of two functionally independent modules (ref. fig. 5.1.5.1.2.1-1): - an I/O module (disk controller) occupyi┆
0x3f800…3f900 (63, 0, 8) Sector 3f09ff00136641 ┆? fAting module address is received in serial form. If two modules interrupt simultaneously, the one with the highest priority and address is chosen. When an interrupt address has been shifted into the interrupt register, further interrupts are disa┆
0x3f900…3fa00 (63, 0, 9) Sector 3f0aff00136641 ┆? fAbled until the address is fetched by the Data Channel. The fetch command, interrupt request (IRQ), is received from the Data Channel in serial form. It contains a four bit address which is compared to the CIA-number from the switch array. If th┆
0x3fa00…3fb00 (63, 0, 10) Sector 3f0bff00136641 ┆? fAey equal each other, the content of the interrupt register is transmitted in serial form to the Data Channel through the interrupt transmit register. If the interrupt register is empty or if a parity error has been detected in the fetch command, th┆
0x3fb00…3fc00 (63, 0, 11) Sector 3f0cff00136641 ┆? fAe interrupt address is replaced by a status message. c) I/O Bus Support The CIA is the only address sourcing unit connected to the I/O Bus and this eliminates the need for bus arbitration. The remaining support functions are described in the f┆
0x3fc00…3fd00 (63, 0, 12) Sector 3f0dff00136641 ┆? fAollowing. 1) Clock Generation The clock signals ]1 and ]2 on the I/O Bus are 1MHz and 8 MHz, respectively. They are derived from a 16 MHz crystal oscillator on the CIA, which also provides the CIA-sequencer with basic timing. [1 and ]2 are ┆
0x3fd00…3fe00 (63, 0, 13) Sector 3f0e3d00136641 ┆? = fAthe time base for interrupt receiving on the I/O Bus. fers of up to 64 words. Further reduced address transfers must be preceded by a new set up. All received addresses are parity checked. 2) Data Phase Besides giving the address type, t┆
0x3fe00…3ff00 (63, 0, 14) Sector 3f0fff00136641 ┆? fA 1 2) Power Supervision The CIA includes a voltage comparator circuit, which monitors the power inputs (+5V, +12V and -12V). If a drop occurs in one of the three voltages that i┆
0x3ff00…40000 (63, 0, 15) Sector 3f00ff00136641 ┆? fAs not so severe as to cause power up reset, a Power Failure flip-flop (PFF) is set and a power failure interrupt is issued on the next interrupt fetch command from the Data Channel. As long as the PFF is set a red LED on the front panel of the C┆
0x40000…40100 (64, 0, 0) Sector 4001ff00136641 ┆@ fA 1 a) Read operation When the address is stable on the Data Bus, the CR80D handshaking procedure (sec. 5.1.3.1) is initiated and data is fetched. The parity is checked and t┆
0x40100…40200 (64, 0, 1) Sector 4002ff00136641 ┆@ fAhe data is transmitted via the transmit register to the Data Channel with a regenerated parity. b) Write operation The data of a write operation arrives from the Data Channel just after the address and is loaded in the data register. A p┆
0x40200…40300 (64, 0, 2) Sector 4003ff00136641 ┆@ fAarity check is performed and the data is then forwarded to the I/O Bus if parity was OK. 3) Termination Phase The main purpose of the termination phase is to make it possible to determine whether a transfer succeeded or not. Two types of ┆
0x40300…40400 (64, 0, 3) Sector 4004ff00136641 ┆@ fAerrors are considered: a) No response detected by time out b) Bit error detected by parity The termination phase is characterized by an acknowledge on the DA-line of the Data Channel. Normally the CIA issues the DA-signal when the t┆
0x40400…40500 (64, 0, 4) Sector 4005ff00136641 ┆@ fAransfer is completed, but if the maximum response time is exceeded, it is issued by the Data Channel. The DA-signal resets the connected CIA to expect a new address phase. This time out condition typically arises when the addressed module is not p┆
0x40500…40600 (64, 0, 5) Sector 4006ff00136641 ┆@ fAresent. If the CIA detects a parity error in the data phase during a write-operation or on the I/O Bus during a read-operation, an error message is sent on the information path simultaneously with the DA-signal. Parity error in the address phas┆
0x40600…40700 (64, 0, 6) Sector 40077500136641 ┆@ u fAe does not result in an error message, because either the CIA-number or control information might be invalid. nctional blocks of the CIA are shown in fig. 5.1.5.1.1-4. a) Data Transfer The information path of the Data Channel is shared by addr┆
0x40700…40800 (64, 0, 7) Sector 3f08ff00136641 ┆? fA 1 b) Interrupt Handling Interrupts from I/O-modules in the Channel Unit are received according to the CR80D Main Bus specifications (sec. 5.1.3.1). This implies that the interrup┆
0x40800…40900 (64, 0, 8) Sector 40099a00136641 ┆@ fA 1 Fig. 5.1.5.1.1-4 The CIA Module FACES /4!e=6 !f=6 !g=6 !h=6 Ml+M;) RE3C#4: 2i=:g=~ JV3C/4!"<6 #6 MB&! =6 !,<6 :]=2'< AMD MB&!,<6 ! ┆
0x40900…40a00 (64, 0, 9) Sector 400aff00136641 ┆@ fA 1 1) Address Phase Three different types of addressing modes are defined for the Data Channel: - single - set up - reduced A single type address is three bytes whi┆
0x40a00…40b00 (64, 0, 10) Sector 400bff00136641 ┆@ fAch are received on the Data Channel information path. The address is stored temporarily in the address register and the four most significant bits are compared to the CIA-number on a switch array. If they match, the address is forwarded to the I/O┆
0x40b00…40c00 (64, 0, 11) Sector 400cff00136641 ┆@ fA Bus and the transfer can proceed. If the control bits on the information path indicate that the address is a "set-up", then it is stored in the Reduced Address Register (RAR) instead of being transmitted on the Data Bus. The address is now use┆
0x40c00…40d00 (64, 0, 12) Sector 400dff00136641 ┆@ fAd as a base to the following reduced address transfers. A reduced address is only one byte and it contains only the CIA-number. When a CIA recognizes its number in a reduced address, it transmits the RAR on the I/O Bus. The RAR is increment┆
0x40d00…40e00 (64, 0, 13) Sector 400eff00136641 ┆@ fAed after each memory transfer to facilitate block transfers of up to 64 words. Further reduced address transfers must be preceded by a new set up. All received addresses are parity checked. 2) Data Phase Besides giving the address type, t┆
0x40e00…40f00 (64, 0, 14) Sector 400fff00136641 ┆@ fAhe control bits of the address phase also specifies whether it is a read or write operation and whether it is a memory or I/O transfer. This information is transmitted to the I/O Bus simultaneously with the address. The data phase is a transfer of┆
0x40f00…41000 (64, 0, 15) Sector 40007d00136641 ┆@ } fA two bytes, lower byte first and then upper byte. 1 ly (PSU) - CR80D Floppy disk Controller - CR80D Floppy disk Controller Adapter (SFA) ┆
0x41000…41100 (65, 0, 0) Sector 4101ff00136641 ┆A fA 1 5.1.5.1.1 The CIA Module The Channel Interface Adapter is the interface between the Data Channel and the dual bus structure of the Channel Unit (fig. 5.1.5.1.1-1). Two versions o┆
0x41100…41200 (65, 0, 1) Sector 4102ff00136641 ┆A fAf the CIA are available, one for interfacing the Data Bus A (CIA-A) and one for interfacing the Data Bus B (CIA-B). The two versions are functionally identical, but the printed circuit board either has an edge connector towards the A-Bus or the B-B┆
0x41200…41300 (65, 0, 2) Sector 41037300136641 ┆A s fAus (figs. 5.1.5.1.1-2 and -3) Fig. 5.1.5.1.1-1 DATA CHANNEL INTERFACES {-! <6 M1' Z -C7-:!<~ B -!/=6'C*-:!<~ B%-!/=6WC*-!/=6)M2&*/=MM, > I!e=6 !Z="(=e*$<kas#r 9x2"<! <6 M8)I:^=~ B#.!#<6 ! <6 M&&:!<~ J#.:!<2.=M2┆
0x41300…41400 (65, 0, 3) Sector 4104b300136641 ┆A 3 fA 1 Fig. 5.1.1.5.1.1-2 The CIA-A Fig. 5.1.5.1.1-3 The CIA-B nt) I/O bus configuration. The system is equipped with three types of I/O c┆
0x41400…41500 (65, 0, 4) Sector 4105ff00136641 ┆A fA 1 The main function of the CIA is to transfer data between the I/O bus and the Data Channel. The CIA is master to the I/O bus but slave to the Data Channel. This means that a trans┆
0x41500…41600 (65, 0, 5) Sector 4106ff00136641 ┆A fAfer is initiated from the Data Channel, which then awaits for the CIA to complete the transfer. Interrupts from the Channel Unit modules are stored in the CIA to be fetched by the Data Channel. The CIA also undertakes several support functions t┆
0x41600…41700 (65, 0, 6) Sector 4107ff00136641 ┆A fAowards the I/O Bus: a) Clock generation b) Power supervision c) Power up reset d) Bus termination The functional blocks of the CIA are shown in fig. 5.1.5.1.1-4. a) Data Transfer The information path of the Data Channel is shared by addr┆
0x41700…41800 (65, 0, 7) Sector 4008a500136641 ┆@ % fAesses, data and error messages. Thus a transfer is divided into three phases. This transfer description is mainly a repetition of parts of sec. 5.1.4.1.4.2. :8=F 28=I!#<:"<>R<2> I E*#<& "< DM L<M% :#<F 2#<> I:g= Ro2M/2 Rl2> IC13!?=4~~ B|2> I:A=!┆
0x41800…41900 (65, 0, 8) Sector 4109a100136641 ┆A ! fA 1 Fig. 5.1.5-1 THE I/O SYSTEM INTERFACES /4!e=6 !f=6 !g=6 !h=6 Ml+M;) RE3C#4: 2i=:g=~ JV3C/4!"<6 #6 MB&! =6 !,<6 :]=2'< AMD MB&!,<6 ! ┆
0x41900…41a00 (65, 0, 9) Sector 410aff00136641 ┆A fA 1 5.1.5.1 Design & Construction The design implements an I/O subsystem that has low overhead, fast transfer rates, no overruns, and no interrupts to the system until a logical entit┆
0x41a00…41b00 (65, 0, 10) Sector 410bff00136641 ┆A fAy of work is completed (i.e., no character by character interrupts from the terminals). The design produced an I/O system that is extremely simple. The heart of the CR80D I/O subsystem is the Data Channel. All bulk I/O is done on a direct memory┆
0x41b00…41c00 (65, 0, 11) Sector 410cff00136641 ┆A fA access (DMA) basis. With the block size determined by the individual application. All I/O controllers are buffered to some degree so that all transfers over the I/O channel are at memory speed (2M words/second) and never wait for mechanical motio┆
0x41c00…41d00 (65, 0, 12) Sector 410dff00136641 ┆A fAn since the transfers always come from a buffer in the I/O controller, rather than from the actual I/O device. For setup, control and status between PU and I/O controllers, programmed I/O (direct from CPUs) can be used concurrently with the Data C┆
0x41d00…41e00 (65, 0, 13) Sector 410eff00136641 ┆A fAhannel DMA transfers. Transfer on the Data Channel does not put any load on the program execution, because the transfer concept is implemented in hardware. The memory system priority on the PU Channel bus always permits I/O accesses (in an on-li┆
0x41e00…41f00 (65, 0, 14) Sector 410fff00136641 ┆A fAne, transaction oriented environment, it is rare that a system is not I/O bound). In the following sections a detailed explanation of the basic modules within a CU is given: - CR80D Channel Interface Adapter (CIA) - CR80D Disk Controller - CR8┆
0x41f00…42000 (65, 0, 15) Sector 4100d500136641 ┆A U fA0D Disk Controller Adapter (DCA) - CR80D Line Termination Unit (LTU) - CR80D V24/V28 (L) Adapter - CR80D Power Supply (PSU) - CR80D Floppy disk Controller - CR80D Floppy disk Controller Adapter (SFA) ┆
0x42000…42100 (66, 0, 0) WangDocumentHead {hdr=WangSectHead {next=(66,0, 1), len=0xff, h3=41136641}, f00=»1366A «, f01=»CPS/SDS/001 «, f02=»vhn «, f03=»KR «, f04=»Kapitel 5.1.5 «, f05=09-10-81 07:11, f06=» «, f07=»03 «, f08=» 163 «, f09= - - : , f10=» «, f11=» «, f12=» «, f13= - - : , f14=29-10-81 11:48, f15=»0088A «, f16=» 64 «, f17=» «, f18=»03 «, f19=» 880 «, f20=» 163 «, f21=» «, f22=» «, f99=020010000110066610a10a80aaca15050000000000000037031e01df}
0x42100…42200 (66, 0, 1) Sector 42024000136641 ┆B @ fA B B A A A A A @ @ @ @ ? ? > > > > = = = = < < < ; ; ; : : : : 9 9 9 8 8 7 7 7 7 6 6 6 6 5 5 5 4 4 4 4 3 3 2 2 2 2 1 1 1 1 1 ) ) ) ]r: Forfatter: Kommentarer: STATISTIK AKTIVITET DATO TID ANV.TID ANSLAG Oprettet / / : : S┆
0x42200…42300 (66, 0, 2) Sector 42034a00136641 ┆B J fA 1 9M% I:]=2#<:^=V V u:b=V V AH! Rv-! <6 C{-! <6 M1' Z -C7-:!<~ B -!/=6'C*-:!<~ B%-!/=6WC*-!/=6)M2&*/=MM, > I!e=6 !Z="(=e*$<kas#r 9x2"<! <6 M8)I:^=~ B#.!#<6 ! <6 M&&:!<~ J#.:!<2.=M2┆
0x42300…42400 (66, 0, 3) Sector 4204ff00136641 ┆B fA 1 5.1.5 The I/O Subsystem The I/O subsystem is composed of one Channel Unit (CU) with a dualized (redundant) I/O bus configuration. The system is equipped with three types of I/O c┆
0x42400…42500 (66, 0, 4) Sector 4205ff00136641 ┆B fAontrollers (interfaces between the I/O buses and the I/O devices): - Disk controllers, which via the Disk Controller adapter interfaces the disk drivers to the I/O sub-system. - Floppy disk controller, which via an adapter is connected to a dual┆
0x42500…42600 (66, 0, 5) Sector 4206ff00136641 ┆B fA floppy disk drive. - Line Termination Units (LTU's), which via the V24/V28 adapters are used for driving the heavy communication protocols towards the TARE-, CCIS-, and SCARS system. The I/O subsystem interfaces to (fig. 5.1.5-1): - the Proce┆
0x42600…42700 (66, 0, 6) Sector 4207ff00136641 ┆B fAssor Sub-System through the dualized CIA (sec. 5.1.5.1.1) - Data Channel (sec. 5.1.4.1.5) - MIA (sec. 5.1.4.1.4.2) link. - the Watchdog Processor through the serial configuration control bus and the CCA (sec. 5.1.5.1.4). - the TARE-, CCIS-, and ┆
0x42700…42800 (66, 0, 7) Sector 41084600136641 ┆A F fASCARS-circuits via the V24/V28(L) adapters (sec. 5.1.5.1.3.2). M2&! "(=~~ BW2I! <6 M /M?.I*:="8=IM2&MP'Mc2! m"2< [MI !?=6 : #wI>K!8=>R 2!8=6 #4 E*8=k L<M% :8=F 28=I!#<:"<>R<2> I E*#<& "< DM L<M% :#<F 2#<> I:g= Ro2M/2 Rl2> IC13!?=4~~ B|2> I:A=!┆
0x42800…42900 (66, 0, 8) WangDocumentHead {hdr=WangSectHead {next=(66,0, 9), len=0xff, h3=41135841}, f00=»1358A «, f01=»CPS/SDS/001 «, f02=»vhn «, f03=»KR «, f04=»Kapitel 4.5 «, f05=09-10-81 06:34, f06=» «, f07=»00 «, f08=» 18 «, f09= - - : , f10=» «, f11=» «, f12=» «, f13= - - : , f14=15-10-81 15:59, f15=»0088A «, f16=» 32 «, f17=» «, f18=»00 «, f19=» 216 «, f20=» 18 «, f21=» «, f22=» «, f99=020010000110066610a10a80aaca15050000000000000037035800df}
0x42900…42a00 (66, 0, 9) Sector 420a2000135841 ┆B XA B B DOKUMENTOVERSIGT Dokument nr: Dokumentnavn: Operat]r: Forfatter: Kommentarer: STATISTIK AKTIVITET DATO TID ANV.TID ANSLAG Oprettet / / : : S┆
0x42a00…42b00 (66, 0, 10) Sector 420bff00135841 ┆B XA 1 1 TABLE OF CONTENTS 4.5 CAMPS SYSTEM SUPPORT FUNCTIONS ........... 198 4.5.1 System Support Functions ┆
0x42b00…42c00 (66, 0, 11) Sector 420cff00135841 ┆B XAonly at Factory .............................. 198 4.5.1.1 Hardware Test Package ............ 199 4.5.1.2 Standard Software Test Package ... 201 4.5.1.3 System Software Test Package ..... 203 4.5.1.4 Factory Test Simul┆
0x42c00…42d00 (66, 0, 12) Sector 420dff00135841 ┆B XAator Configura- tion (TDS) ....................... 206 4.5.2 System Support Functions at the CSSI Site, but not at all Sites ........... 210 4.5.2.1 Software Maintenance ............. 213 4.5.2.2 Data Base Generati┆
0x42d00…42e00 (66, 0, 13) Sector 420eff00135841 ┆B XAon ............. 218 4.5.2.3 System Generation ................ 222 4.5.2.4 Configuration Control ............ 224 4.5.3 System Support Functions at all Sites 224 4.5.3.1 M&D Software ..................... 224 4.5.3.2 ┆
0x42e00…42f00 (66, 0, 14) Sector 420f6600135841 ┆B f XAOff-Line Utilities ............... 224 4.5.4 Generalized Test Monitor ............. 225 M40sI:^=~ J 1!"<6;!#<6 !&<6 ! "$<! <6 {M;(s! 9"c=! "(= Z=q#p!"<6 !&<6 ! "$<!#<6 ! <6 {M)(sC I! <6 ! "(= <q#p!"<6 !#<6 ! "$<!&<6$`i6 {M)(sM &M7 ┆
0x42f00…43000 (66, 0, 15) Sector 0a00ff00135841 ┆ XA 1 4.5 CAMPS SYSTEM SUPPORT FUNCTIONS The CAMPS System Support Functions are non-operational tools used in the development, test, and verification of the operational CAMPS Hardware a┆
0x43000…43100 (67, 0, 0) WangDocumentHead {hdr=WangSectHead {next=(67,0, 1), len=0xff, h3=41136341}, f00=»1363A «, f01=»CPS/SDS/001 «, f02=»vhn «, f03=»FH «, f04=»Kapitel 4.10 «, f05=09-10-81 07:05, f06=» «, f07=»05 «, f08=» 184 «, f09= - - : , f10=» «, f11=» «, f12=» «, f13=15-10-81 15:02, f14=15-10-81 16:00, f15=»0088A «, f16=» 23 «, f17=» «, f18=»05 «, f19=» 384 «, f20=» 184 «, f21=» «, f22=» «, f99=410010000110066610110480aaca15050000000000000037037900df}
0x43100…43200 (67, 0, 1) Sector 43021700136341 ┆C cA C C C 0 0 0 0 / / / . . - - - , , , + + + * * * DOKUMENTOVERSIGT Dokument nr: Dokumentnavn: Operat]r: Forfatter: Kommentarer: STATISTIK AKTIVITET DATO TID ANV.TID ANSLAG Oprettet / / : : ┆
0x43200…43300 (67, 0, 2) Sector 4303a400136341 ┆C $ cA 1 CPS/SDS/001 FH/811020 CAMPS SYSTEM DESIGN SPECIFICATION ISSUE 1.1 CAMPS !/=6)M2&*/=MM, > I!e=6 !Z="(=e*$<kas#r 9x2"<! <6 M8)I:^=~ B#.!#<6 ! <6 M&&:!<~ J#.:!<2.=M2┆
0x43300…43400 (67, 0, 3) Sector 4304ff00136341 ┆C cA 1 1 TABLE OF CONTENTS 4.10 AVAILABILITY, MAINTAINABILITY AND INTEGRITY OF OPERATION ....................┆
0x43400…43500 (67, 0, 4) Sector 4305ff00136341 ┆C cA.......... 334 4.10.1 Availability ........................ 335 4.10.1.1 Definitions ..................... 335 4.10.1.2 Requirements and Verification ... 335 4.10.1.3 Unavailability and Switch-over Time .........┆
0x43500…43600 (67, 0, 5) Sector 4306ff00136341 ┆C cA................... 344 4.10.2 Maintainability ..................... 345 4.10.2.1 Definitions ..................... 345 4.10.2.2 Requirements and Verification ... 345 4.10.3 Integrity of Operation .............. 346 4.10┆
0x43600…43700 (67, 0, 6) Sector 43079d00136341 ┆C cA.3.1 Definition ...................... 346 4.10.3.2 Requirements .................... 347 4.10.3.3 Verification .................... 347 (= Z=q#p!"<6 !&<6 ! "$<!#<6 ! <6 {M)(sC I! <6 ! "(= <q#p!"<6 !#<6 ! "$<!&<6$`i6 {M)(sM &M7 ┆
0x43700…43800 (67, 0, 7) Sector 3008ff00136341 ┆0 cA 1 4.10.1 Availability 4.10.1.1 Availability Definitions a) Availability. The probability of finding an item in a functioning condition at a given time. b) Mean time between Fai┆
0x43800…43900 (67, 0, 8) Sector 00000000000000 ┆ ┆
[…0x97…]
