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Notes: ERRORS IN RAM MEMORIES
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…00……00……00……00……0e……02……00……00……0e…
…0a……02……0a……86…1 …02… …02… …02…
…02…CPS/TCN/018
…02…FC/801205…02……02…#
ERRORS IN RAM MEMORIES
…02……02…CAMPS
1̲ ̲ ̲A̲B̲S̲T̲R̲A̲C̲T̲S̲
1.0 I̲N̲T̲R̲O̲D̲U̲C̲T̲I̲O̲N̲
As the D-module memory design (i.e. 8016 D/128PC/00)
is not yet in current production, it is highly interesting
to carry out investigations on the memory failure rates
which must be estimated for the CAMPS project.
One argument which triggered this investigation, was
the assertion that on a particular Burroughs computer
system equipped with 512K x 16bit RAM memory appeared
an average of 3 faults per day!
It should be noted that the Burroughs memory did include
error correcting feature which limited the effect of
errors to logging only.
In the CAMPS project is quoted 192K x 16 bit (or 164K
x 16 bit respectively) in each redundant PU, but it
is predicted that all CAMPS sites may end up with 2x256kx16
bit which is concordant with the mentioned Burroughs
system. In the following, however, is calculated with
192K of memory containing no error correction..
It is difficult to obtain firm estimates of the memory
error rate within a system this being a combination
of component reliability (also second sources), design
standards, and lay-outs. However, from assertions provided
the range of errors within one PU memory can be expected
to occur from once a day to a rather conservative estimate
of once every 2 weeks.
To complete the picture and get a basis for judgement
a calculation of the consequences of an error causing
a switchover at a rate of:
1 per day
1 per 3 days
1 per week
1 per 10 days
and 1 per 2 weeks
is required. It is considered appropriate if CAMPS
System Engineering could contribute with these calculations.
1.1 O̲U̲T̲L̲I̲N̲E̲
This present report is separated into sections each
containing an aspect of the memory considerations.
In order to present the intentions with this paper,
section 2 contains the conclusion.
Section 3 contains a discussion of Parity VS Error
Correction Checks.
In section 4 the environments causing RAM errors are
discussed.
Section 5 handles the preventive maintenance procedures
for the CAMPS equipment and outlines the availability
requirements.
Section 6 contains some concluding remarks, while section
7 presents the reference list.
2̲ ̲ ̲C̲O̲N̲C̲L̲U̲S̲I̲O̲N̲
It is recommended that for the CAMPS project a redesign
of the RAM memory modules is considered and, if the
technical problems can be overcome, a change of the
design should be performed to include error correction.
Apart from the availability requirements which are
not achieved with high error rates a problem arises
during debugging of CAMPS software.It can be predicted
that there will be software problems which are difficult
to trace and when no distinguishing is possible between
S/W errors and other errors a potential source to troubles
are foreseen. This may cause immense problems in the
test phase, delay the delivery date, and cause endless
arguments with SHAPE prolongating the warranty period.
Hence, the life time costs may very well be smaller
if the design change is made now.
In addition, a change to error correcting memories
may strongly support biddings for other contracts for
which we will compete with other companies offering
memories with error correction.
See also the conclusive, comments, sec. 6.
3̲ ̲ ̲P̲A̲R̲I̲T̲Y̲ ̲C̲H̲E̲C̲K̲I̲N̲G̲ ̲V̲S̲.̲ ̲E̲R̲R̲O̲R̲ ̲C̲O̲R̲R̲E̲C̲T̲I̲O̲N̲
3.1 P̲A̲R̲I̲T̲Y̲ ̲C̲H̲E̲C̲K̲I̲N̲G̲
Parity checking procedures offers a simple low-cost
alternative to more sophisticated methods. It checks
every word prior to being written into the memory and
every word read from the memory. If an error is detected
a message is sent to the WD before the PU halts or
seeks to repeat the instruction. With this present
memory lay-out there is even two parity bits, one for
each byte.
The disadvantage is that an even number of bit errors
are passed on without any indication until the PU halts
and that it cannot trace whether word is actually stored
correctly in the memory. So whenever a fault appears
due to a faulty writing into the memory or a memory
cell being changed due to noise or particle constraints
the PU will most often not be able to reproduce the
correct word.
3.2 E̲R̲R̲O̲R̲ ̲C̲O̲R̲R̲E̲C̲T̲I̲O̲N̲
Error detection and correction offers single bit error
correction and double bit error detection regardless
of the origin of the error in all circumstances providing
a print-out with the failing address to the WD. Because
the word is checked not only when read from, but also
when written into the memory cell (in the same write
cycle) single bit errors are corrected, and as single
bit errors are the most frequent, the reliability of
the RAM is significantly improved. The improvement
has been estimated to be as high as 60 times (ref.
7.8).
T̲A̲B̲L̲E̲ ̲1̲ ̲ ̲C̲O̲M̲P̲A̲R̲I̲S̲O̲N̲ ̲O̲F̲ ̲E̲R̲R̲O̲R̲ ̲S̲T̲R̲A̲T̲E̲G̲I̲E̲S̲ ̲(̲R̲e̲f̲.̲ ̲7̲.̲8̲)̲
̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲
̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲Error Type No Checking Parity
EDC USing Am2960
̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲
̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲
Single-Bit Error System Crash. System halt. Correctable
System runs
Double-Bit Error System crash. System crash. System halt.
Entire RAM Failure System crash. System halt. Correctable
System runs
̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲
̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲
Maybe the most important advantage is that with error
correction, it is possible to distinguish S/W errors
from -particle errors, noise and temperature errors,
and from components with a decreasing performance.
And it is possible to wait to change components showing
spurious errors until it is convenient.
The disadvantage will be the increased number of components
used in a memory system. Even if the parity bits can
be avoided a 5 or 6-bit hamming code must be added.
Thus, the expansion in memory components is:
18 bits - 2 parity bits + 6 hamming code bits = 22%
And the control network must also be added.
4̲ ̲ ̲R̲A̲M̲ ̲M̲E̲M̲O̲R̲Y̲ ̲E̲R̲R̲O̲R̲ ̲T̲Y̲P̲E̲S̲
4.1 G̲E̲N̲E̲R̲A̲L̲
This section contains a brief discussion of the different
error types which may occur in a RAM. They are in
arbitrary order:
- Standard H/W failures
- Infantry problems
- Wear-outs
- Voltage Changes (noise etc.)
- Temperature changes
- Refresh timing
- -Particle errors (soft-errors)
- Programming errors (Soft-ware errors)
4.2 S̲T̲A̲N̲D̲A̲R̲D̲ ̲H̲/̲W̲ ̲F̲A̲I̲L̲U̲R̲E̲S̲
The standard hardware failures are kept reasonably
low as only burned-in components are employed. Still
some memory component errors will occur within a normal
production of RAMs. The MTBF for the memory modules
installed in one site (2 PUs) has been predicted as
follows:
2 x 128k RAM module = 2 = 2 x 200 = 400
2 x 64k RAM module = 2 = 2 x 110 = 220
̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲
Failure rate for 1 site = 620 fpmh
or one H/W memory error every 67 day 2 month.
What can be more appropriate is to observe the MTBF
for failures causing a switchover. This may be derived
from the R&M Program Plan to be = 816 for a PU plus
additional =65 (approx.) for other components creating
a switchover faults will be approx. 47 days.
The above values reflect only the predicted errors
caused by the standard H/W components failures.
4.3 I̲N̲F̲A̲N̲C̲Y̲ ̲P̲R̲O̲B̲L̲E̲M̲S̲
As mentioned above only burnt-in components are employed
thus substantially reducing the number of errors which
may otherwise take place during their infant life.
As a matter of fact one of the burn-in tests is performed
in 160 hours of a working temperature of 125…0e…o…0f…C. If
such a production batch appears to have between 10%
and 20% failures, the failing items are removed and
the test is repeated for another 160 hours. Now, if
the failing items amount less than 7% they are removed
and the remaining batch is being sold. (Ref. 7.4).
After this test very few H/W errors indeed are found.
Those that do, however, may be difficult to locate
as they often display dynamic erros appearing from
slow sense amplifiers, or they are susceptible to fail
with a combination of noise and/or temperature.
4.4 W̲E̲A̲R̲-̲O̲U̲T̲S̲
In the other end of a component's life cycle wear-outs
or mortality problems appear. They are a result of
a degradation in the materials which appears after
maybe 10…0e…7…0f… to 10…0e…8…0f… hours of use. As a useful life for
the CAMPS equipment is set to ten years 9 x 10…0e…4…0f… hours
no problems are expected from this even though the
components are artificially aged through their burn-in
tests.
Exessive voltages (transients) and high working temperatures
are factors which will reduce life of the components.
4.5 V̲O̲L̲T̲A̲G̲E̲ ̲C̲H̲A̲N̲G̲E̲S̲
Voltage changes is one of the most important parameters
causing RAM erros. But voltage changes can be due to
noise or it can be changes in the supply voltages.
Consequently they can be specified as follows:
- pattern sensitivity (noise)
- transients (noise)
- voltage bumps (noise)
- operating voltages
Common to the last 3 items are that they increase the
-particle error rate.
4.5.1 P̲a̲t̲t̲e̲r̲n̲ ̲S̲e̲n̲s̲i̲v̲i̲t̲y̲
The presence of critical nodes of noise which adds
to or subtracts from signal voltages may cause data-dependent
errors. This is a matter catered for by the IC manufacturer,
but it is worth noting that a thorough testing of the
memory's pattern sensitivity cannot be performed on-site
because of the test time involved. A DIAPAT (Diagonal
Pattern) test is appropriate together with a MASEST
(Multiple Address Selection) test, but if a GALPAT
(Galloping Pattern) test must be implied to test for
a possible contamination from one bit to another the
time consumption is too high.
4.5.2 T̲r̲a̲n̲s̲i̲e̲n̲t̲s̲
Current transients on the lines are inevitable, but
they may be reduced by a proper design and decoupling
of the memory modules. Spikes on the lines are especially
important when added to other weaknesses thus creating
a degraded performance.
4.5.3 V̲o̲l̲t̲a̲g̲e̲ ̲B̲u̲m̲p̲s̲
Voltage bumps are a result of noise and transients
on the supply voltage lines. They are small drops in
the voltages which may cause a sense amplifier in a
RAM to fail and as memories become smaller and faster
they will also generate more noise and be more sensitive
to the effects of noise.
In a test performed by Elektronikcentralen MOSTEK showed
minor signs of susceptibility to voltage bumps. (Ref.
7.5).
4.5.4 O̲p̲e̲r̲a̲t̲i̲n̲g̲ ̲V̲o̲l̲t̲a̲g̲e̲s̲
Although it cannot be denied that the input voltages
(V…0f…IL…0e…, V…0f…IH…0e…) have som impact on the error rates the highest
contribution comes from the supply voltages V…0f…BB…0e… and,
especially V…0f…DD…0e…. As can be seen from fig. 1 an increase
of the supply voltages will make a device more susceptible
to noise while a decrease of the supply voltages may
cause timing errors. By obtaining a SHMOO plot the
sensitive margins can be found, but usually the ICs
are well within their limits at nominal voltages.
Also the component will be more susceptible to display
soft errors.
FIGURE 1 (Ref 7.5)
V…0f…DD…0e… vs. V…0f…BB…0e… plot showing the noise sensitive corner
and the speed sensitive corner. The arrows illustrate
the influence of increasing temperature.
4.6 T̲E̲M̲P̲E̲R̲A̲T̲U̲R̲E̲
High temperatures is another important parameter in
the reliability model for ICs, and RAMs are susceptible
to reveal an increased failure rate at elevated temperatures.
This can be verified by the simple fact that a RAM
test may be significantly reduced if run of the borders
of its temperature.
Intel f.inst. issues a failure rate of 25…0e…o…0f…C ambient
temperature, but as the CAMPS equipment is encapsulated
in a tempest rack it would be interesting to know the
failure rate at the specified limit of 70…0e…o…0f…C.
4.7 R̲E̲F̲R̲E̲S̲H̲ ̲T̲I̲M̲I̲N̲G̲
As a memory cell may be compared with a leaking capacitor
it is necessary to refresh its charge currently. With
the refresh cycle to appear will within the margin
at frequent intervals no problem should occur with
a good component. A weak component which is maybe not
fully recharged will be more susceptible to -particle
errors as critical charge is the most important parameter
for this type of error.
4.8 ̲ ̲-̲P̲A̲R̲T̲I̲C̲L̲E̲ ̲E̲R̲R̲O̲R̲S̲
-particle errors or Soft-errors is a relatively new
problem arisen as the increasing demand for higher
RAM densities has reduced the memory cells thus reducing
the stored electron charge. But now the individual
memory cells are susceptible to errors due to small
radiations from -particles as well as uranium and
thorium particles resident in the packaging materials.
-particles are doubly changed helimum nuclei which
when penetrating through a memory cell generates eletron-hole
pairs along its path thus filling up the charge in
the "potential well" which is the storage capacitor.
Fig. 2 shows a schematic of such a soft error creation
(Ref. 7.1).
FIGURE 2…01…(Ref. 7.1)
A characterization of -particle errors would be that
they are non-recurring, random, and occurring only
when empty wells are collecting electrons. For this
reason it might be expected that a soft error always
displayed a "0" instead of a "1", but as some parts
of the memories may be internally inverted as well
as collection also takes place on the gates a logic
"0" may also be changed to a "1".
The increasing demand for infomation has forced the
RAM manufacturers to issue some predictions of soft-error
rates. And for a 16K RAM the recent predictions say
0.1%/1000 hours corresponding to = 1 and a soft-error
rate of = 216 for a 192K x 18 bit RAM which is a
fairly low rate.
It is worth noting though that these predictions are
effective in perfect environments. Factors like low
supply voltages (herein also included negative noise
spikes as soft errors are created in terms of nanoseconds),
slow sense amplifiers, slow refresh timing, etc. will
rapidly increase the soft error rate. Thus, in an IC
which is beginning to be defective an increased number
of soft errors can be expected. See Fig. 3.
FIGURE 3…01…(Ref. 7.9)
4.9 S̲O̲F̲T̲W̲A̲R̲E̲ ̲E̲R̲R̲O̲R̲S̲
Software errors are not able to produce single bit
errors in the memory. However, as both memory errors
and S/W errors may cause a program HALT without providing
information to the CAMPS WD of the cause of the error,
it can become extremely time consuming to identify
S/W errors. This may only be done by dumping out the
contents of the memory and analyze the print-out.
5̲ ̲ ̲M̲A̲I̲N̲T̲E̲N̲A̲N̲C̲E̲ ̲P̲R̲O̲C̲E̲D̲U̲R̲E̲S̲
Whenever an error is reported an action need be taken.
For the CAMPS equipment with two redundant PUs each
containing a main RAM memory area of 192K x 18 bit
a RAM error will result in a report to the Watchdog
either that a parity error was detected or, if the
parity is correct, that the PU is faulty. In either
case a switchover must be performed when the error
occurs in the active PU before the test programs can
be loaded.
5.1 S̲W̲I̲T̲C̲H̲O̲V̲E̲R̲ ̲I̲D̲E̲N̲T̲I̲F̲I̲C̲A̲T̲I̲O̲N̲
The number of switchovers allowed is set by the availability
requirements. It is inevitable that during an upgrading
from warm stand-by to active mode the redundant PU
will be unavailable for some seconds and when the total
amount of switchovers multiplied by the time to upgrade
the PU exceeds the availability requirements of max.
5 min. per 3 months the system is no longer in compliance
with the performance specs.
The type of errors which are totalled when calculating
the number of switchovers are:
- Hardware errors
- Soft errors
- Environmental errors
Software errors
As can be seen from fig. 4 the hardware error contribution
is derived from the PU itself plus a few items in the
I/O crate where an error will also treate a switchover.
The predicted error rate for these items can be found
in the R & M plan to be = 870.
The soft error rate is predicted in para. 3.7 to be
= 216 for one 192K RAM.
The environmental errors caused by noise, transients,
voltage bumps, temperature, etc. are very difficult
to predict as they are a result of the IC quality which
may be varying withing different productions (week
codes) plus the design.
Fig. 4
The software errors are equally difficult to predict.
It can generally be predicted that some nasty S/W errors
will exist after the equipment has been installed although
most - and more obvious errors - have been corrected.
Of course a S/W created error shall not be considered
when calculating the availability, but nevertheless
it will have some impact since a S/W error cannot be
distinguished from the other errors.
5.2 O̲N̲-̲S̲I̲T̲E̲ ̲T̲E̲S̲T̲I̲N̲G̲
When an error is detected the off-line M&D programs
shall be loaded. Assuming the simple case where a RAM
memory error was indicated a RAM test program must
be loaded and executed. In case of a stuck IC there
will be no problem as it will generally be detected
no matter what type of test is executed. But what happens
if no error is detected? Now it may have been an intermittent
problem, or a pattern sensitivity problem occuring
only with very special pattern combinations, or for
that sake a temperature problem. All of these types
are basically H/W errors typically originated in an
IC which starts to be defective.
It may also have been a spurious, non-recurring errors
originated by noise or -particles.
Or it may have originated from a tedious S/W failure
not yet discovered.
It appears, that on-site testing with the purpose of
identifying faulty memory modules, could be quite difficult.
At best, it would be very time consuming which would
leave the CAMPS system operating in a degraded mode
for an unacceptable long period.
In the case where no conclusive result can be obtained
by testing, 3 alternatives exist as described in the
following.
5.2.1 R̲e̲t̲u̲r̲n̲ ̲t̲o̲ ̲D̲e̲p̲o̲t̲
He may return the suspected module to the depot for
a thorough testing. This will be time consuming and
costly.
5.2.2 S̲w̲i̲t̲c̲h̲ ̲B̲a̲c̲k̲ ̲t̲o̲ ̲A̲c̲t̲i̲v̲e̲
He may switch the PU back to active operation trying
to provoke the error. This may cause a lot of switching,
but it will be reasonably safe although provide no
solution to the potential problem.
5.2.3 S̲w̲i̲t̲c̲h̲ ̲B̲a̲c̲k̲ ̲t̲o̲ ̲S̲t̲a̲n̲d̲-̲b̲y̲
He may switch the PU back to stand-by mode. This is
maybe the worst solution since a possible fault is
not detected until an error occurs in the other PU
and it is switched back to active mode. Then there
is a potential risk for a total system failure. This
will not, of course, happen very often, but the availability
requirements states that it may happen only once every
2nd year.
5.3 D̲E̲P̲O̲T̲ ̲T̲E̲S̲T̲I̲N̲G̲
If too many memory boards are returned to the depot
for testing a heavy load will be created. Also, if
several boards are returned because of non-recurrent
errors, an uncertainty will spread and the chances
are long that sooner or later a defective memory module
will be returned to a site. Anyway, the memory modules
will soon suffer from a bad reputation.
6̲ ̲ ̲C̲O̲N̲C̲L̲U̲D̲I̲N̲G̲ ̲R̲E̲M̲A̲R̲K̲S̲
As pointed out in this report the total amount of failures
in a system is a composition of all kinds of errors.
The number of H/W failures can be predicted on a base
of vast experiences, the amount of - particle errors
can be predicted on behalf of scientific experiments,
and the number of problems occurring from S/W programming
failures can be calculated on a base of past experiences.
But on top of these problems a number of other errors
occuring from noise, temperature etc. must be added.
Being related to the unique design of the D-modules,
assumptions rather than estimates of the error rate
can be made, but it is likely that the implications
of these errors will substantially increase f. inst.
the number of soft-errors and diffuse the total error
picture.
In order to differentiate memory errors from other
errors and to keep the system operative simultaneously
receiving an unequivocal report in case of a memory
error, it will be highly advantageous to have error
detection and correction built into the memory modules.
Further arguments supporting that opinion is brought
below.
6.1 A̲R̲T̲I̲C̲L̲E̲S̲
All current articles concerning larger RAM memory systems
will, if not directly recommend error correcting, contain
a positive reference to the principle.
6.2 C̲O̲M̲P̲A̲R̲I̲S̲O̲N̲S̲
Without the benefit of a market survey at least computer
manufacturers as IBM, Borroughs, Varian and ICL all
utilizes error correcting in their large memories and
it is felt certain that a further investigations will
prove that all major computer manufacturers employ
this technique where reliability is considered important.
Borroughs, for example, considered it a significant
draw-back for the NEC-CCIS proposal, in which a CR
80 D computer should be integrated as a front-end processor,
that we did not have error correction.
6.3 E̲C̲O̲N̲O̲M̲Y̲
Development of a new memory module can be roughly estimated
to cost one man-year plus production expencies, all
together in the range of 1 Mill. Dkr. This can easily
be spent in prolonged software test and availability
test phases, or in an extension of the warranty period
where extra 5 visits per site will be equivalent to
this amount.Under all circumstances SHAPE will be unhappy
with the equipment and our reputation will suffer.
6.4 C̲A̲M̲P̲S̲ ̲E̲Q̲U̲I̲P̲M̲E̲N̲T̲ ̲M̲E̲M̲O̲R̲I̲E̲S̲
It is already now predicted that it may be necessary
to extend the memory size from 192K to 256K in order
to contain the CAMPS software. If no excuse can be
found to let the customer pay we will have to do it
ourselves.
If a design change of the RAM modules to incorporate
an error correction feature is made, however, the modules
may be uniformed to 2 x 128K equipped with 64K RAMs
mounted in sockets. Then the recommended spares on
the CAMPS sites (16 sites) may be reduced to 1 module
+ 3 pcs RAMs instead of now 2 modules, and a path is
paved for a trade-off with SHAPE. Consequently SHAPE
will participate in our development costs.
7̲ ̲R̲E̲F̲E̲R̲E̲N̲C̲E̲ ̲L̲I̲S̲T̲
7.1 Alpha - Particles Induced Soft Errors in Dynamic Memories
IEEE, Vol ED-26 No. 1 - Jan.,79.
7.2 Alpha - Particle Tracks in Silicon and their Effect
on Dynamic MOS RAM Reliability
IEEE, Vol ED-26 No. 1 - Jan., 79.
7.3 Intel to Disclose 16-K Static Secrets and to Release
Soft-Error Data.
Electronics, Nov. 22., 1979.
7.4 Memory Data Book and Designers Guide.
MOSTEK, 1979.
7.5 Characterization of Random Access Memories,
Elektronikcentralen, ECR-93, Nov. -79.
7.6 Test og Service p> Mikrodatamatsystemer.
Elektronikcentralen, ECR-96, Aug. -80.
7.7 CR 80 D RAM Failure Rates
CPS/240/TCN/0009, FR, 80-03-11.
7.8 AM 2960 Boosts Memory Reliability.
Advanced Micro Devices, Technical Report, April - 80.
7.9 Sind "Soft Errors" durch - teilchen ein Problem ?
Elektronik 1980 Heft 22.
