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⟦37024594f⟧ Wang Wps File
Length: 4768 (0x12a0)
Types: Wang Wps File
Notes: Spelunked
Names: »~ORPHAN68.00«
Derivation
└─⟦003a8b650⟧ Bits:30006009 8" Wang WCS floppy, CR 0044A
└─ ⟦this⟧ »~ORPHAN68.00«
WangText
C…08…C…09…C…00…C
C !…08…!…09…!…00…!…07…
…0e… …1f……09……1f……0b……86…1
…02…
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…02…CPS/SDS/001
…02…SRA/810227…02……02…
CAMPS
SYSTEM
DESIGN
SPECIFICATION
…02……02…CAMPS
5.1.5 T̲h̲e̲ ̲I̲/̲O̲ ̲S̲u̲b̲s̲y̲s̲t̲e̲m̲
The I/O subsystem is composed of one Channel Unit (CU)
with a dualized (redundant) I/O bus configuration.
The system is equipped with three types of I/O ontrollers
(interfaces between the I/O buses and the I/O devices):
- Disk controllers, which via the Disk Controller
adapter interfaces the disk drivers to the I/O
sub-system.
- Floppy disk controller, which via an adapter is
connected to a dua floppy disk drive.
- Line Termination Units (LTU's), which via the V24/V28
adapters are used for driving the heavy communication
protocols towards the TARE-, CCIS-, and SCARS system.
The I/O subsystem interfaces to (fig. 5.1.5-1):
- the Procssor Sub-System through the dualized CIA
(sec. 5.1.5.1.1) - Data Channel (sec. 5.1.4.1.5)
- MIA (sec. 5.1.4.1.4.2) link.
- the Watchdog Processor through the serial configuration
control bus and the CCA (sec. 5.1.5.1.4).
- the TARE-, CCIS-, andSCARS-circuits via the V24/V28(L)
adapters (sec. 5.1.5.1.3.2).
Fig. 5.1.5-1
THE I/O SYSTEM INTERFACES
5.1.5.1 D̲e̲s̲i̲g̲n̲ ̲&̲ ̲C̲o̲n̲s̲t̲r̲u̲c̲t̲i̲o̲n̲
The design implements an I/O subsystem that has low
overhead, fast transfer rates, no overruns, and no
interrupts to the system until a logical entiy of work
is completed (i.e., no character by character interrupts
from the terminals). The design produced an I/O system
that is extremely simple.
The heart of the CR80D I/O subsystem is the Data Channel.
All bulk I/O is done on a direct memor access (DMA)
basis. With the block size determined by the individual
application. All I/O controllers are buffered to some
degree so that all transfers over the I/O channel are
at memory speed (2M words/second) and never wait for
mechanical motin since the transfers always come from
a buffer in the I/O controller, rather than from the
actual I/O device.
For setup, control and status between PU and I/O controllers,
programmed I/O (direct from CPUs) can be used concurrently
with the Data hannel DMA transfers.
Transfer on the Data Channel does not put any load
on the program execution, because the transfer concept
is implemented in hardware.
The memory system priority on the PU Channel bus always
permits I/O accesses (in an on-lne, transaction oriented
environment, it is rare that a system is not I/O bound).
In the following sections a detailed explanation of
the basic modules within a CU is given:
- CR80D Channel Interface Adapter (CIA)
- CR80D Disk Controller
- CR0D Disk Controller Adapter (DCA)
- CR80D Line Termination Unit (LTU)
- CR80D V24/V28 (L) Adapter
- CR80D Power Supply (PSU)
- CR80D Floppy disk Controller
- CR80D Floppy disk Controller Adapter (SFA)
5.1.5.1.1 T̲h̲e̲ ̲C̲I̲A̲ ̲M̲o̲d̲u̲l̲e̲
The Channel Interface Adapter is the interface between
the Data Channel and the dual bus structure of the
Channel Unit (fig. 5.1.5.1.1-1). Two versions f the
CIA are available, one for interfacing the Data Bus
A (CIA-A) and one for interfacing the Data Bus B (CIA-B).
The two versions are functionally identical, but the
printed circuit board either has an edge connector
towards the A-Bus or the B-us (figs. 5.1.5.1.1-2 and
-3)
Fig. 5.1.5.1.1-1…01…D̲A̲T̲A̲ ̲C̲H̲A̲N̲N̲E̲L̲ ̲I̲N̲T̲E̲R̲F̲A̲C̲E̲S̲
Fig. 5.1.1.5.1.1-2…01…T̲h̲e̲ ̲C̲I̲A̲-̲A̲
Fig. 5.1.5.1.1-3…01…T̲h̲e̲ ̲C̲I̲A̲-̲B̲
The main function of the CIA is to transfer data between
the I/O bus and the Data Channel. The CIA is master
to the I/O bus but slave to the Data Channel. This
means that a tranfer is initiated from the Data Channel,
which then awaits for the CIA to complete the transfer.
Interrupts from the Channel Unit modules are stored
in the CIA to be fetched by the Data Channel.
The CIA also undertakes several support functions owards
the I/O Bus:
a) Clock generation
b) Power supervision
c) Power up reset
d) Bus termination
The functional blocks of the CIA are shown in fig.
5.1.5.1.1-4.
a) D̲a̲t̲a̲ ̲T̲r̲a̲n̲s̲f̲e̲r̲
The information path of the Data Channel is shared
by addesses, data and error messages. Thus a transfer
is divided into three phases. This transfer description
is mainly a repetition of parts of sec. 5.1.4.1.4.2.
