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Notes: CPS/SDS/001
Names: »0562A «
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WangText
…00……00……00……00……00……14……02……00……00……14…
…14……07……13……0c……13……0f……13……00……12……09……12……0a……12……0b……12……02……12…
…11……08……11……09……11……00……11……01……11……02……10……86…1 …02… …02… …02…
…02…CPS/SDS/001
…02…SRA/810115…02……02…
CAMPS SYSTEM DESIGN SPECIFICATION
…02……02…CAMPS
T̲A̲B̲L̲E̲ ̲O̲F̲ ̲C̲O̲N̲T̲E̲N̲T̲S̲
5.2 THE TDX SUBSYSTEM DESIGN .................
5.2.1 General ..............................
5.2.2 TDX Subsystem Description ............
5.2.2.1 The TDX Bus ......................
5.2.2.1.1 TDX Bus Protocols and Frame
Format .......................
5.2.2.1.2 The TDX Bus Data Format ......
5.2.2.2 The TDX CRATE ....................
5.2.2.2.1 Electrical Specification of
the Motherboard Signals ......
5.2.2.3 The TDX Controller ...............
5.2.2.4 The LTUX-S .......................
5.2.2.5 The BSM-X ........................
5.2.2.6 The Power Supply .................
5.2 T̲H̲E̲ ̲T̲D̲X̲ ̲S̲U̲B̲S̲Y̲S̲T̲E̲M̲ ̲D̲E̲S̲I̲G̲N̲
5.2.1 G̲e̲n̲e̲r̲a̲l̲
The aim of this section is:
- to supply documentation and functional description
of the TDX (Telecommunication Data Exchange) subsystem
H/W as implemented in CAMPS.
- to establish a baseline document for the CAMPS
TDX subsystem design.
This section will provide a description of each of
the functional modules/elements within the TDX subsystem.
5.2.2 T̲D̲X̲ ̲S̲u̲b̲s̲y̲s̲t̲e̲m̲ ̲D̲e̲s̲c̲r̲i̲p̲t̲i̲o̲n̲
The TDX subsystem connects the CR80D Processor subsystem
(section 5.1) and the Distribution Equipment (section
5.3), thus providing the communication link between
CR80D processes and the terminals connected via the
Distribution Equipment.
The TDX subsystem interfaces to the following CAMPS
subsystems:
- The Processor subsystem
- The System Status & Control subsystem (section
5.4)
- The Distribution Equipment
This is shown schematically in fig. 5.2.2-1.
The TDX subsystem consists of:
- The dualized TDX bus, TDX bus#1 and TDX bus#2 each
with an associated TDX controller (para. 5.2.2.3).
- TDX Crate Assemblies (para. 5.2.2.2). The number
of TDX Crate Assemblies is determined by the application.
The TDX Crate Assemblies hold the TDX subsystem modules:
- The LTUX-S (TDX Line Termination Unit, para. 5.2.2.4)
- The BSM-X (TDX Bus Switching & Monitoring module,
para. 5.2.2.5)
Each TDX Crate Assembly connected on the TDX bus provides
towards the Distribution Equipment an output capacity
of eight communication channels in its max. configuration.
Each channel conforms with the CCITT V24/V28 and the
EIA RS-232C specifications.
In the following mechanical dimensions will be referred
to as either standard CR80S module or standard CR80S
19" frame where applicable. For further detailed specifications
please refer to section 5.5.
Figure 5.2.2-1…01…TDX Subsystem Interfaces
5.2.2.1 T̲h̲e̲ ̲T̲D̲X̲ ̲B̲u̲s̲
The TDX bus, which links the Processor subsystem and
the TDX Crate Assemblies, is essentially a high data
rate digital link. Data is transferred across the link
in serial form at a clock rate of 1.8432 MHz. The maximum
throughput on the bus is 1.6284 Mbit/second.
Data and clock are transferred on the TDX bus using
the self clocking differential split phase code SPL-D.
The SPL-D code changes the signal level at the start
of each bit-cell, and also in the middle of a bit-cell
if the transmitted data is zero. This is shown in figure
5.2.2.1-1. The SPL-D code allows data and clock to
be transmitted on the same line.
Transmitting the clock together with the data on the
TDX bus has several advantages.
The major advantage is that TDX bus delay has no significance
for the correct decoding, because clock and data are
delayed equally. Also, no need exists to synchronize
a receiver and the transmitter.
A second advantage is that the TDX controller clock,
being continuously transmitted on the Lower Bus (explained
later in this para.), is made available to all connected
TDX devices.
All TDX bus activities, such as communication scheduling
and synchronization of connected devices, are governed
by a TDX controller.
Figure 5.2.2.1.2 shows schematically the connection
of devices and the controller to the TDX bus. As shown
a TDX bus is physically 2 buses, a Lower Bus and an
Upper Bus. The TDX bus devices (LTUX-S and TIA (section
5.1)) are connected with the receiver to the Lower
Bus and the transmitter to the Upper Bus. The TDX controller
is connected with the receiver to the Upper Bus and
the transmitter to the Lower Bus. Thus a transfer of
data between two TDX devices is carried out in two
phases:
1) Data is transmitted by the source device and received
by the TDX controller (Upper Bus).
2) Data is retransmitted by the TDX controller on
the Lower Bus and received by the destination device.
Figure 5.2.2.1-1…01…The SPL-D Code
Figure 5.2.2.1-2…01…TDX Bus Connections
Communication scheduling implies that TDX devices only
can transmit on the Upper Bus when selected to do so.
Selection is carried out by the TDX controller.
A maximum of 255 TDX devices can be connected to the
TDX bus. Among these 255 TDX devices the TIA, which
is the TDX bus interface towards a Processor Unit,
is limited to a maximum of 12.
The LTUX-S interfaces the TDX bus to the Distribution
Equipment.
To convert the dualized TDX bus structure to the single
TDX bus within the TDX Crate Assembly a BSM-X module
is used.
Each TDX Controller, BSM-X and TIA has to be connected
to the TDX bus via a TDX outlet as shown in figure
5.2.2.1-3.
The TDX outlet contains driver and receiver circuitry
and connectors towards the TDX bus and the connected
device. Due to the isolation transformers and a three-state
concept, a device can be connected and disconnected
without disturbing the TDX bus traffic.
The balanced TDX outlet driver can switch +/- 12 V
across the TDX bus, Upper or Lower, in less than 50
ns. When tri-stated the driver represents a load equal
to 25 kohms in parallel with 50 pF (at 10 MHz) towards
the TDX bus.
The balanced TDX outlet receiver has a worst case differential
switching band of +/- 120 mV towards the TDX bus.
Using a value of +/- 240 mV (giving a safety factor
of 6dB) the maximum attenuation between a driver and
any receiver can be calculated to:
ATT…0f…max…0e… = 20 log(12/0.24) = 34 dB
Figure 5.2.2.1-3…01…The TDX Outlet
The Upper and Lower Bus of the TDX bus is each a screened
twisted pair cable.
Three types of screened RF cable can be used. The three
types are shown in fig. 5.2.2.1-4.
For distance below 1000 m the two core screened RF
cable BICC T(M) 3078 are used.
The characteristics of this cable are:
Characteristic impedance: 100 ohm
Nominal capacitance: 52 pF/m
Attenuation at 2 MHz: 2.18 dB/100 m
Diameter: 6.75 mm
Min. bending radius: 35 mm
App. weight: 69 kg/km
Max. operating temperature 70…0e…o…0f…C
Insulation: Polyethylene
For distances up to 1200 m, the RG 22 B/U or the armed
version RG 111 A/U is used. These cables comply with
MIL-SPEC. C-17D:
Characteristic impedance: 95 ohm
Nominal capacitance: 53 pF/m
Attenuation at 2 MHz: 1,3 dB/100 m
Diameter:
RG 22 B/U: 10.8 mm
RG 111 A/U: 12.4 mm
App. weight:
RG 22 B/U: 180 kg/km
RG 111 A/U 300 kg/km
Max. operating temperature 70…0e…o…0f…C
Insulation: Polyethylene
Figure 5.2.2.1-4…01…TDX Balanced, Shielded Twinlead Cable
5.2.2.1.1 T̲D̲X̲ ̲B̲u̲s̲ ̲P̲r̲o̲t̲o̲c̲o̲l̲s̲ ̲a̲n̲d̲ ̲F̲r̲a̲m̲e̲ ̲F̲o̲r̲m̲a̲t̲
The software, firmware, and hardware of the TDX subsystem
may be divided into 4 levels as shown on fig. 5.2.2.1.1-1.
The Host Computer referenced corresponds to a Processor
Unit within the Processor subsystem and the Host I/F
corresponds to the STI/TIA complex (refer to section
5.1) within this Processor Unit.
Information is transferred across the TDX bus in packets.
Each packet contains one or more frames. A frame is
the smallest information block on the bus. A frame
format is shown on fig. 5.2.2.1.1-2.
The protocol levels are explained as:
L̲e̲v̲e̲l̲ ̲1̲:̲
This level is handled by the Front-Ends in the TDX
devices and by the TDX controller. The Front-End is
the interface between the TDX bus and the TDX-packet
protocol routines.
The controller polls the TDX devices according to a
MUX-table. If a Front-End recognizes its device-number
in the MUX-field of the frame on the Lower Bus, and
a frame containing data is transferred from packet
level to the Front-End, it starts a frame transmission
on the Upper Bus. If no frame is ready, the Front-End
does nothing.
Concerning reception the Front-End compares its device-number
to the device number in the CR-ID field of the frames
on the Lower Bus. If a match is found the frame is
transferred to packet level.
The third and last task of the frame level is to detect
bit errors. This is done through a CRC check. If any
error is detected the frame is discarded in the receiving
Front-End. It is left to the TDX-packet level to recover
from the error.
Figure 5.2.2.1.1-1…01…TDX Protocol Levels
Figure 5.2.2.1.1-2…01…TDX Bus Frame Format
L̲e̲v̲e̲l̲ ̲2̲:̲
The TDX-packet protocol serves communication between
two TDX devices of any type. This can be TIA to TIA,
TIA to LTUX-S or LTUX-S to LTUX-S. Packets may consist
of a variable number of frames less than e.g. 8. The
packet protocol makes use of byte 3 and 4 in the frame
format, which contain communication control, sequence
number and data bytecount. A connection between two
TDX devices is always made for transmission in both
directions. The TDX-packet protocol goes only one step
back, which means that only one packet is transmitted
between the reception of two acknowledges (ACKs). In
multiframe packets, frames are numbered sequentially
modulo 8. In this way missing frames are detected,
and by a not-acknowledge (NACK) response, a retransmission
of the erroneous packet is performed. If an error occurs
in the transmission of a single frame packet the missing
response will cause a retransmission. A timer in the
transmitter initiates retransmission of packet N in
case neither ACK nor NACK is received within a specified
time (e.g. lost due to error of the link); transmission
is attempted three times before the protocol gives
up on output.
L̲e̲v̲e̲l̲ ̲3̲:̲
This level serves the I/F between application routines
and the TDX system. This includes set-up and deletion
of TDX channels, change in the assigned TDX-channel
bandwidth, transfer of data buffers and actions upon
unrecoverable transmission errors.
L̲e̲v̲e̲l̲ ̲4̲:̲
Application level which includes all user defined routines
resident in LTUX-S's or in the Processor Subsystem.
5.2.2.1.2 T̲h̲e̲ ̲T̲D̲X̲ ̲B̲u̲s̲ ̲D̲a̲t̲a̲ ̲F̲o̲r̲m̲a̲t̲
Two TDX bus data formats exist. One for the Lower Bus
and one for the Upper Bus. These formats are shown
in figure 5.2.2.1.2-1.
The two formats differ on two points:
- The Lower Bus includes a MUX.NO. (m) in its data
field
- The Upper Bus has an ABORT byte as preamble.
Both Upper and Lower Bus frames are standard HDLC with
bit stuffing in order to have a unique synchronization
byte, the FLAG (01111110). Bit stuffing is performed
between the start-FLAG and the end-FLAG. Each time
five consecutive ONEs ar met in the data stream, a
zero is inserted. The zeros are then removed at the
receiving end, restoring the original data.
The bit stuffing makes the length of frames variable:
- On the Lower Bus between 200 and 236 bits
- On the Upper Bus between 200 and 235 bits
L̲o̲w̲e̲r̲ ̲B̲u̲s̲ ̲F̲o̲r̲m̲a̲t̲
Following the start-FLAG each byte has the following
meaning:
B̲y̲t̲e̲ ̲N̲o̲.̲ ̲1̲.̲ ̲M̲U̲X̲.̲ ̲N̲O̲.̲ ̲m̲:̲
This byte is inserted by the TDX controller to signal
that the device with the number m is to transmit on
the Upper Bus at the end (actually at bit count 241)
of the frame on the Lower Bus.
B̲y̲t̲e̲ ̲N̲o̲.̲ ̲2̲,̲ ̲D̲A̲T̲A̲ ̲T̲Y̲P̲E̲ ̲&̲ ̲H̲O̲S̲T̲/̲M̲O̲D̲E̲ ̲F̲i̲e̲l̲d̲s̲ ̲d̲,̲h̲:̲
The DATA TYPE (d) indicates the data stream number
(channel number) to which the following data in the
frame belong to. Data type 0 and 1 are reserved for
channel set-up and system control purposes.
The HOST/MODE field (h) is defined as:
0000 Destination of the frame is the TDX controller
0001-1100 Destination of the frame is the TIA indicated
1101 Broadcast mode, not used in CAMPS
1110 Destination of the fram is a TDX device
(LTUX-S) indicated in byte 3, TDX DEVICE
NO., source is a TDX Controller or an LTUX-S.
1111 Destination is a TDX device (LTUX-S) indicated
in byte 3, TDX DEVICE NO., source is a
TIA.
B̲y̲t̲e̲ ̲N̲o̲.̲ ̲3̲,̲ ̲T̲D̲X̲ ̲D̲E̲V̲I̲C̲E̲ ̲N̲O̲.̲ ̲t̲:̲
For HOST/MODE field = 0000-1101 this byte indicates
the device number (0-255) of the device where the frame
was originated (source). For HOST/MODE field = 1110-1111
the byte indicates the device no. of the device where
the frame is destinated (destination). Device no. 255
indicates a dummy frame to which normally no device
is assigned.
B̲y̲t̲e̲ ̲N̲o̲.̲ ̲4̲,̲ ̲C̲O̲M̲M̲U̲N̲I̲C̲A̲T̲I̲O̲N̲ ̲B̲Y̲T̲E̲ ̲s̲:̲
This byte is used by the TDX packet protocol control.
B̲y̲t̲e̲ ̲N̲o̲.̲ ̲5̲,̲ ̲F̲R̲A̲M̲E̲ ̲S̲E̲Q̲.̲ ̲N̲O̲.̲ ̲&̲ ̲N̲O̲.̲ ̲O̲F̲ ̲D̲A̲T̲A̲B̲Y̲T̲E̲S̲ ̲I̲N̲ ̲F̲R̲A̲M̲E̲
̲z̲,̲w̲:̲
This byte is inserted by the originating device. The
bits 5-7 contain the frame number within a multiframe
packet. This number (modulo 8) is used by the receiving
packet protocol level to decide whether a frame is
missing or not, and in case of a missing frame (a jump
in frame numbering) to request a retransmission of
the packet.
The bits 0-4 indicate the number of actual data bytes
in a possible partly filled DATA field. The number
of bytes transmitted in the DATA field is always 16,
but only the number of data bytes indicated in bits
0-4 (0-16) are valid data.
Figure 5.2.2.1.2-1…01…TDX Bus Data Format
B̲y̲t̲e̲ ̲N̲o̲.̲ ̲6̲ ̲t̲o̲ ̲B̲y̲t̲e̲ ̲N̲o̲.̲ ̲2̲1̲,̲ ̲D̲A̲T̲A̲ ̲F̲i̲e̲l̲d̲s̲:̲
This is the information field containing data to be
communicated from the originating (source) device to
the receiving (destination) device.
B̲y̲t̲e̲ ̲N̲o̲.̲ ̲2̲2̲ ̲&̲ ̲N̲o̲.̲ ̲2̲3̲,̲ ̲C̲R̲C̲:̲
The Cyclic Redundancy Check (CCITT-16) is inserted
by the originating device, recalculated by the TDX
controller, and utilized by the receiving device to
verify the correctness of the frame.
T̲r̲a̲i̲l̲i̲n̲g̲ ̲O̲N̲E̲S̲ ̲a̲f̲t̲e̲r̲ ̲F̲r̲a̲m̲e̲:̲
Following the frame end-FLAG, the controller inserts
ONES until bit count of the time slot reaches 241.
Then ZEROS are inserted until bit count 249, and then
again ONES until end of time slot (bit count 288) where
a new frame starts. The transition from ONE to ZERO
at bit count 241 is used to start transmission on the
Upper Bus by the selected device.
U̲p̲p̲e̲r̲ ̲B̲u̲s̲ ̲F̲o̲r̲m̲a̲t̲:̲
The format on the Upper Bus is identical to the Lower
Bus format except for the following:
a) An ABORT byte (all ONES) is transmitted preceding
the frame start-FLAG in order to absorb common
mode swing of the bus at switch-on of the TDX device
transmitter, and to synchronize the clock and data
decoder at the TDX controller receiving end.
b) No MUX. NO. is included in the Upper Bus format.
This shifts the format one byte in proportion to
the Lower Bus:
Upper Bus byte no: identical to Lower Bus byte
no:
byte no. 1 byte no. 2
byte no. 2 byte no. 3
byte no. 3 byte no. 4
byte no. 5-20 byte no. 6-21
byte no. 21, 22 byte no. 22,
23
c) No trailing ONES or ZEROS after the frame end-FLAG.
Transmission stop immediately after the end-FLAG.
5.2.2.2 T̲h̲e̲ ̲T̲D̲X̲ ̲C̲r̲a̲t̲e̲
The TDX subsystem modules, the LTUX-S and the BSM-X,
are housed in a standard CR80S 19" frame, the TDX Crate.
Refer to section 5.5 for further mechanical specifications.
The TDX Crate Assembly (a TDX Crate with TDX subsystem
modules) is shown in fig. 5.2.2.2-1.
Beside the TDX subsystem modules the TDX Crate houses
modules belonging to the DM&T subsystem (section 5.3)
and a Power Supply module (para. 5.2.2.6).
The TDX Crate consists of a front crate and a rear
crate. On the back panel of the front crate is a bus
motherboard (Printed Circuit board) for module interconnection
and also edgeconnectors for the front crate mounted
modules. Position of a module in the TDX Crate is restricted
to the positions indicated in fig. 5.2.2.2-1.
The mother board connector signals are shown in fig.
5.2.2.2-2 (6 sheets).
5.2.2.2.1 E̲l̲e̲c̲t̲r̲i̲c̲a̲l̲ ̲S̲p̲e̲c̲i̲f̲i̲c̲a̲t̲i̲o̲n̲ ̲o̲f̲ ̲t̲h̲e̲ ̲M̲o̲t̲h̲e̲r̲ ̲B̲o̲a̲r̲d̲ ̲S̲i̲g̲n̲a̲l̲s̲
TBD.
Figure 5.2.2.2-1…01…The TDX Crate Assembly
Figure 5.2.2.2.2-2 (Sheet 1 of 6)…01…Mother Board Connector Signals, Pos
1 & 2
Figure 5.2.2.2.2-2 (Sheet 2 of 6)…01…Mother Board Connector Signals, Pos 3, 4,
11, 12, & 14
Figure 5.2.2.2.2-2 (Sheet 3 of 6)…01…Mother Board Connector Signals, Pos
7 & 15
Figure 5.2.2.2.2-2 (Sheet 4 of 6)…01…Mother Board Connector Signals, Pos
8 & 16
Figure 5.2.2.2.2-2 (Sheet 5 of 6)…01…Mother Board Connector Signals, Pos
9 & 17
Figure 5.2.2.2.2-2 (Sheet 6 of 6)…01…Mother Board Connector Signals, Pos 10
& 18
5.2.2.3 T̲h̲e̲ ̲T̲D̲X̲ ̲C̲o̲n̲t̲r̲o̲l̲l̲e̲r̲
The TDX Controller, figure 5.2.2.3-1, is the control
device of the TDX bus system. Through it passes all
data between the TDX devices.
The serial TDX bus is clocked and synchronized by the
TDX Controller. The TDX Controller outputs a continuous
bit stream of 1.8432 Mbit/second on the Lower Bus.
This stream is divided into 6400 timeslots/second,
each time slot containing 288 bits.
Each time slot on the Lower Bus contains a standard
HDLC frame with control information (5 bytes), DATA
to be transferred 16 bytes), and CCITT-16 Cyclic Redundancy
Check (CRC, 2 bytes). The HDLC frame starts at the
beginning of a time slot and takes up maximally 236
bits of the 288 bits in the time slot. Figure 5.2.2.1.1-2
shows the HDLC frame.
The controller inserts as the first byte after the
start-FLAG a MUX NO. byte taken from a MUX NO. REGISTER
on the controller. All connected TIAs and LTUX-Ss looks
at this byte. If it corresponds to the device number
of a TIA or a LTUX-S this device has the use of the
Upper Bus for data transmission at the end of the frame
(actually at bit count 241) on the Lower Bus. This
ensures that only one device will transmit on the Upper
Bus at any time. If the selected device has no data
to transmit, no frames will be transmitted on the Upper
Bus during that time slot.
The bandwidth assigned to each device at initialization
time by the MUX NO. TABLE is dynamically changeable
in real time, by request from device to controller.
A transmitted frame on the Upper Bus is received by
the TDX Controller. If the destination is not the controller,
the frame is "opened up", MUX NO. added as first byte,
CRC recomputed and the frame is then transmitted with
a one frame delay on the Lower Bus.
If the destination of an Upper Bus frame is the controller
(e.g. request for bandwidth change) or if no frame
is transmitted by the polled device, the controller
can utilize the then free time slot on the Lower Bus
in a "cycle stealing" manner to output device control
information (e.g. acknowledge of bandwidth change request
to a device) or data frames on the Lower Bus. If no
data is awaiting transmission a dummy frame will be
transmitted.
Figure 5.2.2.3-1…01…The TDX Controller
Transmission is continuous on the Lower Bus, thereby
making it possible to use the highly stable clock of
1.8432 MHz as a master clock for the devices.
According to the block diagram signals from one or
two TDX buses are buffered by drivers and receivers.
In the CAMPS TDX subsystem the TDX Controller only
connects to one TDX bus structure. The en/decoder converts
the SPL-D coded data stream to NRZL-code (Non Return
to Zero Logic-code) before it is loaded into the serial
to parallel converter. Serial data coming from the
parallel to serial converter (MPCC) is converted to
SPL-D code synchronized to the clock coming from the
Clock Control Circuit.
Incoming frames are routed to FIFO 1 (First In First
Out register 1) while be HOST field and CRC field are
checked "on the fly" by the State Controller logics.
If the HOST field was zero (meaning that the controller
is the destination) the frame is forwarded from FIFO
1 to FIFO 2 and the Controller CPU is interrupted.
At this point the CPU has 115 micro seconds to read
the frame from FIFO 2. If the HOST field differed from
zero the frame is loaded from FIFO 1 to FIFO 4, and
then transmitted as the next frame on the Lower Bus.
If a CRC error has occurred the frame in FIFO 1 is
cancelled and a dummy frame (all ONES) will be transmitted
as next frame if no frame is available from the CPU
in FIFO 3.
When the transmitter part of the MPCC requests for
a new frame, the State Controller always starts with
a start-FLAG and then a MUX NO. taken from the MUX
NO. REGISTER. The CPU is then interrupted and has now
155 micro seconds to find the next MUX NO. in the MUX
NO. TABLE and load it into the MUX NO. REGISTER.
After having routed all data of a frame to the MPCC,
the State Controller ends the frame with an end-FLAG,
transmits ONES till bit count 241, transmits ZEROS
till bit count 249 and then transmits ONES till the
end of the time slot (bit count 288) after which a
new frame transmission starts.
I̲n̲t̲e̲r̲f̲a̲c̲e̲ ̲S̲p̲e̲c̲i̲f̲i̲c̲a̲t̲i̲o̲n̲s̲
The TDX Controller has four different interfaces:
- The TDX signal interface
- The Watchdog interface
- The clock generator interface
- The power interface
T̲D̲X̲ ̲I̲n̲t̲e̲r̲f̲a̲c̲e̲ ̲S̲i̲g̲n̲a̲l̲ ̲S̲p̲e̲c̲i̲f̲i̲c̲a̲t̲i̲o̲n̲
The TDX signal interface of the TDX Controller is mechanically
a 37 pin Cannon connector. The pin lay-out is shown
in fig. 5.2.2.3-2.
RXDAT, TXDAT, and DISAB are all differential lines
conforming with the EIA RS-422 recommendations.
R̲X̲D̲A̲T̲1̲/̲2̲
Received data from Upper Bus 1 and 2 of the TDX
buses.
T̲X̲D̲A̲T̲1̲/̲2̲
Transmitted data to Lower Bus 1 and 2 of the TDX
buses. The drivers are tri-statable.
D̲I̲S̲A̲B̲1̲/̲2̲
Transmitter disable lines to the TDX outlets used
to enable the outlet drivers towards 1 of 2 TDX
buses (Lower Buses).
Only Upper Bus 1 and Lower Bus 1 are applicable to
the CAMPS TDX subsystem.
Figure 5.2.2.3-2…01…TDX Bus Connector, Pin Lay-out
W̲a̲t̲c̲h̲d̲o̲g̲ ̲I̲n̲t̲e̲r̲f̲a̲c̲e̲
The Watchdog interface is a 25 pin Cannon connector
which includes a V24/V28 serial communication I/F and
some condition status lines. Pin lay-out shown in fig.
5.2.2.3-3.
V̲2̲4̲/̲V̲2̲8̲ ̲I̲/̲F̲
All lines of this I/F are according to the CCITT
V24/V28 recommendations. This I/F is not used in
CAMPS.
R̲S̲ ̲&̲ ̲T̲S̲
Receive and transmit status are open collector
driver outputs without pull-up resistor. Active
Low. Monitored by the SS&C subsystem (section 5.4).
F̲S̲
Fuse status is an active low open collector driver
output without pull-up resistor. Monitored by the
SS&C subsystem.
B̲S̲
Bus select is an active low input, not used in
CAMPS.
C̲0̲1̲/̲2̲
General purpose active low open collector driver
outputs controlled by the TDX Controller CPU. Monitored
by the SS&C subsystem.
C̲I̲1̲/̲2̲
General purpose active low inputs readable by the
controller CPU, not used in CAMPS.
C̲l̲o̲c̲k̲ ̲G̲e̲n̲e̲r̲a̲t̲o̲r̲ ̲I̲n̲t̲e̲r̲f̲a̲c̲e̲
If an external clock generator of 1.8432 MHz is used,
it has to be connected to the BNC connector on the
front panel.
This input is terminated with 75 ohm and the voltage
levels shall be:
0 ̲Vi ̲5 Volt
Vi(low) ̲0,6 Volt
Vi(high) ̲2 Volt
P̲o̲w̲e̲r̲ ̲I̲n̲t̲e̲r̲f̲a̲c̲e̲
The TDX Controller is a standard CR80S module which
is placed in a TDX Crate Assembly. The TDX Controller
is powered from the crate supply via an edge connector
that fits into a connector on the crate motherboard
(para. 5.2.2.2). The pin lay-out for this edge connector
is shown in fig. 5.2.2.3-4.
P̲o̲w̲e̲r̲ ̲C̲o̲n̲s̲u̲m̲p̲t̲i̲o̲n̲ ̲o̲f̲ ̲t̲h̲e̲ ̲T̲D̲X̲ ̲C̲o̲n̲t̲r̲o̲l̲l̲e̲r̲
+ 5 Volt: 3 A
+ 12 Volt: 0,15 A
- 12 Volt: 0,15 A
Figure 5.2.2.3-3…01…Watchdog I/F Connector, Pin Lay-Out
5.2.2.4 T̲h̲e̲ ̲L̲T̲U̲X̲-̲S̲
The LTUX-S, of which up to 242 can be connected to
the TDX bus, is the standard interface between the
TDX bus and the DM&T subsystem (section 5.3). The LTUX-S
provides towards the DM&T subsystem 4 V24/V28 communication
channels. On the front panel are four switches that
can be used to enable/disable each of the four communication
channels.
The LTUX-S is built around a standard microprocessor
using standard microprocessor interface LSIs as interface
between the TDX bus and the user applications.
The LTUX-S provides up to 16 full duplex individual
logic channels of up to 9.6 kBaud from the user application
to the TDX bus. The microprocessor supports both application
processing of the TDX interface, TDX protocol and TDX
channel set-up. The sum of bandwidth assigned to the
channels through the LTUX-S is dynamically changeable
by request to the TDX Controller.
Overleaf is found the block diagram of the LTUX-S,
fig. 5.2.2.4-1.
The TDX bus signals are buffered, by bus receivers
and a tri-statable driver, before they are routed to/from
the code converter circuit. In this circuit the incoming
SPL-D data stream is converted to NRZL data and a clock
(CLK) which is synchronous to the clock in the TDX
Controller. The outgoing data stream is converted to
SPL-D code synchronized to CLK. When an incoming frame
is received, the State Controller gets a request from
the serial to parallel converter and the contents of
the frame is byte by byte routed to FIFO 1.
During this transfer some of the bytes in the frame
are checked or compared "on the fly" by the State Controller.
If the MUX NO. is equal to the device number (set on
a DIL-switch) and no CRC errors are detected the transmitter
part is activated and a frame will be transmitted when
bit 241 of the incoming data stream has been reached.
Figure 5.2.2.3-4…01…TDX Controller/Crate Connector, Pin Lay-Out
Figure 5.2.2.4-1…01…The LTUX-S
Also the HOST/MODE field is checked to determine whether
the addressing technique is used or not. If used the
contents of the DEVICE NO. field is compared to the
device number, and if equal the contents of FIFO 1
is transferred to FIFO 2. If FIFO 2 is not empty this
transfer is cancelled and FIFO 1 is cleared to be ready
for the next incoming frame. When the transfer from
FIFO 1 to FIFO 2 has succeeded the LTUX-S CPU is interrupted.
The interrupt routine (FRAME-routine) transfers the
frame from FIFO 2 to a free ringbuffer within the CPU
memory space, and the Incoming Scan routine transfers
the frame from the ringbuffer to a data buffer associated
to one out of ten protocol descriptors identified by
the CR-ID block and simultaneous executes the TDX protocol
on the frame. Via the protocol descriptor the frame
is fetched by either the System S/W (channel 0-1) or
by Application S/W (channel 2-9). Transfer is shown
schematically on fig. 5.2.2.4-2 (2 sheeets).
When the transmitter part of the State Controller has
been activated by an incoming frame, it starts to send
the start-FLAG followed by the frame which is transferred
byte by byte from FIFO 3 to the parallel to serial
converter. After the last data byte an end-FLAG is
generated. The CPU is interrupted and will now move
the next outgoing frame from a channel buffer in the
memory to FIFO 3. If no frame is available the CPU
does nothing and the next time the transmitter is activated
FIFO 3 will be empty and no frame is transmitted.
The frame to be transmitted comes from a data buffer
fetched, via a protocol descriptor, by the Outgoing
Scan routine and routed to FIFO 3 directly while executing
the TDX protocol on the frame.
The processor part consists of a PROM-memory area,
a data memory area, serial input/output interface circuits
for four V24 channels, a timer and interrupt control
circuit and an I/O port used for reading a mode select
switch (DIL-switch) and for control of the State Controller.
The mode select switch can be used by the Application
S/W. F.ex. to determine characteristics for the V24
channels such as:
- baudrate
- V24 protocol
Figure 5.2.2.4-2 (Sheet 1 of 2)…01…LTUX-S Data Transfer
Figure 5.2.2.4-2 (Sheet 2 of 2)…01…LTUX-S Data Transfer
The timer circuit has one software controlled timer
with interrupt access to the CPU. It handles one external
interrupt from the State Controller and it controls
two baud rate generators set up by software. The V24/V28
communication ports are interrupt controlled and they
are able to handle async/sync, HDLC, SDLC in full or
half duplex modes.
The LTUX-S is a standard CR80S module placed in the
TDX Crate Assembly. The LTUX-S motherboard bus connector
signals are shown on fig. 5.2.2.4-3.
P̲o̲w̲e̲r̲ ̲C̲o̲n̲s̲u̲m̲p̲t̲i̲o̲n̲ ̲o̲f̲ ̲t̲h̲e̲ ̲L̲T̲U̲X̲-̲S̲
+ 5 Volt: 3 A
+ 12 Volt: 0,15 A
- 12 Volt: 0,15 A
Figure 5.2.2.4-3…01…LTUX-S Bus Connector Lay-Out
5.2.2.5 T̲h̲e̲ ̲B̲S̲M̲-̲X̲
TBD.
5.2.2.5 T̲h̲e̲ ̲P̲o̲w̲e̲r̲ ̲S̲u̲p̲p̲l̲y̲
The TDX Crate power supply is a standard CR80S module.
The Power Supply, as seen from fig. 5.2.2.6-1, consists
of 3 different power supplies namely:
- a + 5 Volt power supply
- a + 12 Volt power supply
- a - 12 Volt power supply
The +5 Volt power supply is a 20 KHz push-pull converter
operating directly on the rectified mains voltage.
The +12 Volt and -12 Volt power supplies are fed from
a full wave rectified transformer output.
The +12 Volt power supply is regulated by a conventional
PWM (Pulse Width Modulated) bucking regulator.
The -12 Volt power supply is regulated by a buck-boost
PWM regulator.
P̲o̲w̲e̲r̲ ̲S̲u̲p̲p̲l̲y̲ ̲F̲e̲a̲t̲u̲r̲e̲s̲
- Output maintained during one missing mains supply
cycle
- Efficiency at maximum load better than 72%
- Constant current limit short circuit protection
- Over voltage protection
- Parallelling of more power supplies possible without
derating
- Remote error sensing facility
E̲l̲e̲c̲t̲r̲i̲c̲a̲l̲ ̲S̲p̲e̲c̲i̲f̲i̲c̲a̲t̲i̲o̲n̲s̲
Maximum load:
+ 5 Volt: 32 A
+ 12 Volt: 2,8 A
- 12 Volt: 1,2 A
Noise & ripple: Better than 60 mV…0f…pp…0e…
Input Voltage: 220V…0f…ac…0e…+10/-15 %
50 Hz + 30/-10%
Figure 5.2.2.6-1…01…The Power Supply
