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CAMPS Instructor's Manual for
MT/RST Course, Week 4
CPS/TMA/007
CDRL Logistics Support No. 03A
Line Item 8.2.4-B
Bent Pau Mortensen
Kurt Nybroe-Nielsen
SHAPE (2), NCS (6), ORP, PBP, CL,
BSP, BF, BJR, BPM, Conf. Mgmt., LU
ILS Train.Mgr. 830617
1
830617
Conf.Mgmt. 83067
2793A/ktd …02… CPS/TMA/007
…02… BPM/830617…02……02…ii
CAMPS Instructor's Manual for
MT/RST Course, Week No. 4…02… Prelim.…02… CAMPS
821011 All Preliminary Issue of
Document
Prelim. 830617 All Completely new update
of
manual
…86…1
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…02…
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830617
TDX SYSTE THEORY 4:1:1 45
CAMPS…0f…
Describe the TDX concept:
- BUS formats
- communication cycles
Evaluation on exercises
- The students must peform exercises in lesson 4.1.4-6
Revision on progress test
- Questions 1, 2 & 7 particularly
Classroom
L
Black board, 3 OH's
HBK: Section 8.2
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830617
TDX CONTRLLER 4:1:2-3 2 x 45 CAMPS…0f…
Describe the TDX controller functions
Describe the TDX bus coding
Describe the CTRL indicators
Evaluation on eercises
- The students must perform exercises in lesson 4.1.4-6
1 and 2 in about 2 hours
Revision on progress test
- Questions 1, 2 & 7 particularly.
Classroom
L
Black board, 2 OH's
HBK: Section 8.2.2.1
TCL…86…1 …02… …02…
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830617
TDX SYSTE TEST 4:1:4-6 3 x 45 CAMPS…0f…
- Indicate the TDX controller module and connections.
- Use the built-in test fac.
- Run the OFF line TDX (bus) test.
Evaluation of exercises
- The students must have performed all steps in Lab.
Guide 4:7:4-6
Training room
GW, DI, EX
Training system, Lab. Guide 2 pages
SLM: Section 4. 7. 2. 1. 8
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830617
TDX TRANMISSION 4:2:1 45 CAMPS…0f…
- Understand the TDX transmission protocol
- Revision of progress test
Classroom
L
lackboard, 1 OH
HBK: Section 8.3…86…1 …02… …02…
…0e… 2793A/ktd
830617
TDX HOST /F (STI/TIA) 4:2:2-3 2 x 45 CAMPS…0f…
- Describe the HOST I/F Functions
- Describe the STI board functions & indicaters
- Describe the TIA board functions
Evaluation of exercises in lesson 4:2:4-6
- The students must have performed the exercises
1 and 2
- Progress test revision 5 and 6
Classroom
L
Black board, 3 OH's
STI
TIA
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830617
TDX CONFIG EXERCISES 4:2:4-6 3 x 45 CAMPS…0f…
- Indicate the TDX HOST modules (STI/TIA) and the
module connections.
- Indicate the LTUX-S modules and the module connectins.
- Indicate the BSM-X modules and the module connections
- Set the DIL switches in the TDX DEVICES
- Test the TDX DEVICES
- During practical exercise
- During evaluation of the exercise
Training room
GW, DI, EX
Training system, Lab. Guide 1 page
SLM: section 4.7.2.1.8
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830617
TDX LTUX- 4:3:1 45 CAMPS…0f…
Describe the LTUX-S functions
Describe the LTUX-S indicators
Describe the LTUX-S switchsetting
Evaluation of xercises in lesson 4:2:4-6
- the students must have performed the exercises
1, 3, 4, 5, 6
- Progress test revision 3 and 4
Classroom
L
Black board, 1 OH
LTS
SLM: Table 4.5.4-4
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830617
BSM-X, L/ ADAPTORS 4:3:2-3 2 x 45 CAMPS…0f…
Describe the BSM-X functions
Describe the BSM-X switches
Describe the BSM-X indicators
Describe the LOW LEVEL ADAPTOR unctions
Evaluation of exercises:
- The students must have performed the exercises
1, 3, 4, 5, 6
- Progress test revision 3, 8, 9, 10, 12
Classroom
L
Black board, 3 OH's
BSX
LLA
SLM: Table 4.5.4-2 & 4.5.4-5 &4.5.4-6
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830617
TDX DEVIE TEST 4:3:4-6 3 x 45 CAMPS…0f…
- Test the LTUX-S module
- Test the opto module
- Test the communication to and from the VDU
- During practicl exercise
- During evaluation of the exercise
Training room
GW, DI, EX
Training System, Lab. Guide 4 pages
SLM…86…1 …02… …02…
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830617
CTX CRATE, WALL OUTLET 4:4:1-2 2 x 45 CAMPS…0f…
- Describe the CTX Crate functions
- Describe the TDX CABLES/outlets
- Describe all cable connections and the module psitioning
in the CTX crates and to the outlets.
Evaluation of exercises in lesson 4:3:4-6
- The students must have performed exercise (1) and
- in excess time - remedied 1-7 faults
Classroom
L
Black board, 8 OH's
CTX
HWB: section 3
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830617
POWER SUPLIES/BP8 4:4:3 45 CAMPS…0f…
- Describe the CTX power supplies and the power distribution
in the CTX crate
- Describe the BP8 (BACK Plane Type 8) fuctions
Evaluation of exercises in lesson 4:3:4-6
- The studenst must have performed all the exercises
Classroom
L
Black board, 2 OH's
TPS…86…1 …02… …02…
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830617
EXERCISE:CRATES & CABLES 4:4:4-6 3 x 45 CAMPS…0f…
- Identify all modules and cable connections in the
CTX crate
- Identify power check points in the crate
- Durng practical exercises
- During evaluation of the exercises
Training room
GW, DI, EX
Training System, Lab. Guide 6 pages
HWB: section 3
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830617
WEEKLY POGRESS TEST 4:5:1-3 3 x 45 CAMPS…0f…
- The results will be used in the student's
final assessment.
The results of this test will be recorded on the
"Studet's Progress Report".
Analysis of the test results
10 answers shall be correct
CAMPS Classroom
(Good separation required)
Progress Test (12 questions on subject covered during
week 4) Test time 45 min.
1 OH
2793A/aml 4:5:1-3
830928
1 of 2
PROGRESS TEST WEEK 4
CAMPS
NAME: ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ SCORE: ̲
̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲
1. How many LTUX-S DEVICES canbe located in a
TDX CRATE?
2. How is the WATCH DOG connected to the TDX SYSTEM?
3. When does a TDX DEVICE transmit?
4. How can you get information about the TDX system
status? Does this action disturb the normal
function?
5. Wht does the number 122 in the command
DO TDX ̲VDU ̲IO122 refer to?
6. Can you exchange TDX CONTROLLERS without changing
anything else?
7. How is the TDX SYSTEM connected to the PROCESSOR?
8. What is the 5th line in the UMO indicating?
9. How can you check that an OPTO MODEM is functioning
correctly?
2793A/aml 4:5:1-3
830928
2 of 2
PROGRESS TEST WEEK 4
CAMPS
10. Which TDX DEVICE transmits on the LOWER BUS?
11. What is the BITRATE of the signal on the TDX
BSSES?
12. What is the function of the WALL OUTLET?
13. What is done to the TDX BUS to prevent reflection?
14. What happens if a DEVICE does not respond to
its
MUX NO.?
15. Does the WALL OUTLET get power from the TDX
BUS?
16. hat is the physical structure of a TDX BUS?
17. What happens if a DEVICE makes a transmission
error?
18. What is the purpose of the FLAG in TDX FRAME?
19. How many OPTO MODEMS can be connected to an
ADAPTOR POWER SUPPLY?
20. Is tere a TDX CONTROLLER in every TDX CRATE?
2793A/aml
ANSWERS TO PROGRESS TEST WEEK 4 830928
1 of 1
LESSON: 4:5:1-3
CAMPS
1. 2.
2. WATCH DOG is connected by the CCB BUS to BSMX-S.
3. When MUX NO. on LOWER BUS hit DEVICE O.
4. Connect a VDU set to 30 Baud to TDX CONTROLLER
and type S and CR. No.
5. 1 2 2
LTUX-S No. in TDX CRATE CHANNEL No.
of LTUX-S.
6. Yes.
7. Through STI/TIA module.
8. IO odule in PU CRATE, which is the STI module.
9. By doing loop test. A loop is mounted on the
OPTO MODEM.
10. TDX CONTROLLER.
11. 1.8432 MHz.
12. It connects the device to TDX BUS.
13. The twisted pair are terminated by 100 ohm.
14. fter 16 scan of MUX TABLE, 3 scan sending out
test
frame and then if no respons the DEVICE is
skiped
on the MUX TABLE.
15. No, from DEVICE.
16. Two sets of twisted pair, each pair shieldet.
17. The DEVICE is asked to retransmit.
18. t indicates the start of a FRAME.
19. 4.
20. No. There is only 2 TDX CONTROLLERs, one per
TDX BUS.
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830617
TROUBLESOOTING 4:5:4-6 3 x 45
CAMPS…0f…
- Isolate and remedy TDX system faults at module
level
- During evaluation of the troubleshooting
Training room
GW, DI, EX
Training System
…0e… 2793A/ktd
MT/RST 4:1:1 830617
TDX SYSTEM THEORY L
1…0f…
General TDX: T̲elecommunication D̲ata E̲xchange or T̲ime
D̲ivision M̲ultiplexed.
H̲I̲G̲H̲ ̲S̲p̲e̲e̲d̲ ̲d̲i̲g̲i̲t̲a̲l̲ ̲l̲i̲k̲:
- Standard HDLC format
(H̲igh level d̲ata l̲ink c̲ontrol)
- incl. EDC protocol
(e̲rror d̲etection & c̲orrection)
T̲D̲X̲ ̲D̲E̲V̲I̲C̲E̲S̲:
- TDX controller (1 per. bus)
- Host I/F STI (suprabus TDX IF, 1 per
CPU)
TIA (T̲DX I̲/F A̲dptor, front
end processor for STI)
- LTUX-S (L̲ine t̲ermin. u̲nits)
TDX I/F to peripheral devices
BSM-X (B̲us S̲witch M̲odule)
OH 1 T̲D̲X̲ ̲B̲U̲S̲: (shielded twinlead-100 ohm-cables)
HBK: Fig. - LOWER bus: Data f̲r̲o̲m̲ controller
82.1.1-3 - UPPER bus: data T̲O̲ controller
SYMCRONIZA- F̲R̲O̲M̲ ̲C̲O̲N̲T̲R̲O̲L̲L̲E̲R̲:
TION Contineous data stream on lower bus:
1.8432 Mbits/sec divided into
6400 timeslots of 288 bits.
Black O̲n̲e̲ ̲T̲i̲m̲e̲s̲l̲o̲t̲:
Board
HDLC FRAME The HDLC fram length may differ from 200
bits (min) to 236 bits (max) due to "bitstuffing"
(For each five "1"'s an extra "0" is inserted).
This is used as an error detection feature.
One HDLC frame contains a total of 25 eight
bit bytes:
2 Flag bytes (0111110)
5 communication control bytes
16 data bytes
2 CRC bytes (c̲yclic r̲edundancy c̲heck)
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MT/RST 4:1:1 830617
TDX SYSTEM THEORY L
2…0f…
LOWER BUS OH 2 S̲T̲A̲R̲T̲ ̲F̲l̲a̲g̲ (1 byte)
FRAME FORMAT HBK: Fig. M̲U̲X̲ ̲N̲O̲ ̲(̲1̲ ̲b̲y̲t̲e̲)̲: The MUX NO is a devie NO,
8.2.1.2 which is generated in the controller - it
is taken from the MUX TABLE. It indicates
which device is a̲l̲l̲o̲w̲e̲d̲ ̲t̲o̲ ̲t̲r̲a̲n̲s̲m̲i̲t̲ ̲d̲a̲t̲a̲
̲o̲n̲ ̲t̲h̲e̲ ̲u̲p̲p̲e̲r̲ ̲b̲u̲s̲ in the next timeslot. All
devices "look" at the MUX NO, and the device
which recognizes it own NO (= device addr.)
starts transmission on the upper bus, when
having received bit 241 of the present timeslot.
C̲R̲-̲I̲D̲ (C̲hannel R̲outing-I̲dentification)
4 bytes:
D̲A̲T̲A̲ ̲T̲Y̲P̲E̲: Identifying a l̲o̲g̲i̲c̲a̲l̲ ̲c̲h̲a̲n̲n̲e̲l̲
̲N̲O̲ through which the data must be outed.
It does not necesseraly correlate with f.ex.
the (four) physical channels in a LTUX.
It merely points to a specific application.
H̲O̲S̲T̲/̲M̲O̲D̲E̲ ̲&̲ ̲D̲E̲V̲.̲ ̲N̲O̲: Describing the source
and destination devices - for the actual
frame.
Black H̲O̲S̲T̲/̲M̲O̲D̲E̲
board O DEST. IS CTRL
"D̲E̲V̲ ̲N̲O̲" 1
IS : DEST. IS 1 of 12 HOST's
SOURCE C
D Broadcast(NOT in CAMPS)
"DEV NO" E Source is a LTUX
IS F Sorce is a HOST
DEST.
C̲O̲M̲M̲U̲N̲I̲C̲A̲T̲I̲O̲N̲ ̲B̲Y̲T̲E̲: Used for information
in a packet transmission (Packet=one or more
frames between two open (logical) channels)
f.ex. First/last frame in a packet.
C̲O̲N̲T̲R̲O̲L̲ ̲B̲Y̲T̲E̲ (Frame seq no + no of data bytes
in frae)
S̲E̲Q̲ ̲N̲O̲: In a packet transmission the frames
are sequentially numbered (seq no.). If the
receiving device detects a jump in seq no's
the frame is discarded and retransmission
is requested.
N̲o̲ ̲o̲f̲ ̲d̲a̲t̲a̲ ̲b̲y̲t̲e̲s̲: The actual number of data
bytes (ma 16) in this frame.
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MT/RST 4:1:1 830617
TDX SYSTEM THEORY L
3…0f…
UPPER BUS OH 3 A̲B̲O̲R̲T̲ ̲B̲Y̲T̲E̲: Dummy byte; no mux no in upper
FRAME FORMAT bus frames because allthe frames are t̲o̲ ̲t̲h̲e̲
̲C̲T̲R̲L̲, and the MUX NO is generated in the
CTRL.
The rest of the frame is equal to the lower
bus frame format.
COMMUNICA- O̲N̲E̲ ̲C̲Y̲C̲L̲E̲: CTRL outputs a frame on the LOWER
TION bus. M̲U̲X̲ ̲N̲O̲ indicates the device which is
allowed o transmit on the upper bus.
All devices "look" at the M̲U̲X̲ ̲N̲O̲ and the
C̲R̲-̲I̲D̲. The device which recognizes its addr.
in the HOST/MODE OR DEV. NO fetches the frame.
Only the CTRL receives the frame on the upper
bus. If the HOST/MODE is [ the contrller
fetches the frame (This might be a request
for change of bandwidth from a device) and
transmits a dummy frame on the lower bus
(f.ex. diagnostic frame). Whenever the frame
is n̲o̲t̲ destined for the CTRL, a MUX NO is
inserted and the frame is - wthout any further
change - transmitted on the lower bus in
the next time slot.
DEVICE The MUX NO is fetched from the MUX table
in
POLLING the CTRL. A device allocated a higher
bandwidth on the bus is represented more
frequently in the table han lower bandwidth
devices.
…0e… 2793A/ktd
MT/RST 4:1:2-3 830617
TDX CONTROLLER L
1…0f…
CTRL - T̲i̲m̲i̲n̲g̲ ̲a̲n̲d̲ ̲s̲y̲n̲c̲r̲o̲n̲i̲z̲a̲t̲i̲o̲n̲ of the TDX bus
FUNCTIONS traffic. Frames received on the uper bus
are delayed one time slot, while the MUX
NO - taken from the MUX table - is inserted
in the frame. The overall TDX system clock
of 1.8432 mHz is supplied from an internal
crystal controlled ascillator.
- B̲a̲n̲d̲w̲i̲d̲t̲h̲ ̲a̲l̲l̲o̲c̲a̲t̲i̲o̲n̲: When a deviceis
increasing the amount of data to be transmitted
- via the TDX bus - it may request a higher
bandwidth allocated to it. The controller
determines where to place the DEV. NO.
in the MUX table, and returns ACK or NACK
(not acknowledged) to the requsting device.
- C̲o̲l̲l̲e̲c̲t̲ ̲d̲i̲a̲g̲n̲o̲s̲t̲i̲c̲ ̲i̲n̲f̲o̲s̲:
If a device have not been transmitteing
within 16 scans of the MUX table, the
CTRL sends a diagnostic frame to the device
- which must be answered. After three
diagnostics without an answer, the deviceis
perceived failing and then skipped in
the MUX table scan.
- W̲a̲t̲c̲h̲ ̲D̲o̲g̲ ̲C̲o̲m̲m̲u̲n̲i̲c̲a̲t̲i̲o̲n̲: The BSM-X (=CCA)
module in the crate which houses the CTRL
provides the communication with the WD.
* controller status to WD
* controller en/disable fro WD
BLOCK DIAGRAM OH 1 E̲N̲C̲O̲D̲E̲R̲/̲D̲E̲C̲O̲D̲E̲R̲: The DATA and clock are transmitted
simultaneously on the lower bus in a so-called
SPLD code (S̲elf Clocking Differential Split
Phase Code) which is like:
- polarity change at start of each bit cell
- polaity change in the middle of a bit
cell to indicate "0".
OH 2 The advantages of this coding are:
- Transmitter and receiver syncronized.
- Correct decoding in spite of cable delay.
OH 2 M̲P̲C̲C̲: (multi Protocol communication controller)
On receved frames the MPCC performs:
- Deletion of abort byte and flag bytes
- Deletion of zeroes from Bitstuffing
- CRC check
- Serial to parallel conversion of each
byte
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MT/RST 4:1:2-3 830617
TDX CONTROLLER L
2…0f…
When transmitting frames the MPCC performs:
- Parallet to serial conversion
- Zero generaion - Bit stuffing
- CRC generation
- Flag byte insertion
D̲A̲T̲A̲ ̲B̲U̲F̲F̲E̲R̲: First in first out registers
(FIFO's) which routes the received frame
to the CPU (MEMORY) when the frame is destined
for the CTRL, and back to the MPCC chen the
frame is or another device.
C̲T̲R̲L̲ ̲L̲O̲G̲I̲C̲: Controls the routing of the
frames in the data buffer, when the CR-ID
is received and the destination is detected.
Controls the MPCC functions.
C̲P̲U̲/̲M̲E̲M̲O̲R̲Y̲: A standard u processor system
which handles the MUX able and diagnostic
communication.
U̲S̲A̲R̲T̲: Performs the communication with the
BSM-X/Watch Dog via 8 (parallel) I/O lines.
Also a V24 port is included. This may be
used to communicate directly with the CTRL
from f.ex. a VDU, 300 baud.
INDICATORS P̲o̲w̲e̲r̲:̲ ̲(̲g̲r̲e̲e̲n̲)̲: ON indicates the presence of +5V, +/-
12V
T̲E̲S̲T̲ ̲(̲R̲E̲D̲)̲: ON when BUILT-In TEST (BIT) is
being executed upon on power up.
OFF when BIT has ended - without detecting
any errors.
R̲X̲ ̲S̲T̲ ̲(̲Y̲E̲L̲L̲O̲W̲)̲: ON indicates that the CTRL
has seleted upper bus 1. OFF indicates selection
of upper bus 2. In the CAMPS system only
one upper bus is connected to each controller;
this is connected to both of the receiver
channels, so the indicator is somehow needless
in this configuration.
T̲ ̲S̲T̲ ̲(̲R̲E̲D̲)̲: ON indicates that an error has
been detected in the transmitted SPL-D code.
OFF indicates error free generation of SPL-D
code.
F̲U̲S̲E̲ ̲(̲R̲E̲D̲)̲: ON indicates an error in the
power which is supplied to the two bus outlet
driver/receiver unit (placed outside the
controller).
OFF indicates that the 2X + 5V is OK.
