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Notes: CPS/TMA/016 (Week 11)
Names: »2986A «
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└─⟦9753ba4d5⟧ Bits:30006173 8" Wang WCS floppy, CR 0253A
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WangText
…00……00……00……00……00……00……00……00……00…1…0a…1…0c…1…0d…1…00…1
1…06…0…09…0…0c…0…0f…0…02…0…05…/…08…/…0b…/…0e…/…01…/ /…07….…0a….…0d….…00….
.…06…-…09…-…0c…-…0f…-…02…-…05…,…0a…,…01……86…1 …02… …02… …02… …02…
Instructor's Manual for
RST Course, Week 11
CPS/TMA/016
Line Item 8.2.4.2
Poul B]je Petersen
Kurt Nybroe-Nielsen
SHAPE (3), NCS (1), ORP, PBP, CL, JJD,
BSP, KJA, Conf.Mgmt.
ILS Train. Mgmt. 821105
Preliminary
821105
…02… CPS/TMA/016
…02… JJD/821105…02…
INSTRUCTORS MANUAL FOR RST COURSE,
WEEK 11 …02… CAMPS
821105 All Prelim. Issue of Document
…0e… 2986A/ktd
PBP/821105
TDX System Review 11:1:1 45 CAMPS…0f…
Describe the TDX concept
- communication cycles
- bus formats
- coding
No check
CAMPS Classroom
Lecture
OH, Whiteboard
…0e… 2986A/ktd
PBP/821105
TDX Bus Formats 11:1:2 45
CAMPS…0f…
Describe the TDX concept
- communication cycles
- bus formats
- coding
No check
CAMPS Classroom
Lecture
OH, Whiteboard
…0e… 2986A/ktd
PBP/821105
TDX Protocol 11:1:3 45
CAMPS…0f…
Describe the TDX protocol levels
No check
CAMPS Classroom
OH
…0e… 2986A/ktd
PBP/821105
TDX BW 11:1:4 45
CAMPS…0f…
Describe the TDX BW allocation principle
Describe the MUX tabe principle
Questions during lesson
CAMPS Classroom
L
…0e… 2986A/ktd
PBP/821105
TDX Controller 11:1:5 45
CAMPS…0f…
Describe the TDX controller at block
diagram level
No check
CAMPS Classroom
L
…0e… 2986A/ktd
PBP/821105
TDX Controller 11:1:6 45
CAMPS…0f…
Describe the TDX controller diagnostic
features
Describe the TDX Ctrl in/out signals
No check
CAMPS Classroom
L
…0e… 2986A/ktd
PBP/821105
TDX Controller 11:2:1 45
CAMPS…0f…
Use the on-line diagnostic features
in the TDX Ctrl
Practical exercises
Computerroom
GW
…0e… 2986A/ktd
PBP/821105
TDX Host I/F 11:2:2 45
CAMPS…0f…
Describe the TDX Host I/F in general
and the TIA module on block diagram level
No check
CAMPS Classroom
L
…0e… 2986A/ktd
PBP/821105
TDX Host I/F 11:2:3 45
CAMPS…0f…
Describe the TDX Host I/F,
TIA module on block diagram level
No check
CAMPS Classroom
L
OH
…0e… 2986A/ktd
PBP/821105
11:2:4
TDX LTUX-S 11:2:5 90
CAMPS…0f…
Describe the LTUX-S functions
Describe the LTUX-S PCB on block
diagram level
CAMPS Classroom
L
OH
…0e… 2986A/ktd
PBP/821105
11:2:6
TDX Devices 11:3:1/2/3 180
CAMPS…0f…
Describe the distinctive features of the
different TDX modules
Define the addressing ranges/possibilities
of the TDX modules
Theoretical and practical exercises
CAMPS Classroom
Computerroom
GW, H
…0e… 2986A/ktd
PBP/821105
11:3:4
??? 11:3:5 90
CAMPS…0f…
Describe the TDX CCA operation, the
BSMX at block diagram level
CAMPS Classroom
L
OH
…0e… 2986A/ktd
PBP/821105
TDX BSM-X 11:3:6 45
CAMPS…0f…
Use the on-line and off-line diagnostic
features of the BSM-X
Define the addressing range of the CCAs in
the TDX modules
Discussions
Practical exercises
CAMPS Classroom
Computerroom
GW, H
…0e… 2986A/ktd
PBP/821105
11:4:1
TDX cables/outlets 11:4:2 90
CAMPS…0f…
Describe the TDX cabling (screening,
grounding
Describe the TDX wall outlets (blockdiagram)
CAMPS Classroom
L
…0e… 2986A/ktd
PBP/821105
CTX crate 11:4:3 45
CAMPS…0f…
Describe the structure of the CTX crate
Describe the positioning of the
modules in the crate
CAMPS Classroom
Computerroom
L, DE
OH
…0e… 2986A/ktd
PBP/821105
CTX power supplies 11:4:4 45
CAMPS…0f…
Describe the characteristics and mounting
of the power supplies available in the
CTX crate
CAMPS Classroom
L
…0e… 2986A/ktd
PBP/821105
TDX Adaptors 11:4:5 45
CAMPS…0f…
Describe the low level adaptors and the
BP8 back plane
CAMPS Classroom
L
…0e… 2986A/ktd
PBP/821105
TDX Adaptors 11:4:6 45
CAMPS…0f…
Mount the straps on all L/L adapters
according to the V24/V28 signals available
Exercises
CAMPS Classroom
GW
…0e… 2986A/ktd
PBP/821105
WATCHDOG 11:5:1 45
CAMPS…0f…
Describe the watchdog functions
Describe the PU monitoring and control
Describe the CU monitoring and control
Describe the TU monitoring and control
CAMPS Classroom
L
…0e… 2986A/ktd
PBP/821105
WD Unit 11:5:2 45
CAMPS…0f…
Describe the WD unit
Describe the crate assy
Describe the cabling
Describe the P.S.
CAMPS Classroom
L
…0e… 2986A/ktd
PBP/821105
WPU Unit 11:5:3 45
CAMPS…0f…
Describe the WD processor unit
functions
CAMPS Classroom
L
…0e… 2986A/ktd
PBP/821105
WCA 11:5:4 45
CAMPS…0f…
Describe the WCA functions and the module at
block diagram level
CAMPS Classroom
L
OH
…0e… 2986A/ktd
PBP/821105
CCBA 11:5:5 45
CAMPS…0f…
Describe the configuration control bus
adaptor functions and module at block
diagram level
CAMPS Classroom
L
…0e… 2986A/ktd
PBP/821105
CCB 11:5:6 45
CAMPS…0f…
Describe the configuration control bus:
- communication, speed
- data format
- connections
- addressing
CAMPS Classroom
L
…0e… 2986A/ktd
11:1:1
PBP/821105
TDX SYSTEM REVIEW L …0f…
General TDX: T̲elecommunication D̲ata Ex̲change (or)
T̲ime D̲ivision Multiplex̲ed
H̲i̲g̲h̲ ̲S̲p̲e̲e̲d̲ ̲D̲i̲g̲i̲t̲a̲l̲ ̲L̲i̲n̲k̲:̲
- Standard HDLC format
(H̲igh level d̲ata l̲ink c̲ontrol)
- Incl EDC protocol
(E̲rror d̲etection and c̲orrection)
T̲D̲X̲ ̲D̲e̲v̲i̲c̲e̲s̲:
- TDX controller (1 per bus)
- Host I/F/STI (S̲uprabus T̲DX I̲/F, 1 per
PU)
Host I/F adaptor/TIA (T̲DX I̲/F A̲daptor)
Front End processor for STI
- LTUX-S (line term. units)
TDX I/F to peripherals
- BSM-X (B̲us S̲witch M̲odule)
B̲U̲S̲: (shielded twinlead cables)
OH - LOWER BUS (data f̲r̲o̲m̲ contoller)
(princip) - UPPER BUS (data t̲o̲ controller)
Synchronization F̲R̲O̲M̲ ̲C̲O̲N̲T̲R̲O̲L̲L̲E̲R̲:
Continous data stream on lower bus. Bit rate:
1.8432 mbits/sec divided into 6400 timeslots
of 288 bits
White-
board 1̲ ̲T̲I̲M̲E̲S̲L̲O̲T̲
Her inds`ttes tegning
HDLC frame: 200-236 bits
(bitstuffing)
HDLC frame - bit 240: all "ONES"
…0e… 2986A/ktd
11:1:1 PBP/821105
TDX SYSTEM REVIEW L …0f…
Communication O̲N̲E̲ ̲C̲Y̲C̲L̲E̲: CTRL outputs a frame on the LOWER
BUS. M̲U̲X̲ ̲N̲O̲ indicates which device on the
bus is allowed to t̲r̲a̲n̲s̲m̲i̲t̲ data on the upper
bus. D̲E̲V̲ ̲N̲O̲ indicates which device on the
bus must fetch the data in the frame.
All devices read both MUX NO AND DEV NO.
The device which recognizes the MUX NO starts
transmission on upper bus when having received
bit 241 of the frame. Only CTRL receives
the frame on the upper bus. After delay of
one timeslot, a new frame is created conaining
though the same destination and data as received
on the upper bus.
Device Polling MUX NO is fetched from the MUX table in
the CTRL. A device allocated higher bandwidth
on the bus is represented more frequently
in the cable than lower bandwidth devices.
Coding SPL-D Code:
(S̲elf Clocking Differential S̲plit Phase Code)
Data and clock transmitted simultaniously
on the same set of wires; advantages:
- Transmitter and receiver synchronized
- Correct decoding in spite of cable delay
Data coding like:
OH (SPLD) - Polarity change at start of each bit cell
White- - Polarity change in the middle of a bit
board cell to indicate "ZERO"
Exercise HO 1) Encode the clock and data to a SPL-D code
2) Decode the SPL-D code to get the data
bits
…0e… 2986A/ktd
11:1:2 PBP/821105
TDX BUS FORMATS L …0f…
Frame Format White- One HDLC frame contains a total of 25
board 8bit bytes.
For synchronization, the first and the last
byte are always flag bytes (01111110), 5
bytes are for communication control, 16 bytes
are the data to be transferred and 2 bytes
are for transmission check (CRC: Cyclic Redundancy
Check)
Bitstuffing Bitstuffing between the two flag bytes makes
the frame length variable. For each five
"1" bytes, an extra "0" is inserted.
Question What is the max and min length of a frame?
Min: All Zeroes - 25 bytes x 8 = 200 bits
Max: 23 bytes x 8 = 184 - all ones -
1̲8̲4̲
5 …0e…+200 = 236…0f…
Lower bus OH 1 CR-ID (Channel Routing Identification) 4
White- bytes:
board
Textbook D̲A̲T̲A̲ ̲T̲Y̲P̲E̲ ̲(CHANNEL NO) (4 bits)
Vol 1,
Indx 5 0 - Channel set up; open and close TDC
channels
1 - Channels for datagrams; e.g. diagnostics
1 of 14 channels in device (LTUX-S only 10
channels). These are logical channels, not
necessarity correlating with physical channels.
H̲O̲S̲T̲/̲M̲O̲D̲E̲
#0 - destination is CTRL
"DEV NO" 1
IS . - destination is 1 of 12 hosts
SOURCE C
D - broadcast mode (not CAMPS)
"DEV NO" E - source is a device (LTUX)
IS F - source is a HOST
DESTIN
D̲E̲V̲I̲C̲E̲ ̲N̲O̲ (see HOST/MODE above)
MODE 0-D: DEV NO is source
MODE E, F: DEV NO is destination…86…1
…02… …02… …02… …02… …02… …02…
…0e… 2986A/ktd
11:1:2 PBP/821105
TDX BUS FORMATS L …0f…
Lower Bus OH 2 C̲O̲M̲M̲U̲N̲I̲C̲A̲T̲I̲O̲N̲ ̲B̲Y̲T̲E̲:̲
For info in a packet transmission (data-packet
= datastream - one or more frames between
two open channels (data type 2-14)) e.g.
first/last frame in a packet, input accept,
etc
C̲O̲N̲T̲R̲O̲L̲ ̲B̲Y̲T̲E̲:̲ (seq. No. + No of data bytes
in frame)
3 bits: seq. No. - frames in a packet sequentially
numbered. Used for error detection and correction:
A CRC error in a frame results in discarding
this frame at receival. The resulting jump
in seq. No. indicates that retransmission
of the missing frame must be requested.
5 bits: Actual No. of data bytes in the frame.
Upper Bus OH 3 Same format as lower bus except:
No MUX number used because the traffic on
this bus is always t̲o̲ the controller. The
FLAG byte inserted just before CR-ID. An
abort Byte (All "1"s) inserted at start to
fill up the frame.
NOTE: Transmission on upper bus STOPS after
last flag - No trailing ONES.
…0e… 2986A/ktd
11:1:5 PBP/821105
TDX CONTROLLER L …0f…
Functions T̲i̲m̲i̲n̲g̲ ̲a̲n̲d̲ ̲s̲y̲n̲c̲h̲r̲o̲n̲i̲z̲a̲t̲i̲o̲n̲ of the TDX bus
traffic. Frames received on upper bus are
delayed one time slot while a MUX NO taken
from the MUX table (BW) is inserted in the
frame. Clock pulses for the bus are applied
on the lower bus.
C̲o̲l̲l̲e̲c̲t̲ ̲d̲i̲a̲g̲n̲o̲s̲t̲i̲c̲ ̲i̲n̲f̲o̲s̲:̲ If a device have
not been transmitting within 16 complete
scans of the MUX table, a diagnostic frame
is sent out (cycle steeling or a dummy frame).
After 3 diagnostics without an answer, the
device is perceived failing and then skipped
in the MUX SCAN; status "failed" is reported
to the watchdog.
S̲t̲a̲t̲u̲s̲ ̲R̲e̲p̲o̲r̲t̲ Status of the controller itself
(PWR, Selftest, diagn. etc) and all devices
(Ready/failed) can be output upon request
from the watchdog or an external (V24) device.
Block Diagram OH (CRTL) D̲r̲i̲v̲e̲r̲s̲/̲R̲e̲c̲e̲i̲v̲e̲r̲s̲:̲ Buffering of the TDX signals
to/from the TDX outlet. RX channel select
(= upper bus select) from CTRL-CPU. TX channel
select (= lower bus select) from watchdog.
S̲P̲L̲-̲D̲ ̲e̲n̲/̲d̲e̲c̲o̲d̲e̲r̲s̲:̲ Clock is supplied from
internal 1.8432 MHz crystal controlled OSC.
M̲P̲C̲C̲ ̲(Multi protocol commun. controller)
On received frames the abort and flag bytes
are deleted. Zero deletion (bit stuffing)
and CRC check is performed. The serial input
is converted to 8 bit bytes at the output.
…0e… 2986A/ktd
11:1:5 PBP/821105
TDX CONTROLLER L …0f…
Block diagram OH T̲h̲e̲ ̲s̲t̲a̲t̲e̲ ̲c̲o̲n̲t̲r̲o̲l̲l̲e̲r̲ (RX part) loads all
the following bytes into F̲I̲F̲O̲ ̲1̲ The two first
bytes (CR-ID) are also loaded into the
H̲I̲T̲ ̲d̲e̲t̲e̲c̲t̲o̲r̲. If a HIT is declared (HOST/
MODE = 0), the frame is destined for the
controller and the incoming bytes are loaded
into F̲I̲F̲O̲ ̲2̲ from where they can be accessed
by the C̲P̲U̲.
A CRC errorfree frame which is not for the
CRTL, is transferred to F̲I̲F̲O̲ ̲3̲ from where
it is transmitted in the next timeslot.
If a CRC error is detected, the entire frame
is discarded and the vacant timeslot is filled
with CPU data from F̲I̲F̲O̲ ̲4̲ or just Zeroes
supplied from the S̲U̲B̲ ̲S̲T̲A̲T̲E̲ ̲C̲T̲R̲L̲ (dummy frame).
During transmission, the MPCC is controlled
from the TX part of the S̲T̲A̲T̲E̲ ̲C̲T̲R̲L̲: MPCC
generates START flag, D̲E̲V̲ ̲N̲O̲ ̲R̲E̲G̲ supplies
the MUX NO, F̲I̲F̲O̲ ̲3̲ is unloaded byte by byte,
the MPCC performs par/ser conversion, CRC
generation, bit stuffing, and inserts STOP
flag. The B̲I̲T̲ ̲C̲O̲U̲N̲T̲E̲R̲ signals to the S̲T̲A̲T̲E̲
̲C̲T̲R̲L̲ to transmit zeroes between bit 240-248.
and ONE's up to bit 288.
The RX and TX part of the MPCC and the STATE
CTRL work simultaneously and the delay of
one timeslot for a frame to pass through
the CTRL is due to the FIFO load/unload.
The CPU part of the CTRL performs the initial
selftesting, the MUX table handling, the
diagnostic routines and the communicaton
with the V24 port/watchdog.
…0e… 2986A/ktd
11:1:6 PBP/821105
TDX CTRL L …0f…
Indicators White- P̲O̲W̲E̲R̲ (green): ON indicates the presence
of
board +/-12V, +5V
T̲E̲S̲T̲ (red): OFF indicates successful pass
of internal diagnostic routines
R̲X̲ ̲S̲T̲ (yellow): ON indicates that the CTRL
has selected upper bus 1. Off indicates selection
of bus 2.
T̲X̲ ̲S̲T̲ (red): OFF indicates errorfree generation
of SPL-D code. ON indicates loss of transmit
data.
F̲U̲S̲E̲ (red): OFF indicates that 2 x +5V power
is supplied to the TDX outlet drivers/receivers.
ON indicates loss of power (fuse for VCC
1 or/and VCC 2).
Connectors B̲N̲C̲ ̲c̲o̲n̲n̲e̲c̲t̲o̲r̲: External clock. Not used in
CAMPS (strap 16 in pos A).
U̲P̲P̲E̲R̲ ̲C̲A̲N̲N̲O̲N̲ ̲c̲o̲n̲n̲e̲c̲t̲o̲r̲:̲ TDX outlet box connection
4,5 Differential
2,3 …0e…Disable transmitters…0f… Active "H"
6,7
8,9 …0e…Transmit data (differential)…0f…
12,13
10,11 …0e…Receive data (differential)…0f…
22-25: VCC 1 Power for receive logic
1,14-16: VCC 2 Power for transmitter logic
17-21: Ground
…0e… 2986A/ktd
11:1:6 PBP/821105
TDX CTRL L …0f…
Connectors CAMPS SDS L̲O̲W̲E̲R̲ ̲C̲A̲N̲N̲O̲N̲ ̲c̲o̲n̲n̲e̲c̲t̲o̲r̲:̲
5.3.4.1 BSM connection (V24 + watchdog communication)
2 C103 TDX DATA Data (IN)
3 C104 RX DATA Data (OUT)
4 C105 RTS Request to send (OUT)
5 C106 CTS Clear to send (IN)
V24 6 C107 DSR Data set ready (IN)
7 GROUND
8 C109 DCD Data carrier detect (IN)
15 C113 TC TX clock (OUT)
20 C108 DTR Data Termin. ready (OUT)
10 COMO2 (command 2) OUT "H" indicates
CTRL ope-
rative
11 COMI2 (command 1) IN "L": Enable
CTRL
12 BS (Busselect) IN "L": select
lower bus
1
"H": select
lower bus
2
13 TX (TX status) OUT "H" indicates
TX OK = TX
ST
TO indicator
BSM
(WD) 22 COMO1 (command 1) OUT "L" indicates
CTRL OK
=
TEST
indicator
23 COMI 1 (command 1) IN Not used
in
CAMPS
24 FS (Fuse status) OUT "H"indicates
wall outlet
power OK
=
Fuse
indicator
25 RS (RX status) OUT "L" indicates
upper bus
1
selected
= RX
ST indicator
…0e… 2986A/ktd
11:1:6 PBP/821105
TDX CTRL L …0f…
Communication V̲2̲4̲ ̲c̲o̲m̲m̲u̲n̲i̲c̲a̲t̲i̲o̲n̲:̲
(ASCII, 300 baud)
C̲o̲m̲m̲a̲n̲d̲s̲
S̲tatus Request the status of all
devices stated in the MUX
table
C̲lear Clear the diganostic table
U̲pper bus Request info about upper
bus connection
B̲us (1)(2) Select upper bus
F̲rames Request info about bus traffic
(half the number of received
or swapped frames in a scan
cycle)…86…1 …02…
…02… …02… …02… …02…
…02… …02…
…0e… 2986A/ktd
11:2:1 PBP/821105
TDX CTRL GW + P …0f…
Group Define a method for On-line check of the
TDX bus traffic, i.e. direct communication
with the controller regardless of the watchdog
(and maint. position).
Practice 1) Realize the above defined method.
2) Clear diagnostic table and read status
for BUS and DEVICES
Question 3) Estimate the time before a change in status
is reported when a device fails
Practice 4) Check the above by switching off one or
more devices.
5) Reestablish the system
…0e… 2986A/ktd
11:2:2 PBP/821105
TDX HOST L …0f…
INTRO The TDX HOST I/F is a High Bandwidth device,
interfacing the CR80 to the TDX subsystem.
Two modules constitute the HOST I/F:
The STI (S̲uprabus T̲DX I̲/F, no suprabus in
CAMPS) performs the CR80 communication via
DMA routines and serves the packet level
(levels 2 and 3) of the TDX protocol.
OH (PRO) The TIA (T̲DX I̲/F A̲daptor) is the front end
processor module to the TDX bus. It serves
the frame level (level 1) of the TDX protocol.
OH (HOST) The STI and the TIA are interconnected via
a 64 pole bus cable - the HI Bus. The three
CPUs on the STI may access the bus as MASTERS,
i.e. is able to drive the address lines.
The TIA CPU accesses as SLAVE, i.e. no address
source capabilities.
STI functions The main blocks on the STI board are:
H̲I̲ ̲b̲u̲s̲ ̲a̲r̲b̲i̲t̲r̲a̲t̲o̲r̲ which controls the traffic
on the HI BUS (Acknowledge upon bus requests).
D̲u̲a̲l̲ ̲p̲r̲o̲c̲e̲s̲s̲o̲r̲s̲ (IN/OUTgoing procs) which
serves the TDX packet protocol. The ingoing
proc moves data from the TIA to the CR80
by demultiplexing the traffic coming from
the TDX system into logical channels. The
outgoing proc moves data from the CR80 to
the TIA by scanning the logical channels
and multiplexing the data into one single
stream.
C̲e̲n̲t̲r̲a̲l̲ ̲R̲A̲M̲. 32 Kbyte dynamic RAM accessible
by HI BUS MASTERS.
M̲A̲I̲N̲ ̲B̲U̲S̲ ̲I̲/̲F̲ is the link between the CR80
channel bus and the HI Bus. It interfaces
the CR80 to the central RAM and provides
the DMA transfer to/from the CR80 memory.
Furthr functons are interrupt handling, power
supervision, and status report (display).
…0e… 2986A/ktd
11:2:2 PBP/821105
TDX HOST L …0f…
STI Block OH (ARB) H̲I̲ ̲B̲U̲S̲ ̲A̲R̲B̲I̲T̲R̲A̲T̲O̲R̲:̲ When a MASTER wants
Diagram access to the HI BUS, it issues an ARQ (access
request) to the abitrator. When the request
is granted, a BAG (bus access granted) is
returned. Now the requesting module can source
the address lines. The priority of the bus
grants is like:
Priority 0: MBIF (CR80 to central RAM access)
Priority 1: MBIF (IN/OUT procs - CR80 DMA
access)
Priority 2: IN/OUT procs access
STI Block OH (DP) D̲U̲A̲L̲ ̲P̲R̲O̲C̲E̲S̲S̲O̲R̲S̲:̲ Hardware wise the ingoing
and outgoing processors are equal. The CPU
is a Zilog Z80 processor and it communicates
via a standard Z80 microbus. The timer/interrupt
controller provides the interrupt routines
to the CPU, e.g.:
- Interrupt from CR80 to the micro process.
- Interrupt when time out on HI BUS
- Interrupt when parity error detected in
central RAM
The firmware (program) is resident in 16K
(2x8K) PROM adrss: [[[[ - 1FFF
2[[[ - 3FFF
Available RAM is 2K (1x2K) adrss: 5[[[ -
57FF.
The address decoder which is a PROM selects
the internal memory (PROM, RAM) or enables
the HI BUS I/F to source the addr. lines
of the HI BUS for external memory access
(central RAM) upon request from the CPU
(MRQ).
The HI BUS interface holds the addr drivers
and receivers for the HI BUS, and the logic
for performing the handshake with the arbitrator
when initiated from the CPU.
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11:2:2 PBP/821105
TDX HOST L …0f…
STI Block C̲E̲N̲T̲R̲A̲L̲ ̲R̲A̲M̲:̲ The central RAM is a 32K byte
Diagram memory in the address area 8[[[ - FFFF. Accessed
from the CR80 for load and change of protocol
parameters (IN/OUT scan tables, channel desciptors
and buffers) and from the IN/OUTgoing process
for utilize of these.
The RAM is a dual byte slave, which means
that an access for read is always to an even
address followed by an access to the ODD
addr one higher, and a write access from
the IN/OUT procs to an ODD addr is followed
by an access to the even addr one lower.
The RAM holds its own counter and refresh
logic. During bus access, the refresh cycle
is inhibited and during a refresh cycle,
a bus access is delayed.
Max delay = 0.5 microsec (refresh time)
Min access time = 875 microsec (double byte).
Max access time = 1375 - -
White
Board
Her inds`ttes tegning
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11:2:2 PBP/821105
TDX HOST L …0f…
MBIF Block OH (MBIF) The MBIF functions are controlled by a
Diagram processor and the data is transferred via
an 8 bit wide internal data bus. The "heart"
of the MBIF is a bit slice processor composed
of 2 x 4 bit ALUs, a 72 bit microprogram
(ROMs) with associated microprogram sequencer
and status multiplexer for microprogram control.
CR80 Access When the HOST is addressed from the CR80
on the main bus, the address bits AD[-5,
AD18, AD19 are compared with the switchsetting
in the DIL switch S2 (CR80 I/O module No).
(S2) If equal a CR request is sent to the processor
where the microsequencer makes a unconditional
jump to a subroutine for CR service, such
as requesting CR80 access to the HI BUS (ARQ
MBI) and routing the data between the main
bus and the memory addressed on the HI BUS
(MASTER function).
CR80 Also the setting of S2 is used for HOST
interrupt interrupt request to the CR80 (SW6, 7, 8
set
system priority P0, P1, P2 and SW4 - SW0 is DEV
NO.)
DMA access When the CR80 has set up DMA descriptors
in the central RAM, the IN/OUTgoing processors
are able to initiate the DMA transfer to/from
the FE RAM (TIA) from/to the CR80 memory
via the MBIF. The DMA sequence is initiated
by INT request from IN/OUT procs. The status
MUX makes the sequencer branch to a DMA micro
subroutine. A request for HI BUS DMA access
(ARQ DMA) is issued to the HI BUS arbitrator
and the DMA buffers are enabled for data
transfer. Also the controller for DMA access
to the CR80 is activated.
TDX DEV NO The TDX device No of the HOST which is set
up
(S1) in DIL switch S2 is read and output to the
FE (TIA) via the HI BUS by the OUTgoing processor.
However, the CR80 is able to request the
OUTgoing processor to change the HOST NO.
Clock The clocks for the HI BUS and for internal
use are derived from the main bus clocks
[1 and [4 (1 MHz, 8 MHz). 4 MHz is generated
by dividing the 8 MHz by 2.
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11:2:2 PBP/821105
TDX HOST L …0f…
Clear & Pwr Det A clear signal used overall in the MBIF
(except microprogram) is generated when:
1. Master clear (MC) from the main bus
2. The microprogram issues clear (PC)
3. After power failure (PF)
The microprogram receives only clear when
MC is active.
The POWER LED is turned ON when:
1 Power OK from the power detector (+/-12V
+5V)
2 Power OK from the HI BUS (PW1)
The power failure (PF) is reset by PC or
MC.
Status display The status display circuit outputs the
signals to turn on the LEDs on the front
panel.
The ON condition is:
DISPLAY TEST: When TEST is active on the HI BUS
IN CAMPS: ??
BUSY: When DMA transfer to/from the HOST
IS active on the main bus
HI DMA: When DMA transfer to/from the MBIF
is active on the HI BUS
P. ERROR: When power is back after a power
failure (PF)
C. ERROR: When time out or parity error on
the MAIN BUS during DMA transfer
M. ERROR When ERROR is active on the HI
BUS. This can be time outs or central
RAM parity error.
IN CAMPS: ??
RX STATE: When RX status is active on the
HI BUS.
IN CAMPS: ??
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11:2:3 PBP/821105
TDX HOST (TIA) L …0f…
TIA Functions The front end module, the TIA, is an intelligent
s̲l̲a̲v̲e̲ on the HI BUS. It performs the TDX
transmit, receive and frame level functions.
The data exchange to and from the STI goes
through a ON-board buffer memory (shared
RAM) accessible by the TIA processor itself
and HI BUS masters.
TIA Block OH (TIA) D̲R̲ ̲&̲ ̲R̲C̲: Buffer the SPL-D coded signals to/
Diagram from the TDX outlet. The two RX channels
are always enabled by the TX enable from
the STATE CTRL.
S̲P̲L̲-̲D̲ ̲E̲N̲/̲D̲E̲C̲O̲D̲E̲R̲S̲:̲ In the RX part, the clock
and data are separated. The derived clock
is used in the TX part to encode the new
data. If a dualized bus is connected, the
clock continuously received on both RX channels
can be supervised (SR4 in Pos A). If one
or both are missing, an ERROR status can
be read by the CPU, and the active RX status
on the HI BUS is cancelled (RS state indicator
on the STI front panel).
The RS channel to be decoded is automatically
selected by means of one shots sensing the
incoming SPL-D code.
P̲o̲w̲e̲r̲ ̲d̲e̲t̲e̲c̲t̲o̲r̲:̲ The absence of VCC (+5V)
or -12V will cause the power LED on the front
panel of both the TIA and the STI to turn
OFF. It is signalled to the STI via the PW
line on the HI BUS. Also the power (2 x +5V)
to the TDX outlet is supervised.
M̲P̲C̲C̲ (Multi protocol comm. controller)
Receiver part: On received frames, the flag
bytes are deleted, zero deletion (Bit stuffing)
and CRC calculation is performed. The serial
input is converted to 8 bit bytes at the
output.
Transmitter part: Parallel to serial conversion,
flag and abort insertion, zero insertion
(Bit stuffing) and CRC generation.
…86…1 …02… …02… …02… …02…
…02… …02…
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11:2:3 PBP/821105
TDX HOST (TIA) L …0f…
TIA Block S̲T̲A̲T̲E̲ ̲C̲O̲N̲T̲R̲O̲L̲L̲E̲R̲. The state controller
Diagram reflects at any time the present state of
frames being received/transmitted and is
as such the logic which controls the traffic
to and from the TDX bus. While a frame is
being received, the MUX and DEV NOs are compared
to the HI BUS signals H[-3 (HOST NO output
from the STI), and the calculated CRC is
checked on the last received byte. All bytes
received are placed in FIFO1.
R̲X̲: If the HOST/MODE NO equals the H[-3 signal
and no CRC error is detected, the state CTRL
enables transfer from FIFO1 to FIFO2. The
frame is transferred when the DMA has finished
reading FIFO2. When the transfer is finished,
the CPU is interrupted to initiate the DMA
transfer of the data from the shared RAM.
T̲X̲: One per 156 microsecs, the CPU polls
FIFO3 to see if it has been emptied. If so,
and if data is available in the shared RAM,
a DMA transfer of a new frame from the shared
RAM to FIFO3 is performed.
When a new frame has been transferred, this
is signalled to the state CRTL by the CPU
and FIFO3. After bit 241 of the next received
frame with the MUX NO equal to H[-3 and without
CRC error, the transmission of the bytes
is performed.
SHARED RAM As the RAM memory can be accessed from both
the onboard DMA and CPU via the microbus,
and from the masters on the HI BUS, an arbitrator
is implemented to control the address and
data buffers between the memory and the buffers.
When addressed from the HI BUS, the three
MSB on the address line are decoded by comparing
with a DIL switch setting. The ingoing and
outgoing processors on the STI board address
the shared RAM in the range #6000 - #7FFF.
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11:2:3 PBP/821105
TDX HOST (TIA) L …0f…
INDICATORS PWR A greem P̲W̲R̲ LED on the front panel indicates,
when ON, the presence of VCC (+5V) and -12V.
TEST When the TIA is initialized (Power up), a
red TEST LED on the front panel is turned
ON. It remains ON until the following conditions
have been fulfilled:
- Self test of PROM and RAM completed and
no errors detected
- Communication with CR80 OK (STI/TIA -
CR80 handshaking)
- The TIA has received a test frame sourced
from and destined for itself. Such a test
frame will be continuously transmitted
every 2 secs until successful reception.
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11:2:4
11:2:5 PBP/821105
TDX LTUX-S L …0f…
LTUX-S functions The LTUX-S is a standard I/F module between
the TDX bus and the medium to low speed peripherals.
It handles all 3 levels of the TDX protocol
(frame, packet, application) and provides
up to 10 logical channels for communication
to the application level. The packet and
application levels are serviced by means
of tn onboard microcomputer.
The LTUX communicates via four V24 I/O ports
connected to a common LTUX motherboard. The
TDX bus connection is via the BSM module
where the bus switching is performed when
necessary.
LTUS-S Block D̲R̲ ̲&̲ ̲R̲C̲:̲ Buffer the SPL-D coded signals to/
Diagram from the BSM. The RX channel to be decoded
is automatically selected by means of one
shots sensing the incoming SPL-D code.
S̲P̲L̲-̲D̲ ̲E̲N̲/̲D̲E̲C̲O̲D̲E̲R̲S̲:̲ In the RX part, the data
and clock is separated. The derived clock
is used in the TX part to encode the new
data. The continuously received clock is
being watched (Strap SR26 in Pos B, only
channel 1). If it is missing, the ERROR LED
(red) on the front panel is turned ON.
Block Diagram OH (LTUX) P̲W̲R̲ ̲D̲E̲T̲. The +/- 12V and +5V (VCC) are being
watched. If any fails, the PWR LED (green)
on the front panel is turned OFF.
M̲P̲C̲C̲ (multi protocol communication controller)
R̲e̲c̲e̲i̲v̲e̲r̲ ̲p̲a̲r̲t̲:̲ On frames received, the flag
bytes are deleted, zero deletion (bit stuffing)
and CRC calculation is performed. The serial
input is converted to 8 bit bytes at the
output.
T̲r̲a̲n̲s̲m̲i̲t̲t̲e̲r̲ ̲p̲a̲r̲t̲: Parallel to serial conversion,
flag and abort byute insertion, zero insertion
(bit stuffing) and CRC generation.
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11:2:4
11:2:5 PBP/821105
TDX LTUX-S L …0f…
Block Diagram S̲T̲A̲T̲E̲ ̲C̲O̲N̲T̲R̲O̲L̲L̲E̲R̲:̲ The state controller
reflects at any time the present state
of frames being received/transmitted and
is as such the logic which controls the
traffic to and from the BSM/TDX BUS. While
a frame is being received, the MUX and
DEV NO bytes are compared to the setting
of an 8 bit DIL switch and the HOST/MODE
byte and the calculated CRC are checked
by addressing a PROM.
R̲E̲C̲: When the HOST/MODE byte contains E or
F, the DEV NO byte will contain the destination
address.
OH If the PROM detects E or F and the DEV NO
is equal to the switch setting and if no
CRC error is detected, then the state controller
enables transfer from FIFO1 to FIFO2. The
transfer is performed when the CPU signals
that reading of FIFO2 has been finished.
After the new loading of FIFO2, the CPU is
interrupted to move the data to the memory.
T̲R̲: One per 156 microsecs, the CPU polls
FIFO3 to see if it has been emptied. If so,
and if outgoing data is available in memory,
the CPU moves new data to FIFI3. When this
transfer is finished and bit 241 of the frame
next received without CRC error and with
the MUX NO equal to the switch setting is
reached, then the transmission of the FIFO3
frame is initiated.
S̲I̲O̲:̲ The communication with the peripherals
(adaptors) goes through two dual ported SIOs
and 4 sets of V24/V28 line receivers/drivers.
The baud rate for each SIO is controlled
from the CTC timer and the information of
baud rate setting is loaded into the CTC
when specified from the operator's console.
Total baud rate for a LTUX in the CAMPS system
is 9600 b/s. E.g. 4 x VDUs connected to one
LTUX must share this baud rate so that each
channel operates on max 2400 baud; if only
one channel is used, this may have 9600 baud.
When receiving and transmitting characters,
the SIOs interrupt the CPU via the CTC interrupt
controller. 4 swtiches on the front panel
are en/disabling the I/O channels, and LEDS
/yellow) indicate an active channel when
ON.
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11:2:6
11:3:1/3 PBP/821105
TDX DEVICES GW …0f…
Group Work 1 Discuss and explain (written) the following
items:
LTUX/TIA HO (1) 1 Divergencies between the LTUX-S and the
TIA modules
CTRL 2 Divergencies between the LTUX/TIA and
the TDX CONTROLLER modules
Group Work 2 HO (2) 1 Discuss addressing possibilities of the
TDX modules
2 Check the above found values by exercise
on the system
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11:3:4
11:3:5 PBP/821105
TDX BSM l …0f…
BSM Functions OH BSM (BUS Switch Module) functions:
(FUNC)
- Transfers the SPL-D coded TDX data to/from
two TDX bus outlets to/from the LTUX-Ss
in one crate.
- Peforms bus switching between two TDX
busses upon remote request via the configuration
control bus from the watchdog processor
or upon local request from a manual operated
switch on the front panel.
- Provides the communication between the
watchdog and the TDX controller via the
CCB (Bus).
- Monitors the CTX crate voltages (+/-12V,
+5V), the TDX outlet connections and supply
voltages (VVC1, VCC2) and reports back
to the watchdog when requested.
Operation Communication with the WD is performed in
7 bit words (C6-C[) with a speed of 4800
baud via the CCB bus. The WD may issue commands
to the TDX controller (en/disable rec., busselect,
status request) and to the BSM (bus switching,
A/D conversion, data requests).
Three words are used to access the BSM:
OH (CW) 1 P̲O̲I̲N̲T̲E̲R̲ The bits C4-C] define the use
of the following data words:
C1, C[ = [[: Status request from BSM
C1, C[ = [1: Additional inputs data request
from BSM
C1, C[ = 1[: A/D converter data request
from BSM (power monitoring)
C1, C[ = 11: A/D converter data request
from BSM (power monitoring)
+ status request from CTRL
C2 = 1: BUS select command to CTRL
and switch command to BSM
C3 = 1: Additional OUTPUT command
to BSM
C4 = 1: Command for A/D conversion
2. D̲A̲T̲A̲ ̲W̲O̲R̲D̲ contains the actual command
bits (select bus N̲O̲, A/D input N̲O̲, etc)
3. S̲T̲R̲O̲B̲E̲ C6=1: Loads the data word into
the "pointed" register
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11:3:4
11:3:5 PBP/821105
BSM-X l …0f…
BSM Block OH D̲R̲/̲R̲E̲C̲ RS 422 is differential line drivers/
Diagram (B.D.) receivers to/from the TDX outlet to/from
the
(TDX BUS bus switch logic.
section) The two rec. signals are OR'ed together so
that the LTUX can always receive on channel
1 regardless of the bus actually selected.
The drivers transfer both he outlet enable
(TX-EN) and the TX data to the selected bus
outlet.
The DR/REC to the CTX bus buffer only the
TX-EN, TX DAT, REC1, REC2 signals.
B̲U̲S̲ ̲S̲W̲I̲T̲C̲H̲:̲ The bus switch logic controls
the enable signals to the RS 422 TDX drivers/receivers.
A switch on the front panel selects the switching
mode:
OFF: Bus switching disabled
AUTO and MAIN LEDs are OFF
AUTO: Bus switching is controlled from
the config. bus I/F (originally
from the watchdog)
AUTO LEDs ON, MAN LED is OFF
MAN: BUS is switched by another switch
on the front panel (BUS1/BUS2)
MAN LED is ON, AUTO LED is OFF
MANUAL mode switch on front panel:
BUS1: Switches to TDX bus 1 if the outlet
is connected and the power V1 (VCC1)
is valid (BUS 1 LED ON).
BUS2: Switches to tDX bus 2 if the outlet
is connected and the power V2 (VCC2)
is valid (BUS 2 LED ON).
N̲O̲T̲E̲: In case a LTUX is transmitting when
switching is ordered (AUTO or MAN),
the change will be delayed until
the transmission has finished.
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11:3:4
11:3:5 PBP/821105
BSM-X l …0f…
BSM Block OH (B.D.) O̲P̲T̲O̲ ̲D̲R̲/̲R̲E̲C̲ For galvanic isolation between
Diagram the modules connected to the CCB bus, the
(CCB BUS signals to/from the bus are transferred via
section) opto-couplers.
C̲O̲N̲F̲I̲G̲ ̲B̲U̲S̲ ̲C̲O̲N̲T̲R̲O̲L̲ The communication to/from
the CCB bus is performed by ASRT (addresable
asynchroneous rec/tr). Each communication
cycle comprises 4 transmission (4 words):
1. The WD transmits addr. (8 bits: A[ -
6 + IDENT = "1")
2. the WD transmits CMMD (8 bits: C[ -
6 + IDENT = "0")
3. The BSM transmits data (8 bits: IO[
- 7)
4. The BSM transmits the command word received,
for check of transmission
Question How many transmissions on the CCB bus are
performed in one poll of the BSM-X
(Answer: 12) ADDR POINTER
DATA POINTER
ADDR DATA WORD
DATA DATA WORD
ADDR STROBE
DATA STROBE
Each BSM has a unique address which is set
up in a 5 bit DIL switch (ADDR bits A[ -
4 = addr's [ - 31 (H)). When the ASRT in
a BSM recognizes its own addr, it converts
the following serial word to a parallel word
and issues a CS (command strobe) for load
into a pointer or a data register (dependent
on
HO (CW) bits C5 and C6). When the "STROBE" word has
been received, additional logic performs
the functions specified in the pointer and
data words. The data requested fromt the
WD is connected by selecting certain inputs
of the multiplexer.
A̲N̲A̲L̲O̲G̲ ̲M̲U̲X̲ ̲+̲ ̲A̲/̲D̲ ̲C̲O̲N̲V̲E̲R̲T̲E̲R̲ When C4 in the
pointer is "1", the data word bits C[ - C2
select one of eight MUX inputs to be the
A/D converter input. This is for monitoring
the
OH (B.D.) +12V, -12V, +5V, V ref and 4 grounds.
…0e… 2986A/ktd
11:3:4
11:3:5 PBP/821105
BSM-X l …0f…
OH (CW) A̲/̲D̲ ̲C̲O̲N̲V̲E̲R̲T̲E̲R̲ When the C[, C1 bits in the
pointer are 0, 1 and 1,1, the 10 bits which
are the digital result of the A/D conversion
are sent to the WD.
OH /B.D.) P̲O̲W̲E̲R̲ ̲D̲E̲T̲/̲V̲R̲E̲F̲ The +12V level has to be
very stable because it sources the ref voltage
for the A/D converter. the Vref is adjusted
to +10,24V.
A drop in +12V to a value below 11,6V is
detected and read by the WD as bit IO 7
OH (CW) set when the pointer bits issued are all
zeroes.
BSM connections Communication with the TDX-CTRL via 25
pin CANNON connector at the front panel.
9 (IN) CC H = CRTL connected
10 (IN) CO2 H = CRTL operative
11 (OUT) COMI 1 H = Disable CTRL
…0f…12 (OUT) BS…0e… L = Select bus 1
H = Select bus 2
13 (IN) TS L = TDX bus clock missing
21 GND
22 (IN) CO1 L = CTRL OK
23 COMI 2 (NOT USED)
24 (IN) FS H = OUTlet fuses OK
OH (CON) Communication with the config bus and TDX
busses 1 and 2 via the CTX motherboard flat
cables and BSM-X panel.
OH Communication with additional input/output
is via a 10 pin wrap connector on the CDX
motherboard
1 GND
2 GND
3 A OUT 2
4 B OUT 2
5 B OUT 1 (?)
6 A OUT 1 (?)
7 A IN 1
8 A IN 2
9 GND
10 GND
…0e… 2986A/ktd
11:3:6 PBP/821105
TDX BSM-X l …0f…
GROUP WORK 1 Discuss the address possibilities (max/min
addr's) of the BSM-Xs in the CAMPS system.
2 Discuss the On-line and Off-line check
and diagnostic possibilities of the individual
BSM modules
3 By exercise on the system check the address
boundaries found above and check/diagnostic
features.
…0e… 2986A/ktd
11:4:1
11:4:2 PBP/821105
TDX CABLES/OUTLETS L …0f…
TDX Cables OH (C) The cable type used as the TDX bus is a two
core screened RF cable (type T (M) 3078)
with a char. impedance of 100 Ohm.
One cable (two cores) is used as lower bus
(i.e. CTRL TX/DEVs RX) and one cable (two
cores) is used as upper bus (i.e. CTRL RX/DEVs
TX).
Termination To prevent reflections on the bus, all cables
must be terminated in both ends with a 100
Ohm resistor.
Screen gad. To prevent ground loops, the screen must
only be connected to ground in o̲n̲e̲ rack.
Normally the CPU rack.
TDX OUTLET OH (0) Connects o̲n̲e̲ TDX.bus - both upper and lower
FUNCTIONS bus - to the modules communicating via the
TDX bus. In the CAMPS dual bus system, 2
outlets are connected to each BSM-X module,
1 outlet is connected to each controller
1 outlet is connected to each HOST I/F (TIA)
The termination of the bus cables and the
grounding of the screens are made directly
on the terminal block of the outlet box.
OUTLET The bus cable connection on the terminal
Connections block is like:
̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲
TX RX
̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲1̲&̲2̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲4̲&̲5̲ ̲ ̲ ̲ ̲ ̲
Black. ̲C̲R̲T̲L̲ ̲O̲U̲T̲L̲E̲T̲ ̲ ̲ ̲ ̲ ̲L̲o̲w̲e̲r̲ ̲b̲u̲s̲ ̲ ̲ ̲ ̲U̲p̲p̲e̲r̲ ̲b̲u̲s̲ ̲
Board
̲O̲T̲H̲E̲R̲ ̲O̲U̲T̲L̲E̲T̲S̲ ̲ ̲ ̲U̲p̲p̲e̲r̲ ̲b̲u̲s̲ ̲ ̲ ̲ ̲L̲o̲w̲e̲r̲ ̲b̲u̲s̲ ̲
Signal The outlet box contains circuits for signal
Adaption adaption to/from the bus from/to the CTRL/DEVICES
and provides galvanic isolation between the
bus cable and the communicating module (READ:
Between the different racks containing TDX
equipment).
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11:4:1
11:4:2 PBP/821105
TDX CABLES/OUTLETS L …0f…
Block Diagram OH (B.D.) S̲u̲p̲p̲l̲y̲ ̲v̲o̲l̲t̲a̲g̲e̲ ̲f̲i̲l̲t̲e̲r̲s̲:̲ Two +5V lines from
the module connected to the outlet box (fused
in the module) supply the circuitry with
power. The voltages supplied are filtered
by means of capacitors to ensure minimum
noise in the circuits.
VCC2 (& GND 2) Supplies the buffer stage
and power output stage
VCC1 (& GND 1) Supplies the logic and the
amplifiers
T̲X̲ ̲P̲A̲R̲T̲:̲ The SPL-D coded data received from
the transmitting module is transferred to
the TDX bus via tri-state, balanced (differential)
galvanic isolated (trafo) power drivers.
The DISAB signal controls the driver to be
in the high impedance condition.
R̲X̲ ̲P̲A̲R̲T̲:̲ The SPL-D coded receive data is
transferred from the bus via galvanic isolators
(capacitors) to a high impedance input (attenuator)
and a differencial receiver.
…0e… 2986A/ktd
11:4:3 PBP/821105
CTX CRATE L …0f…
Func. The CTX crate houses in 25 stations in the
front side the following:
Front OH (F.W.) T̲D̲X̲ ̲m̲o̲d̲u̲l̲e̲s̲:̲
positions
TDX controller
BSM-X
LTUX-S
A̲d̲a̲p̲t̲e̲r̲ ̲m̲o̲d̲u̲l̲e̲s̲:̲
L/L V24/V28 type 1 (1 channel)
L/L V24/V28 type 2 (4 channels)
OPTO transceivers (1 channel)
Optionally V24 monitor (4 channels)
a̲n̲d̲ one power supply for the TDX modules.
Motherboard OH (M.B.) The modules are plugged into a CTX motherboard
which provides:
- Interconnection between the LTUX-S and
adapter modules via the I/O area
- Power distribution from the front side
power supply to the TDX modules and the
adaptor modules (+/-12V, +5V)
- Comminication lines between the BSM-X
and LTUX-Ss
- Power distribution from the rear side
power supply to the adaptor modules (9VAC)
Back positions OH (R.W.) In the rear of the
CTS crate, the following
is to be mounted:
- Main power panel for mains power supply
(mains filter, fuse) to the front side
power supply (TDX modules)
- Adaptor power supply (2 x 9VAC for adaptor
modules
- V24/V28 back panels - BP8 (each 4 channels)
- TSA panel (Temp. Sense Adaptor)
- BSM-X panel
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11:4:4 PBP/821105
CTX POWER SUPPLIES L …0f…
ADAPTOR P.S. OH (PS1) CTX crates containing adaptor modules (low-level
adapter typ 1 & 2 and fiber optic modems
typ OM-2) are equppped with a power supply
which provides power necessary for up to
eight channels (any combination of the above
mentioned adaptors)
The 18V AC is via the CTX motherboard led
to the adaptors where it is rectified and
regulated to the appropriate levels.
TDX P.S. OH (8022) The TDX modules in the CTX crate (LTUX-S,
BSM-X, CTRL) are supplied with power (+5V,
+12V, -12V) from a P.S. type Cr8022. The
DC voltages are distributed to the modules
via the CTX motherboard.
Some characteristics:
- Maximum load:
+5V - 32A (Potmeter adjustable 4,5-5,8V)
+12V - 2,8A
-12V - 1,2A …0e…(not adjusable)…0f…
- All output is short circuit protected
with a constant current limiter
- Output will be maintained during one missing
mains cycle
- Control circuits for all output provide
immediate shut down in case of overvoltage.
- +5V fused (primary 3,15A)
+/-12V fused (primary 0,63A)
- Presence of the outputs is indicated by
LEDs on the front panel
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11:4:5 PBP/821105
TDX ADAPTORS L …0f…
The distribution equipment connected to the
four LTUX-S V24/V28 channels are of the following
types:
Main site VDUs OPTO transceivers
block MSPs (1 channel up to 2400 baud)
diagram
PTR V24/V28 L/L adapters
PTP (Typ 1: 4 channels,
up
Other low speed 1200 baud/ch)
devices (ex TTYs)
OCR V24/V28 L/L adapter
(main site) (Typ 2: 1 channel,
up to 9,6 Kb)
STAT/MUX 4 channel V24/V28 back
(remote VDUs panel adapter (BP8)
MSPs, OCRs (up to 2400 baud/ch)
Low Level To minimize cable emission the standard
Adapters V24/V28 voltages of +/-12V from the LTUX
are reduced to +/-6V and the waveshape of
the signals are changed (slope flattening)
to reduce harmonic generating
BP 8 OH (BP8) The back panel type 8 interconnects any V24/V28
comminicating devices. One panel serves 4
channels. By means of Onboard straps, the
lines can be interchanges or disconnected.
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11:4:5 PBP/821105
TDX L/L ADAPTERS L …0f…
TYP 1 (L/L) OH When the LTUX is operative, it issues DTR
(B.D.1) (data terminal ready) and RTS (request to
H.O. send). If it receives DSR (data set ready),
p. 75 it is allowed to transmit data on TXD or
receive data on RXD.
By means of Onboard straps, the above mentioned
signals can be en/disables, crossed
OH (S.O.) or interconnected in each channel according
+ H.O. to the actual application.
TYP 2(L/L) When the LTUX is operative, it issues DTR
and RTS. If it recieves DSR, it is allowed
to transmit data on TXD or receive data on
RXD.
Before transmitting a character, the LTUX
always verifies that CTS (clear to send)
is ON.
Also this board can be configured to any
application by means of straps.
…0e… 2986A/ktd
11:4:6 PBP/821105
TDX ADAPTORS GW …0f…
L/L Adapter CPS/TCN Two Hand-outs show the strap fields on the
Straps 037 two types of Low Level Adapters
(Hardw.
Assy
Proc.) 1. Indicate where to mount the straps for:
TYP 1: Point to point interface
TYP 1: PTR/PTP - LTUX-X I/F
TYP 2: OCR - LTUX-X I/F
NOTE: The polarity on the data lines
must be changed
2. Check that the actual strap setting on
the boards is equal to that found above
CPS/TCN/ 3 Same for LTUX-X - STAT MUX 2
031 Use L/L adapters 1 & 2 and BP8
page 23
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11:5:1 PBP/821105
WATCHDOG FUNCTIONS L …0f…
Main Functions OH (WD) - Monitors and controls
the CAMPS system configuration
- Provides the communication to/from the
maintenance position.
According th the status info collected from
the system crate assemblies, the WD provides:
- Automatic switching (connect/disconnect)
of the crate assys monitored
- Error reporting on the maint pos VDU/PRINTER.
The configuration control can be operated
manually from the VDU keyboard.
Switches on the different crate assys override
the above mentioned WD controls.
P.U.M&C P̲r̲o̲c̲e̲s̲s̲o̲r̲ ̲u̲n̲i̲t̲ ̲a̲s̲s̲y̲ ̲m̲o̲n̲i̲t̲o̲r̲i̲n̲g̲ ̲a̲n̲d̲ ̲c̲o̲n̲t̲r̲o̲l̲:̲
Both the active and the STANDBY PU regularly
transmit status messages to the WD via the
(WDDC) W̲D̲C̲C̲ ̲1̲ ̲&̲ ̲2̲ (Watchdog control channel). These
are V24 channels operating at 9,6Kb:
- The s̲t̲a̲n̲d̲b̲y̲ ̲P̲U̲ reflects PU condition and
whether or not it is able to "take over"
- The a̲c̲t̲i̲v̲e̲ ̲P̲U̲ status reflects overall
condition and as such "still alive". The
messages to the WD may also contain reconfiguration
commands.
OH (PU) Via the CCB (config control bus) the WD communicates
with the CCA (crate config adapter) in the
PU:
- Supervision of the DC voltage levels
- Monitor & control of PU en/disable state
- Issue of MASTER CLEAR to the MAP
- Issue of MAINTENANCE MODE to the MAP
…0e… 2986A/ktd
11:5:1 PBP/821105
WATCHDOG FUNCTIONS L …0f…
CU (M&C) OH (CU) C̲h̲a̲n̲n̲e̲l̲ ̲u̲n̲i̲t̲ ̲a̲s̲s̲y̲ ̲m̲o̲n̲i̲t̲o̲r̲i̲n̲g̲ ̲a̲n̲d̲ ̲c̲o̲n̲t̲r̲o̲l̲:
The channel unit assy I/O modules (disk controllers,
LTUs) are all electrically connected to both
I/O bus A and I/O bus B. The PUs can claim
control of any I/O module by issuing a "take
overnership" command to the module via the
I/O bus. If the ownership is possible, the
module is assigned to the I/O bus connected
to the claiming PU.
The WD may dis/enable ownership commands
from one or both I/O busses for all modules
together. Manually operated switches on a
control panel (CCUP) override the WD ownership
control for single or all modules.
All WD - CU communication is via the CCB
(bus) to a CCA module in the CU:
- Monitoring of the allow ownership switchsetings
(TOA)
- Monitoring of dualized power supply voltages
- En/disabling of A bus ownership (ADIS)
- En/disabling of B bus ownership (BDIS)
…0e… 2986A/ktd
11:5:1 PBP/821105
WATCHDOG FUNCTIONS L …0f…
TDX M&C C̲T̲X̲ ̲C̲r̲a̲t̲e̲ ̲a̲s̲s̲y̲ ̲m̲o̲n̲i̲t̲o̲r̲i̲n̲g̲ ̲a̲n̲d̲ ̲c̲o̲n̲t̲r̲o̲l̲:̲
The CAMPS dual bus TDX system operates as
two separate systems where each of the busses
has its own controller and is connected to
separate PUs. A set of two LTUXs in each
CTX crate can be connected to either of the
busses. The switching between the busses
is performed by a BSM (bus switch module
= CCA) which is again controlled from the
WD via the CCB (bus). The WD switching can
be disabled by means of a switch on the BSM
front panel.
The WD communication with the BSM via the
CCB (bus) comprises the following:
A̲L̲L̲ ̲C̲T̲X̲ ̲C̲r̲a̲t̲e̲s̲
- Monitoring of the DC supply voltages
- Monitoring of the AUT O/MAN switchsetting
- Monitoring of the rack mounted thermostate
- WD command to switch bus
A̲d̲d̲i̲t̲i̲o̲n̲a̲l̲ ̲i̲n̲ ̲C̲T̲X̲ ̲c̲r̲a̲t̲e̲s̲ ̲c̲o̲n̲t̲a̲i̲n̲i̲n̲g̲ ̲T̲D̲X̲-̲C̲T̲R̲L̲
- Monitoring of the CTRL status
- Monitoring of the bus clock status
- Monitoring of the CTRL - bus outlet powers
…0e… 2986A/ktd
RST 11:5:2 PBP/821105
WATCHDOG UNIT L …0f…
CRATE The watchdog unit consists of three modules
housed in a single bus mini crate with integrated
power supply and fan unit.
OH The three modules:
(Crate) WPU: Watchdog processor unit (= LTU)
H.O. WCA: Watchdog controller adapter
CCBA: Crate configuration bus adapter
Power Supply The main bus motherboard in the crate is
only used for power distribution to the WPU
and the WCA; the WCA is powered by separate
wires from the motherboard.
The CCBA is powered from the CCB (bus) only
(+12V coming from the WCA).
OH (P.S.) The P.S. mains supply is fused with 5A
H.O. (250V) and the output voltages are adjusted
to:
+5.45V (red wire)
+12.7V (yellow wire)
-12.7V (green wire)
Ground (blue wire)
…0e… 2986A/ktd
RST 11:5:3 PBP/821105
WATCHDOG MODULES (WPU) L …0f…
WPU-LTU OH (F.W.) The watchdog processor unit (WPU) is a standard
LTU module (CR8066M) which is a microprocessor
based communication proc. capable of handling
up to four full duplex communication lines.
The WPU is the only module mounted in the
front magazine of the WD crate. The LTU data
bus interfaces (two Cr80 I/O busses) are
not used in the WD configuration.
Functions The WPU is executing all the software used
for the WD application (see WD functions)
The programs are located in the 16K RAM memory
when the WPU is operative.
INIT When the WPU is initialized (power up/resex)
a built-in test, resident in the PROM memory,
is executed. The test includes PROM checksum
test, RAM R/W test and a loop test on the
for I/O ports. During execution, the TEST
and BOOT leds on the front panel is ON. Any
errors detected are indicated by flashing
the TEST led.
Because the RAM test is destructive to data,
the WD programs has to be loaded again after
a successful pass of the test.
BOOT Also resident in the PROM is a bootload program
which starts immediately after the test.
The WD software is permanently resident in
a 16K EPROM on the WCA board. The bootloader
controls the transfer by
OH addressing the EPROM via PIO port A and fetching
the data via PIO port B. When loaded, the
WPU switches to normal mode and the BOOT
led is OFF.
POWER LED The POWER Led - when ON - indidates the presence
of +5V, +12V, -12V on the WPU board.
…0e… 2986A/ktd
RST 11:5:4 PBP/821105
WATCHDOG CPU ADAPTER L …0f…
WCA FUNCTIONS The WCA constitutes the interface between
the WPU and:
OH (SYS) - The WDCC 1 & 2 (WD control channels :
"Alive" and "Ready" from the PUs)
- The CCB (Config. control bus: communication
with the crate assys)
- The maintenance position VDU/Keyb.
- The maintenance position printer
A failsafe circuit always monitors the WPU
"Alive" status. If the WPU does not update
the failsafe circuit at least every one second,
the WD TX line of the CCB (bus) is disconected
in the CCBA.
Also the WCA holds the WPU software in four
4K x 8 EPROMS. The boot process in the WPU
is initiated upon power up or when the CCB
busline BOOT is switched HIGH.
Block Diagram OH (B.D.) I̲n̲t̲e̲r̲n̲a̲l̲ ̲b̲u̲s̲ ̲s̲t̲r̲u̲c̲t̲u̲r̲e̲:̲ The lines from the
3 parallel 8 bit I/O ports (A, B, C) in the
WPU are via V28 rec/drivers led to the internal
WCA busses:
T̲h̲e̲ ̲P̲(̲o̲r̲t̲)̲ ̲A̲ lines are used as data/address
source to the WCA, and the destination -
which is EPROM address, UART TX regs, WPU
CRTL bus I/F, and V24/V28 buffer regs - is
pointed out by the P̲(̲o̲r̲t̲)̲ ̲C̲ lines (lower
byte).
The (upper byte) P̲(̲o̲r̲t̲)̲ ̲C̲ lines are used
by the WPU to sense the UART and the failsafe
status.
The P̲(̲o̲r̲t̲)̲ ̲B̲ lines are used for data transfer
from the UART or the EPROM to the WPU RAM.
…0e… 2986A/ktd
RST 11:5:4 PBP/821105
WATCHDOG CPU ADAPTER L …0f…
Block Diagram C̲o̲m̲m̲a̲n̲d̲ ̲D̲e̲c̲o̲d̲e̲r̲:̲ Latch and 1:8 decoder. To
(cont'd) obtain access to a WCA area the WPU must:
1: Reset the COM DEC
2: Issue a command pointer
3: Strobe the pointer (load)
E̲P̲R̲O̲M̲ ̲a̲r̲r̲a̲y̲:̲ Four 4K x 8 EPROM chips constitute
the 16K memory holding the WPU software.
Addressing is done in two sequences:
- The PA bits are loaded as A8 - A13 with
UPPER L from the COM DEC
OH (BD) - The PA bits used as A[ - A7 with READ
P from the COM DEC reads the data out
onto the PB bus.
U̲A̲R̲T̲:̲ communication between the WPU (parallel
data bus) and the modules attached to the
(serial) CCB bus is provided by the UART.
7 handshake signals (read, load, reset, and
UART status) are communicated via the CBUS.
The UART is hardwired to configure:
8 data bits
1 stop bit
even parity
RX & TX speed = 4800 baud
F̲a̲i̲l̲s̲a̲f̲e̲ ̲l̲o̲g̲i̲c̲: An "alive" message must
be sent from the WPU at least every 1 sec
time period. The message is transmitted via
the UART like other CCB messages. In the
failsafe logis, a 1,42 sec one shot is reset
and the signal AUTOSENSE is read by the WPU,
telling that it is still in control of the
bus. If the one shot times out, the AUTOENB
signal will cause the CCBA to disconnect
the transmit line to the bus.
…0e… 2986A/ktd
RST 11:5:4 PBP/821105
WATCHDOG CPU ADAPTER L …0f…
Block Diagram C̲o̲n̲t̲r̲o̲l̲ ̲b̲u̲s̲ ̲I̲/̲F̲: An external BOOT command
(cont'd) may be received from the CCB (optionally
a switch on the CCBA). Transferred via the
contol bus it starts the bootload program
in the WPU.
OH (BD) After a successful bootload, the WPU issues
EMCEN (ext. master clear enable) via the
PA bus, and returned on the control bus it
master clears the WPU and initiates execution
of the program just loaded.
C̲l̲o̲c̲k̲:̲ The crystal controlled 307.2 KHz
oscillator provides the clocks for the UART
(RX/TX) and for the failsafe logic (MC14469
AART)
P̲o̲w̲e̲r̲ ̲s̲w̲i̲t̲c̲h̲: As the power is supplied from
the WD crate PS and n̲o̲t̲ from any bus A or
B, the power switching is not implemented.
upon power up, the PUR (power up reset) is
generated from the +5V.
…0e… 2986A/ktd
RST 11:5:5 PBP/821105
Config. Control Bus Adapter L …0f…
CCBA Functions OH (DR) The configuration control bus
adapter (CCBA) module is a
switch unit inserted between
the WCA and the CCB (bus).
Relays on the board may disconnect the WD
TX line of the CCB in two ways:
- MANUAL: A panel switch DISABLE/ENABLE
disconnects the WD TX line in the disable
position. This is a useful feature to
prevent WD interference when M&D programs
are executed.
- AUTOMATIC: When the switch is in the ENABLE
position, the AUTO ENB signal - updated
by the 1.42 sec one shot on the WCA board
- provides the control function.
When any of the enabling features is active,
an indication is given in the ENABLE led
on the panel. When inactive, it is reported
back to the WCA on the WD DIS line.
The presence of the +12V - supplied on the
CCB (bus) from the WCA - is indicated in
the POWER led.
Optionally a switch - BOOT - can generate
the boot signal on the CCB for WPU initialization.
…0e… 2986A/ktd
RST 11:5:6 PBP/821105
Config. Control Bus (CCB) L …0f…
To exchange of config status and control
messages between the WD and the system units,
a 16 lead twisted pair flat cable is used.
From the WD (CCBA module) it is daisy chain
connected to all the CCAs and BSM-Xs in the
system.
PIN ASSIGNMENT OH (PIN) As no WD panel control is used
in the CAMPS system, only the
WD lines carry signals.
BUS traffic The data transmission on the CCB is the positive
logic with HIGH (="1") in idle. Levels 0-+12V.
Due to the requirements for galvanic isolation
between the crates, the RX and TX signals
are transferred via optical couplers in all
modules conncted to the bus (except the CCBA);
the power (+12V) for the opto drivers is
supplied via the bus from the CCBA (WD 12V)
The bus communication is a̲s̲y̲n̲c̲h̲r̲o̲n̲o̲u̲s̲ ̲s̲e̲r̲i̲a̲l̲
data transmission at a speed of 4̲8̲0̲0̲ ̲b̲a̲u̲d̲.
BB The data format is:
1 start bit
7 data bit (address and command
1 identifier bit
1 parity bit
1 stop bit
MC 14469 The acynchroneous rec/tr's (AATR) in the
CCAs and the BSM-Xs - when receiving an address
identifier - compares the data bits with
a switch setting. When equal, it will receive
one more word (the command word) and then
transmit two words; first a data word, then
the command word just received (for comm.
control in the WD).
In order to avoid unintentional unit switching,
three such cycles are always traversed by
the WP when using the bus.
…0e… 2986A/ktd
RST 11:5:6 PBP/821105
Config. Control Bus (CCB) L …0f…
MC 14469 Block 1. WD TX Address
(cont'd) Board Pointer
WD RX Data
Pointer (check)
2. WD TX Address
Command
WD RX Data
Command (check)
3 WD TX Address
Strobe
WD RX Data
Strobe (check)
Unit Addressing Only the 5LSB addr. bits are used in the
CAMPS system (5 bits = 32 addresses)
The units are addressed like:
CCAs PU 1 ADDR #1
PU 2 ADDR #2
CU ADDR #3
BSM-Xs TDX CRATE 1 ADDR #1 1
. . .
. . .
. . .
TDX CRATE 13 ADDR #D 1
OH (SW)
…0e… 2986A/ktd
PBP/821105
LESSON 11.1.1
EXERCISE (SPL-D CODE) CAMPS…0f…
1) Clock
SPL-D Code?
DATA: 11001010
̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲
̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲
2) SPL-D Code:
DATA?
…0e… 2986A/ktd
PBP/821105
GROUP WORK 1
H.O. (1)
CAMPS…0f…
Compare the block diagrams of the TIA and LTUX-S and
explain the following divergences:
1) LTUX: Four I/O lines to/from the drivers/receivers
TIA: Twelve I/O lines to/from the drivers/receivers
2) LTUX: Power supplied is VCC, -12V, +12V
TIA: Power supplied is VCC, -12V
3) LTUX: CR-ID check on frames received is on 4 bits
(PROM) + 8 bits (switchsetting)
TIA: CR-ID check on frames received is on 4 bits
4) LTUX: The CPU is able to read the DEV NO bits
TIA: The CPU does not read the ID bits (H[-3)
5) LTUX: The system clock is derived from an on-board
oscillator
TIA: No on-board oscillator exists
̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲
̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲
Compare the block diagram of the TDX controller to
the LTUX/TIA's and discuss the above matters regarding
the controller
…0e… 2986A/ktd
PBP/821105
GROUP WORK 2
H.O. (2)
CAMPS…0f…
Discuss the addressing range of the TDX module(s)
1) What is the max/min address of a LTUX module?
2) What is the max/min address of a HOST I/F?
3) What is the max/min address of a CONTROLLER?
4) How does the user specify and set up a new address?
̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲
̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲
E̲X̲E̲R̲C̲I̲S̲E̲:̲
Check on the system the above mentioned address ranges
like:
- Set up the max possible address in the respective
module and check operation
- Set up max address + 1 and check
- Set up min address and check
- Set up min address minus 1 and check
