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⟦52c1fe2ae⟧ Wang Wps File
Length: 38721 (0x9741)
Types: Wang Wps File
Notes: PC/IMA/001- (week 1)
Names: »3270A «
Derivation
└─⟦2b05c95ac⟧ Bits:30006158 8" Wang WCS floppy, CR 0067A
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WangText
<…08…<…0f…<…07…;…0d…;…05…:…09…:…00…:…06…9…0b……86…1
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3270A/rt
…0f…Protocol Converter 1:1:1-3 LT/821214
Overview L
PC
P̲u̲r̲p̲o̲s̲e̲ Allow communication between CCIS (Honeywell
6000) and CAMPS (CR80), CCIS and SCARS (Burroughs).
Direct communication between these systems
are not possible since the end systems CCIS
and CAMPS/SCARS use different protocols.
Protocols The messages transmitted from any end system
are constructed according to specified rules
concerned with control information to the
transactions such as:
type - length, start -
end - sequence - destination - origination
- error detection - synchronization - etc.
The protocols used by CAMPS and SCARS are
identical, while the ones CCIS uses are different.
CAMPS/SCARS uses a X25 protocol at level
2 and 3.
CCIS uses GRTS/RC (Level 2+3) and DINDAC
(level 4) protocols.
Tasks OH 1 To convert protocols so it appears to end
systems as though no protocol differences
exits.
3270A/rt
…0f…Protocol Converter 1:1:1-3 LT/821214
Overview L PC
M̲e̲s̲s̲a̲g̲e̲s̲ The messages exchanged between the end systems
are of 4 main types:
narrative msg,
data msg,
VDU display,
and comments.
A message to be sent from any of the systems
can have a maximum size of 1̲2̲0̲0̲0̲ ̲b̲y̲t̲e̲s̲ including
the message frame.
The message frame consists of a message header
with information such as:
classification, priority, identifier and
a message trailer with information of end-of-messsage.
A message with this possible size has to
be
SCARS/CAMPS sent in fragments.
In the SCARS/CAMPS protocol the message will
be sent in frames of a maximum of 1̲2̲0̲ ̲b̲y̲t̲e̲s̲
of the message plus frame bytes. Each frame
is acknowledged.
CCIS The message is placed on disk in
OH 2 segments of maximum 1̲1̲0̲6̲ ̲b̲y̲t̲e̲s̲ plus 3̲4̲ ̲b̲y̲t̲e̲s̲
of segment header, but is transferred on
the line in frames of 3̲2̲4̲ ̲b̲y̲t̲e̲s̲ plus 1̲3̲ ̲b̲y̲t̲e̲s̲
of frame according to GRTS/RCI protocol.
Each frame is acknowledged.
Segments marked as last segment in an E1
message, causes PC to generate a SUPER-ACK
towards CCIS. Acknowledgement is to DINDAC
(level 4).
PC Acknowledgements are generated at message-level
but these are transparent to the PC.
PC serves as a postoffice, passing the mail
on without looking into the contents.
3270A/rt
…0f…Protocol Converter 1:1:1-3 LT/821215
Overview L PC
C̲C̲I̲S̲ ̲T̲O̲ OH 3 The frames received from CCIS are stripped
C̲A̲M̲P̲S̲/̲S̲C̲A̲R̲S̲ and checked of its frame-characters:
GRTS/RCI 4 bytes of SYNC, 1 byte START OF HEADER,
SYS 5 bytes of HEADER: format, alternating
SPEC sequence,address,operation, identity
p.21 1 byte START OF TEXT
0-324 bytes of TEXT
1 byte of End/more text
1 byte of FRAME CHECK
The checking of the frame is according to
GRTS/RCI protocol.
DINDAC The first step is to strip of segment header
and to check it according to DINDAC protocol.
The HEADER contains information such as:
sending station - transaction number - segment
SYS number - End of msg/not - msg priority -
msg.
SPEC classification - msg. type - program keyword
p 20 msg. subject code - next msg priority - sequence
number - segment length.
The PC message buffer descriptor is loaded
Data (text) goes into PC message buffer.
Except for the msg buffer descriptor - repeated
for each segment.
X25 level 3 Information frames are set up when data are
available
6 bytes of Message Control Field follow by
1̲-̲1̲2̲0̲ ̲b̲y̲t̲e̲ text from msg buffer.
Message Control Field gets information from
Msg Buffer Descriptor and consists of:
1 byte of Information Field Length
SYS 1 byte of Block (frame) Number
Spec 1 byte of Block (frame) Type: position in
p.17 message
1 byte of Message Priority - to check if
it can be overrided
1 byte of Message Type
3270A/rt
…0f…Protocol Converter 1:1:1-3 LT/821215
Overview L PC
X25 Level 2 The Information Field is set up with
Header: 3 bytes of sequence - address - control
Trailer: 3 bytes with frame check and sequence
Frames Transaction flow can start as soon as the
CAMPS/SCARS to PC message buffer contains enough to fill a
frame: max text in frame: 1̲2̲0̲ ̲b̲y̲t̲e̲s̲
Each frame to be acknowledged by receiver.
If no acknowledgement within 3̲ ̲s̲e̲c̲o̲n̲d̲s̲: retransmit
max number of retransmission: 3̲ ̲t̲i̲m̲e̲s̲ ̲
max number of non-acknowledged frames: 3̲
Messages 3 service messages used:
T̲r̲a̲n̲s̲a̲c̲t̲i̲o̲n̲ ̲a̲c̲k̲n̲o̲w̲l̲e̲d̲g̲e̲m̲e̲n̲t̲ send by receiver
of message to acknowledge reception.
If no acknowledgement within transmission
time of 2x12000 bytes: timeout and retransmit.
If error/insufficient message = no acknowledge
or on CAMPS = acknowledge and present message
in error on VDU to MSO.
C̲h̲a̲n̲n̲e̲l̲ ̲C̲h̲e̲c̲k̲ ̲M̲e̲s̲s̲a̲g̲e̲ send in between messages
to verify good line, is verified by Transaction
acknowledgement.
F̲i̲n̲a̲l̲ ̲N̲u̲m̲b̲e̲r̲ ̲M̲e̲s̲s̲a̲g̲e̲ with information of
number of messages sent is used at the end
of day to verify no loss of messages.
3270A/rt
…0f… Protocol Converter 1:1:1-3 LT/830119
Overview L PC
CAMPS/SCARS to CCIS Frames received from CAMPS/SCARS are checked
and stripped off Header and Trailer leaving
the Information Field.
The Message control Field is checked and
stripped supplying information to the Message
Buffer Descriptor. Data stored at the Message
Buffer.
DINDAC Transaction flow can start when the message
buffer stores enough data to fill a segment.
A segment header is leading data. Header
contains information partly gained from the
Message Buffer Descriptor.
Segment header: 34 bytes
Max text in segment: 1106 bytes
GRTS/RCI The segment is transmitted in frames to CCIS
Each frame: 11 bytes Sync/Header
0-324 bytes text
2 bytes Frame end
CCIS: half duplex - when idle: CCIS is Master
and PC is in receive-mode.
When PC has a segment to be transmitted towards
CCIS,
- "break" (level 2 frame) to CCIS
- CCIS request transmission - frame level
- PC transmit frames
- CCIS acknowledges frames by requesting
transmission
- if error no request transmitted
- timeout = 7 second = retransmission
- max retransmissions = 7 times
- max nonacknowledged frames = 1
PC will indicate last frame in the last segment
to CCIS.
CCIS will respond with SUPER ACK/NAK.
The OK/Error information is transformed to
a Transaction acknowledge if OK, if error
no action to CAMPS/SCARS.
PC will send a frame to CCIS ack-no-request
and CCIS takes charge and PC goes into receive
only mode.
3270A/rt
…0f… Protocol Converter 1:1:1-3 LT/830119
Overview L PC
Service messages Super-ack used to accept messages
Super-nak used to reject messages or at
end of a segment to interrupt sender
requesting change of transmission-direction
Bust-message used to at end of segment to
override for transmission of higher priority
Response = super-nak
No-message = when expected to transmit but
no transmission to be performed.
3270A/rt
…0f… Protocol Converter 1:1:1-3 LT/830119
Overview L PC
CCIS Message OH 4 MSG at CCIS-top are created according to
the E1-format requirements.
to CAMPS/SCARS
MSG sent to DINDAC-(part of CCIS)-stored
in segments.
The GRTS and RCI protocols will separate
data in two frames.
The idle state of the half-duplex connection
between CCIS/PC is PC in receive-mode.
Frame Each frame transmitted to PC will be acknowledged.
Last frame of Last segment of a message is
sent
DINDAC CCIS require PC to respond by TX.DATA-frame.
PC acknowledges to DINDAC by SUPER.ACK.
This SUPER.ACK gives CCIS: next-to-transmit
Message received by PC are checked for message
type on message-level,DINDAC-frame is checked
and stripped, RC1-frame is checked and
stripped.
Data stored in Message Buffer and frame -
information are partly stored in Message
Buffer Descriptor.
Data are transmitted to CAMPS/SCARS according
to X25 protocol in frames supplied with header
- partly with information from Message Buffer
Descriptor - and frame.
Each frame is acknowledge by CAMPS/SCARS.
When the full message is received CAMPS/SCARS
sends a message Transaction Acknowledge to
CCIS-top-level. The message is a service
message and requires no response.
3270A/rt
…0f… Protocol Converter 1:1:1-3 LT/830119
Overview L PC
Trans.Ack. is a very short message.
Transmitted in a frame to PC, which acknowleges
it, strips the frame and checks it and store
Data.
Transmission direction is towards PC, so
PC sends a BREAK to CCIS, which will respond
with a request to transmsit: TX.DATA.
Data transmitted - only one frame. The frame
and segment acknowledgement will be a SUPER.ACK
from DINDAC.
PC responds with frame-acknowledgement also
containing "no-request" which sets CCIS in
Master-mode (PC in receive).
The DATA will be sent on to CCIS-top-level
as a message acknowledge.
There are no retry procedure on message or
segment level. On frame level there are.
CAMPS/SCARS-nonacknowledgement is no transmission
and timeout: 3 sec. Retries: 3
CCIS-nonacknowledgement is no transmission
and timeout: 7sec. Retries: 7.
CAMPS/SCARS Message acknowledgement is a PC created
to CCIS Transaction-acknowledge if a SUPER-ACK is
received by DINDAC.
Nonacknowledgement is no response and timeout
2x12000 character-transmission-time.
3270A/rt
…0f… Protocol Converter 1:1:1-3 LT/830119
Overview L PC
Site-configura-
tion OH 5 A PU can only handle one link. PC = 1 or
2 P.U.
All sites will have one complete PU in spare.
C̲C̲I̲S̲/̲C̲A̲M̲P̲S̲/̲S̲C̲A̲R̲S̲ sites will have 3 PU's:
1 to each of the 2 links mounted in a 19"-rack,
and 1 PU on a trolley. Spare-PU is power
connected.
C̲C̲I̲S̲/̲C̲A̲M̲P̲S̲ site will have 2 PU's: 1 for the
link and 1 in spare, both mounted in a 19"-rack.
VDU-connection To operate the PU a VDU is needed, but
only 1 for all on 1 site.
VDU can be connected/disconnected without
disturbing the system.
Off-line-PU can be connected to VDU for check-out
or troubleshooting.
VDU can be used elsewhere during system-operations.
3270A/rt
…0f… Protocol Converter 1:2:1 LT/830105
Configuration and Modules L PC
Basis OH 1 PU is based upon the CR831 mini-communication
oriented version of CR80- and consists of:
Processor
Crate OH 2 C̲P̲U̲/̲S̲C̲M̲: processing power/system control
module
E̲P̲R̲O̲M̲: stores the software in Read-only-memory.
R̲A̲M̲: stores processes, work area, buffers
in RAM chips.
2̲ ̲L̲T̲U̲'̲s̲: 1 for CCIS, 1 for CAMPS/SCARS. Stores
Low Level software-handling frames - and
buffers.
These 5 modules communicate via a BUS of
16+2 par data lines.
C̲S̲A̲: strapfield - connecting V24 signals
to D25 connector.
L̲I̲A̲-̲N̲: strapfield - connecting V24 signals
to D25 connector.
All units placed in a CR8115 Mini Crate:
CPU/SCM, EPROM, RAM, LTU-A, LTU-B - at the
front - plugged into a motherboard - in which
the BUS is part and through which power is
supplied (+/- 12V, 5V) -
CSA, LIA-N's - at the rear - are connected
via flatcables.
P̲o̲w̲e̲r̲ ̲s̲u̲p̲p̲l̲y̲ is positioned at the back.
Patch Panel P̲a̲t̲c̲h̲ ̲P̲a̲n̲e̲l̲ allows patching of the VDU to
(EMI-rack) either of the PU's inclusive the spare, and
swopping of links by patching the line connections.
Adapter Crate L̲o̲w̲ ̲L̲e̲v̲e̲l̲ ̲A̲d̲a̲p̲t̲e̲r̲s̲ convert CCITT V28 Levels
into L/L V28 (+/-12V into +/-6V).
O̲P̲T̲O̲ ̲T̲/̲R̲ converts electrical signals into
infrared Light pulses - this is done to
overcome RF+ radiation.
P̲o̲w̲e̲r̲ is supplied from the crates own power
supply
2 x 9V A̲C̲, 4.2A
The Adapter Crate contains 4 L/L adaptors
- 2 to each P.U., but only 1 OPTO T/R.
3270A/rt
…0f… Protocol Converter 1:2:1 LT/830105
Configuration and Modules L PC
Filters All inputs and outputs are passed through
a RFI-filter at the border of the EMI-rack.
VDU The Visual Display Unit allows the user to
communicate with the P.U.
Used during upstart and closedown, tests,
verifications, and during troubleshooting.
Need not to be connected during operation,
but then error messages are lost.
Max.Configu-
ration OH. 3 Upper P.U. in separate crate handling one
Link
Lower P.U. in separate crate handling second
Link.
Below Upper and Lower crates are the Adapter
crate and connections between the adapters
and the P.U. are made at the Patch Panel,
where it also is possible to connect the
Spare P.U.
Spare P.U. is positioned outside the EMI-rack
on a trolley, except for one site, where
the spare is the second P.U. in the rack.
3270A/rt
…0f… Protocol Converter 1:2:1 LT/830106
Configuration and Modules L PC
CAMPS to CCIS OH. 2 A message has been created
and is about to send from
CAMPS.
Since the connection CAMPS-PC is full duplex
Line and the first frame can be transmitted.
filter Passes the filter in serial, synchronious
at baud signal level +/-6V.
L/L Adapter Receives the signal- shapes it and convert
into signal level +/-12V.
Patch Panel Passes the signal on to the selected LIA-N
LIA-N Only strapfield. Connects the V24 to D25
connector.
CAMPS/PC
I/F wiring OH.4 Show signal path. V28 L/L only active Link.
102-ground, 103-tx data, 104-tx-data, 105/106
- eliminated - Request-to-send/clear-to-send,
107-Data set Ready Data Terminal Ready, 109-fixed
Corr.det.,
113-tx clock, 115-rx clock.
LTU-A OH.2 Microprocessor controlled with 16Kword buffer
in RAM shared with CPU.
LTU receives the frame,
checks and removes the control information-(header+trailer-),
creates a frame acknowledgement,
stores data in the buffer
and sends an interrupt to CPU/SCM.
CPU CPU fetches the data from LTU and load it
into the RAM, checking and removing the frame.
Keeping track of the position of data within
the message.
This process is continued.
When data sufficient in size to fill a segment
it is gathered, it is supplied with a segment-header
and sent to LTU-B, where it will be stored
in the shared RAM.
3270A/rt
…0f… Protocol Converter 1:2:1 LT/830107
Configuration and Modules L PC
LTU-B The LTU will block data into frames,
supply these with frame information - header
and trailer,
and transmit them - in serial, synchronous
at 2400/4800/9600 baud, on a half duplex
line.
Each frame will be acknowledged by CCIS.
OH.5 Signal will pass through LIA-N strapfield,
the patch panel, the BP-8 strapfield, the
V28L/L performing waveshaping and signallevel
conversion to +/-6V, and the filter to reduce
RF-radiation.
CCIS to CAMPS OH.2 A complete segment need
to be accumulated in LTU-B
shared RAM before the
data-block can be sent
on to the CPU/SCM for
check and removal of segment
header and storage in
RAM-module.
LTU's Furthermore handles Line surveillance,
request for retransmissions, parity generation
and checks,
error statistics (CAMPS/SCARS).
NAK non-acknowledgement - nak - is performed
by not transmitting an acknowledgement expecting
timeout to indicate error.
3270A/rt
…0f… Protocol Converter 1:2:1 LT/830107
Configuration and Modules L PC
VDU-Con-
nection OH.2 During upstart, close down, test verification
or other actions requiring operator's assistance
a VDU has to be connected.
Via the Patch Panel it is selected to which
PU the VDU is connected.
OH.6 Communication with VDU is handled by the
SCM-part of the CPU/SCM, in serial, asynchronious
at 2400 baud, full duplex.
CSA: CPU-SCM-Adapter is to the PU only a
strapfield. Through the Patch Panel - BP8
Adapter Crate Motherboard to the OPTO T/R.
OPTO T/R converts V28 to in infrared signals,
multiplex data with control bits and add
frame bits for synchronization. Signal is
converted to Manchester Code. At reception
the reversed procedure is followed.
3270A/rt
…0f… Protocol Converter 1:2:1 LT/830110
Configuration and Modules L PC
Modules known Minicrate
to the student RAM
LTU - single bus
LIA-N
Adapter Crate
OPTO T/R-OM-2
V28 L/L Adapter
VDU
Modules new CPU/SCM
to the student CSA
EPROM
Patch Panel
Breakout Test Panel
Books avail- PC Equipment Handbook
able at site PC Site Maintenance Manual
PC Assembly Breakdown Manual
3270A/rt
…0f… Protocol Converter 1:2:2 LT/830111
CPU/SCM L PC
Processing OH.1 Performed by CPU of CPU/SCM with SCM as supervisor.
Program to act upon, stored in EPROM.
Memory to be used during processes, in RAM.
CPU C̲P̲U̲ of CPU/SCM is 16bit-word long
with 274 basic instructions, including bit-byte-word-multiple
word manipulations.
Able of addressing 2x64Kwords of memory.
SCM S̲C̲M̲ of CPU/SCM generates timing signals for
synchronization to all modules - clocks -,
receives and detects interrupts,
store the MAC-program (Maintenance Controller:
with INIT (Bootstrap loader) DUMP (mem)
CHECK (modules), communicate with the VDU
CPU:
ALS OH.2 4 Bitslice processors of 4 bits = 16 bit
wide processor.
1 Status and Shift Control. 1 Look Ahead
Carry Generator
IBUS: input. OBUS: output.
Performs the actual processing and contains
the registers RO-R7, MOD, TIMER.
ACMS Address Calculations and Mask functions.
An arithmetic logic unit (ALU) and 16 registers
in 16bit word file: BASE, PROG, PRPC.
TR: Transfer and swap register gives access
to IBUS
OBUS: receives data from ALS
ABUS: connects to AR and internal to file
registers.
3270A/rt
…0f… Protocol Converter 1:2:2 LT/830119
CPU/SCM L PC
PSW 16bit wide status word. R/W via IBUS
1. group: bit 4-7 = condition of ALS
2. group: bit 8-10 = 3 switches = CPU number
3. group: bit 9-3, 11-15 = 1 local interrupt
5 other interrupts
2 for memory paging
in 64K words
CTC Control communication with SCM
Rx: interrupts = time, CPU, I/O's in priorities
Rx: Bus granted upon request
Tx: Bus requested, Lock Bus granted (always)
Fetch instruction CPU sets up an address in AR pointing to
memory and an address in the memory area.
M̲B̲T̲C̲: AD16-19 (mem.page/I/O: up/low byte
or word
R/W = R. TRQ = 1
AR = address (AD 0-15) is present at mainbus
M̲B̲T̲C̲: receives RS = transfer response when
memory module accepts address.
NINS/IDR = receives data from memory via
Datalines.
OP-REG. holds the instruction during decoding and
execution.
u-PROG-SEQ consists of Feed Back Multiplexer used to
perform tests on OP-code,
and the Micro Program Control Unit to setup
addresses for the Micro Program.
MPCU can store and sequence 5 address words
of 12bits.
3270A/rt
…0f… Protocol Converter 1:2:2 LT/830119
CPU/SCM L PC
Micro Prog. 2Kword micro-instructions of 64 bits and
MIR holding 64 bit-instruction during execution,
and 4 registers to hold address lines for
the VARIOUS registers.
One register: MPCU Instruction Register to
alter instruction. MPCU IR is 1 of 4 inputs
to MPCU.
The 3 others are OPREG, interrupts, and results
of data operations (IBUS).
MBI/F M̲B̲T̲C̲: TRQ, R/W, AD16-19, RS,
IDR/NINS, ODR, Parity Check/generation, AR.
SCM: OH.3
Interrupt Recv. 8 bits interrupt code received on one Line
of the mainbus (INR) in serial
- the (INA) acknowledge interrupt is sent
out.
4 interrupt can be stored
- one in each priority (0-3) - 2 bits.
6 bits used for addressing (0-63). Priority
bits are passed on to CPU for CPU to select
the interrupt.
Control M̲A̲D̲: AD 10-19 and R/W used to select memory
area (AD 0-9 feeded from AR of MB I/F)
I̲/̲O̲ ̲A̲D̲: allows decoding of addresses to/from
I/O's
AD 8-10+ DA6 used to address in SI/OI.
Memory 3 areas of 2Kword = 16 bits of data + 2 bits
parity.
P̲R̲O̲M̲S̲: Maintenance Controller (MAC) stored
here
3270A/rt
…0f… Protocol Converter 1:2:2 LT/830112
CPU/SCM L PC
Main Bus Autho- Used to grant CPU control of Mainbus. With
rity Control only one CPU, this will always have control.
Power Condition Power detection and master clear circuit:
Detection
Activation of MC/Power-up = master clear
+ CPU clear to reset the CPU.
5V +/-12V monitored, if too low Power Failure
Interrupt to halt CPU. MC needed. "TEST"
on front "ON".
Timing generator 4̲ ̲c̲l̲o̲c̲k̲s̲ - 8̲,4,2,1̲ Mhz
- 2̲ ̲t̲i̲m̲e̲r̲ ̲i̲n̲t̲e̲r̲r̲u̲p̲t̲s̲ for CPU - 10 msec +
adj. 10-160 usec - generated C̲P̲U̲ ̲i̲n̲t̲e̲r̲r̲u̲p̲t̲
̲p̲r̲i̲o̲r̲i̲t̲y̲: Power failure, timer, I/O.
P.C.I Controls the communication with V24 I/O interface
to VDU(DTE/DCE : 50-19200 baud) in 2400 baud.
Converts parallel (bus) to serial (V24).
To/from controlled by W/R.
The subaddress sets the mode/command.
The I/O - address is as for any I/O.
CSA: OH.4 Transfers the V24 signals via a strapfield
to the D25 connector.
Straps: Site Maint. Man.
3270A/rt
…0f… Protocol Converter 1:2:3 LT/830112
EPROM L PC
General OH.1 For CPU to fetch an instruction stored in
the PROMS, the CPU will set up an address
and the address instruction will appear as
data on the bus.
The module can be accessed by two busses
- only one in PC.
Transfer OH.2 CPU sets TRQ, address, AE.
ADD 12-19 are compared with Module Switch
in A̲D̲D̲R̲E̲S̲S̲ ̲C̲O̲M̲P̲A̲R̲A̲T̲O̲R̲ initiated by M̲E̲M̲O̲R̲Y̲
̲S̲E̲L̲E̲C̲T̲ upon enable signals.
An Access Request signal is sent to A̲U̲T̲H̲O̲R̲I̲T̲Y̲
̲C̲O̲N̲T̲R̲O̲L̲, that will select bus to T̲R̲A̲N̲S̲F̲E̲R̲
̲C̲O̲N̲T̲R̲O̲L̲, that synchronized with a clock from
C̲L̲O̲C̲K̲ ̲G̲E̲N̲E̲R̲A̲T̲O̲R̲ generates RS to CPU via the
selected bus.
PROM select Addresses 11-15 and R/W are received by
A̲D̲D̲R̲E̲S̲S̲ ̲B̲U̲F̲F̲E̲R̲ and sent to
M̲E̲M̲O̲R̲Y̲ ̲S̲E̲L̲E̲C̲T̲ to be decoded by 2 PROM's into
8 lines of PROM selection to the PROM area.
PROM address Addresses 0-12 are latched into
ADDRESS RECEIVER and sent to the
PROM DRIVER to set up the address within
the selected prom.
DATA out DAO-15 will be latched in the DATA OUTPUT
REGISTER.
All 16 bits of data will be used by the
PARITY GENERATOR to generate UP + LP to be
latched in DATA OUTPUT REGISTER.
Timing OH.2 TRANSFER CONTROL controls the timing of addressing
and data transfer.
At the time of RS the
DATA OUTPUT REGISTER changes state and drives
the BUS data lines.
3270A/rt
…0f… Protocol Converter 1:2:3 LT/830117
Patch Panel DE PC
Purpose Patch Provides the connection between the Processor
Panel crate(s) and the Adapter Crate - signal wise.
Allow patching of the VDU to any of the CPU/SCM
Allow swapping between P.U.'s handling CAMPS/CCIS
and SCARS/CCIS.
(Do not allow swapping of LTU's within a
P.U.)
Location Positioned at the rear of the EMI-rack
Function At the rear of the panel the normal connected
Link is made by connection via D25 connectors.
At the front 3 16-lines-plug are available.
Patch core With a patch cable - with a 16-line-jack
at each end - it is possible to:
a) break and patch either of the two link
connection to another link.
b) to patch the link signals to a break-out-
-test-panel to be monitored.
c) to insert the test panel in serial with
the link.
3270A/rt
…0f… Protocol Converter 1:2:3 LT/830117
Breakout Test Panel DE PC
Purpose BTP Allow monitoring of V24 lines without interruption
and to simulate signals.
Function M̲o̲n̲i̲t̲o̲r̲:
A patch cord is connected to the Patch Panel
monitor plug and to the DCE plug on BTP.
A LED-indicator to each Lead will indicate
activity on the Leads:
Less than +/-3V OFF
More than + 3V RED
More than -3V GREEN
Test points in the top row are in use
S̲e̲r̲i̲a̲l̲:̲
A patch cord is connected to the Patch Panel
DCE plug and to BTP DCE plug.
Another patch cord is connected between the
Patch Panel and the BTP DTE plugs.
Indications as for monitor-mode, but the
lower row test points are also active.
Each of the Leads can be opened by setting
the associated switch in down position allowing
+/-12volts (available at the BTP) to be connected
for signal simulation.
A pulse trap to latch and hold (until manual
reset) negative or positive pulses of more
than 3 usec can be patched in any Lead.
Power 220V AC 30 watts max.
3270A/rt
…0f… Protocol Converter 1:3:1 LT/830118
Operation L PC
Modes of ope- Draw 1 4 modes:
ration
M̲a̲i̲n̲t̲e̲n̲a̲n̲c̲e̲:̲ ̲the initial mode after power-up
L̲o̲c̲a̲l̲:̲ initialized but offline. Cmd: INIT
O̲p̲e̲r̲a̲t̲i̲o̲n̲a̲l̲:̲ normal mode. Cmd: LOGON
T̲e̲s̲t̲:̲ On-line test mode - to test each link
Cmd: TEST.
Maintenance (M) . Only MAC (maintenance controller)
in use
Cmd: DUMP - page - start - stop = dumps memory
to the VDU.
Cmd: CHECK - module = runs offline test of
module.
Local (L) . System initiated but off-line
Cmd: MAINTENANCE = back to Maintenance mode
Operational (O) . System is running. End systems
connected.
Cmd: LOGOFF = back to local
Cmd: SHOW/RESET STATISTICS gives/resets number
of frames transmitted, retransmitted, received
errorfree, received with errors.
Test (T) . System is running. End systems connected.
Normal transactions should be suspended.
Cmd: VERIFY - destination - message length
= will send a message to end-system, to be
returned (CAMPS/SCARS by operator).
Cmd: SHOW/RESET STATISTICS = as (O)
Cmd: LOGOFF = into mode local
Summary OH 1 Refer to section 2 of Site Maintenance manual
3270A/rt
…0f… Protocol Converter 1:3:2 LT/830120
Procedures L PC
Preventive S.M.M. Only filters of EMI-Rack and S-fans
sec.3
Corrective OH 1 Explain the logic flow of corrective maintenance.
Aids:
fig. 4.6.3-1 OH 2 S̲y̲s̲t̲e̲m̲ ̲T̲r̲o̲u̲b̲l̲e̲s̲h̲o̲o̲t̲i̲n̲g̲ ̲T̲r̲e̲e̲ sec. 4.6 with
list of completion codes and with the knowledge
fig. 4.6.2-1 OH 3 of s̲o̲f̲t̲w̲a̲r̲e̲ ̲p̲a̲c̲k̲a̲g̲e̲ ̲p̲o̲s̲i̲t̲i̲o̲n̲s̲ places the
error in major parts of system.
Refer to flows in sec. 4.6.
fig. 4.7.3-1 OH 4 O̲f̲f̲-̲l̲i̲n̲e̲ ̲T̲r̲o̲u̲b̲l̲e̲s̲h̲o̲o̲t̲i̲n̲g̲ ̲T̲r̲e̲e̲ sec. 4.7
Replacement Refer to sec. 4.4 for Crate, module and fan
replacement also for the normal state of
Controls/Indicators.
Refer to Installation manual for Panels etc.
Refer to Equipment handbook for straps and
switch settings for modules.
3270A/rt
…0f… Protocol Converter 1:3:3 LT/830118
Operation H PC
Tasks S.M.M.
sec. 2 Exerxise the power-up/down procedure and
the format and use of commands.
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…0f… Protocol Converter 1:4:1 LT/830120
Fautlfinding DI PC
Approach and P.U. requres a very high state of operation
analysis for transactions between end systems can
take place without the P.U. closing down.
An estimation of time required to bring the
system in operational mode again by trouble-
shooting should always be compared with the
time needed to replace the complete P.U.
Make as many observations as possible i.e.
Try to establish if both links have errors
- using verify - or if closed down then make
a note of how far the power-up procedure
can be brought - before you settle for a
diagnosis.
Use the Troubleshooting Trees - but do not
forget to think of what you are asked to
do - they are only aids.
3270A/rt
…0f… Protocol Converter 1:4:2 LT/830120
Use of Aids H PC
Exercise 1 S.M.M. Replace P.U. with spare P.U. - do verify
sec.4.4.1
Exercise 2 S.M.M. Run all module tests following Off-line Trouble-
sec.4.7.3 shooting Procedure
3270A/rt
…0f… Protocol Converter 1:4:3 LT/830120
Troubleshooting H PC
TBD
…0e… 3270A/rt
LT/830202
OVERVIEW 1:1:1-3 3x45 PC
Explain the purpose and taske of the PC.
Describe the message flow through the PC.
N/A
Classroom
L
OH, HO
…0e… 3270A/rt
LT/830202
HARDWARE 1:2:1-3 3x45 PC
Explain the configuration of the PC and sites.
Describe the modules which differs or are
not used in the CAMPS system.
N/A
Classroom
L
HO, OH
…0e… 3270A/rt
LT/830202
OPERATION 1:3:1-3 3x45 PC
Operate the PC from the maintenance VDU.
Perform preventive maintenance on the PC.
Use the Troubleshooting Tree.
Exercise
Classroom and site
L, H
OH, HO
PC Site Maintenance Manual
PC Equipment Handbook
…0e… 3270A/rt
LT/830202
Faultfinding 1:4:1-3 3x45 PC
Troubleshoot and replace to module level
using the available aids.
Exercise
Classroom and site
L, H
OH, HO
PC Site Maintenance Manual
PC Equipment Handbook
Protocol Converter
Instructor's Manual
Contract SHNMO-82-9205-INF
PC/IMA/001
Leif Thorsby
B]rge Hermansen
SHAPE, BHE, KPL, CL, LT
830202
1
830202
3270A/ktd …02… PC/IMA/001
…02… LT/830202…02… ii
…0e… PROTOCOL CONVERTER …02… …02… PC
830202 All Issue 1
…86…1 …02…
…02… …02…
