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Notes: CAMPS SYS DES SPEC
Names: »0484A «
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…02…CPS/SDS/001
…02…SRA/810115…02……02…
CAMPS SYSTEM DESIGN SPECIFICATION
…02……02…CAMPS
5.1.5 T̲h̲e̲ ̲I̲/̲O̲ ̲S̲u̲b̲s̲y̲s̲t̲e̲m̲
The I/O subsystem is composed of one Channel Unit (CU)
with a dualized (redundant) I/O bus configuration.
The system is equipped with two types of I/O controllers
(interfaces between the I/O buses and the I/O devices):
- Disk controllers, which via the Disk Controller
adapter interfaces the disk drivers to the I/O
system.
- Line Termination Units (LTU's), which via the V24/V28
adapters are used for driving the heavy communication
protocols towards the TARE-, CCIS-, and SCARS system.
The I/O subsystem interfaces to (fig. 5.1.5-1):
- the Processor System through the dualized CIA (sec.
5.1.5.1.1) - Data Channel (sec. 5.1.4.1.5) - MIA
(sec. 5.1.4.1.4.2) link.
- the SS&C system through the serial configuration
bus and the CCA (sec. 5.1.5.1.4).
- the TARE-, CCIS-, and SCARS-System via the V24/V28
adapters (sec. 5.1.5.1.3.2).
Fig. 5.1.5-1
THE I/O SYSTEM INTERFACES
5.1.5.1 D̲e̲s̲i̲g̲n̲ ̲&̲ ̲C̲o̲n̲s̲t̲r̲u̲c̲t̲i̲o̲n̲
The I/O subsystem has a design goal of being very efficient
in a transaction, on-line oriented environment. This
environment has constraints different from those of
a batch environment. The figure of merit in an on-line
system is the number of transactions/second/dollar
that can be handled by the system. We also wanted
an I/O subsystem that had low overhead, fast transfer
rates, no overruns, and no interrupts to the system
until a logical entity of work was completed (i.e.,
no character by character interrupts from the terminals).
The resulting design satisfied these goals by implementing
an I/O system that was extremely simple.
The heart of the CR80D I/O subsystem is the Data Channel.
All bulk I/O is done on a direct memory access (DMA)
basis. With the block size determined by the individual
application. All I/O controllers are buffered to some
degree so that all transfers over the I/O channel are
at memory speed (2M words/second) and never wait for
mechanical motion since the transfers always come from
a buffer in the I/O controller, rather than from the
actual I/O device.
For setup, control and status between PU and I/O controllers,
programmed I/O (direct from CPUs) can be used concurrently
with the Data Channel DMA transfers.
The channel does not execute channel programs as on
many systems, but it does do data transfer in parallel
with program execution. The memory system priority
on the PU Channel bus always permits I/O accesses (in
an on-line, transaction oriented environment, it is
rare that a system is not I/O bound).
In the following sections is given a detailed explanation
of the basic modules within a CU:
- CR80D Channel Interface Adapter (CIA)
- CR80D Disk Controller
- CR80D Disk Controller Adapter (DCA)
- CR80D Line Termination Unit (LTU)
- CR80D V24/V28 (L) Adapter
- CR80D Power Supply (PSU)
- CR80D Floppy disk Controller
- CR80D Floppy disk Controller Adapter
5.1.5.1.1 T̲h̲e̲ ̲C̲I̲A̲ ̲M̲o̲d̲u̲l̲e̲
The Channel Interface Adapter is the interface between
the Data Channel and the dual bus structure of the
Channel Unit (fig. 5.1.5.1.1-1). Two versions of the
CIA are available, one for interfacing the Data Bus
A (CIA-A) and one for interfacing the Data Bus B (CIA-B).
The two versions are functionally identical, but the
printed circuit board either has an edge connector
towards the A-Bus or the B-Bus (figs. 5.1.5.1.1-2 and
-3)
Fig. 5.1.5.1.1-1…01…D̲A̲T̲A̲ ̲C̲H̲A̲N̲N̲E̲L̲ ̲I̲N̲T̲E̲R̲F̲A̲C̲E̲S̲
Fig. 5.1.1.5.1.1-2…01…T̲h̲e̲ ̲C̲I̲A̲-̲A̲
Fig. 5.1.5.1.1-3…01…T̲h̲e̲ ̲C̲I̲A̲-̲B̲
The main function of the CIA is to transfer data between
the I/O bus and the Data Channel. The CIA is master
to the I/O bus but slave to the Data Channel. This
means that a transfer is initiated from the Data Channel,
which then awaits for the CIA to complete the transfer.
Interrupts from the Channel Unit modules are stored
in the CIA to be fetched by the Data Channel.
The CIA also undertakes several support functions towards
the I/O Bus:
a) Clock generation
b) Power supervision
c) Power up reset
d) Bus termination
The functional blocks of the CIA are shown in fig.
5.1.5.1.1-4.
D̲a̲t̲a̲ ̲T̲r̲a̲n̲s̲f̲e̲r̲
The information path of the Data Channel is shared
by addresses, data and error messages. Thus a transfer
is divided into three phases. This transfer description
is mainly a repetition of parts of sec. 5.1.4.1.4.2.
Fig. 5.1.5.1.1-4
The CIA Module
A̲d̲d̲r̲e̲s̲s̲ ̲P̲h̲a̲s̲e̲
Three different types of addressing are defined for
the Data Channel:
- single
- set up
- reduced
A single type address is three bytes which are received
on the information path. The address is stored temporarily
in the address register and the four most significant
bits are compared to the CIA-number on a switch array.
If they match, the address is forwarded to the I/O
Bus and the transfer can proceed.
If the control bits on the information path indicate
that the address is a "set-up", then it is stored in
the Reduced Address Register (RAR) instead of being
transmitted on the Data Bus. The address is now used
as a base to the following reduced address transfers.
A reduced address is only one byte and it contains
only the CIA-number. When a CIA recognizes its number
in a reduced address, it transmits the RAR on the I/O
Bus.
The RAR is incremented after each memory transfer to
facilitate block transfers of up to 256 words. When
the lower 8 bits of the RAR reach 255, further reduced
address transfers must be preceded by a new set up.
All received addresses are parity checked.
D̲a̲t̲a̲ ̲P̲h̲a̲s̲e̲
Besides giving the address type, the control bits of
the address phase also specifies whether it is a read
or write operation and whether it is a memory or I/O
transfer. This information is transmitted to the I/O
Bus simultaneously with the address. The data phase
is a transfer of two bytes, lower byte first and then
upper byte.
a) R̲e̲a̲d̲ ̲o̲p̲e̲r̲a̲t̲i̲o̲n̲
When the address is stable on the Data Bus, the
CR80D handshaking procedure (sec. 5.1.3.1) is initiated
and data is fetched. The parity is checked and
the data is transmitted via the transmit register
to the Data Channel with a regenerated parity.
b) W̲r̲i̲t̲e̲ ̲o̲p̲e̲r̲a̲t̲i̲o̲n̲
The data of a write operation arrives from the
Data Channel just after the address and is loaded
in the data register. A parity check is performed
and the data is then forwarded to the I/O Bus if
parity was OK.
T̲e̲r̲m̲i̲n̲a̲t̲i̲o̲n̲ ̲P̲h̲a̲s̲e̲
The main purpose of the termination phase is to make
it possible to determine whether a transfer succeeded
or not.
Two types of errors are considered:
a) No response detected by time out
b) Bit error detected by parity
The termination phase is characterized by an acknowledge
on the DA-line of the Data Channel.
Normally the CIA issues the DA-signal when the transfer
is completed, but if the maximum response time is exceeded,
it is issued by the Data Channel. The DA-signal resets
the connected CIA to expect a new address phase. This
time out condition typically arises when the addressed
module is not present.
If the CIA detects a parity error in the data phase
during a write-operation or on the I/O Bus during a
read-operation, an error message is sent on the information
path simultaneously with the DA-signal. Parity error
in the address phase does not result in an error message,
because either the CIA-number or control information
might be invalid.
I̲n̲t̲e̲r̲r̲u̲p̲t̲ ̲H̲a̲n̲d̲l̲i̲n̲g̲
Interrupts from I/O-modules in the Channel Unit are
received according to the CR80D Main Bus specifications
(sec. 5.1.3.1). This implies that the interrupting
module address is received in serial form. If two
modules interrupt simultaneously, the one with the
highest priority and address is chosen.
When an interrupt address has been shifted into the
interrupt register, further interrupts are disabled
until the address is fetched by the Data Channel.
The fetch command, interrupt request (IRQ), is received
from the Data Channel in serial form. It contains
a four bit address which is compared to the CIA-number
from the switch array. If they equal each other, the
content of the interrupt register is transmitted in
serial form to the Data Channel through the interrupt
transmit register. If the interrupt register is empty
or if a parity error has been detected in the fetch
command, the interrupt address is replaced by a status
message.
I̲/̲O̲ ̲B̲u̲s̲ ̲S̲u̲p̲p̲o̲r̲t̲
The CIA is the only address sourcing unit connected
to the I/O Bus and this eliminates the need for bus
arbitration. The remaining support functions are described
in the following.
C̲l̲o̲c̲k̲ ̲G̲e̲n̲e̲r̲a̲t̲i̲o̲n̲
The clock signals ]1 and ]2 on the I/O Bus are 1MHz
and 8 MHz, respectively. They are derived from a 16
MHz crystal oscillator on the CIA, which also provides
the CIA-sequencer with basic timing. [1 and ]2 are
the time base for interrupt receiving on the I/O Bus.
P̲o̲w̲e̲r̲ ̲S̲u̲p̲e̲r̲v̲i̲s̲i̲o̲n̲
The CIA includes a voltage comparator circuit, which
monitors the power inputs (+5V, +12V and -12V). If
a drop occurs in one of the three voltages that is
not so severe as to cause power up reset, a Power Failure
flip-flop (PFF) is set and a power failure interrupt
is issued on the next interrupt fetch command from
the Data Channel.
As long as the PFF is set a red LED on the front panel
of the CIA is activated.
A special interrupt fetch command is used to reset
the PFF.
P̲o̲w̲e̲r̲ ̲u̲p̲ ̲R̲e̲s̲e̲t̲
CR80D-modules connected to a dual bus structure generate
power up reset on their own. The CIA, however, can
also be used as interface towards a single bus, and
therefore a power up reset (not used in this system)
is carried to the I/O Bus.
The power up reset observes the Master Clear specifications
of the CR80D Main Bus (sec. 5.1.3.1).
I̲/̲O̲ ̲B̲u̲s̲ ̲T̲e̲r̲m̲i̲n̲a̲t̲i̲o̲n̲
The physical appearance of the I/O Bus is a motherboard
and the signals are electrically terminated in one
end by the CIA and in the other by a terminating board,
the MBT.
5.1.5.1.1.1 M̲e̲c̲h̲a̲n̲i̲c̲a̲l̲ ̲&̲ ̲E̲l̲e̲c̲t̲r̲i̲c̲a̲l̲ ̲S̲p̲e̲c̲i̲f̲i̲c̲a̲t̲i̲o̲n̲s̲
M̲e̲c̲h̲a̲n̲i̲c̲a̲l̲ ̲D̲i̲m̲e̲n̲s̲i̲o̲n̲s̲ ̲o̲f̲ ̲t̲h̲e̲ ̲C̲I̲A̲
Height: 263 mm
Width: 17,1 mm ( l Module)
Depth: 280 mm
E̲l̲e̲c̲t̲r̲i̲c̲a̲l̲ ̲S̲p̲e̲c̲i̲f̲i̲c̲a̲t̲i̲o̲n̲s̲ ̲f̲o̲r̲ ̲t̲h̲e̲ ̲C̲I̲A̲
P̲o̲w̲e̲r̲ ̲C̲o̲n̲s̲u̲m̲p̲t̲i̲o̲n̲
+ 5V: 3 A
+ 12V: 80 mA
- 12V: 80 mA
C̲I̲A̲/̲D̲a̲t̲a̲ ̲C̲h̲a̲n̲n̲e̲l̲ ̲S̲i̲g̲n̲a̲l̲s̲
The Data Channel signals are pulsed with a nominal
pulse width of 62.5 ns.
Transformer driver specifications:
I…0f…OL…0e… max …0f…-…0e… 100 mA
V…0f…O…0e… max …0f…-…0e… 10 V
Receiver specification:
Sensitivity 0.2 V
Hysteresis 30 mV
The signals are terminated in the PU-end and in the
CU end by a 120 Ohm shunt resistor.
5.1.5.1.2 T̲h̲e̲ ̲D̲i̲s̲k̲ ̲C̲o̲n̲t̲r̲o̲l̲l̲e̲r̲ ̲a̲n̲d̲ ̲t̲h̲e̲ ̲D̲i̲s̲k̲ ̲C̲o̲n̲t̲r̲o̲l̲l̲e̲r̲ ̲A̲d̲a̲p̲t̲e̲r̲
(̲D̲C̲A̲)̲
The Disk Controller and the DCA constitute the complete
interface between the CR80D I/O buses and up to 4 disk
drives. Any combination of drives from Control Data
Corporation's (CDC) SMD, MMD, and CMD families is possible.
5.1.5.1.2.1 T̲h̲e̲ ̲D̲i̲s̲k̲ ̲C̲o̲n̲t̲r̲o̲l̲l̲e̲r̲ ̲M̲o̲d̲u̲l̲e̲
The Disk Controller module consists of two functionally
independent modules (ref. fig. 5.1.5.1.2.1-1):
- an I/O module (disk controller) occupying 1 of
the possible 62 in-crate module addresses.
- a RAM module forming 16K (32K) of the possible
1M words of in-crate memory.
The controller receives commands and delivers status
via its own bus control logic, whereas instructions
concerning disk operations, are fetched from the RAM.
The RAM is furthermore used as a data buffer.
Fig. 5.1.5.1.2.1-1
The Disk Controller
The controller contains two independent I/O bus ports
implemented by physically separate IC packages. Thus
no interface chip can simultaneously cause failure
of both ports. Each port of the controller has a 6-bit
configurable controller number, as well as a 2-bit
interrupt priority setting. The only requirement is
that the controller must be assigned a controller number
distinct from controller numbers located within the
same channel unit.
A power-on condition causes a controller reset and
also gives an interrupt to one of the two Processor
Units to which it is attached. The output of the Power
On detection circuit is also used to control all the
Data bus transceivers so that a controller being powered
down will not cause interference on the I/O buses during
the power transient. This is possible because the
power circuit operates with very low supply voltage
and special transceivers are used which correctly stay
in a high impedance state as long as the supply voltage
is too low for correct functioning of the board logic
circuitry.
Logically only one of the two ports of the controller
is active, while the other port, the alternative, is
utilized in the event of a path failure of the primary
port. There is an "ownership" bit associated with
each port which indicates whether it is the primary
port or the alternate. Ownership is changed only by
a PU issuing a TAKE OWNERSHIP I/O command. Executing
this special command will cause the controller to define
its primary and alternate port designation and to do
a controller reset. Any attempt to use a controller
which is not owned by a given Processor Unit will result
in an ownership violation. If a Processor Unit determines
that a controller is malfunctioning on its Data Channel
it can issue a DISABLE PORT command which logically
disconnects the port from that I/O controller. However,
this does not affect the ownership status.
Thus, if the problem is within the port, the alternate
path can be used, but if the problem is in the common
part of the controller, ownership is not forced upon
the other Processor Unit.
D̲i̲s̲k̲ ̲C̲o̲n̲t̲r̲o̲l̲l̲e̲r̲ ̲S̲e̲c̲t̲i̲o̲n̲
The disk controller part is a standard I/O module,
called DIF (Disk I/F and Formatter), which responds
to I/O commands from the currently selected I/O bus.
The controller interfaces to the disk adaptor (DCA)
for connection of max. 4 disk drives in daisy chain.
The DIF (Disk I/F and formatter) provides all controller
and formatter functions for the disk drives connected.
When a daisy chain configuration is used (Fig. 5.1.5.1.2.1-2),
only one drive may be written to or read from at a
time. However, overlapped seeks are possible, since
all drives are at all times monitored for "seek over"
conditions.
The communication with a Processor Unit is carried
out via the I/O bus (I/O-commands), while memory is
accessed via the internal micro-bus. The memory is
used for data transfer to and from disk and for information
between a Processor Unit and the DIF.
An o̲p̲e̲r̲a̲t̲i̲o̲n̲ is defined as a task for the DIF concerning
a specified drive. An operation may include for instance
reading or writing data or initiation of a seek (move
of recording heads). During an operation, the DIF
is considered busy.
When the DIF is not busy, a Processor Unit CPU may
initiate an operation by an I/O-command. Information
about the desired operation must have been stored in
the memory by the CPU. As long as the DIF is busy
with the operation, it will not receive requests for
more operations. The DIF indicates by a bit in its
status word whether it is busy or not. If enabled,
an interrupt is sent to the CPU when the operation
has been completed (Operation Complete (OPC) interrupt).
Return information to the CPU primarily consists of:
1) A status word concerning the DIF and the latest
operation, and
2) A unit flag word concerning the disk drives.
Interrupts may be caused by certain changes in the
status word (OPC - and ICM (Illegal Command Interrupts)
and by the unit flags (unit interrupt). Unit interrupts
and OPC interrupt may be masked off.
The DIF provides generation and checking of a 2 byte
CRC code added to the address field as well as to the
data field of each sector.
During an operation, various checks are carried out
considering the status lines of the drive, memory parity,
CRC check, validity of address field etc.
Fig. 5.1.5.1.2.1-2
Max. Disk Drive Configuration
The DIF consists of:
- a micro-programmed disk control processor
- a data synchronizer and serial/parallel converter
- drive control logics and
- bus control logics
The control processor interprets instructions stored
in the RAM memory, controls and monitors the drives,
performs word and byte oriented formatting and data
transfers, and does all the sequencing of operations.
The processor includes an ALU (Arithmetic & Logic
Unit) and 16 registers for handling memory addresses
and disk parameters such as:
- cylinder number
- head number
- sector number
- drive status etc.
The data synchronizer and serial/parallel converter
include shift register, CRC generator/checker, byte
synchronizer and sequencer for the serial data and
clock.
The drive control transmits control signals as well
as cylinder, head, and sector numbers from the control
processor. The status of the drive(s) is received
and transferred to the control processor. Furthermore,
the drive control transfers "seek complete" and "drive
not busy" conditions to the bus control.
The bus control logic (disk) interprets commands from
the internal I/O bus. It puts drive and controller
status on the internal I/O bus, requests the control
processor for operations, sets interrupt masks etc.
Furthermore, it generates interrupts in accordance
with status and masks.
R̲A̲M̲ ̲M̲e̲m̲o̲r̲y̲ ̲S̲e̲c̲t̲i̲o̲n̲
The RAM memory part consists of:
- a RAM
- RAM control
- address and data multiplexers
- bus control logic
- switch array
The RAM part of the Disk Controller module forms 16
K or 32 K words (type dependent) of the memory space
connected to the currently selected bus. Each word
consists of 16 bit data and 2 bit parity in accordance
with CR80D standard.
The RAM is dual ported. One port is connected to the
current I/O bus, and one port is connected to the disk
controller, cf. fig. 5.1.5.1.2.1-1.
The RAM Control switches via the multiplexers the access
over between the disk controller and the internal I/O
bus in turn. For this purpose the RAM Control receives
requests from the bus control logic (RAM) and the disk
control processor. The bus control logic (RAM) transfers
data and address between the internal I/O bus and the
RAM.
Memory transfer rate:
From/to a disk: 625 Kwords/second
From/to I/O Bus: 2 Mwords/second
The actual address space covered by the RAM is set
by switches on the printed circuit board (fig. 5.1.5.1.2.1-3):
switch no: 1 2 3 4 5 6
bank select, AD19-AD18
(switch 6 = MSB)
32K section within selected
bank: SW4 = AD17
SW3 = AD16
SW2 = AD15
For 16K version: SW 1 = AD14
For 32K version: SW 1 = "don't care"
Fig. 5.1.5.1.2.1-3…01…R̲A̲M̲ ̲A̲D̲D̲R̲E̲S̲S̲ ̲S̲W̲I̲T̲C̲H̲
I̲/̲O̲ ̲B̲u̲s̲ ̲P̲o̲r̲t̲
The RAM will respond to the bus, only if AD 19-18 and
AD17-14 (for 32K version: AD17-15) match the switch
settings and LS1-0 = 00 (indicating I/O)
Response time from TRQ(L) = 0 and AE(L) = 0
to RS(L) = 0: max. 900 ns
typ. 450 ns
(These signals are described in sec. 5.1.3).
D̲i̲s̲k̲ ̲C̲o̲n̲t̲r̲o̲l̲l̲e̲r̲ ̲P̲o̲r̲t̲
The RAM will always respond to the controller port.
For 16K version, the lower 14 address bits are used,
and for 32K version, the lower 15 address bits are
used as address relative to the start of the RAM space
included.
A brief description of the commands issued from a PU
to the Disk Controller is given on the following pages.
The Address/Command format is shown in fig. 5.1.5.1.2.1-4,
and the Command Code interpretation is shown in table
5.1.5.1.2.1-5.
R̲e̲a̲d̲ ̲S̲t̲a̲t̲u̲s̲ ̲W̲o̲r̲d̲
The DIF puts its status word on the mainbus data lines
DA15 - DA0.
R̲e̲a̲d̲ ̲S̲t̲a̲t̲u̲s̲ ̲W̲o̲r̲d̲,̲ ̲C̲l̲e̲a̲r̲ ̲I̲n̲t̲e̲r̲r̲u̲p̲t̲
As "Read Status Word" except that the interrupt flag
internal in the DIF is cleared, thus enabling the DIF
to send further interrupts. This is a message to the
DIF, that an interrupt is received.
R̲e̲a̲d̲ ̲U̲n̲i̲t̲ ̲F̲l̲a̲g̲s̲
The DIF puts the unit flag (4 bit) on the mainbus data
lines DA3-DA0.
R̲e̲a̲d̲ ̲U̲n̲i̲t̲ ̲F̲l̲a̲g̲s̲,̲ ̲C̲l̲e̲a̲r̲ ̲I̲n̲t̲e̲r̲r̲u̲p̲t̲
As "Read Unit Flags" except that the interrupt flag
internal in the DIF is cleared.
R̲e̲s̲e̲t̲
This command immediately forces the DIF to execute
the start up routine.
R/W: '0' = input PU - DIF
'1' = output PU - DIF
OPC interrupt: During output (R/W = 1) - except RESET
- this bit is interpreted as the mask
bit for OPC - interrupt:
'0' = enable
'1' = disable
AD10 is ignored if R/W = 0
Command code: These two bits specify together with
R/W the command.
Module address: Specifies the module to which the
I/O
is related. The module address is
selected by means of switches in the
DIF.
Fig. 5.1.5.1.2.1-4…01…A̲D̲D̲R̲E̲S̲S̲ ̲F̲O̲R̲M̲A̲T̲
R/W Command Code Command
̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲
̲ ̲ ̲ ̲ ̲ ̲ ̲
0 0 0 read status word.
0 0 1 read status word, clear interrupt.
0 0 0 read unit flags.
0 1 1 read unit flags, clear interrupt.
1 0 0 reset.
1 0 1 load unit interrupt mask
1 1 0 load instruction pointer,
initiate operation.
1 1 1 terminate operation.
Table 5.1.5.1.2.1-5…01…C̲O̲M̲M̲A̲N̲D̲ ̲I̲N̲T̲E̲R̲P̲R̲E̲T̲A̲T̲I̲O̲N̲
L̲o̲a̲d̲ ̲U̲n̲i̲t̲ ̲I̲n̲t̲e̲r̲r̲u̲p̲t̲ ̲M̲a̲s̲k̲
The mainbus datalines DA3-DAO are loaded into the unit
interrupt mask (UIM) register. This register determines,
which of the unit flags may cause interrupt or not.
L̲o̲a̲d̲ ̲I̲n̲s̲t̲r̲u̲c̲t̲i̲o̲n̲ ̲P̲o̲i̲n̲t̲e̲r̲,̲ ̲I̲n̲i̲t̲i̲a̲t̲e̲ ̲O̲p̲e̲r̲a̲t̲i̲o̲n̲
The mainbus datalines DA15 - DAO are interpreted as
the start address of an instruction field in the memory.
The operation specified here is then carried out.
The DIF will by busy until the operation has been
completed, and if enabled an OPC interrupt is sent
when the DIF is ready.
If this command is issued while the DIF is busy, it
will be ignored, except that the ICM bit of the status
word is set and an interrupt is sent. The current
operation is not affected.
T̲e̲r̲m̲i̲n̲a̲t̲e̲ ̲o̲p̲e̲r̲a̲t̲i̲o̲n̲
An internal termination flag is set, and the current
operation will be terminated when allowed. Depending
on the kind and progress of the current operation,
this may be completed in a normal way regardless of
the terminate command. When the DIF is ready (i.e.
operation is over), a bit in the status word tells,
if the operation has been terminated by the terminate
command. Also in this case an OPC interrupt is sent
if enabled.
5.1.5.1.2.2 T̲h̲e̲ ̲D̲C̲A̲
The DCA (Disk Controller Adapter) is the interface
between the Disk Controller and one or more (max. 4)
disk drives, as shown on fig. 5.1.5.1.2.1-2.
The DCA is connected to the disk drive(s) via at least
2 flat cables and a maximum of 5 flat cables (4 disks
connected). One flat cable (the A cable), is a common
bus (daisy chain) for all connected drives. Furthermore,
each drive is connected to the DCA via an individual
flat cable (the B cable).
The A cable is a 30 twisted pair flat cable. Each
B cable is a 26 conductor flat cable with ground plane
and drain wire.
A disk operation performed by the Disk Controller has
to contain information about:
- The disk drive to be used (1 of 4).
- The disk cylinder number (head position)
- The Head number and
- The disk sector number.
These control signals, of which not all have to be
used in every operation, are forwarded to the connected
drive(s) via the DCA control register and the common
A cable.
The disk drive number latched in the control register
selects via the Data & Clock multiplexer and the status
multiplexer the B cable connected to the selected drive.
The B cable transfers serial data & clock signals
to/from the selected drive plus status signals such
as "seek end" and "unit selected" from the selected
drive.
The "seek end" status signal from all connected drives
is, via the Drive interrupt circuitry, sent to the
Controller as an interrupt condition (if not masked)
for a Processor Unit. Another status signal which
causes an interrupt (if not masked) to a Processor
Unit is the "Unit Ready" signal transferred via the
A cable (only accessed from the selected drive).
The DCA furthermore contains circuitry to monitor supply
voltages and clock signals. If a power or clock failure
in the controller or the DCA is detected then the connected
drive(s) is (are) disabled.
Fig. 5.1.5.1.2.2-1
The DCA Module
5.1.5.1.2.3 M̲e̲c̲h̲a̲n̲i̲c̲a̲l̲ ̲&̲ ̲E̲l̲e̲c̲t̲r̲i̲c̲a̲l̲ ̲S̲p̲e̲c̲i̲f̲i̲c̲a̲t̲i̲o̲n̲s̲
M̲e̲c̲h̲a̲n̲i̲c̲a̲l̲ ̲d̲i̲m̲e̲n̲s̲i̲o̲n̲s̲ ̲o̲f̲ ̲t̲h̲e̲ ̲D̲i̲s̲k̲ ̲C̲o̲n̲t̲r̲o̲l̲l̲e̲r̲
Height: 412,6 mm ( 10 U crate)
Width: 17,1 mm ( 1 Module)
Depth: 305 mm
The Disk Controller is a front crate mounted module.
P̲o̲w̲e̲r̲ ̲C̲o̲n̲s̲u̲m̲p̲t̲i̲o̲n̲ ̲o̲f̲ ̲t̲h̲e̲ ̲D̲i̲s̲k̲ ̲C̲o̲n̲t̲r̲o̲l̲l̲e̲r̲
+ 5V: 8 A
+12U: 0.5 A
M̲e̲c̲h̲a̲n̲i̲c̲a̲l̲ ̲d̲i̲m̲e̲n̲s̲i̲o̲n̲s̲ ̲o̲f̲ ̲t̲h̲e̲ ̲D̲C̲A̲
Height: 412,6 mm ( 10 U crate)
Width: 17,1 mm ( 1 Module)
Depth: 160 mm
The DCA is a rear crate mounted module.
P̲o̲w̲e̲r̲ ̲c̲o̲n̲s̲u̲m̲p̲t̲i̲o̲n̲ ̲o̲f̲ ̲t̲h̲e̲ ̲D̲C̲A̲
+ 5V: 1,5 A
-12V: 0,3 A
E̲l̲e̲c̲t̲r̲i̲c̲a̲l̲ ̲s̲p̲e̲c̲i̲f̲i̲c̲a̲t̲i̲o̲n̲ ̲o̲f̲ ̲t̲h̲e̲ ̲D̲i̲s̲k̲ ̲C̲o̲n̲t̲r̲o̲l̲l̲e̲r̲/̲D̲C̲A̲
F̲l̲a̲t̲ ̲C̲a̲b̲l̲e̲ ̲C̲o̲n̲n̲e̲c̲t̲i̲o̲n̲ ̲B̲u̲s̲
TBD.
5.1.5.1.3 T̲h̲e̲ ̲L̲i̲n̲e̲ ̲T̲e̲r̲m̲i̲n̲a̲t̲i̲o̲n̲ ̲U̲n̲i̲t̲ ̲(̲L̲T̲U̲)̲ ̲a̲n̲d̲ ̲t̲h̲e̲ ̲V̲2̲4̲/̲V̲2̲8̲(̲L̲)̲
A̲d̲a̲p̲t̲e̲r̲
The LTU and the V24/V28(L) Adapter constitutes the
heavy protocol driving interface between the CR80D
I/O buses and up to 4 external V24/V28 communication
lines. The 4 communication lines can be served with
a speed of up to 9,6 KBaud full duplex on each channel,
dependent of protocol.
5.1.5.1.3.1 T̲h̲e̲ ̲L̲T̲U̲ ̲M̲o̲d̲u̲l̲e̲
The LTU is a standard CR80D I/O module occupying 1
of 62 possible in-crate module addresses. It communicates
with the Processor Unit CPUs via FIFO oriented block
transfers. A block diagram of the LTU is shown on
fig. 5.1.5.1.3.1-1.
The LTU is divided into two major parts:
- The interface circuitry towards the I/O bus.
- The V24/V28 communication controlling microprocessor
part.
Fig. 5.1.5.1.3.1-1
The LTU Module
Communication between the I/O bus interface and the
microprocessor section is done via a RAM area, called
the shared RAM, on the LTU.
The I/O bus interface contains two independent I/O
bus ports implemented by physically separate IC packages.
Thus no interface chip can simultaneously cause failure
of both ports. Each port of the LTU has a 6-bit configurable
controller number, as well as an interrupt priority
setting. The only requirement is that the LTU must
be assigned an I/O number distinct from I/O controller
numbers located within the same channel unit.
The functions of the dual I/O bus ports plus the Bus
Select circuitry are equal to the dual port description
given in sec. 5.1.5.1.2.1 (The Disk Controller).
Furthermore, the I/O interface circuitry contains:
- An Interface Control (incl. Interrupt Logic)
- An Address Counter
- A Sequencer (micro programmed)
The microprocessor part contains:
- A system RAM
- A Bootload PROM
- A microprocessor section
When a LTU is addressed the Interface Control takes
over the control of the LTU. It handles all accesses
from a PU, and controls that no new access is started
before the current is finished. Upon address recognition,
the Interface Control gives a start signal to the Sequencer.
The Sequencer is controlled by a microprogram. This
program handles the access to the shared RAM, Loading
of the Address Counter, parity control and the hand
shaking between a PU and the microprocessor section
when sharing the shared RAM area. Part of the addressing
bits (bit 6-11) are by the Sequencer decoded as an
instruction to the LTU.
The Address Counter is a 16 bit up/down counter which
holds the next address in shared RAM to be accessed
from a PU. The loading is as mentioned controlled
by the Sequencer which when it detects a "Load Address
counter" instruction, loads the Address Counter with
the contents of the I/O bus Data lines.
The Shared Ram area is a 16K x 9 bits (8 bit data +
1 parity bit) dynamic RAM. It is the data exchange
interface between I/O bus and the LTU microprocessor
part. Access to this RAM is controlled by the Shared
RAM Control Logic. Normally, the microprocessor part
has direct access to the Shared RAM, but if a PU wants
to access this area, a bus request signal is sent from
the Sequencer. As soon as the microprocessor part
has finished a possible access to the shared RAM, the
bus is shifted over to the I/O bus and controlled by
the Sequencer. After finishing the access, the RAM
bus is returned to the microprocessor part.
The microprocessor part of the LTU runs the V24/V28
communication ports transferring data to/from the Shared
Ram area. The firmware programs controlling the microprocessor
are resident in the System RAM which is a 16K x 9 bit
(8 bit data + 1 bit parity) dynamic RAM.
The firmware is loaded to the system RAM due to a multi
step bootload procedure. The PU issues a "boot load"
command to the LTU. This puts the LTU in bootload
mode, having the effect that all microprocessor section
reads are performed in the bootload PROM ("shadow"
PROM) and all writes are done to the System RAM. The
bootload PROM is a "shadow PROM" because the PROM in
the bootload mode during read operations occupies the
8K lower bytes of the system RAM. The microprocessor
now executes the programs resident in the PROM starting
with an offline diagnostic test program. If the test
reveals no failures then the PROM resident bootload
program is executed. If the test detects a failure,
no bootloading is performed. The bootload program
takes care of loading the LTU firmware from the Shared
RAM, to which it has been loaded from a PU, to the
System RAM. Handshaking between a PU and the microprocessor
part during bootload is performed via a status word
in the shared RAM. When the bootload has finished,
the LTU is set in normal mode by a "programmed clear"
command from the PU, and the LTU starts executing the
firmware program.
The microprocessor section contains hardware necessary
to serve the serial communication channels:
- Serial input/output circuitry, which converts parallel
data to serial data for transmission and vice versa
for reception.
- DMA circuitry for fast data transfer between serial
input/output circuitry and shared RAM.
- Timer circuitry for generating the different baud
clocks for each channel. Baud rates are under
Software control.
- Parallel I/O circuitry giving an extended set of
control signals on the V24/V28 communication lines.
Via the Transceiver block, the electrical conversion
between TTL level signals and line level signals and
vice versa is performed. These Transceivers are standard
circuitry in accordance with CCITT's V24/V28 and EIA's
RS-232C recommendations.
In the following, a short description of the commands
issued from a PU to control the LTU is given.
Fig. 5.1.5.1.3.1-2 shows the Address format on the
I/O bus when addressing a LTU, and table 5.15.1.3.1-3
gives the different command interpretations.
P̲r̲o̲g̲r̲a̲m̲m̲e̲d̲ ̲C̲l̲e̲a̲r̲
This command makes the module go through an overall
clear routine. This clear command does not have any
effect on the data stored in the RAM areas. The Address
Counter will be reset and point at location 0 in the
shared RAM.
B̲o̲o̲t̲l̲o̲a̲d̲ ̲C̲o̲m̲m̲a̲n̲d̲
By this command, the module first goes through the
clear routine, and then sets the LTU in bootload mode.
Before the bootload operation takes place, the bootloader
performs an off line diagnostic self test to ensure
that there is no failure in the module.
I̲n̲t̲e̲r̲r̲u̲p̲t̲ ̲R̲e̲q̲u̲e̲s̲t̲
The result of this command is an interrupt issued to
the LTU microprocessor.
"0" data transfer PU - LTU
R/W: "1" data transfer PU - LTU
Module type: LS1 "0" I/O Module
LS0 "0"
Command Code: These 6 bits together with R/W specify
the actual command to the LTU.
Module address: The 6 bits together with LS1 and LS0
is the module address. The module
address is selectable by means of
switches.
Fig. 5.1.5.1.3.1-2…01…A̲D̲D̲R̲E̲S̲S̲ ̲F̲O̲R̲M̲A̲T̲
̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲
̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲
ADDR. 6-11
R/W 11 10 9 8 7 6 Command
̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲
̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲
0 l 0 0 0 0 0 Programmed clear
0 1 1 0 0 0 0 Set module in Bootload
Mode
0 0 1 0 0 0 0 Interrupt request to
micro-
processor.
1 0 0 0 0 1 1 Load Address Counter
0 0 0 0 0 0 0 Read Status Word B(0),
B(1), P 2
Read word B(P), B(P+1)
0 0 0 0 1 0 0 Fetch word B(P+2), B(P+3)
0 0 0 0 1 0 1 Read Lower Byte B(P)
P P+1
1 0 0 1 0 0 0 Write word B(P), B(P+1)
P P+2
1 0 0 0 0 0 1 Write lower byte B(P),
P P+1
0 0 0 1 0 1 1 Read Parity Status
̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲
̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲
Table 5.1.5.1.3.1-3…01…C̲O̲M̲M̲A̲N̲D̲ ̲I̲N̲T̲E̲R̲P̲R̲E̲T̲A̲T̲I̲O̲N̲
L̲o̲a̲d̲ ̲A̲d̲d̲r̲e̲s̲s̲ ̲C̲o̲u̲n̲t̲e̲r̲
Before an access, read or write, to the shared RAM
can be performed by a PU, it is necessary to load the
Address Counter with an address pointing to the location
in shared RAM where the access is to take place. The
address loaded by this command is the contents of the
I/O bus Data lines. Since the size of the Shared RAM
is 16K bytes, the "pointer" must have a value:
0 …0f…-…0e… pointer …0f…-…0e… 3FFF Hex.
R̲e̲a̲d̲ ̲S̲t̲a̲t̲u̲s̲ ̲W̲o̲r̲d̲ ̲B̲(̲0̲)̲,̲ ̲B̲(̲1̲)̲,̲ ̲P̲ ̲ ̲2̲
This command resets the pointer (P) (held in Address
counter) and reads the Status word contained in the
bytes B(0) and B(1). The pointer is auto incremented
to 2.
R̲e̲a̲d̲ ̲W̲o̲r̲d̲ ̲B̲(̲P̲)̲,̲ ̲B̲(̲P̲+̲1̲)̲,̲ ̲F̲e̲t̲c̲h̲ ̲B̲(̲P̲+̲2̲)̲,̲ ̲B̲(̲P̲+̲3̲)̲
This command reads a word (two bytes) from the shared
RAM location addressed by the pointer. To give faster
response to the PU, the next word is fetched and kept
ready for the next transfer.
R̲e̲a̲d̲ ̲L̲o̲w̲e̲r̲ ̲B̲y̲t̲e̲ ̲B̲(̲P̲)̲,̲ ̲P̲ ̲ ̲P̲+̲1̲
This command reads 1 byte from the shared RAM location
to which the pointer points. The result is placed
in the lower part of the I/O bus data lines. The pointer
is incremented by one.
W̲r̲i̲t̲e̲ ̲W̲o̲r̲d̲ ̲B̲(̲P̲)̲,̲ ̲B̲(̲P̲+̲1̲)̲,̲ ̲P̲ ̲ ̲P̲+̲2̲
This command writes a word (2 bytes) to the shared
RAM location to which the pointer points. To give
faster response, the data is latched and response sent
to the PU. Then the data is stored in the RAM. The
pointer is incremented by 2.
W̲r̲i̲t̲e̲ ̲L̲o̲w̲e̲r̲ ̲B̲y̲t̲e̲ ̲B̲(̲B̲)̲,̲ ̲P̲ ̲ ̲ ̲P̲+̲1̲
This command writes the lower byte of the I/O bus data
lines into the shared RAM location addressed by the
pointer. Data is latched to give faster response.
The pointer is incremented by one.
W̲r̲i̲t̲e̲ ̲U̲p̲p̲e̲r̲ ̲B̲y̲t̲e̲ ̲B̲(̲P̲)̲,̲ ̲P̲ ̲ ̲ ̲P̲+̲1̲
This command writes the upper byte of the I/O bus data
lines into the shared RAM location to which the pointer
points. Data is latched to give faster response.
The pointer is incremented by one.
R̲e̲a̲d̲ ̲P̲a̲r̲i̲t̲y̲ ̲S̲t̲a̲t̲u̲s̲
This command reads the parity status. If there has
been a parity error in any of the two RAM areas, the
status word will be 01 Hex. If no error the status
word will be 00 Hex.
5.1.5.1.3.2 T̲h̲e̲ ̲V̲2̲4̲/̲V̲2̲8̲(̲L̲)̲ ̲A̲d̲a̲p̲t̲e̲r̲
TBD.
5.1.5.1.3.3 M̲e̲c̲h̲a̲n̲i̲c̲a̲l̲ ̲&̲ ̲E̲l̲e̲c̲t̲r̲i̲c̲a̲l̲ ̲S̲p̲e̲c̲i̲f̲i̲c̲a̲t̲i̲o̲n̲s̲
M̲e̲c̲h̲a̲n̲i̲c̲a̲l̲ ̲D̲i̲m̲e̲n̲s̲i̲o̲n̲s̲ ̲o̲f̲ ̲t̲h̲e̲ ̲L̲T̲U̲
Height: 412,6 mm ( 10 U crate)
Width: 17,1 mm ( 1 Module)
Depth: 305 mm
The LTU is a front crate mounted module.
P̲o̲w̲e̲r̲ ̲C̲o̲n̲s̲u̲m̲p̲t̲i̲o̲n̲ ̲o̲f̲ ̲t̲h̲e̲ ̲L̲T̲U̲
+ 5V: 4 A
+12V: 0,25 A
-12V: 0,15 A
M̲e̲c̲h̲a̲n̲i̲c̲a̲l̲ ̲D̲i̲m̲e̲n̲s̲i̲o̲n̲s̲ ̲o̲f̲ ̲t̲h̲e̲ ̲V̲2̲4̲/̲V̲2̲8̲(̲L̲)̲ ̲A̲d̲a̲p̲t̲e̲r̲
Height: 412,6 mm ( 10 U crate)
Width: 17,1 mm ( 1 Module)
Depth: 160 mm
The Adapter is a rear crate mounted module.
P̲o̲w̲e̲r̲ ̲C̲o̲n̲s̲u̲m̲p̲t̲i̲o̲n̲ ̲o̲f̲ ̲t̲h̲e̲ ̲A̲d̲a̲p̲t̲e̲r̲
+ 5V: TBD
+12V: TBD
-12V: TBD
E̲l̲e̲c̲t̲r̲i̲c̲a̲l̲ ̲S̲p̲e̲c̲i̲f̲i̲c̲a̲t̲i̲o̲n̲ ̲o̲f̲ ̲t̲h̲e̲ ̲L̲T̲U̲/̲A̲d̲a̲p̲t̲e̲r̲ ̲F̲l̲a̲t̲c̲a̲b̲l̲e̲
C̲o̲n̲n̲e̲c̲t̲i̲o̲n̲ ̲B̲u̲s̲
Fig. 5.1.5.1.3.3-1 shows the signals transferred on
the flatcable bus. The circuits used for each circuitry,
with the exception of CALL, are in accordance with
CCITT's V24 - and EIA's RS-232C Recommendation.
Fig. 5.1.5.1.3.3-1
LTU Flatcable I/O Connector
5.1.5.1.4 T̲h̲e̲ ̲F̲l̲o̲p̲p̲y̲ ̲D̲i̲s̲k̲ ̲C̲o̲n̲t̲r̲o̲l̲l̲e̲r̲ ̲&̲ ̲A̲d̲a̲p̲t̲e̲r̲
TBD.
5.1.5.1.4.1 M̲e̲c̲h̲a̲n̲i̲c̲a̲l̲ ̲&̲ ̲E̲l̲e̲c̲t̲r̲i̲c̲a̲l̲ ̲S̲p̲e̲c̲i̲f̲i̲c̲a̲t̲i̲o̲n̲s̲
M̲e̲c̲h̲a̲n̲i̲c̲a̲l̲ ̲S̲p̲e̲c̲i̲f̲i̲c̲a̲t̲i̲o̲n̲ ̲f̲o̲r̲ ̲t̲h̲e̲ ̲F̲l̲o̲p̲p̲y̲ ̲D̲i̲s̲k̲ ̲C̲o̲n̲t̲r̲o̲l̲l̲e̲r̲
Height: 412,6 mm ( 10 U crate)
Width: 17,1 mm ( 1 Module)
Depth: 305 mm
The Floppy Disk Controller is a front crate mounted
module.
P̲o̲w̲e̲r̲ ̲C̲o̲n̲s̲u̲m̲p̲t̲i̲o̲n̲ ̲f̲o̲r̲ ̲t̲h̲e̲ ̲F̲l̲o̲p̲p̲y̲ ̲D̲i̲s̲k̲ ̲C̲o̲n̲t̲r̲o̲l̲l̲e̲r̲
+ 5V: TBD
+12V: TBD
-12V: TBD
M̲e̲c̲h̲a̲n̲i̲c̲a̲l̲ ̲S̲p̲e̲c̲i̲f̲i̲c̲a̲t̲i̲o̲n̲ ̲f̲o̲r̲ ̲t̲h̲e̲ ̲A̲d̲a̲p̲t̲e̲r̲
Height: 412,6 mm ( 10 U crate)
Width: 17,1 mm ( 1 Module)
Depth: 160 mm
P̲o̲w̲e̲r̲ ̲C̲o̲n̲s̲u̲m̲p̲t̲i̲o̲n̲ ̲f̲o̲r̲ ̲t̲h̲e̲ ̲A̲d̲a̲p̲t̲e̲r̲
Not applicable.
E̲l̲e̲c̲t̲r̲i̲c̲a̲l̲ ̲S̲p̲e̲c̲i̲f̲i̲c̲a̲t̲i̲o̲n̲s̲ ̲f̲o̲r̲ ̲t̲h̲e̲ ̲F̲l̲o̲p̲p̲y̲ ̲D̲i̲s̲k̲ C̲o̲n̲t̲r̲o̲l̲l̲e̲r̲/̲A̲d̲a̲p̲t̲e̲r̲
̲F̲l̲a̲t̲c̲a̲b̲l̲e̲ ̲B̲u̲s̲
TBD.
5.1.5.1.5 T̲h̲e̲ ̲C̲C̲A̲ ̲(̲C̲r̲a̲t̲e̲ ̲C̲o̲n̲f̲i̲g̲u̲r̲a̲t̲i̲o̲n̲ ̲A̲d̲a̲p̲t̲e̲r̲
This module is considered a part of the SS&C system
and is therefore treated within the SS&C section of
the System Design (sec. 5.4).
5.1.5.1.6 T̲h̲e̲ ̲P̲o̲w̲e̲r̲ ̲S̲u̲p̲p̲l̲y̲
TBD.
5.1.5.2 D̲o̲c̲u̲m̲e̲n̲t̲a̲t̲i̲o̲n̲
TBD.
5.1.5.3 E̲n̲v̲i̲r̲o̲n̲m̲e̲n̲t̲
TBD.
