OctetView
0x00000…00100 (0, 0, 0) Sector 04824130343832 ┆ A0482A ┆
0x00100…00200 (0, 0, 1) Sector 00000000000000 ┆ ┆
0x00200…00300 (0, 0, 2) Sector ff00e0ffffffff ┆ ` ┆
0x00300…00306 (0, 0, 3) WangDocument {d00=0x50, d01=0x31, d02=0x41, ptr=(37,0, 8), d05=0x00}
0x00306…0030c WangDocument {d00=0x50, d01=0x33, d02=0x41, ptr=(51,0, 0), d05=0x00}
0x0030c…00320 50 33 41 46 08 00 52 12 41 48 08 4d 00 00 00 00 00 00 00 00 ┆P3AF R AH M ┆
0x00320…00340 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ┆ ┆
[…0x5…]
0x003e0…00400 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 0c ┆ ┆
0x00400…00500 (0, 0, 4) Sector 00000000000000 ┆ ┆
0x00500…00600 (0, 0, 5) Sector 86312020202020 ┆ 1 8 X 7 Q? > 7 d 0 Y N ~<d N ~<) 0uH &4'>( 1c5 & & ┆
0x00600…00700 (0, 0, 6) Sector 421c402600415b ┆B @& A[' , X% % PO P ; P1A + C g x g V W O 8 :Z Z < e 5031A g FM < {C < { ; 1 C 0w! .f .f 8 : 9 < t x 2161A2171A Z Z - , - , ┆
0x00700…00800 (0, 0, 7) Sector 00000000000000 ┆ ┆
[…0x8…]
0x01000…01100 (1, 0, 0) WangDocumentBody
[…0x2…]
0x01300…01400 (1, 0, 3) Sector 0104ff00503241 ┆ P2A.4.5.7.a.4, 3.4.5.7.a.7 Case Test Step No. Station Action Expected Results 7.26.4 OC Quit the TDX test by entering from the OC: Refer to Appendix QUIT(CR) B,┆
0x01400…01500 (1, 0, 4) Sector 0105b600503241 ┆ 6 P2A sec. 1.4 Comments: TEST WITNESSES TEST QA QAR CTION: PU#2/CU/TDX#2 Functional Test SRS REFERENCE: Secs. 3.4.5.1.o, 3┆
0x01500…01600 (1, 0, 5) Sector 00004e00503241 ┆ N P2A 1 Expected Results 7.24.1 N/A Power down TU#10 N/A Connect the PTP/R to J25 in the V24 fil- ter box┆
0x01600…01700 (1, 0, 6) Sector 00000000000000 ┆ ┆
[…0x1…]
0x01800…01900 (1, 0, 8) WangDocumentBody
[…0x38…]
0x05100…05200 (5, 0, 1) Sector 0502ff00503141 ┆ P1A 1 1 TEST STEPS TEST NO.: 2/1 FUNCTION: PU#1/CU/TDX#1 Functional Test SRS REFERENCE: Secs. 3.4.5.1.o, 3┆
0x05200…05300 (5, 0, 2) Sector 0503ff00503141 ┆ P1A.4.5.7.a.4, 3.4.5.7.a.7 Case Test Step No. Station Action Expected Results 7.33.4 OC Quit the TDX test by entering from the OC: Refer to Appendix QUIT(CR) B,┆
0x05300…05400 (5, 0, 3) Sector 0504b600503141 ┆ 6 P1A sec. 1.4 Comments: TEST WITNESSES TEST QA QAR CTION: PU#1/CU/TDX#1 Functional Test SRS REFERENCE: Secs. 3.4.5.1.o, 3┆
0x05400…05500 (5, 0, 4) Sector 0505ff00503141 ┆ P1A 1 3.2.3.1.4 Test Termination Power Down the system as Follows: a) Depress "START" push button on Disk Drive # 2 and wait until the "START" and "READY" indicators are "OFF". ┆
0x05500…05600 (5, 0, 5) Sector 0506ff00503141 ┆ P1Ab) Remove the Disk Pack from Disk Drive # 2, close the lid and push the drive back in rack B c) The two scratch Floppy Disks are removed from the Floppy Disk drive in rack C. Close the lids. d) The Power Switch (2) on each Mains Switch is set to┆
0x05600…05700 (5, 0, 6) Sector 0507c000503141 ┆ @ P1A "OFF". e) N.A. f) Power Down all connected Terminals i.e. VDUs, MSPs, OC, PTP/PTR, as applicable. g) Disconnect the OC from the leftmost V24/V28(L/L) adaptor in the Adaptor crate Comments: TES┆
0x05700…05800 (5, 0, 7) Sector 0000ee00503141 ┆ n P1Aof rack C, and replace this adaptor with the originally mounted OPTO transceiver. h) Disconnect the two V24 cables (at the WDP rear crate), remove the short extension cable and reconnect the two cables to J1 and J3 respectively. ecs. 3.4.5.1.o, 3┆
0x05800…05900 (5, 0, 8) WangDocumentBody
[…0x1ff…]
0x25800…25900 (37, 0, 8) WangDocumentHead {hdr=WangSectHead {next=(37,0, 9), len=0xff, h3=41503141}, f00=»5031A «, f01=»CPS/TPR/048 «, f02=»bko «, f03=»OJG «, f04=»Table of Cont. «, f05=13-06-84 08:39, f06=» 2 «, f07=»48 «, f08=» 4574 «, f09=05-10-84 09:54, f10=» «, f11=»00 «, f12=» 2 «, f13=05-10-84 10:29, f14=10-10-84 11:46, f15=»0482A «, f16=» 82 «, f17=» 3 «, f18=»44 «, f19=» 1140 «, f20=» 5306 «, f21=» «, f22=» «, f99=200010000110462710110280aaca15050000000000000138037101df}
0x25900…25a00 (37, 0, 9) WangDocumentBody
[…0xd6…]
0x33000…33100 (51, 0, 0) WangDocumentHead {hdr=WangSectHead {next=(51,0, 1), len=0xff, h3=41503341}, f00=»5033A «, f01=»CPS/TPR/048 «, f02=»bko «, f03=»OJG «, f04=»3.2.3.3 «, f05=13-06-84 08:50, f06=» 1 «, f07=»36 «, f08=» 3337 «, f09=27-09-84 13:55, f10=» «, f11=»01 «, f12=» 13 «, f13=27-09-84 14:10, f14=28-09-84 09:57, f15=»0482A «, f16=» 91 «, f17=» 1 «, f18=»45 «, f19=» 1336 «, f20=» 3655 «, f21=» «, f22=» «, f99=010010000110462710110280aaca1505000000000000003803ab01df}
0x33100…33200 (51, 0, 1) WangDocumentBody
[…0x6…]
0x33800…33900 (51, 0, 8) Sector 33097f00503341 ┆3 P3A Comments: TEST WITNESSES TEST QA QAR TESTVDU#1 Enter from TEST VDU#1: DO OPEN1E(CR) TESTVDU#1 display as (Appendix A, sec. 4.43a) specified in appendix DO CLO┆
0x33900…33a00 (51, 0, 9) Sector 330aff00503341 ┆3 P3A 1 1 TEST STEPS TEST NO.: 2/3 FUNCTION: Watchdog Processor System Test SRS REFERENCE: N/A ┆
0x33a00…33b00 (51, 0, 10) Sector 330bff00503341 ┆3 P3A Case Test Step No. Station Action Expected Results 15.8 TESTVDU#1 Boot the TDX3 test TEST VDU#1 display in program as follows: accorda┆
0x33b00…33c00 (51, 0, 11) Sector 330cff00503341 ┆3 P3Ance with appen- BA 1025 dix B sec. 7.16 BM 140 BO 631 15.9 TESTVDU#2 Boot the TDX3 test TEST VDU#1 display in program as follows: accordance with appen- BA 1025 dix B sec. 7.16 BM 140 BO 631 15.10 OC Enter from the OC: Refer to appen┆
0x33c00…33d00 (51, 0, 12) Sector 330dff00503341 ┆3 P3Adix B CCB(CR) sec. 22.7 98 19 FF 00 02 00(CR) (Switch on TDX BUS#1) 15.11 OC Enter from the OC: Refer to appendix B CCB(CR) sec. 22.7 98 19 FF 00 02 00(CR) (Switch on TDX BUS#1) 15.12 TESTVDU#1 Enter from TEST VDU#1: DO OPEN19(CR) TESTV┆
0x33d00…33e00 (51, 0, 13) Sector 330eff00503341 ┆3 P3ADU#1 display as (Appendix A, sec. 4.22a) specified in appendix DO CLOSE19(CR) B sec. 30.25 (Appendix A, sec. 4.22b) Comments: TEST WITNESS┆
0x33e00…33f00 (51, 0, 14) Sector 330f1b00503341 ┆3 P3AES TEST QA QAR Case Test Step No. Station Action Expected Results 13.15 TESTVDU#1 Enter from TEST VDU#1: TEST VDU#1 display DO OPEN18(CR) as specifie┆
0x33f00…34000 (51, 0, 15) Sector 3300ff00503341 ┆3 P3A 1 1 TEST STEPS TEST NO.: 2/3 FUNCTION: Watchdog Processor System Test SRS REFERENCE: N/A ┆
0x34000…34100 (52, 0, 0) Sector 3401ff00503341 ┆4 P3A Case Test Step No. Station Action Expected Results 14.15 TESTVDU#1 Enter from TEST VDU#1: TEST VDU#1 display DO OPEN1E(CR) as specifie┆
0x34100…34200 (52, 0, 1) Sector 3402ff00503341 ┆4 P3Ad in (Appendix A, sec. 4.43a) appendix B, sec. DO CLOSE1E(CR) 30.24 (Appendix A, sec. 4.43b) 14.16 TESTVDU#2 Enter from TEST VDU#2: TEST VDU#1 display DO OPEN1E(CR) as specified in (Appendix A, sec. 4.43a) appendix B, sec. DO CLOSE1E(CR┆
0x34200…34300 (52, 0, 2) Sector 3403ff00503341 ┆4 P3A) 30.23 (Appendix A, sec. 4.43b) 14.17 TESTVDU#1/ Quit the TDX2 test by TEST VDUs #1, #2 dis- TESTVDU#2 entering from TEST VDU#1 play as shown in and TEST VDU#2: QUIT(CR) appendix B sec. 1.4. ┆
0x34300…34400 (52, 0, 3) Sector 34046d00503341 ┆4 m P3A Comments: TEST WITNESSES TEST QA QAR ndix B CCB(CR) sec. 21.1 A4 1E 00(CR) 14.4 OC Enter from the OC: Refer to appendix B CCB(CR) sec. 21.2 A4 1E 01(CR) 14.5 OC Enter from t┆
0x34400…34500 (52, 0, 4) Sector 3405ff00503341 ┆4 P3A 1 1 TEST STEPS TEST NO.: 2/3 FUNCTION: Watchdog Processor System Test SRS REFERENCE: N/A ┆
0x34500…34600 (52, 0, 5) Sector 3406ff00503341 ┆4 P3A Case Test Step No. Station Action Expected Results 15.1 N/A Depress both CONTROL N/A SHIFT and CLEAR on TEST VDU#1. 15.2 N/A De┆
0x34600…34700 (52, 0, 6) Sector 3407ff00503341 ┆4 P3Apress both CONTROL N/A SHIFT and CLEAR on TEST VDU#2. 15.3 OC Enter from the OC: Refer to appendix B CCB(CR) sec. 22.1 A4 19 00(CR) 15.4 OC Enter from the OC: Refer to appendix B CCB(CR) sec. 22.2 A4 19 01(CR) 15.5 OC Enter from t┆
0x34700…34800 (52, 0, 7) Sector 3308ff00503341 ┆3 P3Ahe OC: Refer to appendix B CCB(CR) sec. 22.3 A4 19 02(CR) 15.6 OC Enter from the OC: Refer to appendix B CCB(CR) sec. 22.4 A4 19 03(CR) 15.7 OC Enter from the OC: Refer to appendix B CCB(CR) sec. 22.5 A4 19 04(CR) ┆
0x34800…34900 (52, 0, 8) Sector 3409ff00503341 ┆4 P3A 14.9 OC Enter from the OC: Refer to appendix B CCB(CR) sec. 21.7 98 1E FF 00 02 00(CR) (Switch on TDX BUS#1) 14.10 TESTVDU#1 Enter from TEST VDU#1: DO OPEN1E(CR) TESTVDU#1 display as (Appendix A, sec. 4.43a) specified in appendix DO CLO┆
0x34900…34a00 (52, 0, 9) Sector 340ad700503341 ┆4 W P3ASE1E(CR) B sec. 30.23 (Appendix A, sec. 4.43b) Comments: TEST WITNESSES TEST QA QAR DU#2 display DO OPEN18(CR) as specifie┆
0x34a00…34b00 (52, 0, 10) Sector 340bff00503341 ┆4 P3A 1 1 TEST STEPS TEST NO.: 2/3 FUNCTION: Watchdog Processor System Test SRS REFERENCE: N/A ┆
0x34b00…34c00 (52, 0, 11) Sector 340cff00503341 ┆4 P3A Case Test Step No. Station Action Expected Results 14.13 TESTVDU#2 Enter from TEST VDU#2: TEST VDU#2 display DO OPEN1E(CR) as specifie┆
0x34c00…34d00 (52, 0, 12) Sector 340dff00503341 ┆4 P3Ad in (Appendix A, sec. 4.43a) appendix B, sec. DO CLOSE1E(CR) 30.24 (Appendix A, sec. 4.43b) 14.14 N/A Depress both CONTROL N/A SHIFT and CLEAR on TEST VDU#1. 14.15 N/A Depress both CONTROL N/A SHIFT and CLEAR on TEST VDU#2. ┆
0x34d00…34e00 (52, 0, 13) Sector 340eff00503341 ┆4 P3A 14.16 OC Enter from the OC: Refer to appendix B CCB(CR) sec. 21.8 98 1E FF 00 01 00(CR) (Switch on TDX BUS#2) Comments: TEST WITNESSES ┆
0x34e00…34f00 (52, 0, 14) Sector 340f1800503341 ┆4 P3A TEST QA QAR Case Test Step No. Station Action Expected Results 13.15 TESTVDU#1 Enter from TEST VDU#1: TEST VDU#1 display DO OPEN18(CR) as specifie┆
0x34f00…35000 (52, 0, 15) Sector 3400ff00503341 ┆4 P3A 1 1 TEST STEPS TEST NO.: 2/3 FUNCTION: Watchdog Processor System Test SRS REFERENCE: N/A ┆
0x35000…35100 (53, 0, 0) Sector 3501c700503341 ┆5 G P3A) 30.21 (Appendix A, sec. 4.20b) Comments: TEST WITNESSES TEST QA QAR L N/A SHIFT and CLEAR on TEST VDU#1. 13.2 N/A De┆
0x35100…35200 (53, 0, 1) Sector 3502ff00503341 ┆5 P3A 1 1 TEST STEPS TEST NO.: 2/3 FUNCTION: Watchdog Processor System Test SRS REFERENCE: N/A ┆
0x35200…35300 (53, 0, 2) Sector 3503ff00503341 ┆5 P3A Case Test Step No. Station Action Expected Results 14.1 N/A Depress both CONTROL N/A SHIFT and CLEAR on TEST VDU#1. 14.2 N/A De┆
0x35300…35400 (53, 0, 3) Sector 3504ff00503341 ┆5 P3Apress both CONTROL N/A SHIFT and CLEAR on TEST VDU#2. 14.3 OC Enter from the OC: Refer to appendix B CCB(CR) sec. 21.1 A4 1E 00(CR) 14.4 OC Enter from the OC: Refer to appendix B CCB(CR) sec. 21.2 A4 1E 01(CR) 14.5 OC Enter from t┆
0x35400…35500 (53, 0, 4) Sector 3505ff00503341 ┆5 P3Ahe OC: Refer to appendix B CCB(CR) sec. 21.3 A4 1E 02(CR) 14.6 OC Enter from the OC: Refer to appendix B CCB(CR) sec. 21.4 A4 1E 03(CR) 14.7 OC Enter from the OC: Refer to appendix B CCB(CR) sec. 21.5 A4 1E 04(CR) ┆
0x35500…35600 (53, 0, 5) Sector 35067f00503341 ┆5 P3A Comments: TEST WITNESSES TEST QA QAR 13.8 OC Enter from the OC: Refer to appendix B CCB(CR) sec. 20.6 94 18 FF FF(CR) ┆
0x35600…35700 (53, 0, 6) Sector 3507ff00503341 ┆5 P3A 1 1 TEST STEPS TEST NO.: 2/3 FUNCTION: Watchdog Processor System Test SRS REFERENCE: N/A ┆
0x35700…35800 (53, 0, 7) Sector 3408ff00503341 ┆4 P3A Case Test Step No. Station Action Expected Results 14.8 OC Enter from the OC: Refer to appendix B CCB(CR) sec. 21.6 94 1E FF FF(CR) ┆
0x35800…35900 (53, 0, 8) Sector 3509ff00503341 ┆5 P3A 1 1 TEST STEPS TEST NO.: 2/3 FUNCTION: Watchdog Processor System Test SRS REFERENCE: N/A ┆
0x35900…35a00 (53, 0, 9) Sector 350aff00503341 ┆5 P3A Case Test Step No. Station Action Expected Results 13.11 TESTVDU#2 Enter from TEST VDU#2: TEST VDU#2 display DO OPEN18(CR) as specifie┆
0x35a00…35b00 (53, 0, 10) Sector 350bff00503341 ┆5 P3Ad in (Appendix A, sec. 4.20a) appendix B, sec. DO CLOSE18(CR) 30.22 (Appendix A, sec. 4.20b) 13.12 N/A Depress both CONTROL N/A SHIFT and CLEAR on TEST VDU#1. 13.13 N/A Depress both CONTROL N/A SHIFT and CLEAR on TEST VDU#2. ┆
0x35b00…35c00 (53, 0, 11) Sector 350cff00503341 ┆5 P3A 13.14 OC Enter from the OC: Refer to appendix B CCB(CR) sec. 20.8 98 18 FF 00 01 00(CR) (Switch on TDX BUS#2) Comments: TEST WITNESSES ┆
0x35c00…35d00 (53, 0, 12) Sector 350d1800503341 ┆5 P3A TEST QA QAR Case Test Step No. Station Action Expected Results 12.15 TESTVDU#1 Enter from TEST VDU#1: TEST VDU#1 display DO OPEN17(CR) as specifie┆
0x35d00…35e00 (53, 0, 13) Sector 350eff00503341 ┆5 P3A 1 1 TEST STEPS TEST NO.: 2/3 FUNCTION: Watchdog Processor System Test SRS REFERENCE: N/A ┆
0x35e00…35f00 (53, 0, 14) Sector 350fff00503341 ┆5 P3A Case Test Step No. Station Action Expected Results 13.15 TESTVDU#1 Enter from TEST VDU#1: TEST VDU#1 display DO OPEN18(CR) as specifie┆
0x35f00…36000 (53, 0, 15) Sector 3500ff00503341 ┆5 P3Ad in (Appendix A, sec. 4.20a) appendix B, sec. DO CLOSE18(CR) 30.22 (Appendix A, sec. 4.20b) 13.16 TESTVDU#2 Enter from TEST VDU#2: TEST VDU#1 display DO OPEN18(CR) as specified in (Appendix A, sec. 4.20a) appendix B, sec. DO CLOSE18(CR┆
0x36000…36100 (54, 0, 0) Sector 3601ff00503341 ┆6 P3A Case Test Step No. Station Action Expected Results 13.1 N/A Depress both CONTROL N/A SHIFT and CLEAR on TEST VDU#1. 13.2 N/A De┆
0x36100…36200 (54, 0, 1) Sector 3602ff00503341 ┆6 P3Apress both CONTROL N/A SHIFT and CLEAR on TEST VDU#2. 13.3 OC Enter from the OC: Refer to appendix B CCB(CR) sec. 20.1 A4 18 00(CR) 13.4 OC Enter from the OC: Refer to appendix B CCB(CR) sec. 20.2 A4 18 01(CR) 13.5 OC Enter from t┆
0x36200…36300 (54, 0, 2) Sector 3603ff00503341 ┆6 P3Ahe OC: Refer to appendix B CCB(CR) sec. 20.3 A4 18 02(CR) 13.6 OC Enter from the OC: Refer to appendix B CCB(CR) sec. 20.4 A4 18 03(CR) 13.7 OC Enter from the OC: Refer to appendix B CCB(CR) sec. 20.5 A4 18 04(CR) ┆
0x36300…36400 (54, 0, 3) Sector 36047f00503341 ┆6 P3A Comments: TEST WITNESSES TEST QA QAR 12.8 OC Enter from the OC: Refer to appendix B CCB(CR) sec. 19.6 94 17 FF FF(CR) ┆
0x36400…36500 (54, 0, 4) Sector 3605ff00503341 ┆6 P3A 1 1 TEST STEPS TEST NO.: 2/3 FUNCTION: Watchdog Processor System Test SRS REFERENCE: N/A ┆
0x36500…36600 (54, 0, 5) Sector 3606ff00503341 ┆6 P3A Case Test Step No. Station Action Expected Results 13.8 OC Enter from the OC: Refer to appendix B CCB(CR) sec. 20.6 94 18 FF FF(CR) ┆
0x36600…36700 (54, 0, 6) Sector 3607ff00503341 ┆6 P3A 13.9 OC Enter from the OC: Refer to appendix B CCB(CR) sec. 20.7 98 18 FF 00 02 00(CR) (Switch on TDX BUS#1) 13.10 TESTVDU#1 Enter from TEST VDU#1: DO OPEN18(CR) TESTVDU#1 display as (Appendix A, sec. 4.20a) specified in appendix DO CLO┆
0x36700…36800 (54, 0, 7) Sector 3508d700503341 ┆5 W P3ASE18(CR) B sec. 30.21 (Appendix A, sec. 4.20b) Comments: TEST WITNESSES TEST QA QAR DU#2 display DO OPEN17(CR) as specifie┆
0x36800…36900 (54, 0, 8) Sector 3609ff00503341 ┆6 P3Ad in (Appendix A, sec. 4.18a) appendix B, sec. DO CLOSE17(CR) 30.20 (Appendix A, sec. 4.18b) 12.12 N/A Depress both CONTROL N/A SHIFT and CLEAR on TEST VDU#1. 12.13 N/A Depress both CONTROL N/A SHIFT and CLEAR on TEST VDU#2. ┆
0x36900…36a00 (54, 0, 9) Sector 360aff00503341 ┆6 P3A 12.14 OC Enter from the OC: Refer to appendix B CCB(CR) sec. 19.8 98 17 FF 00 01 00(CR) (Switch on TDX BUS#2) Comments: TEST WITNESSES ┆
0x36a00…36b00 (54, 0, 10) Sector 360b1800503341 ┆6 P3A TEST QA QAR Refer to appendix B CCB(CR) sec. 18.8 98 16 FF 00 01 00(CR) (Switch on TDX BUS#2) 11.15 TESTVDU#1 Enter from TEST VDU#1: DO OPEN16(CR) TEST VDU#1 (Appendix A, sec. 4.16a) display as specified DO CLOSE16(CR) in appendix ┆
0x36b00…36c00 (54, 0, 11) Sector 360cff00503341 ┆6 P3A 1 1 TEST STEPS TEST NO.: 2/3 FUNCTION: Watchdog Processor System Test SRS REFERENCE: N/A ┆
0x36c00…36d00 (54, 0, 12) Sector 360dff00503341 ┆6 P3A Case Test Step No. Station Action Expected Results 12.15 TESTVDU#1 Enter from TEST VDU#1: TEST VDU#1 display DO OPEN17(CR) as specifie┆
0x36d00…36e00 (54, 0, 13) Sector 360eff00503341 ┆6 P3Ad in (Appendix A, sec. 4.18a) appendix B, sec. DO CLOSE17(CR) 30.20 (Appendix A, sec. 4.18b) 12.16 TESTVDU#2 Enter from TEST VDU#2: TEST VDU#1 display DO OPEN17(CR) as specified in (Appendix A, sec. 4.18a) appendix B, sec. DO CLOSE17(CR┆
0x36e00…36f00 (54, 0, 14) Sector 360fc700503341 ┆6 G P3A) 30.19 (Appendix A, sec. 4.18b) Comments: TEST WITNESSES TEST QA QAR L N/A SHIFT and CLEAR on TEST VDU#1. 12.2 N/A De┆
0x36f00…37000 (54, 0, 15) Sector 3600ff00503341 ┆6 P3A 1 1 TEST STEPS TEST NO.: 2/3 FUNCTION: Watchdog Processor System Test SRS REFERENCE: N/A ┆
0x37000…37100 (55, 0, 0) Sector 3701ff00503341 ┆7 P3Ahe OC: Refer to appendix B CCB(CR) sec. 19.3 A4 17 02(CR) 12.6 OC Enter from the OC: Refer to appendix B CCB(CR) sec. 19.4 A4 17 03(CR) 12.7 OC Enter from the OC: Refer to appendix B CCB(CR) sec. 19.5 A4 17 04(CR) ┆
0x37100…37200 (55, 0, 1) Sector 37027f00503341 ┆7 P3A Comments: TEST WITNESSES TEST QA QAR ndix B CCB(CR) sec. 18.5 A4 16 04(CR) 11.8 OC Enter from the OC: Refer to appendix B CCB(CR) sec. 18.6 94 16 FF FF(CR) ┆
0x37200…37300 (55, 0, 2) Sector 3703ff00503341 ┆7 P3A 1 1 TEST STEPS TEST NO.: 2/3 FUNCTION: Watchdog Processor System Test SRS REFERENCE: N/A ┆
0x37300…37400 (55, 0, 3) Sector 3704ff00503341 ┆7 P3A Case Test Step No. Station Action Expected Results 12.8 OC Enter from the OC: Refer to appendix B CCB(CR) sec. 19.6 94 17 FF FF(CR) ┆
0x37400…37500 (55, 0, 4) Sector 3705ff00503341 ┆7 P3A 12.9 OC Enter from the OC: Refer to appendix B CCB(CR) sec. 19.7 98 17 FF 00 02 00(CR) (Switch on TDX BUS#1) 12.10 TESTVDU#1 Enter from TEST VDU#1: DO OPEN17(CR) TESTVDU#1 display as (Appendix A, sec. 4.18a) specified in appendix DO CLO┆
0x37500…37600 (55, 0, 5) Sector 3706d700503341 ┆7 W P3ASE17(CR) B sec. 30.19 (Appendix A, sec. 4.18b) Comments: TEST WITNESSES TEST QA QAR n appen- DO CLOSE16(CR) dix B sec. 30.┆
0x37600…37700 (55, 0, 6) Sector 3707ff00503341 ┆7 P3A 1 1 TEST STEPS TEST NO.: 2/3 FUNCTION: Watchdog Processor System Test SRS REFERENCE: N/A ┆
0x37700…37800 (55, 0, 7) Sector 3608ff00503341 ┆6 P3A Case Test Step No. Station Action Expected Results 12.11 TESTVDU#2 Enter from TEST VDU#2: TEST VDU#2 display DO OPEN17(CR) as specifie┆
0x37800…37900 (55, 0, 8) Sector 3709ff00503341 ┆7 P3A 1 1 TEST STEPS TEST NO.: 2/3 FUNCTION: Watchdog Processor System Test SRS REFERENCE: N/A ┆
0x37900…37a00 (55, 0, 9) Sector 370aff00503341 ┆7 P3A Case Test Step No. Station Action Expected Results 11.13 N/A Depress both CONTROL N/A SHIFT and CLEAR on TEST VDU#2. 11.14 OC E┆
0x37a00…37b00 (55, 0, 10) Sector 370bff00503341 ┆7 P3Anter from the OC: Refer to appendix B CCB(CR) sec. 18.8 98 16 FF 00 01 00(CR) (Switch on TDX BUS#2) 11.15 TESTVDU#1 Enter from TEST VDU#1: DO OPEN16(CR) TEST VDU#1 (Appendix A, sec. 4.16a) display as specified DO CLOSE16(CR) in appendix ┆
0x37b00…37c00 (55, 0, 11) Sector 370cff00503341 ┆7 P3AB, sec. (Appendix A, sec. 4.16b) 30.18 11.16 TESTVDU#2 Enter from TEST VDU#2: DO OPEN16(CR) TEST VDU#2 display as (Appendix A, sec. 4.16a) specified in appendix DO CLOSE16(CR) B, sec. 30.17. (Appendix A, sec. 4.16b) ┆
0x37c00…37d00 (55, 0, 12) Sector 370d8800503341 ┆7 P3A Comments: TEST WITNESSES TEST QA QAR 11.1 N/A Depress both CONTROL N/A SHIFT and CLEAR on TEST VDU#1. 11.2 N/A De┆
0x37d00…37e00 (55, 0, 13) Sector 370eff00503341 ┆7 P3A 1 1 TEST STEPS TEST NO.: 2/3 FUNCTION: Watchdog Processor System Test SRS REFERENCE: N/A ┆
0x37e00…37f00 (55, 0, 14) Sector 370fff00503341 ┆7 P3A Case Test Step No. Station Action Expected Results 12.1 N/A Depress both CONTROL N/A SHIFT and CLEAR on TEST VDU#1. 12.2 N/A De┆
0x37f00…38000 (55, 0, 15) Sector 3700ff00503341 ┆7 P3Apress both CONTROL N/A SHIFT and CLEAR on TEST VDU#2. 12.3 OC Enter from the OC: Refer to appendix B CCB(CR) sec. 19.1 A4 17 00(CR) 12.4 OC Enter from the OC: Refer to appendix B CCB(CR) sec. 19.2 A4 17 01(CR) 12.5 OC Enter from t┆
0x38000…38100 (56, 0, 0) Sector 3801ff00503341 ┆8 P3A Case Test Step No. Station Action Expected Results 11.5 OC Enter from the OC: Refer to appendix B CCB(CR) sec. 18.3 A4 16 02(CR) 11┆
0x38100…38200 (56, 0, 1) Sector 3802ff00503341 ┆8 P3A.6 OC Enter from the OC: Refer to appendix B CCB(CR) sec. 18.4 A4 16 03(CR) 11.7 OC Enter from the OC: Refer to appendix B CCB(CR) sec. 18.5 A4 16 04(CR) 11.8 OC Enter from the OC: Refer to appendix B CCB(CR) sec. 18.6 94 16 FF FF(CR) ┆
0x38200…38300 (56, 0, 2) Sector 3803ff00503341 ┆8 P3A 11.9 OC Enter from the OC: Refer to appendix B CCB(CR) sec. 18.7 98 16 FF 00 02 00(CR) (Switch on TDX BUS#1) Comments: TEST WITNESSES ┆
0x38300…38400 (56, 0, 3) Sector 38041500503341 ┆8 P3A TEST QA QAR Case Test Step No. Station Action Expected Results 10.13 TESTVDU#2 Enter from TEST VDU#2: DO OPEN15(CR) TEST VDU#2 display (Appendi┆
0x38400…38500 (56, 0, 4) Sector 3805ff00503341 ┆8 P3A 1 TEST STEPS TEST NO.: 2/3 FUNCTION: Watchdog Processor System Test SRS REFERENCE: N/A Case Test Step No. Station Actio┆
0x38500…38600 (56, 0, 5) Sector 3806ff00503341 ┆8 P3An Expected Results 11.10 TESTVDU#1 Enter from TEST VDU#1: DO OPEN16(CR) TEST VDU#1 display (Appendix A, sec. 4.16a) as specified in appen- DO CLOSE16(CR) dix B sec. 30.┆
0x38600…38700 (56, 0, 6) Sector 3807ff00503341 ┆8 P3A17 (Appendix A, sec. 4.16b) 11.11 TESTVDU#2 Enter from TEST VDU#2: DO OPEN16(CR) (Appendix A, sec. 4.16a) TEST VDU#2 display DO CLOSE16(CR) as specified in (Appendix A, sec. 4.16b) appendix B, sec. 30.18. 11.12 N/A Depress both CO┆
0x38700…38800 (56, 0, 7) Sector 3708cf00503341 ┆7 O P3ANTROL N/A SHIFT and CLEAR on TEST VDU#1. Comments: TEST WITNESSES TEST QA QAR r System Test SRS REFERENCE: N/A ┆
0x38800…38900 (56, 0, 8) Sector 3809ff00503341 ┆8 P3A Case Test Step No. Station Action Expected Results 10.17 TESTVDU#1 Enter from TEST VDU#1: DO OPEN15(CR) TEST VDU#1 (Appendix A, se┆
0x38900…38a00 (56, 0, 9) Sector 380aff00503341 ┆8 P3Ac. 4.14a) display as specified DO CLOSE15(CR) in appendix B, sec. (Appendix A, sec. 4.14b) 30.16 10.18 TESTVDU#2 Enter from TEST VDU#2: DO OPEN15(CR) TEST VDU#2 display (Appendix A, sec. 4.14a) as specified in DO CLOSE15(CR) appendix B,s┆
0x38a00…38b00 (56, 0, 10) Sector 380bca00503341 ┆8 J P3Aec. 30.15 (Appendix A, sec. 4.14b) Comments: TEST WITNESSES TEST QA QAR CB(CR) sec. 17.2 A4 15 01(CR) 10.5 OC Enter from t┆
0x38b00…38c00 (56, 0, 11) Sector 380cff00503341 ┆8 P3A 1 1 TEST STEPS TEST NO.: 2/3 FUNCTION: Watchdog Processor System Test SRS REFERENCE: N/A ┆
0x38c00…38d00 (56, 0, 12) Sector 380dff00503341 ┆8 P3A Case Test Step No. Station Action Expected Results 11.1 N/A Depress both CONTROL N/A SHIFT and CLEAR on TEST VDU#1. 11.2 N/A De┆
0x38d00…38e00 (56, 0, 13) Sector 380eff00503341 ┆8 P3Apress both CONTROL N/A SHIFT and CLEAR on TEST VDU#2. 11.3 OC Enter from the OC: Refer to appendix B CCB(CR) sec. 18.1 A4 16 00(CR) 11.4 OC Enter from the OC: Refer to appendix B CCB(CR) sec. 18.2 A4 16 01(CR) ┆
0x38e00…38f00 (56, 0, 14) Sector 380f8a00503341 ┆8 P3A Comments: TEST WITNESSES TEST QA QAR 10.8 TESTVDU#1 Boot the TDX2 test TEST VDU#1 display in program as follows: accorda┆
0x38f00…39000 (56, 0, 15) Sector 3800ff00503341 ┆8 P3A 1 1 TEST STEPS TEST NO.: 2/3 FUNCTION: Watchdog Processor System Test SRS REFERENCE: N/A ┆
0x39000…39100 (57, 0, 0) Sector 3901ff00503341 ┆9 P3Ax B CCB(CR) sec. 17.6 94 15 FF FF(CR) 10.11 OC Enter from the OC: Refer to appendix B CCB(CR) sec. 17.7 98 15 FF 00 02 00(CR) (Switch on TDX BUS#1) 10.12 TESTVDU#1 Enter from TEST VDU#1: DO OPEN15(CR) TEST VDU#1 display (Appendix A, ┆
0x39100…39200 (57, 0, 1) Sector 3902f400503341 ┆9 t P3Asec. 4.14a) as specified in DO CLOSE15(CR) appendix B sec. 30.15 (Appendix A, sec. 4.14b) Comments: TEST WITNESSES TEST QA QAR DU#1 displa┆
0x39200…39300 (57, 0, 2) Sector 3903ff00503341 ┆9 P3A 1 1 TEST STEPS TEST NO.: 2/3 FUNCTION: Watchdog Processor System Test SRS REFERENCE: N/A ┆
0x39300…39400 (57, 0, 3) Sector 3904ff00503341 ┆9 P3A Case Test Step No. Station Action Expected Results 10.13 TESTVDU#2 Enter from TEST VDU#2: DO OPEN15(CR) TEST VDU#2 display (Appendi┆
0x39400…39500 (57, 0, 4) Sector 3905ff00503341 ┆9 P3Ax A, sec. 4.14a) as specified in DO CLOSE15(CR) appendix B, sec. (Appendix A, sec. 4.14b) 30.16 10.14 N/A Depress both CONTROL N/A SHIFT and CLEAR on TEST VDU#1. 10.15 N/A Depress both CONTROL N/A SHIFT and CLEAR on TEST VDU#┆
0x39500…39600 (57, 0, 5) Sector 3906ff00503341 ┆9 P3A2. 10.16 OC Enter from the OC: Refer to appendix B CCB(CR) sec. 17.8 98 15 FF 00 01 00(CR) (Switch on TDX BUS#2) Comments: TEST WITNESS┆
0x39600…39700 (57, 0, 6) Sector 39071b00503341 ┆9 P3AES TEST QA QAR pecified in DO CLOSE14(CR) appendix B sec. 30.13 (Appendix A, sec. 4.12b) 9.17 TESTVDU#1/ Quit the TDX1 test by TEST VDUs #1, #2 dis- TESTVDU#2 entering from TEST VDU#1 play as shown in and TEST VDU#2: QUIT(CR) appendi┆
0x39700…39800 (57, 0, 7) Sector 3808ff00503341 ┆8 P3A 1 1 TEST STEPS TEST NO.: 2/3 FUNCTION: Watchdog Processor System Test SRS REFERENCE: N/A ┆
0x39800…39900 (57, 0, 8) Sector 3909ff00503341 ┆9 P3A 1 1 TEST STEPS TEST NO.: 2/3 FUNCTION: Watchdog Processor System Test SRS REFERENCE: N/A ┆
0x39900…39a00 (57, 0, 9) Sector 390aff00503341 ┆9 P3A Case Test Step No. Station Action Expected Results 10.1 N/A Depress both CONTROL N/A SHIFT and CLEAR on TEST VDU#1. 10.2 N/A De┆
0x39a00…39b00 (57, 0, 10) Sector 390bff00503341 ┆9 P3Apress both CONTROL N/A SHIFT and CLEAR on TEST VDU#2. 10.3 OC Enter from the OC: Refer to appendix B CCB(CR) sec. 17.1 A4 15 00(CR) 10.4 OC Enter from the OC: Refer to appendix B CCB(CR) sec. 17.2 A4 15 01(CR) 10.5 OC Enter from t┆
0x39b00…39c00 (57, 0, 11) Sector 390cff00503341 ┆9 P3Ahe OC: Refer to appendix B CCB(CR) sec. 17.3 A4 15 02(CR) 10.6 OC Enter from the OC: Refer to appendix B CCB(CR) sec. 17.4 A4 15 03(CR) 10.7 OC Enter from the OC: Refer to appendix B CCB(CR) sec. 17.5 A4 15 04(CR) ┆
0x39c00…39d00 (57, 0, 12) Sector 390d7f00503341 ┆9 P3A Comments: TEST WITNESSES TEST QA QAR TVDU#1 Enter from TEST VDU#1: DO OPEN14(CR) (Appendix A, sec. 4.12a) DO CLOSE14(CR) TEST VDU#1 display as (Appendi┆
0x39d00…39e00 (57, 0, 13) Sector 390eff00503341 ┆9 P3A 1 1 TEST STEPS TEST NO.: 2/3 FUNCTION: Watchdog Processor System Test SRS REFERENCE: N/A ┆
0x39e00…39f00 (57, 0, 14) Sector 390fff00503341 ┆9 P3A Case Test Step No. Station Action Expected Results 10.8 TESTVDU#1 Boot the TDX2 test TEST VDU#1 display in program as follows: accorda┆
0x39f00…3a000 (57, 0, 15) Sector 3900ff00503341 ┆9 P3Ance with appen- BA 1025 dix B sec. 7.8 BM 140 BO 630 10.9 TESTVDU#2 Boot the TDX2 test TEST VDU#2 display in program as follows: accordance with appen- BA 1025 dix B sec. 7.8 BM 140 BO 630 10.10 OC Enter from the OC: Refer to appendi┆
0x3a000…3a100 (58, 0, 0) Sector 3a01ff00503341 ┆: P3A Case Test Step No. Station Action Expected Results 9.12 N/A Depress both CONTROL N/A SHIFT and CLEAR on TEST VDU#1. 9.13 N/A De┆
0x3a100…3a200 (58, 0, 1) Sector 3a02ff00503341 ┆: P3Apress both CONTROL N/A SHIFT and CLEAR on TEST VDU#2. 9.14 OC Enter from the OC: Refer to appendix B CCB(CR) sec. 16.8 98 14 FF 00 01 00(CR) (Switch on TDX BUS#2) 9.15 TESTVDU#1 Enter from TEST VDU#1: DO OPEN14(CR) TEST VDU#1 displa┆
0x3a200…3a300 (58, 0, 2) Sector 3a03ff00503341 ┆: P3Ay (Appendix A, sec. 4.12a) as specified in DO CLOSE14(CR) appendix B, sec. 30.14 (Appendix A, sec. 4.12b) Comments: TEST WITN┆
0x3a300…3a400 (58, 0, 3) Sector 3a041e00503341 ┆: P3AESSES TEST QA QAR 1 TEST STEPS TEST NO.: 2/3 FUNCTION: Watchdog Processor System Test SRS REFERENCE: N/A ┆
0x3a400…3a500 (58, 0, 4) Sector 3a05ff00503341 ┆: P3A 1 1 TEST STEPS TEST NO.: 2/3 FUNCTION: Watchdog Processor System Test SRS REFERENCE: N/A ┆
0x3a500…3a600 (58, 0, 5) Sector 3a06ff00503341 ┆: P3A Case Test Step No. Station Action Expected Results 9.16 TESTVDU#2 Enter from TEST VDU#2: DO OPEN14(CR) TEST VDU#2 display (Appendi┆
0x3a600…3a700 (58, 0, 6) Sector 3a07ff00503341 ┆: P3Ax A, sec. 4.12a) as specified in DO CLOSE14(CR) appendix B sec. 30.13 (Appendix A, sec. 4.12b) 9.17 TESTVDU#1/ Quit the TDX1 test by TEST VDUs #1, #2 dis- TESTVDU#2 entering from TEST VDU#1 play as shown in and TEST VDU#2: QUIT(CR) appendi┆
0x3a700…3a800 (58, 0, 7) Sector 3908b400503341 ┆9 4 P3Ax B sec. 1.4. Comments: TEST WITNESSES TEST QA QAR er from the OC: Refer to appendix B CCB(CR) sec. 16.1 A4 14 00(CR) 9.4┆
0x3a800…3a900 (58, 0, 8) Sector 3a09ff00503341 ┆: P3A OC Enter from the OC: Refer to appendix B CCB(CR) sec. 16.2 A4 14 01(CR) 9.5 OC Enter from the OC: Refer to appendix B CCB(CR) sec. 16.3 A4 14 02(CR) 9.6 OC Enter from the OC: Refer to appendix B CCB(CR) sec. 16.4 A4 14 03(CR) 9.7 OC┆
0x3a900…3aa00 (58, 0, 9) Sector 3a0ae700503341 ┆: g P3A Enter from the OC: Refer to appendix B CCB(CR) sec. 16.5 A4 14 04(CR) Comments: TEST WITNESSES TEST QA QAR ENCE: N/A ┆
0x3aa00…3ab00 (58, 0, 10) Sector 3a0bff00503341 ┆: P3A 1 1 TEST STEPS TEST NO.: 2/3 FUNCTION: Watchdog Processor System Test SRS REFERENCE: N/A ┆
0x3ab00…3ac00 (58, 0, 11) Sector 3a0cff00503341 ┆: P3A Case Test Step No. Station Action Expected Results 9.8 OC Enter from the OC: Refer to appendix B CCB(CR) sec. 16.6 94 14 FF FF(CR) ┆
0x3ac00…3ad00 (58, 0, 12) Sector 3a0dff00503341 ┆: P3A9.9 OC Enter from the OC: Refer to appendix B CCB(CR) sec. 16.7 98 14 FF 00 02 00(CR) (SWITCH ON TDX BUS#1) 9.10 TESTVDU#1 Enter from TEST VDU#1: DO OPEN14(CR) (Appendix A, sec. 4.12a) DO CLOSE14(CR) TEST VDU#1 display as (Appendi┆
0x3ad00…3ae00 (58, 0, 13) Sector 3a0eff00503341 ┆: P3Ax A, sec. 4.12b) specified in appendix B sec. 30.13 9.11 TESTVDU#2 Enter from TEST VDU#2: DO OPEN14(CR) TEST VDU#2 display (Appendix A, sec. 4.12a) as specified in DO CLOSE14(CR) appendix B, sec. 30.14 (Appendix A, sec. 4.12b) ┆
0x3ae00…3af00 (58, 0, 14) Sector 3a0f8f00503341 ┆: P3A Comments: TEST WITNESSES TEST QA QAR TEST STEPS TEST NO.: 2/3 FUNCTION: Watchdog Processor System Test SRS REFERENCE: N/A ┆
0x3af00…3b000 (58, 0, 15) Sector 3a00ff00503341 ┆: P3A 1 1 TEST STEPS TEST NO.: 2/3 FUNCTION: Watchdog Processor System Test SRS REFERENCE: N/A ┆
0x3b000…3b100 (59, 0, 0) Sector 3b01ff00503341 ┆; P3Aer from the OC: Refer to appendix B CCB(CR) sec. 15.8 98 13 FF 00 01 00(CR) (Switch on TDX BUS#2) 8.15 TESTVDU#1 Enter from TEST VDU#1: DO OPEN13(CR) TEST VDU#1 (Appendix A, sec. 4.9a) display as speci- DO CLOSE13(CR) fied in appendix B┆
0x3b100…3b200 (59, 0, 1) Sector 3b02ff00503341 ┆; P3A, (Appendix A, sec. 4.9b) sec. 30.12 8.16 TESTVDU#2 Enter from TEST VDU#2: TEST VDU#2 display as DO OPEN13(CR) specified in appendix (Appendix A, sec. 4.9a) B sec. 30.11 DO CLOSE13(CR) (Appendix A, sec. 4.9b) ┆
0x3b200…3b300 (59, 0, 2) Sector 3b038200503341 ┆; P3A Comments: TEST WITNESSES TEST QA QAR .1 A4 13 00(CR) 8.4 OC Enter from the OC: Refer to appendix B CCB(CR) sec. 15.2 A4 13 01(CR) ┆
0x3b300…3b400 (59, 0, 3) Sector 3b04ff00503341 ┆; P3A 1 1 TEST STEPS TEST NO.: 2/3 FUNCTION: Watchdog Processor System Test SRS REFERENCE: N/A ┆
0x3b400…3b500 (59, 0, 4) Sector 3b05ff00503341 ┆; P3A Case Test Step No. Station Action Expected Results 9.1 N/A Depress both CONTROL N/A SHIFT and CLEAR on TEST VDU#1. 9.2 N/A Depr┆
0x3b500…3b600 (59, 0, 5) Sector 3b06e300503341 ┆; c P3Aess both CONTROL N/A SHIFT and CLEAR on TEST VDU#2. Comments: TEST WITNESSES TEST QA QAR ec. 15.3 A4 13 02(CR) 8.6┆
0x3b600…3b700 (59, 0, 6) Sector 3b07ff00503341 ┆; P3A 1 1 TEST STEPS TEST NO.: 2/3 FUNCTION: Watchdog Processor System Test SRS REFERENCE: N/A ┆
0x3b700…3b800 (59, 0, 7) Sector 3a08ff00503341 ┆: P3A Case Test Step No. Station Action Expected Results 9.3 OC Enter from the OC: Refer to appendix B CCB(CR) sec. 16.1 A4 14 00(CR) 9.4┆
0x3b800…3b900 (59, 0, 8) Sector 3b091000503341 ┆; P3A QA QAR Case Test Step No. Station Action Expected Results 7.12 N/A Depress both CONTROL N/A SHIFT and CLEAR on TEST VDU#1. 7.13 N/A De┆
0x3b900…3ba00 (59, 0, 9) Sector 3b0aff00503341 ┆; P3A 1 1 TEST STEPS TEST NO.: 2/3 FUNCTION: Watchdog Processor System Test SRS REFERENCE: N/A ┆
0x3ba00…3bb00 (59, 0, 10) Sector 3b0bff00503341 ┆; P3A Case Test Step No. Station Action Expected Results 8.10 TESTVDU#1 Enter from TEST VDU#1: TEST VDU#1 display as DO OPEN13(CR) specified┆
0x3bb00…3bc00 (59, 0, 11) Sector 3b0cff00503341 ┆; P3A in appendix (Appendix A, sec. 4.9a) B sec. 30.11 DO CLOSE13(CR) (Appendix A, sec. 4.9b) 8.11 TESTVDU#2 Enter from TEST VDU#2: DO OPEN13(CR) TEST VDU#2 (Appendix A, sec. 4.9a) display as speci- DO CLOSE13(CR) fied in appendix B, (A┆
0x3bc00…3bd00 (59, 0, 12) Sector 3b0dff00503341 ┆; P3Appendix A, sec. 4.9b) sec. 30.12 8.12 N/A Depress both CONTROL N/A SHIFT and CLEAR on TEST VDU#1. Comments: TEST WITNESSES TE┆
0x3bd00…3be00 (59, 0, 13) Sector 3b0e1200503341 ┆; P3AST QA QAR Case Test Step No. Station Action Expected Results 7.16 TESTVDU#2 Enter from TEST VDU#2: TEST VDU#2 display as DO OPEN2(CR) specified┆
0x3be00…3bf00 (59, 0, 14) Sector 3b0fff00503341 ┆; P3A 1 1 TEST STEPS TEST NO.: 2/3 FUNCTION: Watchdog Processor System Test SRS REFERENCE: N/A ┆
0x3bf00…3c000 (59, 0, 15) Sector 3b00ff00503341 ┆; P3A Case Test Step No. Station Action Expected Results 8.13 N/A Depress both CONTROL N/A SHIFT and CLEAR on TEST VDU#2. 8.14 OC Ent┆
0x3c000…3c100 (60, 0, 0) Sector 3c01ff00503341 ┆< P3A 1 1 TEST STEPS TEST NO.: 2/3 FUNCTION: Watchdog Processor System Test SRS REFERENCE: N/A ┆
0x3c100…3c200 (60, 0, 1) Sector 3c02ff00503341 ┆< P3A Case Test Step No. Station Action Expected Results 8.1 N/A Depress both CONTROL N/A SHIFT and CLEAR on TEST VDU#1. 8.2 N/A Depr┆
0x3c200…3c300 (60, 0, 2) Sector 3c03ff00503341 ┆< P3Aess both CONTROL N/A SHIFT and CLEAR on TEST VDU#2. 8.3 OC Enter from the OC: Refer to appendix B CCB(CR) sec. 15.1 A4 13 00(CR) 8.4 OC Enter from the OC: Refer to appendix B CCB(CR) sec. 15.2 A4 13 01(CR) ┆
0x3c300…3c400 (60, 0, 3) Sector 3c048700503341 ┆< P3A Comments: TEST WITNESSES TEST QA QAR 7.8 OC Enter from the OC: Refer to appendix B CCB(CR) sec. 14.6 94 12 FF FF(CR) ┆
0x3c400…3c500 (60, 0, 4) Sector 3c05ff00503341 ┆< P3A 1 1 TEST STEPS TEST NO.: 2/3 FUNCTION: Watchdog Processor System Test SRS REFERENCE: N/A ┆
0x3c500…3c600 (60, 0, 5) Sector 3c06ff00503341 ┆< P3A Case Test Step No. Station Action Expected Results 8.5 OC Enter from the OC: Refer to appendix B CCB(CR) sec. 15.3 A4 13 02(CR) 8.6┆
0x3c600…3c700 (60, 0, 6) Sector 3c07ff00503341 ┆< P3A OC Enter from the OC: Refer to appendix B CCB(CR) sec. 15.4 A4 13 03(CR) 8.7 OC Enter from the OC: Refer to appendix B CCB(CR) sec. 15.5 A4 13 04(CR) 8.8 OC Enter from the OC: Refer to appendix B CCB(CR) sec. 15.6 94 13 FF FF(CR) 8.9┆
0x3c700…3c800 (60, 0, 7) Sector 3b08ff00503341 ┆; P3A OC Enter from the OC: Refer to appendix B CCB(CR) sec. 15.7 98 13 FF 00 02 00(CR) (Switch on TDX BUS#1) Comments: TEST WITNESSES TEST┆
0x3c800…3c900 (60, 0, 8) Sector 3c09ff00503341 ┆< P3A Case Test Step No. Station Action Expected Results 7.12 N/A Depress both CONTROL N/A SHIFT and CLEAR on TEST VDU#1. 7.13 N/A De┆
0x3c900…3ca00 (60, 0, 9) Sector 3c0aff00503341 ┆< P3Apress both CONTROL N/A SHIFT and CLEAR on TEST VDU#2. 7.14 OC Enter from the OC: Refer to appendix B CCB(CR) sec. 14.8 98 12 FF 00 01 00(CR) (Switch on TDX BUS#2) 7.15 TESTVDU#1 Enter from TEST VDU#1: TEST VDU#1 display DO OPEN2(CR) ┆
0x3ca00…3cb00 (60, 0, 10) Sector 3c0bff00503341 ┆< P3Aas specified in (Appendix A, sec. 4.8a) appendix B, sec. DO CLOSE2(CR) 30.10 (Appendix A, sec. 4.8b) Comments: TEST WITNESSES ┆
0x3cb00…3cc00 (60, 0, 11) Sector 3c0c1400503341 ┆< P3ATEST QA QAR A, sec. 4.7a) appendix B, sec. DO CLOSE1(CR) 30.8 (Appendix A, sec. 4.7b) 6.18 TESTVDU#2 Enter from TEST VDU#2: TEST VDU#2 display as DO OPEN1(CR) specified in appendix (Appendix A, sec. 4.7a) B sec. 30.7 DO CLOSE1(CR) ┆
0x3cc00…3cd00 (60, 0, 12) Sector 3c0dff00503341 ┆< P3A 1 1 TEST STEPS TEST NO.: 2/3 FUNCTION: Watchdog Processor System Test SRS REFERENCE: N/A ┆
0x3cd00…3ce00 (60, 0, 13) Sector 3c0eff00503341 ┆< P3A Case Test Step No. Station Action Expected Results 7.16 TESTVDU#2 Enter from TEST VDU#2: TEST VDU#2 display as DO OPEN2(CR) specified┆
0x3ce00…3cf00 (60, 0, 14) Sector 3c0fff00503341 ┆< P3A in appendix (Appendix A, sec. 4.8a) B sec. 30.9 DO CLOSE2(CR) (Appendix A, sec. 4.8b) Comments: TEST WITNESSES ┆
0x3cf00…3d000 (60, 0, 15) Sector 3c001400503341 ┆< P3ATEST QA QAR ROL N/A SHIFT and CLEAR on TEST VDU#2. 7.3 OC Enter from the OC: Refer to appendix B CCB(CR) sec. 14.1 A4 12 00(CR) 7.4 OC Enter from the OC: Refer to appendix B CCB(CR) sec. 14.2 A4 12 01(CR) 7.5 OC Enter from the OC┆
0x3d000…3d100 (61, 0, 0) Sector 3d01ff00503341 ┆= P3A: Refer to appendix B CCB(CR) sec. 14.3 A4 12 02(CR) 7.6 OC Enter from the OC: Refer to appendix B CCB(CR) sec. 14.4 A4 12 03(CR) 7.7 OC Enter from the OC: Refer to appendix B CCB(CR) sec. 14.5 A4 12 04(CR) ┆
0x3d100…3d200 (61, 0, 1) Sector 3d027800503341 ┆= x P3A Comments: TEST WITNESSES TEST QA QAR program as follows: accordance with appen- BA 1025 dix B sec. 7.1 BM 140 BO 62F 6.10 OC Enter from the OC: Refer to appendix B┆
0x3d200…3d300 (61, 0, 2) Sector 3d03ff00503341 ┆= P3A 1 1 TEST STEPS TEST NO.: 2/3 FUNCTION: Watchdog Processor System Test SRS REFERENCE: N/A ┆
0x3d300…3d400 (61, 0, 3) Sector 3d04ff00503341 ┆= P3A Case Test Step No. Station Action Expected Results 7.8 OC Enter from the OC: Refer to appendix B CCB(CR) sec. 14.6 94 12 FF FF(CR) ┆
0x3d400…3d500 (61, 0, 4) Sector 3d05ff00503341 ┆= P3A7.9 OC Enter from the OC: Refer to appendix B CCB(CR) sec. 14.7 98 12 FF 00 02 00(CR) (Switch on TDX BUS#1) 7.10 TESTVDU#1 Enter from TEST VDU#1: TEST VDU#1 display as DO OPEN2(CR) specified in appendix (Appendix A, sec. 4.8a) B sec. 30.9┆
0x3d500…3d600 (61, 0, 5) Sector 3d06ff00503341 ┆= P3A DO CLOSE2(CR) (Appendix A, sec. 4.8b) 7.11 TESTVDU#2 Enter from TEST VDU#2: TEST VDU#2 display DO OPEN2(CR) as specified in (Appendix A, sec. 4.8a) appendix B, sec. DO CLOSE2(CR) 30.10 (Appendix A, sec. 4.8b) ┆
0x3d600…3d700 (61, 0, 6) Sector 3d078800503341 ┆= P3A Comments: TEST WITNESSES TEST QA QAR SHIFT and CLEAR on TEST VDU#1. 6.15 N/A Depress both CONTROL N/A SHIFT and CLEAR on TEST VDU#2. 6.16 O┆
0x3d700…3d800 (61, 0, 7) Sector 3c08ff00503341 ┆< P3A 1 1 TEST STEPS TEST NO.: 2/3 FUNCTION: Watchdog Processor System Test SRS REFERENCE: N/A ┆
0x3d800…3d900 (61, 0, 8) Sector 3d091000503341 ┆= P3A QA QAR .2 5.34 TESTVDU#2 Enter from TEST VDU#2: TEST VDU #2 display IR 1A07(CR) as specified in ap- pendix B, sec. 30.3 5.35 OC Enter from the OC: Refer to appendix D CCB(CR) sec. 12.14 98 03 0F 00 00 00(CR) (Enable CU Bus A and B) ┆
0x3d900…3da00 (61, 0, 9) Sector 3d0aff00503341 ┆= P3A 1 1 TEST STEPS TEST NO.: 2/3 FUNCTION: Watchdog Processor System Test SRS REFERENCE: N/A ┆
0x3da00…3db00 (61, 0, 10) Sector 3d0bff00503341 ┆= P3A Case Test Step No. Station Action Expected Results 6.17 TESTVDU#1 Enter from TEST VDU#1: TEST VDU#1 display DO OPEN1(CR) as specified ┆
0x3db00…3dc00 (61, 0, 11) Sector 3d0cff00503341 ┆= P3Ain (Appendix A, sec. 4.7a) appendix B, sec. DO CLOSE1(CR) 30.8 (Appendix A, sec. 4.7b) 6.18 TESTVDU#2 Enter from TEST VDU#2: TEST VDU#2 display as DO OPEN1(CR) specified in appendix (Appendix A, sec. 4.7a) B sec. 30.7 DO CLOSE1(CR) ┆
0x3dc00…3dd00 (61, 0, 12) Sector 3d0dbf00503341 ┆= ? P3A (Appendix A, sec. 4.7b) Comments: TEST WITNESSES TEST QA QAR x B CCB(CR) sec. 13.2 A4 11 01(CR) 6.5 OC Enter from the OC┆
0x3dd00…3de00 (61, 0, 13) Sector 3d0eff00503341 ┆= P3A 1 1 TEST STEPS TEST NO.: 2/3 FUNCTION: Watchdog Processor System Test SRS REFERENCE: N/A ┆
0x3de00…3df00 (61, 0, 14) Sector 3d0fff00503341 ┆= P3A Case Test Step No. Station Action Expected Results 7.1 N/A Depress both CONTROL N/A SHIFT and CLEAR on TEST VDU#1. 7.2 N/A Depr┆
0x3df00…3e000 (61, 0, 15) Sector 3d00ff00503341 ┆= P3Aess both CONTROL N/A SHIFT and CLEAR on TEST VDU#2. 7.3 OC Enter from the OC: Refer to appendix B CCB(CR) sec. 14.1 A4 12 00(CR) 7.4 OC Enter from the OC: Refer to appendix B CCB(CR) sec. 14.2 A4 12 01(CR) 7.5 OC Enter from the OC┆
0x3e000…3e100 (62, 0, 0) Sector 3e01ff00503341 ┆> P3A Case Test Step No. Station Action Expected Results 6.8 TESTVDU#1 Boot the TDX1 test TEST VDU#1 display in program as follows: accordan┆
0x3e100…3e200 (62, 0, 1) Sector 3e02ff00503341 ┆> P3Ace with appen- BA 1025 dix B sec. 7.1 BM 140 BO 62F 6.9 TESTVDU#2 Boot the TDX1 test TEST VDU#2 display in program as follows: accordance with appen- BA 1025 dix B sec. 7.1 BM 140 BO 62F 6.10 OC Enter from the OC: Refer to appendix B┆
0x3e200…3e300 (62, 0, 2) Sector 3e03ff00503341 ┆> P3A CCB(CR) sec. 13.6 94 11 FF FF(CR) 6.11 OC Enter from the OC: Refer to appendix B CCB(CR) sec. 13.7 98 11 FF 00 02 00(CR) (Switch on TDX BUS#1) 6.12 TESTVDU#1 Enter from TEST VDU#1: DO OPEN1(CR) (Appendix A, sec. 4.7a) Test VDU#1 dis┆
0x3e300…3e400 (62, 0, 3) Sector 3e04f100503341 ┆> q P3Aplay as DO CLOSE1(CR) specified in appendix (Appendix A, sec. 4.7b) B sec. 30.7 Comments: TEST WITNESSES TEST QA QAR ┆
0x3e400…3e500 (62, 0, 4) Sector 3e05ff00503341 ┆> P3A 1 1 TEST STEPS TEST NO.: 2/3 FUNCTION: Watchdog Processor System Test SRS REFERENCE: N/A ┆
0x3e500…3e600 (62, 0, 5) Sector 3e06ff00503341 ┆> P3A Case Test Step No. Station Action Expected Results 6.13 TESTVDU#2 Enter from TEST VDU#2: TEST VDU#2 display DO OPEN1(CR) as specified ┆
0x3e600…3e700 (62, 0, 6) Sector 3e07ff00503341 ┆> P3Ain (Appendix A, sec. 4.7a) appendix B, sec. DO CLOSE1(CR) 30.8 (Appendix A, sec. 4.7b) 6.14 N/A Depress both CONTROL N/A SHIFT and CLEAR on TEST VDU#1. 6.15 N/A Depress both CONTROL N/A SHIFT and CLEAR on TEST VDU#2. 6.16 O┆
0x3e700…3e800 (62, 0, 7) Sector 3d08ff00503341 ┆= P3AC Enter from the OC: Refer to appendix B CCB(CR) sec. 13.8 98 11 FF 00 01 00(CR) (Switch on TDX BUS#2) Comments: TEST WITNESSES TEST┆
0x3e800…3e900 (62, 0, 8) Sector 3e09ff00503341 ┆> P3AB, sec. 30.2 5.34 TESTVDU#2 Enter from TEST VDU#2: TEST VDU #2 display IR 1A07(CR) as specified in ap- pendix B, sec. 30.3 5.35 OC Enter from the OC: Refer to appendix D CCB(CR) sec. 12.14 98 03 0F 00 00 00(CR) (Enable CU Bus A and B) ┆
0x3e900…3ea00 (62, 0, 9) Sector 3e0a9800503341 ┆> P3A Comments: TEST WITNESSES TEST QA QAR splay in accordance Display with appendix B sec. 1.1 ┆
0x3ea00…3eb00 (62, 0, 10) Sector 3e0bff00503341 ┆> P3A 1 1 TEST STEPS TEST NO.: 2/3 FUNCTION: Watchdog Processor System Test SRS REFERENCE: N/A ┆
0x3eb00…3ec00 (62, 0, 11) Sector 3e0cff00503341 ┆> P3A Case Test Step No. Station Action Expected Results 6.1 N/A Depress both CONTROL N/A SHIFT and CLEAR on TEST VDU#1. 6.2 N/A Depr┆
0x3ec00…3ed00 (62, 0, 12) Sector 3e0dff00503341 ┆> P3Aess both CONTROL N/A SHIFT and CLEAR on TEST VDU#2. 6.3 OC Enter from the OC: Refer to appendix B CCB(CR) sec. 13.1 A4 11 00(CR) 6.4 OC Enter from the OC: Refer to appendix B CCB(CR) sec. 13.2 A4 11 01(CR) 6.5 OC Enter from the OC┆
0x3ed00…3ee00 (62, 0, 13) Sector 3e0eff00503341 ┆> P3A: Refer to appendix B CCB(CR) sec. 13.3 A4 11 02(CR) 6.6 OC Enter from the OC: Refer to appendix B CCB(CR) sec. 13.4 A4 11 03(CR) 6.7 OC Enter from the OC: Refer to appendix B CCB(CR) sec. 13.5 A4 11 04(CR) ┆
0x3ee00…3ef00 (62, 0, 14) Sector 3e0f7800503341 ┆> x P3A Comments: TEST WITNESSES TEST QA QAR Comments: TEST WITNESSES TEST QA ┆
0x3ef00…3f000 (62, 0, 15) Sector 3e00ff00503341 ┆> P3A 1 1 TEST STEPS TEST NO.: 2/3 FUNCTION: Watchdog Processor System Test SRS REFERENCE: N/A ┆
0x3f000…3f100 (63, 0, 0) Sector 3f01ff00503341 ┆? P3A 1 1 TEST STEPS TEST NO.: 2/3 FUNCTION: Watchdog Processor System Test SRS REFERENCE: N/A ┆
0x3f100…3f200 (63, 0, 1) Sector 3f02ff00503341 ┆? P3A Case Test Step No. Station Action Expected Results 5.26 N/A Depress both CONTROL N/A SHIFT and CLEAR on TEST VDU#1. 5.27 N/A De┆
0x3f200…3f300 (63, 0, 2) Sector 3f03ff00503341 ┆? P3Apress both CONTROL N/A SHIFT and CLEAR on TEST VDU#2. 5.28 OC Enter from the OC: Refer to appendix B CCB(CR) sec. 12.13 98 03 0F 00 08 00(CR) (Disable CU Bus B, Enable CU Bus A) 5.29 TESTVDU#1 Enter from TEST VDU#1: TEST VDU #1 display┆
0x3f300…3f400 (63, 0, 3) Sector 3f04ff00503341 ┆? P3A IR 1A25(CR) as specified in ap- pendix B, sec. 30.4 5.30 TESTVDU#1 Enter from TEST VDU#1: TEST VDU #1 display IR 1A01(CR) as specified in ap- pendix B, sec. 30.5 ┆
0x3f400…3f500 (63, 0, 4) Sector 3f055000503341 ┆? P P3A Comments: TEST WITNESSES TEST QA QAR Comments: TEST WITNESSES TEST QA QAR Comments: TEST WITNESSES TEST QA QAR┆
0x3f500…3f600 (63, 0, 5) Sector 3f06ff00503341 ┆? P3A 1 1 TEST STEPS TEST NO.: 2/3 FUNCTION: Watchdog Processor System Test SRS REFERENCE: N/A ┆
0x3f600…3f700 (63, 0, 6) Sector 3f07ff00503341 ┆? P3A Case Test Step No. Station Action Expected Results 5.31 TESTVDU#1 Enter from TEST VDU#1: TEST VDU #1 display IR 1A07(CR) as specified ┆
0x3f700…3f800 (63, 0, 7) Sector 3e08ff00503341 ┆> P3Ain ap- pendix B, sec. 30.6 5.32 TESTVDU#2 Enter from TEST VDU#2: TEST VDU #2 display IR 1A25(CR) as specified in ap- pendix B, sec. 30.1 5.33 TESTVDU#2 Enter from TEST VDU#2: TEST VDU #2 display IR 1A01(CR) as specified in ap- pendix ┆
0x3f800…3f900 (63, 0, 8) Sector 3f09ff00503341 ┆? P3As both CONTROL N/A SHIFT and CLEAR on TEST VDU#1. 5.19 N/A Depress both CONTROL N/A SHIFT and CLEAR on TEST VDU#2. Comments: TES┆
0x3f900…3fa00 (63, 0, 9) Sector 3f0a2400503341 ┆? $ P3AT WITNESSES TEST QA QAR CCB(CR) sec. 11.16 98 02 0F 00 00 00(CR) (Release Master Clear PU#2, Normal Mode) 4.20 N/A Examine TEST VDU#2 Display in accordance Display with appendix B sec. 1.1 ┆
0x3fa00…3fb00 (63, 0, 10) Sector 3f0bff00503341 ┆? P3A 1 1 TEST STEPS TEST NO.: 2/3 FUNCTION: Watchdog Processor System Test SRS REFERENCE: N/A ┆
0x3fb00…3fc00 (63, 0, 11) Sector 3f0cff00503341 ┆? P3A Case Test Step No. Station Action Expected Results 5.20 TESTVDU#1 Enter from TEST VDU#1: TEST VDU #1 display IR 1A25(CR) as specified in a┆
0x3fc00…3fd00 (63, 0, 12) Sector 3f0dff00503341 ┆? P3Ap- pendix B, sec. 30.1 5.21 TESTVDU#1 Enter from TEST VDU#1: TEST VDU #1 display IR 1A01(CR) as specified in ap- pendix B, sec. 30.2 5.22 TESTVDU#1 Enter from TEST VDU#1: TEST VDU #1 display IR 1A07(CR) as specified in ap- pendix B, s┆
0x3fd00…3fe00 (63, 0, 13) Sector 3f0eff00503341 ┆? P3Aec. 30.3 5.23 TESTVDU#2 Enter from TEST VDU#2: TEST VDU #2 display IR 1A25(CR) as specified in ap- pendix B, sec. 30.4 5.24 TESTVDU#2 Enter from TEST VDU#2: TEST VDU #2 display IR 1A01(CR) as specified in ap- pendix B, sec. 30.5 5.25 TE┆
0x3fe00…3ff00 (63, 0, 14) Sector 3f0fff00503341 ┆? P3ASTVDU#2 Enter from TEST VDU#2: TEST VDU #2 display IR 1A07(CR) as specified in ap- pendix B, sec. 30.6 Comments: TEST WITNESSES TEST QA ┆
0x3ff00…40000 (63, 0, 15) Sector 3f000b00503341 ┆? P3A QAR ST WITNESSES TEST QA QAR c. 11.10 98 02 0F 00 04 00(CR) (PU#2 enable, Maintenance Mode) Comments: TEST WITNESSES TEST QA Q┆
0x40000…40100 (64, 0, 0) Sector 4001ff00503341 ┆@ P3A 1 1 TEST STEPS TEST NO.: 2/3 FUNCTION: Watchdog Processor System Test SRS REFERENCE: N/A ┆
0x40100…40200 (64, 0, 1) Sector 4002ff00503341 ┆@ P3A Case Test Step No. Station Action Expected Results 5.7 OC Enter from the OC: Refer to appendix B CCB(CR) sec. 12.5 A4 03 0F(CR) 5.8 ┆
0x40200…40300 (64, 0, 2) Sector 4003ff00503341 ┆@ P3AOC Enter from the OC: Refer to appendix B CCB(CR) sec. 12.6 A4 03 06(CR) 5.9 OC Enter from the OC: Refer to appendix B CCB(CR) sec. 12.7 A4 03 07(CR) 5.10 OC Enter from the OC: Refer to appendix B CCB(CR) sec. 12.8 A4 03 08(CR) 5.11 O┆
0x40300…40400 (64, 0, 3) Sector 4004ff00503341 ┆@ P3AC Enter from the OC: Refer to appendix B CCB(CR) sec. 12.9 94 03 0F 00(CR) 5.12 N/A The CU Bus A DIS/AUTO N/A switch on the CUCP front panel is set to DIS. 5.13 OC Enter from the OC: Refer to appendix B CCB(CR) sec. 12.10 94 03 0F 00┆
0x40400…40500 (64, 0, 4) Sector 40059900503341 ┆@ P3A(CR) Comments: TEST WITNESSES TEST QA QAR Comments: TEST WITNESSES TEST QA QAR┆
0x40500…40600 (64, 0, 5) Sector 4006ff00503341 ┆@ P3A 1 1 TEST STEPS TEST NO.: 2/3 FUNCTION: Watchdog Processor System Test SRS REFERENCE: N/A ┆
0x40600…40700 (64, 0, 6) Sector 4007ff00503341 ┆@ P3A Case Test Step No. Station Action Expected Results 5.14 N/A The CU Bus A DIS/AUTO N/A switch on the CUCP front panel is set to AUTO. ┆
0x40700…40800 (64, 0, 7) Sector 3f08ff00503341 ┆? P3A5.15 OC Enter from the OC: Refer to appendix B CCB(CR) sec. 12.11 98 03 0F 00 00 00(CR) 5.16 Intentionally deleted 5.17 OC Enter from the OC: Refer to appendix B CCB(CR) sec. 12.12 98 03 0F 00 04 00(CR) (Disable CU Bus A) 5.18 N/A Depres┆
0x40800…40900 (64, 0, 8) Sector 4009ff00503341 ┆@ P3A00(CR) (PU#2 Normal Mode) 4.17 OC Enter from the OC: Refer to appendix B CCB(CR) sec. 11.15 98 02 0F 00 08 00(CR) (Set Master Clear PU#2, Normal Mode) 4.18 N/A Depress both CONTROL N/A SHIFT and CLEAR on TEST VDU#2. 4.19 OC Enter from┆
0x40900…40a00 (64, 0, 9) Sector 400aff00503341 ┆@ P3A the OC: Refer to appendix B CCB(CR) sec. 11.16 98 02 0F 00 00 00(CR) (Release Master Clear PU#2, Normal Mode) 4.20 N/A Examine TEST VDU#2 Display in accordance Display with appendix B sec. 1.1 ┆
0x40a00…40b00 (64, 0, 10) Sector 400b6a00503341 ┆@ j P3A Comments: TEST WITNESSES TEST QA QAR : Refer to appendix B CCB(CR) sec. 11.6 94 02 0F 00(CR) Comments: ┆
0x40b00…40c00 (64, 0, 11) Sector 400cff00503341 ┆@ P3A 1 1 TEST STEPS TEST NO.: 2/3 FUNCTION: Watchdog Processor System Test SRS REFERENCE: N/A ┆
0x40c00…40d00 (64, 0, 12) Sector 400dff00503341 ┆@ P3A Case Test Step No. Station Action Expected Results 5.1 N/A Depress both CONTROL N/A SHIFT and CLEAR on TEST VDU#1. 5.2 N/A Depr┆
0x40d00…40e00 (64, 0, 13) Sector 400eff00503341 ┆@ P3Aess both CONTROL N/A SHIFT and CLEAR on TEST VDU#2. 5.3 OC Enter from the OC: Refer to appendix B CCB(CR) sec. 12.1 A4 03 0E(CR) 5.4 OC Enter from the OC: Refer to appendix B CCB(CR) sec. 12.2 A4 03 01(CR) 5.5 OC Enter from the OC┆
0x40e00…40f00 (64, 0, 14) Sector 400fff00503341 ┆@ P3A: Refer to appendix B CCB(CR) sec. 12.3 A4 03 02(CR) 5.6 OC Enter from the OC: Refer to appendix B CCB(CR) sec. 12.4 A4 03 03(CR) Comments: ┆
0x40f00…41000 (64, 0, 15) Sector 40002a00503341 ┆@ * P3A TEST WITNESSES TEST QA QAR c. 11.10 98 02 0F 00 04 00(CR) (PU#2 enable, Maintenance Mode) Comments: TEST WITNESSES TEST QA Q┆
0x41000…41100 (65, 0, 0) Sector 41010900503341 ┆A P3AAR dix B CCB(CR) sec. 10.15 98 01 0F 00 04 00(CR) (Release Master Clear PU#1, Maintenance Mode) Comments: TEST WITNESSES TEST QA QAR┆
0x41100…41200 (65, 0, 1) Sector 4102ff00503341 ┆A P3A 1 1 TEST STEPS TEST NO.: 2/3 FUNCTION: Watchdog Processor System Test SRS REFERENCE: N/A ┆
0x41200…41300 (65, 0, 2) Sector 4103ff00503341 ┆A P3A Case Test Step No. Station Action Expected Results 4.12 OC Enter from the OC: Refer to appendix B CCB(CR) sec. 11.11 94 02 0F 00(CR)┆
0x41300…41400 (65, 0, 3) Sector 4104ff00503341 ┆A P3A 4.13 OC Enter from the OC: Refer to appendix B CCB(CR) sec. 11.12 98 02 0F 00 0C 00(CR) (Set Master Clear PU#2, Maintenance Mode) 4.14 N/A Depress both CONTROL N/A SHIFT and CLEAR on TEST VDU#2. 4.15 OC Enter from the OC: Refer to ap┆
0x41400…41500 (65, 0, 4) Sector 4105ff00503341 ┆A P3Apendix B CCB(CR) sec. 11.13 98 02 0F 00 04 00(CR) (Release Master Clear PU#2, Maintenance Mode) Comments: TEST WITNESSES TEST QA QAR┆
0x41500…41600 (65, 0, 5) Sector 41060700503341 ┆A P3A the OC: Refer to appendix B CCB(CR) sec. 10.18 98 01 0F 00 00 00(CR) (Release Master Clear PU#1, Normal Mode) 3.20 N/A Examine TEST VDU#1 Display in accordance Display with appendix B sec. 1.1 ┆
0x41600…41700 (65, 0, 6) Sector 4107ff00503341 ┆A P3A 1 1 TEST STEPS TEST NO.: 2/3 FUNCTION: Watchdog Processor System Test SRS REFERENCE: N/A ┆
0x41700…41800 (65, 0, 7) Sector 4008ff00503341 ┆@ P3A Case Test Step No. Station Action Expected Results 4.16 OC Enter from the OC: Refer to appendix B CCB(CR) sec. 11.14 98 02 0F 00 00 ┆
0x41800…41900 (65, 0, 8) Sector 4109ff00503341 ┆A P3A Case Test Step No. Station Action Expected Results 4.1 OC Enter from the OC: Refer to appendix B CCB(CR) sec. 11.1 A4 02 0E(CR) 4.2┆
0x41900…41a00 (65, 0, 9) Sector 410aff00503341 ┆A P3A OC Enter from the OC: Refer to appendix B CCB(CR) sec. 11.2 A4 02 01(CR) 4.3 OC Enter from the OC: Refer to appendix B CCB(CR) sec. 11.3 A4 02 02(CR) 4.4 OC Enter from the OC: Refer to appendix B CCB(CR) sec. 11.4 A4 02 03(CR) 4.5 OC┆
0x41a00…41b00 (65, 0, 10) Sector 410bff00503341 ┆A P3A Enter from the OC: Refer to appendix B CCB(CR) sec. 11.5 A4 02 0F(CR) 4.6 OC Enter from the OC: Refer to appendix B CCB(CR) sec. 11.6 94 02 0F 00(CR) Comments: ┆
0x41b00…41c00 (65, 0, 11) Sector 410c3f00503341 ┆A ? P3A TEST WITNESSES TEST QA QAR F 00 04 00(CR) (Enable PU#1, Maintenance mode) Comments: TEST WITNESSES TEST QA ┆
0x41c00…41d00 (65, 0, 12) Sector 410dff00503341 ┆A P3A 1 1 TEST STEPS TEST NO.: 2/3 FUNCTION: Watchdog Processor System Test SRS REFERENCE: N/A ┆
0x41d00…41e00 (65, 0, 13) Sector 410eff00503341 ┆A P3A Case Test Step No. Station Action Expected Results 4.7 OC Enter from the OC: Refer to appendix B CCB(CR) sec. 11.7 98 02 0F 00 00 00┆
0x41e00…41f00 (65, 0, 14) Sector 410fff00503341 ┆A P3A(CR) 4.8 Intentionally deleted 4.9 OC Enter from the OC: Refer to appendix B CCB(CR) sec. 11.8 98 02 0F 00 01 00(CR) (PU#2 disable) 4.10 OC Enter from the OC: Refer to appendix B CCB(CR) sec. 11.9 94 02 0F 00(CR) 4.11 OC Enter from the ┆
0x41f00…42000 (65, 0, 15) Sector 4100ff00503341 ┆A P3AOC: Refer to appendix B CCB(CR) sec. 11.10 98 02 0F 00 04 00(CR) (PU#2 enable, Maintenance Mode) Comments: TEST WITNESSES TEST QA Q┆
0x42000…42100 (66, 0, 0) Sector 4201ff00503341 ┆B P3Apendix B CCB(CR) sec. 10.15 98 01 0F 00 04 00(CR) (Release Master Clear PU#1, Maintenance Mode) Comments: TEST WITNESSES TEST QA QAR┆
0x42100…42200 (66, 0, 1) Sector 42020700503341 ┆B P3A N/A The EN/DIS switch on N/A the CCBA front panel is set to DIS 2.3 OC Enter from the OC: Refer to appendix B CCB(CR) sec. 10.2 A4 01 03(CR) 2.4 N/A The EN/DIS switch on N/A the CCBA front panel is set to EN ┆
0x42200…42300 (66, 0, 2) Sector 4203ff00503341 ┆B P3A 1 1 TEST STEPS TEST NO.: 2/3 FUNCTION: Watchdog Processor System Test SRS REFERENCE: N/A ┆
0x42300…42400 (66, 0, 3) Sector 4204ff00503341 ┆B P3A Case Test Step No. Station Action Expected Results 3.16 OC Enter from the OC: Refer to appendix B CCB(CR) sec. 10.16 98 01 0F 00 00 ┆
0x42400…42500 (66, 0, 4) Sector 4205ff00503341 ┆B P3A00(CR) (PU#1 Normal Mode) 3.17 OC Enter from the OC: Refer to appendix B CCB(CR) sec. 10.17 98 01 0F 00 08 00(CR) (Set Master Clear PU#1, Normal Mode) 3.18 N/A Depress both CONTROL N/A SHIFT and CLEAR on TEST VDU#1. 3.19 OC Enter from┆
0x42500…42600 (66, 0, 5) Sector 4206ff00503341 ┆B P3A the OC: Refer to appendix B CCB(CR) sec. 10.18 98 01 0F 00 00 00(CR) (Release Master Clear PU#1, Normal Mode) 3.20 N/A Examine TEST VDU#1 Display in accordance Display with appendix B sec. 1.1 ┆
0x42600…42700 (66, 0, 6) Sector 42076a00503341 ┆B j P3A Comments: TEST WITNESSES TEST QA QAR : Refer to appendix B CCB(CR) sec. 10.8 94 01 0F 00(CR) Comments: ┆
0x42700…42800 (66, 0, 7) Sector 4108ff00503341 ┆A P3A 1 1 TEST STEPS TEST NO.: 2/3 FUNCTION: Watchdog Processor System Test SRS REFERENCE: N/A ┆
0x42800…42900 (66, 0, 8) Sector 4209ff00503341 ┆B P3A 1 1 TEST STEPS TEST NO.: 2/3 FUNCTION: Watchdog Processor System Test SRS REFERENCE: N/A ┆
0x42900…42a00 (66, 0, 9) Sector 420aff00503341 ┆B P3A Case Test Step No. Station Action Expected Results 3.7 OC Enter from the OC: Refer to appendix B CCB(CR) sec. 10.9 98 01 0F 00 00 00┆
0x42a00…42b00 (66, 0, 10) Sector 420bff00503341 ┆B P3A(CR) 3.8 Intentionally deleted 3.9 OC Enter from the OC: Refer to appendix B CCB(CR) sec. 10.10 98 01 0F 00 01 00(CR) (Disable PU#1) 3.10 OC Enter from the OC: Refer to appendix B CCB(CR) sec. 10.11 94 01 0F 00(CR) 3.11 OC Enter from t┆
0x42b00…42c00 (66, 0, 11) Sector 420cff00503341 ┆B P3Ahe OC: Refer to appendix B CCB(CR) sec. 10.12 98 01 0F 00 04 00(CR) (Enable PU#1, Maintenance mode) Comments: TEST WITNESSES TEST QA ┆
0x42c00…42d00 (66, 0, 12) Sector 420d0c00503341 ┆B P3A QAR Case Test Step No. Station Action Expected Results 1.6 OC Enter from the OC: Refer to appendix B PU2(CR) sec. 9.4 10 02 00 00 54 4┆
0x42d00…42e00 (66, 0, 13) Sector 420eff00503341 ┆B P3A 1 1 TEST STEPS TEST NO.: 2/3 FUNCTION: Watchdog Processor System Test SRS REFERENCE: N/A ┆
0x42e00…42f00 (66, 0, 14) Sector 420fff00503341 ┆B P3A Case Test Step No. Station Action Expected Results 3.12 OC Enter from the OC: Refer to appendix B CCB(CR) sec. 10.13 94 01 0F 00(CR)┆
0x42f00…43000 (66, 0, 15) Sector 4200ff00503341 ┆B P3A 3.13 OC Enter from the OC: Refer to appendix B CCB(CR) sec. 10.14 98 01 0F 00 0C 00(CR) (Set Master Clear PU#1, Maintenance Mode) 3.14 N/A Depress both CONTROL N/A SHIFT and CLEAR on TEST VDU#1. 3.15 OC Enter from the OC: Refer to ap┆
0x43000…43100 (67, 0, 0) Sector 4301ff00503341 ┆C P3A Case Test Step No. Station Action Expected Results 2.1 OC Enter from the OC: Refer to appendix B CCB(CR) sec. 10.1 A4 01 03(CR) 2.2┆
0x43100…43200 (67, 0, 1) Sector 4302ff00503341 ┆C P3A N/A The EN/DIS switch on N/A the CCBA front panel is set to DIS 2.3 OC Enter from the OC: Refer to appendix B CCB(CR) sec. 10.2 A4 01 03(CR) 2.4 N/A The EN/DIS switch on N/A the CCBA front panel is set to EN ┆
0x43200…43300 (67, 0, 2) Sector 43038600503341 ┆C P3A Comments: TEST WITNESSES TEST QA QAR lizers are set to off. 2) The three rotary switches on the By-Pass panel are all set to the Frequency Stabilizer posit┆
0x43300…43400 (67, 0, 3) Sector 4304ff00503341 ┆C P3A 1 1 TEST STEPS TEST NO.: 2/3 FUNCTION: Watchdog Processor System Test SRS REFERENCE: N/A ┆
0x43400…43500 (67, 0, 4) Sector 4305ff00503341 ┆C P3A Case Test Step No. Station Action Expected Results 3.1 OC Enter from the OC: Refer to appendix B CCB(CR) sec. 10.3 A4 01 0E(CR) 3.2┆
0x43500…43600 (67, 0, 5) Sector 4306ff00503341 ┆C P3A OC Enter from the OC: Refer to appendix B CCB(CR) sec. 10.4 A4 01 01(CR) 3.3 OC Enter from the OC: Refer to appendix B CCB(CR) sec. 10.5 A4 01 02(CR) 3.4 OC Enter from the OC: Refer to appendix B CCB(CR) sec. 10.6 A4 01 03(CR) 3.5 OC┆
0x43600…43700 (67, 0, 6) Sector 4307ff00503341 ┆C P3A Enter from the OC: Refer to appendix B CCB(CR) sec. 10.7 A4 01 0F(CR) 3.6 OC Enter from the OC: Refer to appendix B CCB(CR) sec. 10.8 94 01 0F 00(CR) Comments: ┆
0x43700…43800 (67, 0, 7) Sector 42083f00503341 ┆B ? P3A TEST WITNESSES TEST QA QAR . Station Action Expected Results 1.1 N/A The EN/DIS switch on N/A the CCBA front panel is set to EN 1.2 OC Examin┆
0x43800…43900 (67, 0, 8) Sector 4309ff00503341 ┆C P3Ae print out on Refer to appendix B the OC. sec 9.1 1.3 Enter from the OC: PUANSW(SP)D(CR) Refer to appendix B CCA(SP)1-3(CR) sec. 9.2 BSMX(SP)11-1F(CR) CCBUM(CR) 1.4 N/A Examine TEST VDU#1 and Displays in compli- TEST VDU#2 displays a┆
0x43900…43a00 (67, 0, 9) Sector 430aff00503341 ┆C P3Ance with appendix B sec. 1.1 1.5 OC Enter from the OC: Refer to appendix B PU1(CR) sec. 9.3 10 01 00 00 54 45 53 54(CR) Comments: TEST┆
0x43a00…43b00 (67, 0, 10) Sector 430b2300503341 ┆C # P3A WITNESSES TEST QA QAR k) PU#2 cable interchanges Interchange the TIA#1 (rear crate, slot 15) TDX connection and the TIA#2 (rear crate, slot 16) TDX connection. 3.2.3.3.2 Test Initialization The ┆
0x43b00…43c00 (67, 0, 11) Sector 430cff00503341 ┆C P3A 1 1 TEST STEPS TEST NO.: 2/3 FUNCTION: Watchdog Processor System Test SRS REFERENCE: N/A ┆
0x43c00…43d00 (67, 0, 12) Sector 430dff00503341 ┆C P3A Case Test Step No. Station Action Expected Results 1.6 OC Enter from the OC: Refer to appendix B PU2(CR) sec. 9.4 10 02 00 00 54 4┆
0x43d00…43e00 (67, 0, 13) Sector 430eff00503341 ┆C P3A5 53 54(CR) 1.7 OC Enter from the OC: Refer to appendix B LPR(CR) sec. 9.5 10 01 00 00 0D 0A 54 MSP print out: 45 53 54 1B 48 0D(CR) (CR)(LF)TEST (Formfeed) ┆
0x43e00…43f00 (67, 0, 14) Sector 430f5300503341 ┆C S P3A Comments: TEST WITNESSES TEST QA QAR lose the lids. 3.2.3.3.3 Test Steps The teststeps for testgroup no. 2, testprocedure no. 3 (2/3), is given in the following preceded by a testoverview. rinted circuit┆
0x43f00…44000 (67, 0, 15) Sector 4300ff00503341 ┆C P3A 1 1 TEST STEPS TEST NO.: 2/3 FUNCTION: Watchdog Processor System Test SRS REFERENCE: N/A ┆
0x44000…44100 (68, 0, 0) Sector 4401ff00503341 ┆D P3A Test Case/ Reference Action SRS Reference All WDP test N/A 1. WDP V24 interfaces N/A 2. WDP CCBA interface┆
0x44100…44200 (68, 0, 1) Sector 4402ff00503341 ┆D P3A N/A 3. PU#1 CCA test N/A 4. PU#2 CCA test N/A 5. CU CCA test N/A 6. TU#1 BSM-X test N/A 7. TU#2 BSM-X test N/A 8. TU#3 BSM-X test N/A 9. TU#4 BSM-X test N/A 10. TU#5 BSM-X test N/A 11. TU#6 BSM-X test N/A 12. TU#7 BSM-X test N/A 13. TU#8┆
0x44200…44300 (68, 0, 2) Sector 44036300503341 ┆D c P3A BSM-X test N/A 14. TU#14 BSM-X test N/A 15. TU#9 BSM-X test N/A 16. TU#11 BSM-X test N/A put power switch on all three stabilizers are set to off. 2) The three rotary switches on the By-Pass panel are all set to the Frequency Stabilizer posit┆
0x44300…44400 (68, 0, 3) Sector 4404ff00503341 ┆D P3A 1 1 TEST OVERVIEW TEST NO.: 2/3 FUNCTION: Watchdog Processor Functional Capabilities ┆
0x44400…44500 (68, 0, 4) Sector 4405ff00503341 ┆D P3A Test Case/ Reference Action SRS Reference 17. TU#13 BSM-X test N/A 18. TU#10 BSM-X test N/A 19. TU#17 ┆
0x44500…44600 (68, 0, 5) Sector 44064c00503341 ┆D L P3ABSM-X test N/A 20. TU#15 BSM-X test N/A 21. RESYNC MODULE TEST N/A 4) Power switch (1) on the Watchdog Processor Unit rear panel is set to "ON". 5) Power switch (2) in the rear crate of PU#1 is set to "ON" 6) Power switch (2) in the rea┆
0x44600…44700 (68, 0, 6) Sector 4407ff00503341 ┆D P3A 1 1 TEST STEPS TEST NO.: 2/3 FUNCTION: Watchdog Processor System Test SRS REFERENCE: N/A ┆
0x44700…44800 (68, 0, 7) Sector 4308ff00503341 ┆C P3A Case Test Step No. Station Action Expected Results 1.1 N/A The EN/DIS switch on N/A the CCBA front panel is set to EN 1.2 OC Examin┆
0x44800…44900 (68, 0, 8) Sector 4409ff00503341 ┆D P3A Power Switch (2) on each Mains Switch is set to "OFF". 2) Power Switch (1) on the rear panel of each 80S Blower Unit is set to "ON". 3) Power Switch (2) in the rear crate of each TU is set to "ON". 4) Power Switch (1) on each CR80S Power S┆
0x44900…44a00 (68, 0, 9) Sector 440a3f00503341 ┆D ? P3Aupply (1 in the front crate of each TU) is set to "ON". 2) a) The RESET switch on the Configuration Control Adaptor (CCA) front panel is set away from RESET. b) PU#1: The CCA address switch on the CCA printed circuit board (PCB┆
0x44a00…44b00 (68, 0, 10) Sector 440bff00503341 ┆D P3A 1 k) PU#2 cable interchanges Interchange the TIA#1 (rear crate, slot 15) TDX connection and the TIA#2 (rear crate, slot 16) TDX connection. 3.2.3.3.2 Test Initialization The ┆
0x44b00…44c00 (68, 0, 11) Sector 440cff00503341 ┆D P3Atestengineers and testwitnesses are in the testroom and ready to perform and supervise the test. Power Up the System as follows: a) Power Up all connected terminals i.e. VDUs, MSPs, OC, PTP/PTR, as applicable. b) The input Power Switch on the ┆
0x44c00…44d00 (68, 0, 12) Sector 440dff00503341 ┆D P3Afront panel of each Frequency Stabilizer is set to "ON". c) The power switch (2) on Mains switch no. 1 is set to "ON" wait 15 secs. d) The power switch (2) on each of the remaining Mains Switches is set to "ON". e) Mount a Disk Pack with the t┆
0x44d00…44e00 (68, 0, 13) Sector 440eff00503341 ┆D P3Aest software in Disk Drive no. 2, close the lid and push the drive back in rack B. Activate the WRITE PROTECT pushbutton. f) Activate "START" push button on Disk Drive No. 2 and wait until the "READY" indicator stays "ON". g) Insert a scratch Fl┆
0x44e00…44f00 (68, 0, 14) Sector 440ff100503341 ┆D q P3Aoppy Disk in each of the two drives in the Floppy Disk drive of rack B, and close the lids. 3.2.3.3.3 Test Steps The teststeps for testgroup no. 2, testprocedure no. 3 (2/3), is given in the following preceded by a testoverview. rinted circuit┆
0x44f00…45000 (68, 0, 15) Sector 4400ff00503341 ┆D P3A 1 1 TEST OVERVIEW TEST NO.: 2/3 FUNCTION: Watchdog Processor Functional Capabilities ┆
0x45000…45100 (69, 0, 0) Sector 4501ff00503341 ┆E P3Ao AUTO. b) The BUS 1/Bus 2 switch is set to BUS 1. c) The address switch on each BSM-X is set to 1X hexadecimal, where X equals the number of the TU in which the actual BSM-X is placed. E. g. the BSM-X in TU#5 is given the address 15 hexadec┆
0x45100…45200 (69, 0, 1) Sector 4502ff00503341 ┆E P3Aimal. (This should be carried out prior to the test but can be verified at this point). 2) All LTUX-Ss: a) The CH 1 switch ON/OFF is set to ON b) The CH 2 switch ON/OFF is set to ON c) The CH 3 switch ON/OFF is set to ON d) The CH┆
0x45200…45300 (69, 0, 2) Sector 4503ff00503341 ┆E P3A 4 switch ON/OFF is set to ON h) Switch settings on frequency stabilizer rack: 1) The input power switch on all three stabilizers are set to off. 2) The three rotary switches on the By-Pass panel are all set to the Frequency Stabilizer posit┆
0x45300…45400 (69, 0, 3) Sector 45040b00503341 ┆E P3Aion. nt is now connected to the system as shown in fig. 3.2.4.3.1-1. Carry out/control the following: a) OC, TEST VDU#1, TEST VDU#2, and MSP set up: 1) Asynchronous communication 2) 7 bit character length 3) Even parity check/generation ┆
0x45400…45500 (69, 0, 4) Sector 4505ff00503341 ┆E P3A 1 i) Setting of power switches in Computer racks: 1) Power switch (2) on each Mains switch is set to "OFF". 2) Power switch (2) on the Disk Drive rear panel is set to "ON" 3┆
0x45500…45600 (69, 0, 5) Sector 4506ff00503341 ┆E P3A) Power switch (1) on the Floppy Disk Drive rear panel is set to "ON". 4) Power switch (1) on the Watchdog Processor Unit rear panel is set to "ON". 5) Power switch (2) in the rear crate of PU#1 is set to "ON" 6) Power switch (2) in the rea┆
0x45600…45700 (69, 0, 6) Sector 4507ff00503341 ┆E P3Ar crate of the CU is set to "ON" 7) Power switch (2) in the rear crate of the PU#2 is set to "ON". 8) Power switch (2) in the rear panel of each 80M fan unit is set to "ON". 9) Power switch (2) in the rear crate of the Adaptor Crate is set ┆
0x45700…45800 (69, 0, 7) Sector 4408ff00503341 ┆D P3Ato "ON" 10) Power switch (1) in the rear panel of the 80S Blower Unit is set to "ON" 11) Power switch (1) on each CR80M Power supply (6 front crate mounted modules) is set to "ON". k) Setting of Power Switche in Line Termination racks: 1)┆
0x45800…45900 (69, 0, 8) Sector 4509af00503341 ┆E / P3A 1 FIGURE 3.2.3.3.1-1 CONNECTION OF THE TESTEQUIPMENT ┆
0x45900…45a00 (69, 0, 9) Sector 450aff00503341 ┆E P3A 1 2) a) The RESET switch on the Configuration Control Adaptor (CCA) front panel is set away from RESET. b) PU#1: The CCA address switch on the CCA printed circuit board (PCB┆
0x45a00…45b00 (69, 0, 10) Sector 450bff00503341 ┆E P3A) is set to 01 hexadecimal. PU#2: The CCA address switch on the CCA printed circuit board (PCB) is set to 02 hexadecimal. d) Switch settings in CU front crate modules. 1) Switches on the Channel Unit Control Panel (CUCP) front panel is ┆
0x45b00…45c00 (69, 0, 11) Sector 450cff00503341 ┆E P3Aset as: a) The CU Bus A Switch DIS/AUTO is set to AUTO b) The CU Bus B switch DIS/AUTO is set to AUTO c) The Disk Ctrl. No. 1 switch AAEN/AUTO/BAEN is set to AUTO d) The Disk Ctrl. No. 2 switch AAEN/AUTO/BAEN is set to AUTO e) Th┆
0x45c00…45d00 (69, 0, 12) Sector 450dff00503341 ┆E P3Ae Disk Ctrl. No. 3 switch AAEN/AUTO/BAEN is set to AUTO f) The LTU No. 1 switch AAEN/AUTO/BAEN is set to AUTO g) The LTU No. 2 switch AAEN/AUTO/BAEN is set to AUTO h) The LTU No. 3 switch AAEN/AUTO/BAEN is set to AUTO i) The LTU No. ┆
0x45d00…45e00 (69, 0, 13) Sector 450ea200503341 ┆E " P3A4 switch AAEN/AUTO/BAEN is set to AUTO k) The LTU No. 5 switch AAEN/AUTO/BAEN is set to AUTO l) The SD.FD.CTRL switch AAEN/AUTO/BAEN is set to AUTO em as follows: 1 1. Subs┆
0x45e00…45f00 (69, 0, 14) Sector 450fff00503341 ┆E P3A 1 e) Switch settings in CU rear crate modules: 1) a) The RESET switch on the CCA module front panel is set away from RESET b) The CCA address switch on the CCA printed circuit┆
0x45f00…46000 (69, 0, 15) Sector 4500ff00503341 ┆E P3A board (PCB) is set to 03 hexadecimal. f) Switch settings in WDP rear crate modules: 1) The EN/DIS switch on the front panel of the CCBA is set to DIS. g) Switch settings in TU modules 1) All BSM-Xs: a) The AUTO/MAN/OFF switch is set t┆
0x46000…46100 (70, 0, 0) Sector 4601ff00503341 ┆F P3A 1 4. Connect TEST VDU#2 to J27 in the V24 FILTER BOX. 5. Disconnect the two V24 cables connected to the J1 and J2 connectors on the leftmost Back Panel 8 located in the rear of t┆
0x46100…46200 (70, 0, 1) Sector 4602ff00503341 ┆F P3Ahe Adapter crate. 6. Disconnect the V24 cable connected to the MIA in PU#1 and connect TESTCABLE#1 between above mentioned (para. 5) J1 and the MIA. 7. Disconnect the V24 cable connected to the MIA in PU#2 and connect TESTCABLE#2 between above┆
0x46200…46300 (70, 0, 2) Sector 4603ff00503341 ┆F P3A mentioned (para. 5) J2 and the MIA. 8. Disconnect the two V24 cables connected to J1 and J2 respectively on the WCA front panel in the rear crate of the WDP. 9. Connect TESTCABLE#3 between the above mentioned (para. 8) J1 and J2. The testeq┆
0x46300…46400 (70, 0, 3) Sector 4604ff00503341 ┆F P3Auipment is now connected to the system as shown in fig. 3.2.4.3.1-1. Carry out/control the following: a) OC, TEST VDU#1, TEST VDU#2, and MSP set up: 1) Asynchronous communication 2) 7 bit character length 3) Even parity check/generation ┆
0x46400…46500 (70, 0, 4) Sector 46057b00503341 ┆F { P3A 4) 1 stop bit 5) 2400 Baud communication speed TEST VDU#1 and #2 should furthermore be set to echomode (ECHO=Y) 7.40.2 OC Activate the AUX link Group 6 test as fol- lows: Enter from the OC: O┆
0x46500…46600 (70, 0, 5) Sector 4606ff00503341 ┆F P3A 1 b) Switch settings in PU#1 and PU#2 front crate modules: 1) The NRM/MAIN switch on the MAP module front panel is set to NRM. 2) The EN/DIS switch on the MAP module front pane┆
0x46600…46700 (70, 0, 6) Sector 4607ff00503341 ┆F P3Al is set to EN. 3) The host number switch (S1) on the PU#2 STI is set to #01 as follows: S1,4 : CLOSED S1,3 : CLOSED S1,2 : CLOSED S1,1 : OPEN c) Switch settings in PU#1 and PU#2 rear crate modules: 1) The Baudrate select switch┆
0x46700…46800 (70, 0, 7) Sector 4508e700503341 ┆E g P3Aes 1-4 (S1) on the MAP Interface Adapter (MIA) Printed Circuit Board (PCB) is set to #A which corresponds to a transmission speed of 2400 Baud: Switch 1: CLOSED Switch 2: OPEN Switch 3: CLOSED Switch 4: OPEN ┆
0x46800…46900 (70, 0, 8) WangDocumentHead {hdr=WangSectHead {next=(70,0, 9), len=0xff, h3=41503341}, f00=»5033A «, f01=»CPS/TPR/048 «, f02=»bko «, f03=»OJG «, f04=»3.2.3.3 «, f05=13-06-84 08:50, f06=» 1 «, f07=»36 «, f08=» 3337 «, f09=12-07-84 08:31, f10=» «, f11=»08 «, f12=» 305 «, f13=12-07-84 08:53, f14=16-07-84 11:03, f15=»0482A «, f16=» 91 «, f17=» 1 «, f18=»44 «, f19=» 1372 «, f20=» 3642 «, f21=» «, f22=» «, f99=880010000110462710110280aaca1505000000000000003803ab01df}
0x46900…46a00 (70, 0, 9) Sector 460a5b00503341 ┆F [ P3A F F F F E E E E D D D D C C C B B B B A A A @ @ @ ? ? ? > > > = = = = < < < ; ; ; ; : : : 9 9 9 9 8 8 8 7 7 7 7 6 6 6 5 5 5 5 4 4 4 3 3 3 2 2 2 2 1 1 1 0 0 0 0 / / / . . . . - - - , , ANV.TID ANSLAG Oprettet / / : : S S S S S S S S┆
0x46a00…46b00 (70, 0, 10) Sector 460bb600503341 ┆F 6 P3A 1 CPS/TPR/048 OJG/840615 FACTORY ACCEPTANCE TEST SPECIFICATION AND PROCEDURES, SITE 4 CAMPS !e=6 !Z="(=e*$<kas#r 9x2"<! <6 M8)I:^=~ B#.!#<6 ! <6 M&&:!<~ J#.:!<2.=M2┆
0x46b00…46c00 (70, 0, 11) Sector 460cff00503341 ┆F P3A 1 3.2.3.3 Test Procedure 3 This testprocedure serves to verify the Watchdog Processor System i.e. the Watchdog Processor Unit (WDP), the Configuration Control Bus Adapter (CCBA), th┆
0x46c00…46d00 (70, 0, 12) Sector 460dff00503341 ┆F P3Ae Channel Unit Control Panel (CUCP), the TDX Bus Switching Modules (BSM-Xs) and the Configuration Control Adapters (CCAs). 3.2.3.3.1 Test Set Up The test is performed via an Operator Console (OC) which is a printer and keyboard, a TEST VDU#1 an┆
0x46d00…46e00 (70, 0, 13) Sector 460eff00503341 ┆F P3Ad a TEST VDU#2 all with V24/V28 interface and a Medium Speed Printer (MSP) with OPTO interface. The above mentioned testequipment is connected to the system as follows: 1 1. Subs┆
0x46e00…46f00 (70, 0, 14) Sector 460fff00503341 ┆F P3Atitute the leftmost OPTO transceiver in the rack C Adapter crate with a V24/V28(L/L) adapter (1 channel), and connect the OC to the V24 connector on the front panel of the adaptor. 2. Connect the MSP to the remaining OPTO transceiver in the Adapt┆
0x46f00…47000 (70, 0, 15) Sector 46005200503341 ┆F R P3Aer crate in rack C. 3. Connect TEST VDU#1 to J26 in the V24 FILTER BOX. BW2I! <6 M /M?.I*:="8=IM2&MP'Mc2! m"2< [MI !?=6 : #wI>K!8=>R 2!8=6 #4 E*8=k L<M% :8=F 28=I!#<:"<>R<2> I E*#<& "< DM L<M% :#<F 2#<> I:g= Ro2M/2 Rl2> IC13!?=4~~ B|2> I:A=!┆
0x47000…47100 (71, 0, 0) Sector 4701ff00521241 ┆G R A DE UXTAREAA 0130 2531130 004 = ZNY SSSSS/YYYYY 005 = Z 201130Z AUG 006 = FM COMBALTAP 007 = TO PLACCIS 008 = BT 009 = N A T O S E C R E T CRYPTO SECURITY 010 = SIC BEF/BEG 011 = TEST THE QUICK BROWN FOX JUMPS OVER THE LAZY DOG 01234567890 012 = TE┆
0x47100…47200 (71, 0, 1) Sector 47026f00521241 ┆G o R AST THE QUICK BROWN FOX JUMPS OVER THE LAZY DOG 01234567890 013 = TEST MESSAGE NO. 1 014 = BT 015 = NNNN 1.4.a,b,d,e,f 2. Several RI's in FL2 (min. one local) 3.1.4.a,b,d,e,f 3. Garbled RI in FL2 3.1.4.a, c, d 4. Retrieval of relayed messages 3┆
0x47200…47300 (71, 0, 2) Sector 4703ff00521241 ┆G R A 1 TEST MESSAGES MESSAGE NO.: 2 FUNCTION: Relay of Incoming Messages 001 = VZCZCBNA0001 HH 002 = ZZ RCPSK RISCAR┆
0x47300…47400 (71, 0, 3) Sector 4704ff00521241 ┆G R AS RICCIS 003 = DE UXTAREAA 0130 2531130 004 = ZNY SSSSS/YYYYY 005 = Z 201130Z AUG 006 = FM COMBALTAP 007 = TO RICCIS/PLACCIS RCPSK/SHAPE RISCARS/PLASCARS 008 = BT 009 = N A T O S E C R E T CRYPTO SECURITY 010 = SIC BEF/BEG 011 = TEST TH┆
0x47400…47500 (71, 0, 4) Sector 4705ad00521241 ┆G - R AE QUICK BROWN FOX JUMPS OVER THE LAZY DOG 01234567890 012 = TEST THE QUICK BROWN FOX JUMPS OVER THE LAZY DOG 01234567890 013 = TEST MESSAGE NO. 2 014 = BT 015 = NNNN g load part of the 240 hour test, period no. 1 (6 hour's normal load) fulfil the 2┆
0x47500…47600 (71, 0, 5) Sector 4706ff00521241 ┆G R A 1 TEST MESSAGES MESSAGE NO.: 3 FUNCTION: Relay of Incoming Messages 001 = VZCZCBNA0001 HH 002 = ZZ RIABAB 003 =┆
0x47600…47700 (71, 0, 6) Sector 4707ff00521241 ┆G R A DE UXTAREAA 0130 2531130 004 = ZNY SSSSS/YYYYY 005 = Z 201130Z AUG 006 = FM COMBALTAP 007 = TO PLACCIS 008 = BT 009 = N A T O S E C R E T CRYPTO SECURITY 010 = SIC BEF/BEG 011 = TEST THE QUICK BROWN FOX JUMPS OVER THE LAZY DOG 01234567890 012 = TE┆
0x47700…47800 (71, 0, 7) Sector 23006f00521241 ┆# o R AST THE QUICK BROWN FOX JUMPS OVER THE LAZY DOG 01234567890 013 = TEST MESSAGE NO. 3 014 = BT 015 = NNNN y one The msg. is external RI in FL2 relayed in accor- dance to RI in FL2 1.2 Log RECORDS are collected on the printer 2.1 Inc. msg. incl┆
0x47800…47900 (71, 0, 8) Sector 4709ff00521241 ┆G R A. one local RI and The msg. is dis- two external RI's in FL2 tributed locally and relayed in accordance to the specified external RI's. The local RI is removed on the relayed msg's. 2.2 LOG RECORDS are collected on the printer 3.1 Inc. msg. incl┆
0x47900…47a00 (71, 0, 9) Sector 470aff00521241 ┆G R A. one RI in FL2 which The msg. is rejec- is not recognized in local/global ted to MSO for RI table garble correction. 3.2 LOG RECORDS are collected on the printer 4.1 Retrieve (RERN) the msg's which are The msg's are relayed by the MDCO/MSO d┆
0x47a00…47b00 (71, 0, 10) Sector 470b9700521241 ┆G R Aesplayed. Comments: TEST WITNESSES TEST QA QAR ELAY FUNCTION CAMPS > I!e=6 !Z="(=e*$<kas#r 9x2"<! <6 M8)I:^=~ B#.!#<6 ! <6 M&&:!<~ J#.:!<2.=M2┆
0x47b00…47c00 (71, 0, 11) Sector 470cff00521241 ┆G R A 1 TEST STEPS FUNCTION: ORBIT Control 1 TEST STE┆
0x47c00…47d00 (71, 0, 12) Sector 470dff00521241 ┆G R AP ACTION RESULT 5.1 Inc. msg. incl. one external RI in The msg. is re- FL2 and one operating signal equal layed and the ZXY5 in FL4 digit in the operating signal is decremented. 6.1 Inc. msg. incl. on┆
0x47d00…47e00 (71, 0, 13) Sector 470eff00521241 ┆G R Ae external RI in The msg. is re- FL2 and one operating signal equal jected to MSO, ZXY0 in FL4 caused by invalid operating signal. Comments: ┆
0x47e00…47f00 (71, 0, 14) Sector 470f7000521241 ┆G p R A TEST WITNESSES TEST QA QAR 1 procedure is to verify requirements for the CAMPS Relay Function in accordance to CPS/TCN/068. 1.1 SYSTEM TEST CONDITIONS The test will b┆
0x47f00…48000 (71, 0, 15) Sector 4700ff00521241 ┆G R A 1 TEST MESSAGES MESSAGE NO.: 1 FUNCTION: Relay of Incoming Messages 001 = VZCZCBNA0001 HH 002 = ZZ RICCIS 003 =┆
0x48000…48100 (72, 0, 0) Sector 4801ff00521241 ┆H R A 1 TEST OVERVIEW FUNCTION: Relay of Incoming Messages 1 ┆
0x48100…48200 (72, 0, 1) Sector 4802ff00521241 ┆H R A TEST CASE DESCRIPTION CPS/TCN/068 REF. 1. One external RI in FL2 3.1.4.a,b,d,e,f 2. Several RI's in FL2 (min. one local) 3.1.4.a,b,d,e,f 3. Garbled RI in FL2 3.1.4.a, c, d 4. Retrieval of relayed messages 3┆
0x48200…48300 (72, 0, 2) Sector 48030e00521241 ┆H R A.1.4.f :f= R 5M_* R 5Cq5MB' R*5Cq5M[2 R45Cq5M 2M[- RA5Cq5:^=~ BL5C`5M{) RV5Cq5M . R`5Cq5M@1MI1:h= Rp5Cr4IMM.:^=~ B}5I:g=~ J 5IC$3I > S C_* ┆
0x48300…48400 (72, 0, 3) Sector 4804ff00521241 ┆H R A 1 TEST OVERVIEW FUNCTION: ORBIT Control 1 TEST ┆
0x48400…48500 (72, 0, 4) Sector 4805ff00521241 ┆H R ACASE DESCRIPTION CPS/TCN/068 REF. 5. Operating signal equal ZXY5 3.2.1.3 6. Operating signal equal ZXY0 3.2.1.3 Performance: During load part of the 240 hour test, period no. 1 (6 hour's normal load) fulfil the 2┆
0x48500…48600 (72, 0, 5) Sector 48062b00521241 ┆H + R A0% of relay messages requirements. ┆
0x48600…48700 (72, 0, 6) Sector 4807ff00521241 ┆H R A 1 TEST STEPS FUNCTION: Relay of Incoming Messages 1 ┆
0x48700…48800 (72, 0, 7) Sector 4708ff00521241 ┆G R A TEST STEP ACTION RESULT 1.1 Incoming msg. including only one The msg. is external RI in FL2 relayed in accor- dance to RI in FL2 1.2 Log RECORDS are collected on the printer 2.1 Inc. msg. incl┆
0x48800…48900 (72, 0, 8) WangDocumentHead {hdr=WangSectHead {next=(72,0, 9), len=0xff, h3=41521241}, f00=»5212A «, f01=»CPS/TPR/050 «, f02=»dhh «, f03=»PFM «, f04=» «, f05=02-08-84 10:44, f06=» 1 «, f07=»05 «, f08=» 5212 «, f09=07-08-84 09:33, f10=» «, f11=»01 «, f12=» 21 «, f13=07-08-84 10:04, f14=09-08-84 10:58, f15=»0482A «, f16=» 11 «, f17=» 1 «, f18=»09 «, f19=» 120 «, f20=» 5467 «, f21=» «, f22=» «, f99=100030000110052710110280aaca15050000000000000138032600df}
0x48900…48a00 (72, 0, 9) Sector 480a0b00521241 ┆H R A H H H H H H H G G G G # # DOKUMENTOVERSIGT Dokument nr: Dokumentnavn: Operat]r: Forfatter: Kommentarer: STATISTIK AKTIVITET DATO TID ANV.TID ANSLAG Oprettet ┆
0x48a00…48b00 (72, 0, 10) Sector 480bb200521241 ┆H 2 R A 1 CPS/TPR/050 840802 # TEST SPECIFICATION AND PROCEDURES FOR CAMPS RELAY FUNCTION CAMPS > I!e=6 !Z="(=e*$<kas#r 9x2"<! <6 M8)I:^=~ B#.!#<6 ! <6 M&&:!<~ J#.:!<2.=M2┆
0x48b00…48c00 (72, 0, 11) Sector 480c4a00521241 ┆H J R A 1 I:^=~ B[.Mr)Cp.:]=~ Bp.MP- Rm.> IM)-MI,:^=~ B~.> IMB'IM2& 9x2"<!Z="(=^#Vk"$<:]=2#<:^=~ J6.! <6 M8) R6.> I! <6 M8)I!h=6 ! =6 M")IM"):g=~ J /:h=2>=M?.Mj': < Zn.C / E*:=k 0wM% !;=4C┆
0x48c00…48d00 (72, 0, 12) Sector 480dff00521241 ┆H R A 1 TABLE OF CONTENTS 1 ┆
0x48d00…48e00 (72, 0, 13) Sector 480e7900521241 ┆H y R A 1 SCOPE .......................................... 4 1.1 SYSTEM TEST CONDITIONS ..................... 4 0C 0! <6 M1' R 0C 0! <6 M1' Z 0CR0Mc&!.=6 ! <6 M1' R40C.1! <6 M1' RC0C.1! <6 M1' RR0C.1!$<5CQ0!$<6 !&<6 Mc&! "(=6 E '<M% ! "2<┆
0x48e00…48f00 (72, 0, 14) Sector 480fff00521241 ┆H R A 1 1 SCOPE The purpose of this test procedure is to verify requirements for the CAMPS Relay Function in accordance to CPS/TCN/068. 1.1 SYSTEM TEST CONDITIONS The test will b┆
0x48f00…49000 (72, 0, 15) Sector 4800d400521241 ┆H T R Ae conducted on an integrated CAMPS at the factory just after validation of the 240 hour test, by the CR test engineers. CAMPS external channel TRC PTOP will be feed with test messages prepared on a TTY. 2#<> I:g= Ro2M/2 Rl2> IC13!?=4~~ B|2> I:A=!┆
0x49000…49100 (73, 0, 0) Sector 00000000000000 ┆ ┆
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