top - download
⟦76dac2e7d⟧ Wang Wps File
Length: 93635 (0x16dc3)
Types: Wang Wps File
Notes: CPS/SDS/001
Names: »0480A «
Derivation
└─⟦7c0ec4e20⟧ Bits:30006001 8" Wang WCS floppy, CR 0036A
└─ ⟦this⟧ »0480A «
WangText
/…00……00……00……00…'…0a……00……00…'…0b…'
&…09…&…0d…&…02…&
& &…05…%…09…%…0b…%…0c…%…00…%
$…09…$…0e…$
#…0b…#…0f…#…00…#…02…#…05…#…06…#…07……1b……00……1b… …1b……05……1a……0a……1a……00……1a……05……1a……06……19……0c……19……00……19……01……19……07……18……0e……18……02……18……07……17……86…1 …02… …02… …02…
…02…CPS/SDS/001
…02…SRA/810115…02……02…
CAMPS SYSTEM DESIGN SPECIFICATION
…02……02…CAMPS
T̲A̲B̲L̲E̲ ̲O̲F̲ ̲C̲O̲N̲T̲E̲N̲T̲S̲
5 SUBSYSTEM SPECIFICATION ......................
5.1 CR80D SYSTEM DESIGN ......................
5.1.1 Scope ................................
5.1.2 CR80D Crate Assy. ....................
5.1.3 CR80D MAIN BUS (DMB) .................
5.1.3.1 Functional Description of the DMB
5.1.3.2 Electrical Specification of the
DMB ..............................
5.1.4 Processor Sub-System (PRS) ...........
5.1.4.1 Design & Construction ............
5.1.4.1.1 Functional Description of the
CR80D Control Bus (DCB) ......
5.1.4.1.2 Electrical Description of the
DCB ..........................
5.1.4.1.3 Central Processing Unit and
CACHE Memory (CPU/CACHE) .....
5.1.4.1.3.1 The CPU ..................
5.1.4.1.3.2 The CACHE Memory CTRL ....
5.1.4.1.3.3 Mechanical & Electrical
Specifications ...........
5.1.4.1.4 The MAP and Map Interface Adapter
(MIA) ........................
5.1.4.1.4.1 The MAP Module ...........
5.1.4.1.4.2 The MIA Module ...........
5.1.4.1.4.3 Mechanical & Electrical
Specifications ...........
5.1.4.1.5 The Data Channel .............
5.1.4.1.6 The RAM ......................
5.1.4.1.6.1 Mechanical & Electrical
Specifications ...........
5.1.4.1.7 The STI/TIA Modules ..........
5.1.4.1.7.1 The TIA ..................
5.1.4.1.7.2 The STI ..................
5.1.4.1.7.3 Mechanical & Electrical
Specifications ...........
5.1.4.1.8 The CCA Module ...............
5.1.4.1.2 The Power Supply .............
5.1.4.2 Documentation ....................
5.1.4.3 Environment ......................
5.1.5 I/O Sub-System .......................
5.1.5.1 Design & Construction ............
5.1.5.1.1 The CIA Module ...............
5.1.5.1.1.1 Mechanical & Electrical
Specifications ...........
5.1.5.1.2 The Disk CTRL & DCA ..........
5.1.5.1.2.1 The Disc CTRL ............
5.1.5.1.2.2 The DCA ..................
5.1.5.1.2.3 Mechanical & Electrical
Specifications ...........
5.1.5.1.3 The LTU & Adapter ............
5.1.5.1.3.1 The LTU ..................
5.1.5.1.3.2 The V24/V28(L) Adapter ...
5.1.5.1.3.3 Mechanical & Electrical
Specification ............
5.1.5.1.4 The Floppy Disk Controller &
Adapter ......................
5.1.5.1.4.1 Mechanical & Electrical
Specification ............
5.1.5.1.5 The CCA ......................
5.1.5.1.6 The Power Supply .............
5.1.5.2 Documentation ....................
5.1.5.3 Environment ......................
5̲ ̲ ̲S̲Y̲S̲T̲E̲M̲ ̲B̲R̲E̲A̲K̲-̲D̲O̲W̲N̲
This chapter presents a more detailed specification
of the major H/W and S/W packages which has been identified
in chapter 4.
5.1 C̲R̲8̲0̲D̲ ̲S̲Y̲S̲T̲E̲M̲ ̲D̲E̲S̲I̲G̲N̲
5.1.1 S̲c̲o̲p̲e̲
The scope of this document is:
- to supply documentation and functional specification
of the present CR80D H/W configuration
- to define a baseline document for the CR80D H/W
configuration
This section will provide a general description of
the two main CR80D assemblies
- the Processor Unit Assembly (PU) (sec. 5.1.4)
- the Channel Unit Assembly (CU) (sec. 5.1.5)
Furthermore, other subsystems interfaced from the PU
and the CU, if any, are referenced.
To provide a more comprehensive understanding of the
CR80D system each of the assemblies are broken down
into basic functional elements (i.e. crate, buses and
modules) each given a detailed functions/mechanical
description.
5.1.2 C̲R̲8̲0̲D̲ ̲C̲r̲a̲t̲e̲ ̲A̲s̲s̲e̲m̲b̲l̲y̲
The CR80D modules/elements are mechanical selfcontained
units housed in a standard 19" mechanical frame, the
CR80D crate assembly shown on fig. 5.1.2-1.
The crate assembly consists of a front crate and a
rear crate (interface adapter crate) placed back to
back. On the back panels of the two crates are bus
motherboards (Printed circuit boards) for module interconnections
and also edge connectors for front-rear crate interconnections.
As an example the front crate back panel is shown on
fig. 5.1.2-2.
The rear crate has no main buses, but it has a control
and power bus in the upper row, motherboard or individual
connectors in the middle row and individual connectors
in the lower row. Cables external to the crate assembly
(subsystem interface cables) are connected to interface
adapter modules in the rear crate. Adapter modules
are connected to modules in the front crate by flat
cables as shown in fig. 5.1.2-3.
Figure 5.1.2-2…01…F̲r̲o̲n̲t̲ ̲C̲r̲a̲t̲e̲ ̲B̲a̲c̲k̲ ̲P̲a̲n̲e̲l̲
Figure 5.1.2-3…01…F̲r̲o̲n̲t̲ ̲t̲o̲ ̲R̲e̲a̲r̲ ̲C̲r̲a̲t̲e̲ ̲F̲l̲a̲t̲ ̲C̲a̲b̲l̲e̲
Figure 5.1.2-1…01…C̲R̲8̲0̲D̲ ̲C̲r̲a̲t̲e̲ ̲A̲s̲s̲e̲m̲b̲l̲y̲ ̲(̲F̲r̲o̲n̲t̲ ̲V̲i̲e̲w̲)̲
5.1.3 C̲R̲8̲0̲D̲ ̲M̲a̲i̲n̲ ̲B̲u̲s̲ ̲(̲D̲M̲B̲)̲
Within a crate the DMB is a printed circuit board (mother
board) equipped with connectors for the module interface
(ref. fig. 5.1.3-1 below).
Figure 5.1.3-1…01…C̲R̲8̲0̲D̲ ̲M̲o̲t̲h̲e̲r̲ ̲B̲o̲a̲r̲d̲
The DMB is terminated in both ends by termination boards
to form a set of transmission lines well suitable as
the communication path between the modules.
Within a PU the DMB is terminated in each end by a
Main Bus Termination module (MBT). This module contains,
apart from the passive terminating circuitry, also
the inverter circuitry supporting the I/O interrupt
system (sec. 5.1.3.1).
Within a CU the DMB is terminated in one end by a MBT,
and in the other end by a CIA (sec. 5.1.5.1.1), which
apart from the CIA circuitry described contains the
passive terminating circuitry.
The mother board provides a parallel bus structure
with 50 lines in parallel (excepting the power and
ground lines).This implies that the D-main bus does
not put any restriction on the location of the modules
within a crate. Pin lay-out for the DMB connectors
is shown in fig. 5.1.3-2 and fig. 5.1.3-3 shows how
the modules plugs in onto the DMBs.
Figure 5.1.3-2…01…C̲R̲8̲0̲D̲ ̲M̲a̲i̲n̲ ̲B̲u̲s̲ ̲C̲o̲n̲n̲e̲c̲t̲o̲r̲ ̲-̲ ̲P̲i̲n̲ ̲L̲a̲y̲o̲u̲t̲
Figure 5.1.3-3…01…D̲ ̲M̲o̲d̲u̲l̲e̲s̲ ̲o̲n̲ ̲t̲h̲e̲ ̲D̲M̲B̲s̲
5.1.3.1 F̲u̲n̲c̲t̲i̲o̲n̲a̲l̲ ̲D̲e̲s̲c̲r̲i̲p̲t̲i̲o̲n̲ ̲o̲f̲ ̲t̲h̲e̲ ̲C̲R̲8̲0̲D̲ ̲M̲a̲i̲n̲ ̲B̲u̲s̲ ̲(̲D̲M̲B̲)̲
In a Processor Unit (PU) two transfer buses are available
for module intercommunication; the Processor Bus (PB)
and the Channel Bus (CB). The two buses are from a
functional point of view different:
- The PB is used by CPU modules for data and instruction
communication with memory modules and for set-up,
status and control communication with the MAP module.
- The CB is not available to the CPUs but is used
by the STI(Host I/F) and MAP modules for information
exhange with the connected subsystems (I/O subsystem,
TDX subsystem). The cache memory section of a CPU
though, has m̲o̲n̲i̲t̲o̲r̲i̲n̲g̲ ̲a̲c̲c̲e̲s̲s̲ to the CB (sec. 5.1.4.1.3).
Concerning the mechanical, electrical and timing characteristics
the two buses are identical. The buses and their connection
in the system is illustrated in fig. 5.1.3.1-1.
…01…Figure 5.1.3.1-1
C̲o̲n̲n̲e̲c̲t̲i̲o̲n̲,̲ ̲M̲a̲i̲n̲b̲u̲s̲e̲s̲ ̲i̲n̲ ̲a̲ ̲P̲U̲
In the Channel unit two transfer buses are available
for information exchange between the I/O modules and
the PUs. These two buses are functionally equal and
are used as back up for each other in redundant systems.
The buses and their connection in the system are shown
in figure 5.1.3.1-2 below.
Figure 5.1.3.1-2…01…C̲o̲n̲n̲e̲c̲t̲i̲o̲n̲,̲ ̲M̲a̲i̲n̲ ̲B̲u̲s̲e̲s̲ ̲i̲n̲ ̲a̲ ̲C̲U̲
In the following a detailed description of the mechanical
and electrical characteristics of the buses are given.
The interface specifications for the four buses are
the same (The CR80D Main Bus specifications) except
for supply voltages.
M̲a̲s̲t̲e̲r̲ ̲T̲i̲m̲i̲n̲g̲
Two signals [1(A35) and [2(A38) (both generated on
the MAP) are available for I/O interrupt timing and
for internal timing in the modules connected to the
DMB. The timing signals are shown below in fig. 5.1.3.1-3,
[1 being a 1 MHz clock and [2 a 8 MHz clock. [1 is
derived from [2.
Figure 5.1.3.1-3…01…T̲i̲m̲i̲n̲g̲ ̲S̲i̲g̲n̲a̲l̲s̲
I̲/̲O̲ ̲I̲n̲t̲e̲r̲r̲u̲p̲t̲ ̲S̲i̲g̲n̲a̲l̲s̲
The CR80D System is based on serial transmission of
the interrupt code from the interrupting I/O module
using the lines INA (A32) and INR (A33).
The interrupt code consists of 8 bits, of which 2 are
priority bits and the remaining 6 bits are the I/O
module number. The 8 bits are transmitted within one
[1 (1MHZ) cycle each bit synchronized to the [2 (8
MHZ) clock. The interrupt code is transmitted on the
INR line (fig 5.1.3.1-4).
INR is an open collector line. Thus all the I/O modules
can transmit on the same line, which means that if
one module is transmitting an "L" and another an "H",
the line will contain the "L".
INA is an open collector line too. It is driven from
the Main Bus termination boards (MBT or CIA), one in
each end of the Bus. The contents of INA is INR inverted.
Each of the interrupting I/O modules compares for each
of the eight bits the contents of INA with the bits
it is transmitting to INR. If the compare does not
match, which means that a module with a higher interrupt
code is transmitting at the same time, the module disables
the transferring of its code to INR until the next
1 MHZ period.
In this way the contents of INR will be unique and
correspond to the highest priority interrupt transmitted
during that period. The module which detects this situation
has got its interrupt acknowledge and will stop the
interrupt sending.
If two modules interrupting at the same time have the
same priority, it is the module with the highest address
that overrides the other.
Figure 5.1.3.1-4 …01…The I/O Interrupt System
The 6 I/O module number bits indicate the possibility
of 64 I/O module addresses within a crate. However,
two of the 64 module addresses are restricted:
- Address 00 (The idle situation)
- Address 63 (Used by the MAP or CIA)
M̲a̲s̲t̲e̲r̲ ̲C̲l̲e̲a̲r̲ ̲(̲M̲C̲)̲
The Master Clear signal MC (B29) (not used in the CU)
is used to force some PU modules into a well defined
state. The signal is activated upon power up or upon
activating a "Master Clear" button on the front panel
of the MAP (Provided that a switch on the front panel
of the MAP is set to "PU disable"). The RAM modules
must not use the MC, in order to preserve their contents
during a button activated MC. Only the power up sequence
must be used for resetting a RAM. Below (fig. 5.1.3.1-5)
is shown the MC signal sequencing during power up and
button activation.
Figure 5.1.3.1-5…01…M̲a̲s̲t̲e̲r̲ ̲C̲l̲e̲a̲r̲
The MC also initiates, where implemented, a module
built-in selftest routine with the purpose of detecting
possible module functional errors.
D̲a̲t̲a̲ ̲a̲n̲d̲ ̲A̲d̲d̲r̲e̲s̲s̲ ̲L̲i̲n̲e̲s̲
The information communicated on the parallel CR80D
data bus, DAO-DA15 (A2 - B9), is 16 bit data + 2 bit
parity. There is one parity bit for each of the two
8 bit bytes; UP (A28) is upper byte parity and LP (B28)
is lower byte parity. When an address sourcing module
(CPU, DMA) is reading from the memory it specifies
- read upper byte in addressed word
- read lower byte in addressed word
- read addressed word
Both parity bits must be correct in either case. As
far as memory modules are concerned all read operations
are word read operations leaving it to the address
sourcing module to extract the relevant part of the
data to be processed. Odd parity is used for both bytes,
meaning that the number of one's in a byte plus the
corresponding parity bit should be odd.
The data bus is bidirectional. Data can be transferred
in both directions on the bus, with the source/destination
being indicated by the address lines, LS0 (A26), LS1
(B26) and the R/W (read/write) signal. When the R/W
is low ("0") a read operation is performed by the address
destination module, which recognizes the address supplied
by the addres sourcing module (CPU,DMA), transmitting
data to the data bus (the address sourcing module receives
the data). When the R/W is high ("1") a write operation
is performed by the address sourcing module transmitting
data to the databus (the selected address destination
module receives the data).
Addresses are transmitted, by address sourcing modules,
to the Address bus consisting of 20 lines (AD0 - AD19(A16-B19,
A21-B25, A36, B36)). This permits addressing of up
to 1 Mega words (2 Mega bytes) and 64 I/O modules.
For a summary of CR80D Main Bus addressing refer to
table 5.1.3.1-6. The MAP module referenced in the table
and the term "Logical Address" will be given a detailed
description in sec. 5.1.4.1.4.
T̲r̲a̲n̲s̲f̲e̲r̲ ̲C̲o̲n̲t̲r̲o̲l̲ ̲S̲i̲g̲n̲a̲l̲s̲
Four signals on the DMB are used for controlling the
information transfer on the bus. Three of the signals
TRQ (A31, Transfer Request), AE (A37, Address Enable)
and BD (A29, Block Disable) are used as address Validity
controls during a read operation, and simultaneously
as address and data validity control during write operations.
TRQ is generated from the addres sourcing module (CPU,
DMA) specifying that the contents of the address bus
(except AD 18 & AD 19) are valid.
BD is transmitted from the MAP module causing the CPUs/DMAs
to switch off address lines AD 10-17.
AE is transmitted from the MAP module indicating the
validity of a complete modified (mapped) address field
(AD0-AD19).
The fourth signal RS (A30, Response Signal) is the
response signal from the address destination module.
TABLE 5.1.3.1-6
A̲d̲d̲r̲e̲s̲s̲i̲n̲g̲ ̲S̲p̲e̲c̲i̲f̲i̲c̲a̲t̲i̲o̲n̲ ̲f̲o̲r̲ ̲a̲n̲ ̲A̲d̲d̲r̲e̲s̲s̲ ̲S̲o̲u̲r̲c̲i̲n̲g̲ ̲M̲o̲d̲u̲l̲e̲ ̲i̲n̲ ̲a̲ ̲P̲U̲…01…C̲o̲n̲t̲a̲i̲n̲i̲n̲g̲ ̲a̲
̲M̲A̲P̲ ̲M̲o̲d̲u̲l̲e̲
During a read operation RS = logical "0" indicates
that data are being transmitted.
During write operations the falling edge of RS indicates
that data has been accepted. Signal relationships are
shown below in fig. 5.1.3.1-7.
Figure 5.1.3.1-7…01…S̲i̲g̲n̲a̲l̲ ̲R̲e̲l̲a̲t̲i̲o̲n̲s̲h̲i̲p̲s̲
5.1.3.2 E̲l̲e̲c̲t̲r̲i̲c̲a̲l̲ ̲D̲e̲s̲c̲r̲i̲p̲t̲i̲o̲n̲ ̲o̲f̲ ̲t̲h̲e̲ ̲C̲R̲8̲0̲D̲ ̲M̲a̲i̲n̲ ̲B̲u̲s̲
In the following the electrical specification for modules
connected to the main bus are given.
P̲o̲w̲e̲r̲ ̲L̲i̲n̲e̲s̲
Pin No. Description
̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲
̲ ̲ ̲ ̲ ̲ ̲
A11, B11 +/- 24 V
A12, B12 - 12V
A13, B13 GND ground for +/- 12V
A14, B14 + 12V
A40, A41,
B40, B41 + 5V
A42, A43,
B42, B43 GND ground for + 5V
The power lines are not fed through a flat cable extension
(if any).
Maximum power consumption per connector:
+ 24V, - 24V: 1A
+ 12V, - 12V: 4A
+ 5V: 10A
SIGNAL LINES, DATA LINES 3 SIDER FRA KLADDEN
1 SIDE
2. SIDE
3. SIDE
5.1.4 T̲h̲e̲ ̲P̲r̲o̲c̲e̲s̲s̲o̲r̲ ̲S̲u̲b̲-̲S̲y̲s̲t̲e̲m̲ ̲(̲P̲R̲S̲)̲
The CAMPS Processor System is composed of a dual set
of Processor Unit Assemblies (PUs), capable of individual
operation, with multiple Central Processing Units (CPUs),
memory modules (RAMs), buses and control.
The PRS interfaces to:
- The I/O subsystem (sec. 5.1.5) through the dualized
MIA (sec. 5.1.4.1.4.2) - Data Channel (sec. 5.1.4.1.5)
- CIA (sec. 5.1.5.1.1) Link
- The System Status & Controller (SS&C) through the
MIA V24/V28 link (9.6 Kbaud) and the CCA (sec.
5.1.4.1.8) serial configuration bus (sec. 5.4).
The SS&C (sec. 5.4) coordinates and monitors the
operation of the dual PUs within the system.
- The dualized Telecommunication Data Exchange System
(TDX Subsystem, sec. 5.2) through the STI/TIA (sec.
5.1.4.1.7) complex and the TDX buses
Fig. 5.1.4-1 shows in schematic the PRS and its interfaces
towards the above mentioned subsystems.
Fig. 5.1.4-1…01…T̲h̲e̲ ̲P̲r̲o̲c̲e̲s̲s̲o̲r̲ ̲S̲y̲s̲t̲e̲m̲ ̲I̲n̲t̲e̲r̲f̲a̲c̲e̲s̲
5.1.4.1 D̲e̲s̲i̲g̲n̲ ̲&̲ ̲C̲o̲n̲s̲t̲r̲u̲c̲t̲i̲o̲n̲
This section will focus on a detailed description of
the basic elements/modules from which a PU is put together.
These basic elemens are:
- CR80D Control Bus (DCB)
- CR80D Central Processing Unit (CPU)
- CR80D Memory Mapping Unit (MAP)
- CR80D MAP Interface Adapter (MIA)
- CR80D Random Access Memory (RAM)
- CR80D Supra-, TDX Bus Interface (STI)
- CR80D TDX Bus Interface Adapter (TIA)
- CR80D Data Channel
- CR80D Power Supply (PSU)
5.1.4.1.1 F̲u̲n̲c̲t̲i̲o̲n̲a̲l̲ ̲D̲e̲s̲c̲r̲i̲p̲t̲i̲o̲n̲ ̲o̲f̲ ̲t̲h̲e̲ ̲C̲R̲8̲0̲D̲ ̲C̲o̲n̲t̲r̲o̲l̲ ̲B̲u̲s̲
̲(̲D̲C̲B̲)̲
A third bus structure in a PU is the DCB, the task
of which is
- To transfer the bus authority control signals (request
& grant signals)
- To transfer the interrupt notification signals
B̲u̲s̲ ̲A̲u̲t̲h̲o̲r̲i̲t̲y̲ ̲C̲o̲n̲t̲r̲o̲l̲ ̲S̲i̲g̲n̲a̲l̲s̲
Included on the MAP module (sec. 5.1.4.1.4.1) is an
arbitration function for the address sourcing modules
on the PB and the CB, governing the bus access for
these modules. The arbitration is controlled by means
of two sets of special signals one set for the PB (Processsor
Bus) and one set for the CB (Channel Bus).
For the CB the following signals are used:
- Channel Bus Request: CRQ0 - CRQ3
- Channel Bus Grant: CBG0 - CBG3
The CRQ (0-3) signals are generated on the address
sourcing modules addressing via the CB (up to 4 modules)
and the CBG (0-3) signals are generated on the MAP
module. Each address sourcing module has one dedicated
request signal and one dedicated grant signal, which
is monitored to determine whether bus access is allowed
or not. The modules are served cyclically, meaning
that all modules on the CB have the same access rights
when requesting.
The PB authority is controlled by means of the signals:
- Processor Bus Request: PRQ0 - PRQ4
- Processor Bus Grant: PBG0 - PBG4
- Lock Bus Grant: LBG
Each address sourcing module addressing via the PB
(up to 5 modules) has its own set of PRQ, PBG signals.
A common line LBG signal can be activated by an address
sourcing module to stop bus arbitration when it has
bus access (Semaphore protected operation). The signal
lines sequences are shown on fig. 5.1.4.1.1-1 and are
valid for both the PB and the CB taking into account
that no LBG facility exists on the CB.
Figure 5.1.4.1.1-1…01…B̲u̲s̲ ̲A̲u̲t̲h̲o̲r̲i̲t̲y̲ ̲S̲i̲g̲n̲a̲l̲ ̲S̲e̲q̲u̲e̲n̲c̲e̲
I̲n̲t̲e̲r̲r̲u̲p̲t̲ ̲S̲i̲g̲n̲a̲l̲s̲
Interrupts from all sources (I/O modules and CPUs)
are received by and stored in the MAP. The interrupts
are communicated to relevant CPUs by using the INT0-INT2
(interrupt notification) lines together with the IST
(interrupt strobe) line. The INT0 - INT2 contains in
binary coding information of the type of interrupt
(Notify CPU#, Timer interrupt) and CPU number (if Notify
CPU#) according to table 5.1.4.1.1-2 below.
INT (2:0) Function
̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲
000 Notify CPU #0
001 Notify CPU #1
010 Notify CPU #2
011 Notify CPU #3
100 Notify CPU #4
101 Not used
110 Not used
111 Timer interrupt
Table 5.1.4.1.1-2…01…I̲n̲t̲e̲r̲r̲u̲p̲t̲ ̲T̲y̲p̲e̲s̲
The Notify CPU# is generated whenever the MAP module
detects an I/O or a CPU Interrupt request, with a priority
greater than the priority of the process being executed
at the present. If the priority is less than or equal
to that of the running process then the request is
queued waiting to be issued until proper conditions
are met.
KAPITEL 5.1.4.1.2 SKRIVES P< SKRIVEMASKINE…01…OG FYLDER EN SIDE.
5.1.4.1.3 C̲e̲n̲t̲r̲a̲l̲ ̲P̲r̲o̲c̲e̲s̲s̲i̲n̲g̲ ̲U̲n̲i̲t̲ ̲a̲n̲d̲ ̲C̲A̲C̲H̲E̲ ̲M̲e̲m̲o̲r̲y̲ ̲(̲C̲P̲U̲/̲C̲A̲C̲H̲E̲)̲
5.1.4.1.3.1 T̲h̲e̲ ̲C̲P̲U̲
The CPU part of the CPU/CACHE module is a general purpose
processing unit with a 16 bit word length and capable
of addressing 256 K words of memory. The CPU has two
instruction sets. The standard instruction repertoire
has 274 basic arithmetic, logic, transfer and special
instructions including bit, byte, word and multiple
word manipulations.
The standard instruction set is contained in app. 700
words of a 2K x 64 bits Prom.
An alternative instruction set may contain:
- Decimal Arithmetic instructions
- Instructions supporting high level language
- Monitor routines (micro-coded)
- User defined instruction
Internal registers include 8 general purpose accumulator
or index registers (R0-R7), a base register (BASE),
a program base register (PROG), a program counter (PC),
a timer register(TIMER), a process status word (PSW)
and a modify register (MODIFY).
Instructions are provided to save and load all registers
minimizing overhead when switching processes.
Instructions can be addressed, relative to PROG, indexed
relative to PC. Data is always addressed relatively
to the base register BASE.
Instructions are addressed in the 16 bit words. Data
may be addressed in several formats:
- single bit
- 8 bit bytes
- 16 bit words
- 32 bit words
- n x 16 bit words, where n = 1,2,3 ........... 16
The Processor Bus Interface H/W supports the CPU in
fetching and storing data while the processing part
is running (refer to fig 5.1.4.1.3.1-1).
Access to buffers in the Main Bus interface is controlled
by H/W, eliminating processor overhead.
Three buses are provided internally:
- The Input Bus (IBUS)
- The Output Bus (OBUS)
- The Address Bus (ABUS)
Two ALUs (Arithmetic Logic Units) are included, allowing
address and data manipulations to be performed simultaneously,
or allowing address calculations involving three elements
to be performed in one cycle when employing base register
addressing.
The micro-instruction cycle time is 250 ns.
Figure 5.1.4.1.3.1-1…01…C̲P̲U̲/̲C̲A̲C̲H̲E̲
The CPU can operate in 2 modes:
- System mode (AD17 = Logical "1")
- User mode (AD17 = Logical "0")
In the system mode all instructions in the instruction
set can be exectued, and the CPU has access to all
main memory locations.
In the user mode, only a subset of the instruction
set may be executed, and access to parts of the main
memory is prohibited.
Three types of interrupts exist in the system.
These are:
- I/O Interrupts
- CPU Interrupts
- Timer Interrupts
The interrupts are resolved by hardware within the
MAP module (sec. 5.1.4.1.4.1).
Independent masks for the three interrupt types are
available in the process status word.
I/O interrupts are grouped in 4 priority levels. Only
interrupts with priority higher than the priority of
the process executing in the CPU are serviced.
I/O interrupts can either be handled by a user defined
micro-program or result in switching of software process.
Timer interrupts (normally occurring each 150 us) are
serviced by micro-program. When a timer interrupt is
recieved the TIMER register is decremented and tested
(2 cycles). If negative a local interrupt is generated.
CPU interrupts are serviced by the micro-program, handling
the message related to the interrupt. Depending on
the message a switch of software process may take place,
or the current process may continue executing.
5.1.4.1.3.2 T̲h̲e̲ ̲C̲A̲C̲H̲E̲ ̲M̲e̲m̲o̲r̲y̲ ̲a̲n̲d̲ ̲C̲o̲n̲t̲r̲o̲l̲
This part of the CPU/CACHE consists of a 1K x 38 bit
static RAM memory, the CACHE memory and a control unit
performing read or write operations in the CACHE memory
when required.
The CACHE memory concept relies on the basic principle
that, in the step by step execution of a program, a
CPU originated read operation at an address has a high
average probability of being repeated.
Fundamentally the CACHE memory provides a small (compared
to main memory) high speed buffer containing copies
of previously accessed main memory locations. Addresses
and corresponding data accessed by the CPU are stored
in the CACHE memory which reduces the number of accesses
to slower main memory, increasing the overall system
speed.
Two advantages when using CACHE memories are obtained:
- Loading of the Processor Bus is reduced, allowing
for the use of more CPUs before bus contention
occurs. The max. number of CPU/CACHEs to be connected
without risk of continuous bus contention has been
estimated to 5, compared to 2 when using CPUs without
CACHE memory.
- Average access time when performing memory read
operations is reduced, thus improving the speed
of each CPU. The speed improvement has been estimated
to be within 5-20%, compared to a CPU without a
CACHE memory.
Generally the presence of the CACHE memory is only
visible to the programmer in terms of improved execution
speed, as the need for CACHE handling software is eliminated.
Below fig. 5.1.4.1.3.2-1, the CACHE memory word format
is shown.
Figure 5.1.4.1.3.2-1…01…C̲A̲C̲H̲E̲ ̲M̲e̲m̲o̲r̲y̲ ̲W̲o̲r̲d̲ ̲F̲o̲r̲m̲a̲t̲
Each word is divided into 9 fields:
- The CACHE parity field which contains the parity
bit that together with the MODE FIELD and the LPAGE-FIELD
gives even parity if the VALID FIELD bit is set
to logical "1".
- The VALID FIELD indicates whether the actual CACHE
location has valid data or not. Logical "1" corresponds
to "Valid".
- The MODE FIELD indicates the CPU-mode (System or
User) at the time the CACHE location was loaded.
A logical "1" corresponds to system mode.
- The LPAGE FIELD (Logical Page Field) and PHPAGE
FIELD (Physical Page field) are address information
fields partly identifying the address of the main
memory location copied in the MS and LS BYTE fields.
- The MS and LS BYTE fields contain the actual copy
of the addressed main memory location. The UP (Upper
parity) and LP (Lower parity) fields contain the
corresponding parity bits.
C̲A̲C̲H̲E̲ ̲M̲e̲m̲o̲r̲y̲ ̲A̲d̲d̲r̲e̲s̲s̲i̲n̲g̲
Three address sources are able to address a location
in the CACHE memory:
- The local CPU, providing a logical address as CACHE
entry.
- Another address sourcing module (CPU) in the same
Processor Unit Assembly, using the P̲r̲o̲c̲e̲s̲s̲o̲r̲ ̲B̲u̲s̲
and through the MAP provides a physical (mapped)
address.
- Another address sourcing module (DMA) in the same
Processor Unit assembly using the C̲h̲a̲n̲n̲e̲l̲ ̲B̲u̲s̲ and
through the MAP provides a physical (mapped) address.
In all three cases, the address provided is divided
into two fields (see fig. 5.1.4.1.3.2-2).
Figure 5.1.4.1.3.2-2
The low order address (10 bits) designates which of
the 1K CACHE locations to be accessed while the PAGE
field (physical or logical) is compared to the corresponding
page field in the CACHE word (Fig 5.1.4.1.3.2-1).
From this it is obvious that
- Each of the 1K CACHE-locations is shared between
main memory locations with identical low order
address providing a unique mapping function from
any given main memory location to one CACHE memory
location and a one-to-many mapping function from
one CACHE location to main memory.
C̲A̲C̲H̲E̲ ̲A̲c̲t̲i̲v̲i̲t̲y̲ ̲D̲u̲r̲i̲n̲g̲ ̲a̲ ̲C̲P̲U̲ ̲R̲e̲a̲d̲ ̲O̲p̲e̲r̲a̲t̲i̲o̲n̲
During a read operation the CACHE Controller distinguishes
between one of two read operations:
- Non-Semaphore protected read. (No Lock Bus Grant)
- Semaphore protected read. (Lock Bus Grant)
During a non-semaphore protected read, the 10 Low order
address bits from the CPU (AD0-AD9) are used for selecting
a word in the CACHE memory. The word is read and the
contents of the MSBYTE and LSBYTE FIELD is presented
to the CPU, provided that:
- The VALID FIELD indication is set.
̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ - CURRENT
CPU
mode
x
MODEFIELD
=
0.
This
to
ensure
that
data
in
a
CACHE
Location
updated
in
system
mode
(MODEFIELD
=
"1")
cannot
be
accessed
by
the
CPU
in
User
mode
(User
mode
=
"0").
- Equality exists between the LPAGE FIELD and the
logical page provided by the CPU
- No CACHE parity error is detected
If all of these conditions are met, a HIT is said to
take place, enabling the CPU to continue operation
at max. speed because no Processor Bus cycle (Bus Request,
Bus Grant) is initiated to get data from main memory.
If any of the tests fails a Processor Bus cycle is
initiated. During this bus cycle all data parity, address
and CPU mode is assembled by the CACHE controller and
stored in the CACHE memory, setting the VALID bit.
Should the bus operation terminate unsuccessfully (time-out,
parity, "no-access", or "page-fault" error) then the
CACHE controller will ignore the bus operation completely,
not updating the CACHE memory.
If a semaphore-protected read is initated from the
CPU a Processor Bus cycle is always required in order
to subject the main memory access to "Processor Bus
Authority Control" (performed by the MAP module). The
semaphore protection is part of certain CPU instructions
having the effect that the actual CPU, when a Processor
Bus Grant is given, issues a Lock Bus Grant hereby
stopping bus arbitration. Data accessed by the CPU
using this read mode is copied by the CACHE memory
if no errors occurred.
C̲A̲C̲H̲E̲ ̲A̲c̲t̲i̲v̲i̲t̲y̲ ̲D̲u̲r̲i̲n̲g̲ ̲a̲ ̲C̲P̲U̲ ̲W̲r̲i̲t̲e̲ ̲O̲p̲e̲r̲a̲t̲i̲o̲n̲
When the CPU performs a write operation a Processor
Bus cycle is a̲l̲w̲a̲y̲s̲ initiated (main memory update,
I/O update, MAP change). Detecting this situation the
CACHE controller reads the CACHE memory locations pointed
to by the low order address bits to check if:
- The VALID bit is set
̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲
- Current CPU-mode x (MODEFIELD) = 0
- The contents of the LPAGE-FIELD equals the Logical
page provided by the CPU
- No CACHE parity error detected
If these conditions are met and the Processor Bus cycle
is successful then the CACHE memory location is updated
with data written to main memory, CPU mode and parity.
If one or more of the conditions are not met no CACHE
updating takes place.
If a CACHE parity error is detected or the Bus operation
is unsuccessful while the other conditions are met
then the CACHE memory location is deleted (i.e the
VALID FIELD is set to logical "0"). In general it can
be said that:
- Only successful CPU-write operations involving
main memory locations previously copied by the
CACHE memory will result in a CACHE memory updating.
D̲e̲l̲e̲t̲i̲o̲n̲ ̲o̲f̲ ̲C̲A̲C̲H̲E̲ ̲M̲e̲m̲o̲r̲y̲ ̲L̲o̲c̲a̲t̲i̲o̲n̲(̲s̲)̲
The CACHE memory contents may be deleted in individual
locations or all locations.
Single locations are deleted when:
- the CACHE controller detects that a write operation
is initiated, and successfully terminated, by an
address sourcing module other than the CPU connected
to the CACHE, involving main memory locations copied
in the CACHE memory.
To detect this the CACHE controller continuously monitors
the Processor and Channel Bus for successful write
operations, comparing the physical (mapped) addresses
to these contained in the PHPAGE-FIELD in the addressed
CACHE memory location, and deleting (resetting the
VALID FIELD) CACHE locations corresponding to the main
memory locations having been updated.
All locations are deleted (all VALID FIELD bits are
reset) when:
- The logical to physical address mapping function
for a CPU is changed by the CPU
This is done to ensure system security.
C̲A̲C̲H̲E̲/̲C̲P̲U̲ ̲T̲e̲s̲t̲i̲n̲g̲ ̲F̲a̲c̲i̲l̲i̲t̲i̲e̲s̲
In addition to the above mentioned CACHE controller
functions the CACHE controller also takes care of:
- Testing the CACHE memory when told to do so by
the CPU
- Signalling the CPU when CACHE parity errors are
detected
- Disabling/enabling the CACHE memory functions
A CACHE test sequence can be initiated by the CPU.
Once started, the sequence can be performed concurrently
with internal CPU action. The result of the test is
loaded into the IDR (Internal Data Register, see fig.
5.1.4.1.3.1-1) of the CPU, which in case of a detected
fault may instruct the controller to disable further
CACHE operations, indicating that by lighting an "error
LED" on the front panel of the CPU/CACHE module.
Disabling the CACHE is under CPU firmware control.
When disabled all CACHE locations are cleared. Enabling
the CACHE is carried out either by:
- Activating a "reset" push button on the front panel,
or
- Executing a "CACHE-enable" CPU micro-instruction
If the CACHE controller, when reading a CACHE memory
location, detects a parity error two actions are performed:
- The faulty CACHE memory location is deleted (VALID
FIELD = logical "0", and
- The occurence of a fault is signalled to the CPU
This facility enables the CPU to measure the rate of
or the total number of CACHE memory errors and to disable
the CACHE if too many errors or a too high error rate
is detected.
5.1.4.1.3.3 M̲e̲c̲h̲a̲n̲i̲c̲a̲l̲ ̲a̲n̲d̲ ̲E̲l̲e̲c̲t̲r̲i̲c̲a̲l̲ ̲S̲p̲e̲c̲i̲f̲i̲c̲a̲t̲i̲o̲n̲s̲
M̲e̲c̲h̲a̲n̲i̲c̲a̲l̲ ̲D̲i̲m̲e̲n̲s̲i̲o̲n̲s̲ ̲o̲f̲ ̲a̲ ̲C̲P̲U̲/̲C̲A̲C̲H̲E̲ ̲M̲o̲d̲u̲l̲e̲:̲
Height: 412,6 mm ( 10 U Crate)
Width: 17,1 mm ( 1 Module)
Depth: 305 mm
P̲o̲w̲e̲r̲ ̲C̲o̲n̲s̲u̲m̲p̲t̲i̲o̲n̲ ̲f̲o̲r̲ ̲a̲ ̲C̲P̲U̲/̲C̲A̲C̲H̲E̲ ̲M̲o̲d̲u̲l̲e̲:̲
+ 5V: 16A
The CPU/CACHE is a front crate mounted module
5.1.4.1.4 M̲A̲P̲ ̲a̲n̲d̲ ̲M̲I̲A̲ ̲(̲M̲A̲P̲ ̲I̲n̲t̲e̲r̲f̲a̲c̲e̲ ̲A̲d̲a̲p̲t̲e̲r̲)̲ ̲M̲o̲d̲u̲l̲e̲s̲
The MAP/MIA modules provides more different essential
functions in the CR80D system:
- Perform the logical to physical address translation
and access protection
- Control the CR80D Data Channel Transfer and protocol
- Set up DMA (Direct Memory Access) between main
memory in the Processor Unit and I/O modules in
the Channel Unit (Data transferred on the Data
Channel)
- Generate the Master Timing signals [1 and [2 to
CPUs in the PU
- Service Timer, I/O and CPU interrupts
- Control the protocols and communication associated
with an V24 communication port on the MIA
- Contain system boot load procedures in a PROM (Programmable
Read Only Memory) on the MIA module
The MAP/MIA Connection is shown in fig 5.1.4.1.4-1.
Figure 5.1.4.1.4-1…01…MAP MIA CONNECTION
5.1.4.1.4.1 T̲h̲e̲ ̲M̲A̲P̲ ̲M̲o̲d̲u̲l̲e̲
Below in fig. 5.1.4.1.4.1-1 is shown a blocked diagram
of the MAP, indicating the major functional blocks
within the MAP:
- The Bus Timing & Control
- The Processor Bus and Channel Bus interface
- The Mapping/Address Translation Block
- The Access Control Logic
- The DMA and Data/Address Register Block
- The Processor- and Channel Bus Arbitration Logic
- The Control, Timing and Command Logic
- The micro-processor section
Fig. 5.1.4.1.4.1-1…01…T̲h̲e̲ ̲M̲A̲P̲ ̲M̲o̲d̲u̲l̲e̲
B̲u̲s̲ ̲T̲i̲m̲i̲n̲g̲ ̲&̲ ̲C̲o̲n̲t̲r̲o̲l̲
This section of the MAP generates the following signals
on the Processor and Channel Bus:
- Clock signals ([1 and [2) for synchronizaion and
timing of activities in the Processor Unit
- The Master Clear signal MC activated either due
to a power on situation or by activating a push-button
on the front panel of the MAP
For further specifications please refer to sec 5.1.3.1.
P̲r̲o̲c̲e̲s̲s̲o̲r̲ ̲a̲n̲d̲ ̲C̲h̲a̲n̲n̲e̲l̲ ̲B̲u̲s̲ ̲I̲n̲t̲e̲r̲f̲a̲c̲e̲
These blocks only function as buffers/drivers between
the CR80D Main buses and the MAP, controlled by signals
on the Main buses or from the MAP. These control signals
are described in sec. 5.1.4.1.1.
M̲a̲p̲p̲i̲n̲g̲/̲A̲d̲d̲r̲e̲s̲s̲ ̲T̲r̲a̲n̲s̲l̲a̲t̲i̲o̲n̲ ̲B̲l̲o̲c̲k̲
Memory addresses generated by the address sourcing
modules in a PU, such as CPUs, Data Channel DMA (on
the MAP) and TDX bus DMA (on the STI/TIA), are translated
from the logical address space to the physical address
space. A more detailed block diagram of the address
translation H/W is shown in fig. 5.1.4.1.4.1-2.
Fig. 5.1.4.1.4.1-2…01…Mapping/Address Translation Block
Each of the address sourcing modules in a PU has a
set of two 6 bit segment registers assigned to it.
A maximum of 10 address sourcing modules can be connected
to the Processor Bus plus Channel Bus in a PU, five
on the Processor Bus (CPUs) and five on the Channel
Bus (DMA functions, including the Data Channel DMA
on the MAP). Hence, as seen from fig. 5.1.4.1.4.1-2,
we have two segment register banks each containing
ten 6-bit registers.
The Processor Bus arbitration Logic (CPUs) or the Channel
Bus arbitration Logic (DMA functions) selects which
of the ten segments to be used.
The logical address bit 16 (AD16), if CPU addressing,
or the R/W signal, if DMA addressing, selects which
of the two banks to be used.
This bank select is interpreted as follows:
- When the address sourcing module is a CPU then
AD16 = logical "1" if we have a Program fetch.
If the operation is a Data read/write then AD16
= logical "0".
- When the address source is a DMA, then:
R/W = logical "0" corresponds to read
R/W = logical "1" corresponds to write
The selected 6 bits plus the address source supplied
6 bits (AD10 - AD15) forms a 12 bit address bus for
the 4K x 18 bit RAM containing the logical to physical
address translation tables. The complete physical address
is the combination of the address source supplied 10
bits (AD0 - AD9) and 14 out of the 18 bits addressed
in the translation table.
Without changing the segment register set up it is
seen that the address source supplied 16 address bits
(AD0 - AD15) are able to address:
- 64K words of program and 64K words of data for
a CPU or
- 64K words of read only memory and 64K words of
write only memory for a DMA
The implemented memory address translation allows an
efficient utilization of memory since programs and
data not need to be contiguous areas, but may be divided
into pages of 1 K words distributed around the physical
address space. This is illustrated below in fig. 5.1.4.1.4.1-3.
Figure 5.1.4.1.4.1-3…01…A̲d̲d̲r̲e̲s̲s̲ ̲T̲r̲a̲n̲s̲l̲a̲t̲i̲o̲n̲
The inherent logical separation of programs and data
in the CR80D architecture is well suited for restricting
unauthorized access to data and processes and for preventing
non-intended modification of programs.
Security features are implemented in the Central Processor
by means of privileged instructions and memory protection.
The objectives of the protective mechanisms in the
CR80D processor are:
- to protect data belonging to a process against
non-intended modification by other processes and
against non-authorized reading;
- to protect programs against non-intended modifications,
and
- to prevent processes from monopolizing the processor
The protection mechanisms are as mentioned implemented
by introducing a processor state variable which can
take two values:
- USER STATE
- SYSTEM STATE
and by dividing the instruction set into privileged
or non-privileged instructions. The privileged instructions
can only be executed in the SYSTEM STATE.
Attempted execution of privileged instruction in the
USER STATE generates a local interrupt upon which the
CPU will automatically enter the SYSTEM STATE.
The output from the tranlation table RAM is 18 bit
data. Two bits are upper byte and lower byte parity
bits (odd parity), which are compared against 2 odd
parity bits generated in the Parity checking logic
based on the remaining 16 bits. The result is presented
to the Access Control logic. 14 of these 16 bits are
as mentioned above part of the physical address generated.
The remaining 2 bits are access protection bits that
together with the address source provided address bit
AD17 are decoded as:
AD17 1 SYSTEM STATE 0 USER STATE
Protection
bits
̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲
̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲
00 Page absent Page absent
01 Full access Full access
10 Full access Read only
11 Full access No access
Address sourcing modules on the Channel Bus can only
operate in the User State.
Only CPUs can use both the System and user state mode.
The access control bits, the address bit AD17 and the
parity check result is handled/interpreted by the access
control logic block.
The segment registers and the translation tables may
be accessed by a CPU by normal I/O operations. The
segment registers and the translation tables together
occupy one I/O address within the PU.
By issuing a special bus access, which is neither I/O
nor memory access, the CPU may read the access protection
bits for any word among the 128 K words of logical
memory address space.
The access protection bits are returned as the two
LSBs in the data word.
A̲c̲c̲e̲s̲s̲ ̲C̲o̲n̲t̲r̲o̲l̲ ̲L̲o̲g̲i̲c̲
Two main functions are carried out within this block:
- Access protection control
- Physical address destination control
A̲c̲c̲e̲s̲s̲ ̲P̲r̲o̲t̲e̲c̲t̲i̲o̲n̲ ̲C̲o̲n̲t̲r̲o̲l̲
The two access control bits, the address line 17 (AD17)
and the parity check result are all monitored and it
is determined whether the address sourcing module will
be allowed to access (R/W) the addressed memory location
or not. If a parity error is detected or the AD17,
protection bit combination reveals a "Page absent"
or "no access" condition access is inhibited, i.e.
the physical address and its associated control signal
will not be presented to the memory. This is also valid
if a "read only" condition is detected upon an attempted
write to a memory location. The inhibited access will
be detected by the address sourcing module as a "Time-out"
(no response signal from the memory device (RS)). The
cause of the "time-out" condition can be fetched in
an access status register on the MAP. Each of the address
sourcing modules on the PB and the CB (incl. the "on
MAP" Data Channel DMA) has an access status register
attached to it. An access status register is accessed
by a normal I/O transfer. The format of the access
status register is shown below in fig. 5.1.4.1.4.1-4.
Figure 5.1.4.1.4.1-4…01…A̲c̲c̲e̲s̲s̲ ̲S̲t̲a̲t̲u̲s̲ ̲R̲e̲g̲i̲s̲t̲e̲r̲
The access status register is changed after each I/O
or memory access. Thus, when a CPU/DMA reads its own
access status register this will be changed after the
access.
A̲d̲d̲r̲e̲s̲s̲ ̲D̲e̲s̲t̲i̲n̲a̲t̲i̲o̲n̲ ̲C̲o̲n̲t̲r̲o̲l̲
The destination of the physical address and thereby
the bus to transmit it on is controlled by this circuitry
in accordance with the four most significant bits of
the address field as defined below in fig. 5.1.4.1.4.1-5.
Figure 5.1.4.1.4.1-5…01…D̲e̲s̲t̲i̲n̲a̲t̲i̲o̲n̲ ̲C̲o̲n̲t̲r̲o̲l̲
It should be noted that an I/O address is as presented
by the address sourcing module and is not subjected
to any address mapping.
When a CPU addresses a memory location present in the
PU the 10 least significant bits of the address will
be driven from the CPU during the complete transfer,
while the upper 7 bits of the logical address will
be driven first from the CPU and used by the MAP for
generation of the physical address and afterwards the
MAP will take over and drive the upper 14 address bits
and present the physical address on the processor bus.
If the memory location is present in the CU then the
physical address will be transmitted on the Data Channel.
For the DMA modules on the channel bus the same principle
as for the CPUs on the Processor bus is used.
When the CPU addresses an I/O module - if it is not
the MAP itself - the MAP will transmit the address
either to the channel bus or to the data channel dependent
of the DA field in the address.
When a DMA addresses an I/O module the address will
be transmitted either to the Data channel, if the DA
field differs from zero, or to the Channel bus.
This addressing scheme means that all I/O modules except
the MAP is connected to either the Data channel or
to the Channel Bus and not to the Processor Bus.
D̲M̲A̲ ̲&̲ ̲D̲a̲t̲a̲/̲A̲d̲d̲r̲e̲s̲s̲ ̲R̲e̲g̲i̲s̲t̲e̲r̲s̲
The DMA and Data/Address registers are used as a Data/Address
(single or block) communication boundary between the
PU and the MIA/Data Channel system.
A data transfer on the Data Channel can be done in
one of two ways:
- A single word transfer
- A multiple word (block) transfer
A single word transfer takes place when a CPU wants
to read/write a data word from/to a device in the channel
unit. This is detected by the access control logic,
which latches the address and data (if write) in the
data/address registers activating the control (MAP/MIA
BUS control) and Command Logic to perform the single
transfer of the address (in three bytes) and data (in
2 bytes) towards the MIA/Data Channel.
A block transfer is initiated upon CPU request. This
involves the DMA function on the MAP. The DMA is really
only 1/2 of the DMA system, with the other half on
the MIA. Together with the microprocessor on the MAP,
the CPU performs a DMA set up specifying:
- Data source, incl. address information
- Data destination, incl. address information
- Block size
The block transfer mode initiates a "set up" transfer
to the MIA, which in turn initiates the MIA/Data Channel
system, including the other 1/2 DMA (a FIFO and a word
counter) to perform the block transfer, through the
FIFO. A more detailed explanation will be qiven in
section 5.1.4.1.4.2 (the MIA module).
P̲r̲o̲c̲e̲s̲s̲o̲r̲ ̲&̲ ̲C̲h̲a̲n̲n̲e̲l̲ ̲B̲u̲s̲ ̲A̲r̲b̲i̲t̲r̲a̲t̲i̲o̲n̲ ̲L̲o̲g̲i̲c̲s̲
Beside the MAP module up to five address sourcing modules
can be connected to the Processor Bus (which the MAP
cannot access) and up to four can be connected to the
Channel Bus.
Control of the bus access for these modules is taken
care of in the arbitration logics on the MAP by means
of a set of individual handshake signals for each address
sourcing module. The handshake procedure assures full
utilization of the bandwidth on each bus (up to 4 Mwords/second
on each bus).
The handshake signals are described more specifically
in sec. 5.1.4.1.1.
On the Processor Bus, the handshake signals also include
a Lock Bus Grant signal line (LBG, not existing on
the Channel bus) which is accessed by a CPU when it
is performing a "Semaphore protected" operation. This
enables a CPU to perform multiple operations (for instance
read/modify write operations or block updating) without
any other CPU taking over the Processor Bus in between.
The LBG inhibits the Processor Bus arbitration when
accessed.
T̲h̲e̲ ̲M̲i̲c̲r̲o̲-̲p̲r̲o̲c̲e̲s̲s̲o̲r̲ ̲S̲y̲s̲t̲e̲m̲
This section explains the functions of the micro-processor
system shown on the block diagram. To a high degree,
references to the previous sections are used in the
explanations, since the purpose of this section is
to show how hardware is organized to implement the
functions described earlier.
M̲i̲c̲r̲o̲-̲P̲r̲o̲c̲e̲s̲s̲o̲r̲
The micro-processor (MP) handles interrupts, Data Channel
DMA, V24 communications port, self test, and system
start up.
Communication with the CR80D CPUs located in the Processing
Unit is carried out via the MP-RAM, which is accessible
from the Processor Bus using I/O commands.
I̲n̲t̲e̲r̲r̲u̲p̲t̲ ̲P̲r̲o̲c̲e̲s̲s̲i̲n̲g̲ is performed with all tables located
in the MP-RAM. The MP fetches interrupt vectors from
Interrupt Receiver and Interrupt Scanner, and CPUs
are notified via Interrupt Transmitter (Notify CPU
#).
D̲a̲t̲a̲ ̲C̲h̲a̲n̲n̲e̲l̲ ̲D̲M̲A̲ transfers are set up by the MP upon
request from CPUs. Optionally, the MP may be programmed
to a DMA handling, which is more intelligent than described.
For instance, queued DMA requests and block multiplexing
might be implemented this way.
The V̲2̲4̲ ̲P̲o̲r̲t̲ may be used either as CR80D I/O part or
as peripheral part for the MP dependent on a "normal/,maintenance"
mode switch on the MAP front Panel.
In the normal mode, the MP handles blocking of data
with buffer areas located in MP-RAM, sets up baud rate
and other control variables, and controls the communication
between the CR80D and the external device.
In the maintenance mode case, the MP executes commands
from the port, thus providing a tool for debugging
the CR80D system, since the MP may access all memory
and I/O devices accessible from the appropriate Processing
Unit.
S̲e̲l̲f̲ ̲T̲e̲s̲t̲ ̲a̲n̲d̲ ̲S̲y̲s̲t̲e̲m̲ ̲S̲t̲a̲r̲t̲ ̲U̲p̲ is performed by the MP
upon Master Clear of the PU. The procedure includes:
o Check of all registers and RAM areas in the MAP
o Check of most important control functions
o Initialization of registers and RAM resident Tables
including Translation Tables
o Activation of a CR80D CPU in the PU
M̲P̲ ̲R̲A̲M̲ ̲a̲n̲d̲ ̲P̲R̲O̲M̲
These together form a micro-processor memory space
of max. 24 K bytes, connected to the MP bus.
The P̲r̲o̲c̲e̲s̲s̲o̲r̲ ̲B̲u̲s̲ may access this memory by I/O instructions
using either an internal memory pointer, "P", or special
I/O instructions, which are decoded to certain RAM
locations.
The pointer may be used for:
V24 data buffer
CR80D PROM program
Loading of interrupt tables
Test purposes
Note, that only one c̲o̲m̲m̲o̲n̲ pointer exists for these
applications.
I̲n̲t̲e̲r̲r̲u̲p̲t̲ ̲P̲r̲o̲c̲e̲s̲s̲i̲n̲g̲
Interrupts from all sources in the system are received
and stored in the MAP. I/O interrupts are sensed on
the INA line (serial) while CPU interrupts are loaded
directly to the MAP RAM area from the interrupting
CPU. Each interrupt in the system (CPU, I/O) has an
interrupt vector (IV) with an associated priority (P(IV)).
A total of 4.096 interrupts exist within the system.
An interrupt vector is a 12 bit word composed as shown
overleaf in fig. 5.1.4.1.4.1-6.
11 8 7 6 5 0
CA P MA
CA: crate address: 0 is Processor Unit
1-15 is a Channel Unit
(one of fifteen possible)
P: interrupt priority (local priority)
MA: if I/O interrupt: MA indicates I/O module
address.
if CPU interrupt: the three MSBs indicate
the
source CPU. The three LSBs
indicate 1 of 8 possible
interrupt vectors for that
CPU.
Fig. 5.1.4.1.4.1-6…01…I̲N̲T̲E̲R̲R̲U̲P̲T̲ ̲V̲E̲C̲T̲O̲R̲
The priority of a CPU interrupt is always three (P
= 11 binary) which means that no I/O interrupt vector
from an I/O module in a PU can be assigned a priority
higher than two (P = 10 binary) to ensure interpretation
of the MA field as an I/O address.
A part of the RAM area (on the MAP) is used for tables
on the basis of which an interrupt vector is interpreted.
Three tables are used:
- IV record table
- Pool descriptor table
- CPU priority table
The IV record table contains a record (one byte) for
each of the possible interrupts (4.096). The IV is
used as an entry to this table giving the system priority
of the interrupt (bits 0-3), a pool index which is
a pointer to the Pool descriptor table (bit 4-6) and
an occurred flag (bit 7) which is set when the corresponding
interrupt occurs and is reset from the CPU servicing
it when a new interrupt is allowed.
The Pool descriptor table contains up to eight descriptors
(each one byte) associated with the above mentioned
pool index.
The pool index is used as an entry to this table giving
a set of CPU's (bit 0-4), which may be notified when
an interrupt with the corresponding pool index is received,
and a pool disable bit (bit 5) which is set by the
MAP when a CPU in the pool has been notified and reset
by the CPU that was notified.
The CPU priority table contains the priority of each
CPU in the PU.
The IV principle is shown on fig. 5.1.4.1.4.1-7 overleaf.
Notification of a CPU is only initiated if one of the
CPUs in the IV associated Pool descriptor has a priority
lower than the IV System priority and the pool is not
disabled.
Each of these tables are accessible from a CPU using
FIFO oriented I/O instructions. Each change in the
tables done by a CPU has to be signalled to the MAP,
except when resetting the occurred flag bit.
Two more areas are created within the MP-RAM:
- Notification descriptor area
- IV queue area
The Notification descriptor area contains the IV which
caused notification of a CPU. Two bytes are used for
each CPU, with the contents corresponding to the IV.
The IV is loaded from the MAP and read from the interrupted
CPU.
The IV queue area is used for intermediate storage
for the IVs not currently allowed to notify a CPU (P(IV)…0f…-…0e…P(CPU)
or Pool disable is set).
C̲o̲n̲t̲r̲o̲l̲,̲ ̲T̲i̲m̲i̲n̲g̲ ̲&̲ ̲C̲o̲m̲m̲a̲n̲d̲ ̲L̲o̲g̲i̲c̲
This block together with the 9 bit wide MAP/MIA Bus
(MMB, 8 bit + parity) controls and monitors the result
of data transfer to/from the MIA/Data Channel. A set
of 4 control/timing signals are issued from the MAP
to the MIA:
- COV (Command bus valid)
- MCL (Master clear)
- RFI (Reset FIFO)
- CLK (8 MHz Clock)
From the MIA, the MAP receives 8 control signals:
- IRY (Interrupt Ready)
- BTH (Block Transfer Halted)
- BTO (Block Transfer On)
- STR (Single Transfer Response)
- STE (Single Transfer Error)
- FMY (FIFO Empty)
- FFU (FIFO Full)
- TIM (Timer)
The six bits of the MAP/MIA Command Bus (MCB) are used
to define communication between the MAP & the MIA/Data
Channel. The two MSBs (MCB5, MCB4) define a set of
four command classes:
- single type
- set up type
- FIFO type
- Internal MIA type
The least significant bit (MCB0) is the sense/control
(S/C) bit, defining the direction on the MMB:
- Read from MIA
- Write to MIA
The two bits (MCB1, MCB2) define the type of transfer
as I/O type or memory type (memory high byte, memory
low byte or memory word).
The last bit (MCB3) tells whether the operation is
a write to or a read from a Channel Unit.
5.1.4.1.4.2 T̲h̲e̲ ̲M̲I̲A̲ ̲M̲o̲d̲u̲l̲e̲
The MIA (MAP Interface Adapter) is the interface between
the MAP and the Data Channel. A block schematic of
the MIA is shown overleaf in fig. 5.1.4.1.4.2-1. The
fundamental function of the MIA is to communicate with
Channel Units connected to the Data Channel.
…01…Fig. 5.1.4.1.4.2-1
T̲h̲e̲ ̲M̲I̲A̲
The Data Channel contains an information bus (IB),
an interrupt data line (ID) and five timing and control
signals. The IB is shared by data addresses and error
messages and the ID line is shared by interrupt requests
and interrupt responses, timed by the IT (interrupt
timing signal).
The MIA is furthermore equipped with a V24 interface,
which makes it possible to communicate with a terminal.
The communication is controlled by the micro-processor
on the MAP.
Towards the Data Channel the MIA is the master but
towards the MAP, the MIA is a slave.
The authority of the Data Channel belongs to the MIA
i.e. no CU can access the Data Channel except when
commanded by the MIA.
Transfer on the IB is carried out as:
- Single transfer
- Set up transfer
- Reduced transfer
A transfer always consists of an address phase, a data
phase, and a termination phase.
A̲d̲d̲r̲e̲s̲s̲ ̲P̲h̲a̲s̲e̲
To address one memory location out of 1 Mword memory
in a CU 24 bits are necessary, 4 bits for the CU address
and 20 bits for the memory address. The MMB is 9 bits
wide (8 bit data + 1 parity bit) indicating the necessity
of 3 transfers of 9 bits (8 bit data + 1 parity bit)
to transfer the whole address.
To address an I/O module in a CU only 16 bits are necessary
(see table 5.1.3.1-6) 4 bits for CU address and 12
bits for I/O module number and I/O command. Still,
the transfer is exactly as indicated for a memory operation
leaving 8 bits as "don't cares". Furthermore, 3 x
2 bits identifying the operation are transferred, i.e.
each transfer on the Data channel consists of 11 bits
in parallel (8 address/data bits, 2 control bits and
1 parity bit).
Overleaf on fig. 5.1.4.1.4.2-2 is shown the 10 bits
of the 3 transferred address cycles. (The parity bit
is omitted).
Fig. 5.1.4.1.4.2-2…01…A̲D̲D̲R̲E̲S̲S̲ ̲P̲H̲A̲S̲E̲
CU is the Channel Unit address (1-15). AF0, AF1 and
AF2 are the address of a memory location if memory
operation. If the operation is an I/O read/write,
the lower half of AF1 and the whole AF2 constitutes
the I/O address and command, the upper half of AF1
and the whole AFO being "don't cares". The six bits
C0-C5 are the control bits indicating the type of operation.
C5 and C4 indicate whether the operation is a read
or a write. C3 and C2 indicate either:
- I/O or
- Memory low byte or
- Memory high byte or
- Memory word.
While C1 and C0 indicate the transfer mode:
- Single transfer
- Set up transfer
- Reduced transfer
The address phase is identified by the address timing
signal AT issued on the Data Channel by the MIA together
with each of the three address cycles.
D̲a̲t̲a̲ ̲P̲h̲a̲s̲e̲
The data phase is two cycles each carrying one byte
of data, two control bits and 1 parity bit. If a word
is transmitted the first cycle contains the lower byte.
If only one byte is transmitted, it is placed in the
first or second cycle according to whether it is a
lower or upper byte. The content of the passive cycle
is undefined, but with correct parity. 10 bits of
each Data cycle is shown below in fig. 5.1.4.1.4.2-3
(The parity bit is intentionally left out).
Fig. 5.1.4.1.4.2-3…01…D̲A̲T̲A̲ ̲P̲H̲A̲S̲E̲
The data are present on the Data Channel when the data
timing signal DT is issued either by the MIA during
write or by the addressed CU during read operations.
T̲e̲r̲m̲i̲n̲a̲t̲i̲o̲n̲ ̲P̲h̲a̲s̲e̲
The termination phase contains an acknowledge from
the addressed Channel Unit that resets the Data Channel
to be ready for a new transfer.
- W̲r̲i̲t̲e̲ ̲O̲p̲e̲r̲a̲t̲i̲o̲n̲
When the MIA has finished the address and data
phase, it awaits the data acknowledge signal (DA).
This together with a DT signal is transmitted
by the Channel Unit.
If the Channel Unit has detected an error condition,
a message is transmitted on the IB-lines along
with the DA and DT signals.
- R̲e̲a̲d̲ ̲O̲p̲e̲r̲a̲t̲i̲o̲n̲
If the Channel Unit detects no errors, the transfer
is terminated during the data phase by a DA-signal
simultaneously with the second data cycle.
If on the other hand an error is detected, the
data phase is omitted and the DA-signal and the
DT-signal are transmitted together with an error
message on the IB-lines.
If the addressed Channel Unit does not respond
within 4 microseconds, a time out condition is
reached, and the MIA terminates the unsuccessful
transfer with a DA-signal and a DT-signal.
T̲r̲a̲n̲s̲f̲e̲r̲ ̲M̲o̲d̲e̲s̲
Three modes exist:
- Single transfer
- Set up transfer
- Reduced transfer
S̲i̲n̲g̲l̲e̲ ̲T̲r̲a̲n̲s̲f̲e̲r̲
This mode is used when transferring one word (or byte).
The sequence is governed by the MAP issuing the three
address cycles on the MMB along with the single transfer
command on the MCB timed with the CLK signal. …86…1
…02… …02… …02… …02…
This information is by the MIA sequencer routed to
the Data Channel, the MAP Command decoded to the six
control signals C0-C5. During a write operation, the
MAP furthermore supplies the data word to be written,
and this is also in two data cycles forwarded to the
Data Channel. The MIA monitors the Data Channel termination
phase to determine whether the transfer:
- ended with success
- ended with an error status
- ended as a time-out
In the first case, the MIA accesses the STR line indicating
the correct transfer. In case of a read operation,
the MIA writes the data word received from the addressed
Channel Unit into two registers RD1 & RD2. The STR
signal tells the MAP to access the MIA to read these
two registers.
In the second and third case, the MIA signals the error
condition by activating the STE line instead. This
causes the MAP to access (read) the register RD1 on
the MIA in which the MIA has written an error status.
The STR and STE signals are reset each time the MAP
initiates a single transfer.
R̲e̲d̲u̲c̲e̲d̲ ̲T̲r̲a̲n̲s̲f̲e̲r̲
When performing a block transfer (DMA) between memory
in a PU and I/O or memory in a CU, this mode is applied.
It is preceded by a set up transfer during which the
MAP issues a three cycle address. Before the last
address cycle is issued, the MAP must load a transfer
counter on the MIA with the number of data words to
be transferred (max. 256). Along with each address
cycle, the MAP issues the set up command on the MCB.
The address cycles are forwarded on the Data Channel.
The effect of the set up is that:
- a Reduced Address Register (RAR) on the MIA is
loaded with the first address cycle bits containing
the Channel Unit number.
- a RAR on the CIA (see sec. 5.1.5.1.1) in the addressed
Channel Unit is loaded with all three address cycle
bits containing apart from the CU number, the address
of the I/O or memory location where the transfer
starts.
When the last of the three address cycles has been
issued, the Reduced transfer starts. This is governed
by the MIA sequencing logic releaving the MAP for other
tasks.
When the block transfer starts, this is signalled to
the MAP by setting the BTO flag.
The Reduced transfer only has one address cycle being
the address loaded to the RAR on the MIA during set
up. This is transmitted to the Channel Bus, and the
CIA that recognizes the CU number puts the complete
memory or I/O address, loaded into its RAR during the
set up, onto the Channel Unit I/O Bus.
The data phase is similar to that of a single transfer
with the exception that the data path now goes through
the FIFO.
W̲r̲i̲t̲e̲ ̲O̲p̲e̲r̲a̲t̲i̲o̲n̲
After the Reduced address has been issued, the MIA
transmits the data word (two data cycles). The data
is fetched from an internal FIFO holding 64 9-bit bytes
(8 data + 1 parity).
After the transmission of the last data cycle, the
MIA awaits the DA signal from the Channel Unit. This
causes:
- The Transfer Counter is decremented
- The RAR on the CIA is:
if memory operation: incremented
if I/O operation: unchanged
In case the FIFO becomes empty before the Terminal
Count (TC) reaches zero, the block transfer becomes
pending and does not continue until the FIFO contains
at least 2 bytes. This situation is signalled to the
MAP by resetting the BTO flag and setting the FMY signal.
The FIFO may be loaded during a block transfer. If
the data received from the MAP contains a parity error,
no action is taken. The data simply ripples through
the FIFO and are transmitted to the Data Channel with
a parity error.
R̲e̲a̲d̲ ̲O̲p̲e̲r̲a̲t̲i̲o̲n̲
Each time the MIA receives a data word from the Data
Channel the TC is decremented. The RAR on the CIA
is incremented if it is a memory operation. The data
word is loaded into the FIFO simultaneously with the
checking of parity errors.
If the FIFO becomes full before the TC reaches zero,
then the MAP is notified by the FIFO Full (FFU) flag.
In this case the block transfer is pending the BTO
is reset. The transfer does not continue until the
MAP has read at least 2 bytes from the FIFO. The MAP
may drain the FIFO during the block transfer.
If the data contains a parity error, then the MIA stops
the block transfer and notifies the MAP by setting
the BTH flag simultaneously loading the Block Transfer
Error (BTE) register.
The data received from the CU may contain an error
message. In this case, the MIA stops the block transfer,
loads the BTE register with the error message plus
an error status and sets the BTH signal high.
If the CU does not response at all, the MIA issues
the DA signal, sets the BTH signal and loads the BTE
with an error status.
During a Reduced transfer, the MAP can issue a single
transfer. The MAP issues only the first address cycle
to the MIA and then waits for the BTO flag to be reset.
After that, the rest of the single transfer may be
issued as usual. When the single transfer has ended,
the reduced transfer continues setting the BTO flag.
In case of an erroneous transfer on the Data Channel,
the MIA stops the block transfer by setting the BTH
signal high and clearing the BTO signal.
To ensure that the FIFO is empty before a retransmission
of the block the MAP must issue a Reset FIFO (RFI)
signal on the RFI-line. After this, the block transfer
is initiated as usual by the Set Up Transfer.
I̲n̲t̲e̲r̲r̲u̲p̲t̲
The MIA is equipped with a polling controller which
is capable of fetching interrupts from 15 Channel Units.
All 15 possible CU addresses are polled cyclicly independent
of the number of CUs present.
The polling controller frees the MAP from the set up
of interrupt requests. However, by a command the MAP
may request an interrupt vector from a CU.
Interrupt requests are transmitted in serial form on
the Interrupt Data (ID) line synchronously with the
Interrupt Timing (IT) on the IT-line. Interrupt responses,
issued by a CU are received in serial form on the ID-line
synchronously with the IT signal. All responses from
CUs are terminated by an Interrupt Acknowledge (IA)
signal issued on the IA-line by the CU in question.
In case no response is received after an interrupt
request the MIA issues the IA signal and terminates
the interrupt procedure.
M̲I̲A̲ ̲C̲o̲n̲t̲r̲o̲l̲l̲e̲d̲ ̲I̲n̲t̲e̲r̲r̲u̲p̲t̲ ̲R̲e̲q̲u̲e̲s̲t̲s̲
The polling controller transmits automatically the
interrupt request word. The response from the CU may
either be a Module Address (MA) or Status Word (SW)
depending on the MSB of the response.
If the response is a Status Word containing a "No Interrupt"
code the MIA issues a new interrupt request containing
the next CU in the polling sequence, without notifying
the MAP.
In case the response is a Module Address or a Status
Word that does not contain a "No Interrupt" code, the
MIA notifies the MAP by setting the Interrupt Ready
(IRY) flag. Simultaneously the polling sequence is
stopped and it does not continue until the MAP has
read an Interrupt Module Address (IMA) register. When
the polling sequence continues the IRY flag is cleared.
As the Module Address may originate from several Channel
Units the MAP must read an Interupting Channel Unit
(ICU) register before reading the IMA register. If
the ICU register is read after the IMA register then
the ICU register does not hold valid data.
The ICU register is an eight bit register. The 4 least
significant bits hold the CU address and he 4 most
significant bits hold a status code.
M̲A̲P̲ ̲C̲o̲n̲t̲r̲o̲l̲l̲e̲d̲ ̲I̲n̲t̲e̲r̲r̲u̲p̲t̲ ̲R̲e̲q̲u̲e̲s̲t̲s̲ ̲
By a command the MAP may write an interrupt request
word into an Interrupt Request Register (IRR). In this
case the MIA completes any ongoing interrupt request
and notifies the MAP if necessary. After this the MIA
issues the contents of the IRR on the Data Channel.
The result from a MAP controlled interrupt request
will always be notified to the MAP by the IRY flag.
This is in force whether the CU responds or not. The
status of the response is contained in the 4 most significant
bits of the ICU register.
S̲e̲r̲i̲a̲l̲ ̲I̲/̲O̲ ̲I̲n̲t̲e̲r̲f̲a̲c̲e̲ ̲(̲S̲I̲O̲I̲)̲
The MIA contains a programable SIOI which makes it
possible for the CR80D system to communicate with a
"Data Terminal Equipment".
The SIOI conforms to the following:
- EIA Specification RS 232C
- CCITT Recommendation V24/V28
The communication can be synchronous or asynchronous,
full or half duplex.
Sixteen different baud rates are manually selectable
by a code switch, which is mounted on the front plate.
The functional operation of the SIOI is programmed
by a set of commands and data supplied by the MAP.
These commands and data specify items, such as synchronous
or asynchronous mode, baud rate, number of bits per
character, etc.
After programming, the SIOI is ready to perform the
desired communication function.
C̲P̲U̲ ̲N̲o̲t̲i̲f̲i̲c̲a̲t̲i̲o̲n̲ ̲&̲ ̲T̲i̲m̲e̲r̲ ̲I̲n̲t̲e̲r̲r̲u̲p̲t̲
As mentioned in sec. 5.1.4.1.4.1 (The MAP, interrupt
processing) the MAP informs the CPU upon reception
of an interrupt by the "Notify CPU #" issued on the
INT0-INT2 lines. In fact it is the MIA that accesses
these lines, plus the IST (Interrupt Strobe) line,
commanded to do so by the MAP.
It is also the MIA that generates the fast timer interrupts.
The timer interrupt consists of a code which is generated
by the MIA. The code is issued on the INT (2:0) lines
together with the timing signal on the IST line in
accordance with the Main Bus specification. The time
between two timer interrupts is strap selectable on
the MIA, and can be adjusted in steps of 10 microsec.
in the interval 10 microsec. - 160 microsec.
As the timer interrupt code is issued on the same lines
as the CPU notification codes the MIA delays the CPU
notification if the timer interrupt and a CPU notification
"collides" within the MIA.
T̲h̲e̲ ̲"̲O̲n̲ ̲M̲I̲A̲"̲ ̲P̲R̲O̲M̲
The PROM part of the MIA contains a 4K x 18 bit PROM.
Sixteen bits are data and 2 bits parity bits. One parity
bit for each data byte. The PROM is addressed by the
MAP as a Single Transfer of the memory word type. As
for the PROM addressing, the PROM is placed as the
upper 4K words of the total 16 Mwords physical address
space.
Thus if the address is …0f…-…0e… FFF000 (HEX) then the 3 least
significant digits are the PROM address.
If the address is …0f…-…0e… FFF000 (HEX) then the whole address
is transmitted on the Data Channel. As mentioned before
all transfers include a termination phase during which
the addressed CU issues a DA signal. This is still
in force but the MIA issues the DA signal on the DA-line
as soon as the MIA detects a PROM address rather than
a Data Channel address. Thus all the CUs on Data Channel
are reset.
The MIA detects whether it is a PROM address or a Data
Channel address after the second address byte has been
received from the MAP.
If it is a PROM address then the third address byte
is never issued on the Data Channel.
The data from the addressed PROM location is loaded
into the RD1 and RD2 registers and simultaneously the
STR flag is set. After this the MAP fetches the contents
of the two registers.
5.1.4.1.4.3 M̲e̲c̲h̲a̲n̲i̲c̲a̲l̲ ̲&̲ ̲E̲l̲e̲c̲t̲r̲i̲c̲a̲l̲ ̲S̲p̲e̲c̲i̲f̲i̲c̲a̲t̲i̲o̲n̲s̲
M̲e̲c̲h̲a̲n̲i̲c̲a̲l̲ ̲D̲i̲m̲e̲n̲s̲i̲o̲n̲s̲ ̲o̲f̲ ̲t̲h̲e̲ ̲M̲A̲P̲ ̲M̲o̲d̲u̲l̲e̲
Height: 412,6 mm ( 10 U Crate)
Width: 17,1 mm ( 1 Module)
Depth: 305 mm
The MAP is a front crate mounted module.
P̲o̲w̲e̲r̲ ̲C̲o̲n̲s̲u̲m̲p̲t̲i̲o̲n̲ ̲o̲f̲ ̲t̲h̲e̲ ̲M̲A̲P̲
+ 5 V: 12A
M̲e̲c̲h̲a̲n̲i̲c̲a̲l̲ ̲D̲i̲m̲e̲n̲s̲i̲o̲n̲s̲ ̲o̲f̲ ̲t̲h̲e̲ ̲M̲I̲A̲ ̲M̲o̲d̲u̲l̲e̲
Height: 412,6 mm ( 10 U Crate)
Width: 17,1 mm ( 1 Module)
Depth: 160 mm
The MIA is a rear crate mounted module.
P̲o̲w̲e̲r̲ ̲C̲o̲n̲s̲u̲m̲p̲t̲i̲o̲n̲ ̲o̲f̲ ̲t̲h̲e̲ ̲M̲I̲A̲
+ 5V: 5 A
+12V: 0,25 A
-12V: 0,25 A
E̲l̲e̲c̲t̲r̲i̲c̲a̲l̲ ̲S̲p̲e̲c̲i̲f̲i̲c̲a̲t̲i̲o̲n̲ ̲o̲f̲ ̲t̲h̲e̲ ̲M̲A̲P̲/̲M̲I̲A̲ ̲F̲l̲a̲t̲c̲a̲b̲l̲e̲ ̲B̲u̲s̲
̲(̲M̲M̲B̲ ̲a̲n̲d̲ ̲M̲C̲B̲)̲
The levels for all signals between the MAP and the
MIA are normal TTL levels.
High: 2.0V V…0f…IN…0e… 5.0V; 2.44 V…0f…OUT…0e… 5.0V
Low: =0 V…0f…IN…0e… 0.8V;0V V…0f…OUT…0e… 0.5V
The load for the different signals are as specified
in the following (all currents are numerical values).
M̲M̲B̲ ̲(̲M̲A̲P̲/̲M̲I̲A̲ ̲D̲a̲t̲a̲ ̲B̲u̲s̲)
3-state signals with the following requirements.
Drivers: I…0f…OH…0e… 5.2mA
I…0f…OL…0e… 16.0mA
I…0f…0…0e…off 100 microA
Receivers: I…0f…IH…0e… 100 microA
I…0f…IL…0e… 0.5mA
M̲C̲B̲ ̲(̲M̲A̲P̲/̲M̲I̲A̲ ̲C̲o̲m̲m̲a̲n̲d̲ ̲B̲u̲s̲)̲
Control and timing signals:
Drivers: I…0f…OH…0e… 6.3mA
I…0f…OL…0e… 16.0mA
Receivers: I…0f…IH…0e… 100 microA
I…0f…IL…0e… 0.5mA
M̲I̲A̲/̲D̲a̲t̲a̲ ̲C̲h̲a̲n̲n̲e̲l̲ ̲S̲i̲g̲n̲a̲l̲s̲
These signals are transformer coupled and pulsed with
a nominal pulse width of 62.5 ns.
Transformer driver specifications:
I…0f…OL…0e… max. 100mA
V…0f…0…0e… max. 10V
Receiver specification:
Threshold: 1V
Hysteresis: 30mV
The signals are terminated by 120 ohm shunt resistor
at both ends of the Data Channel (i.e. at the PU and
the CU).
5.1.4.1.5 T̲h̲e̲ ̲D̲a̲t̲a̲ ̲C̲h̲a̲n̲n̲e̲l̲
The CR80D Data Channel is a twisted pair flat cable
which forms the communication path bewteen the CR80D
Processor Unit (PU) and up to 15 Channel Units (CU)
as illustrated in fig. 5.1.4.1.5-1.
The connected units are DC-isolated from each other
in order to reduce ground current problems in large
systems. This is obtained by coupling the signals to
the channel via transformer circuits.
The channel is divided into two different paths, one
for information and one for interrupts. The information
path is used for both addresses and data and is a parallel
bus with a width of one byte. The interrupt path is
serial.
All exchange of information is initiated by the Processor
Unit, which issues the address before each data transfer.
The electrical rate of transfer is 8 Mbytes/s for the
information path and 8 Mbit/s for the interrupt path.
In fig. 5.1.4.1.5-2 overleaf, is listed the signals
on the 25 twisted part flat cable bus.
Figure 5.1.4.1.5-1…01…DATA CHANNEL CONNECTIONS
SIGNAL NAME
IB 0 INFORMATION BIT 0 (LSB)
IB 1 INFORMATION BIT 1
IB 2 INFORMATION BIT 2
IB 3 INFORMATION BIT 3
IB 4 INFORMATION BIT 4
IB 5 INFORMATION BIT 5
IB 6 INFORMATION BIT 6
IB 7 INFORMATION BIT 7
IB 8 INFORMATION BIT 8
IB 9 INFORMATION BIT 9
IB P INFORMATION PARITY
AT ADDRESS TIMING
DT DATA TIMING
DA DATA ACKNOWLEDGE
ID INTERRUPT DATA
IT INTERRUPT TIMING
IA INTERRUPT ACKNOWLEDGE
Figure 5.1.4.1.5-2…01…S̲i̲g̲n̲a̲l̲s̲ ̲o̲n̲ ̲t̲h̲e̲ ̲D̲a̲t̲a̲ ̲C̲h̲a̲n̲n̲e̲l̲
5.1.4.1.6 T̲h̲e̲ ̲R̲A̲M̲ ̲M̲o̲d̲u̲l̲e̲
The RAM module is a standard storage module used as
program and data storage in the CR80D system. The module
has dual ported interface to two transfer buses; Processor
and Channel Bus in a Processor Unit and I/O Bus A and
B in a Channel Unit. The two ports can be accessed
simultaneously without restriction due to an arbiter
function located in the module. The arbitration is
performed so that no time is waisted when both ports
are serviced, meaning that the memory chips are operated
at minimum cycle time 375 ns, and thereby gives a fast
access time from both ports. The module can be equipped
with different types and quantities of dynamic RAM
chips to give a memory area of either 64K words or
128K words.
The functional blocks in the module are shown in figure
5.1.4.1.6-1 and shortly described below.
Two identical circuits perform the interface function
to the two transfer buses. Those circuits are:
D̲a̲t̲a̲ ̲I̲n̲p̲u̲t̲ ̲R̲e̲g̲i̲s̲t̲e̲r̲
Storage for data to be loaded into the RAM area. Due
to the use of this register the response time during
write operation is as low as 190ns - 280ns.
D̲a̲t̲a̲ ̲O̲u̲t̲p̲u̲t̲ ̲R̲e̲g̲i̲s̲t̲e̲r̲
Storage for data fetched from the RAM area. This register
ensures that service of the other port can be performed
without influencing the first accessed port.
A̲d̲d̲r̲e̲s̲s̲ ̲R̲e̲c̲e̲i̲v̲e̲r̲
This circuit consists of two parts, a buffer for the
least significant bits (AD0-AD6, row address) and a
register for the most significant bits (AD7-AD13, column
address) so that the bus transfer can be terminated
before the RAM area operation is completed (write operation).
A̲d̲d̲r̲e̲s̲s̲ ̲B̲u̲f̲f̲e̲r̲
The circuit receives the address bits used for selection
of different sections of the RAM area.
A̲d̲d̲r̲e̲s̲s̲ ̲C̲o̲m̲p̲a̲r̲a̲t̲o̲r̲
This circuit consists of comparators comparing bus
address with the contents of the switch settings, and
thereby allows the RAM area to be located within the
total memory space, and if necessary disable parts
of the RAM area.
The following functional blocks are common for both
buses as described below:
S̲w̲i̲t̲c̲h̲ ̲C̲i̲r̲c̲u̲i̲t̲
The switches define the module address within the total
memory area, and define an upper and a lower limit
to be disabled, if necessary.
Figure 5.1.4.1.6-1…01…The RAM Module
R̲A̲M̲ ̲C̲o̲n̲t̲r̲o̲l̲: This circuit performs a number of controls:
- D̲e̲c̲o̲d̲i̲n̲g̲: the addressed section of the RAM area
is selected, by generation of the proper RAM chip
select.
- A̲u̲t̲h̲o̲r̲i̲t̲y̲: controls, which of the three possible
sources, (bus 1, bus 2 or refresh) that may access
the RAM area. The circuit is designed so that
all the sources will be serviced, and so that the
RAM is operated at maximum speed.
The outputs from the circuit perform the control
of the internal communication paths.
- S̲e̲q̲u̲e̲n̲c̲e̲ ̲a̲n̲d̲ ̲T̲i̲m̲i̲n̲g̲: receive input from the Authority
control and generate all the required timing signals
sequences for operation of the module.
- R̲e̲f̲r̲e̲s̲h̲: contains a 16 MHZ crystal oscillator
for timing of the module, and the counters required
for generation of the refresh address to the dynamic
RAM chips. The refresh address is seven bits and
the refresh rate is one refresh per 15 usec.
R̲A̲M̲ ̲A̲r̲e̲a̲: The memory is divided in four sections each
consisting of 18x1 bit RAM chips, corresponding to
16 or 32K word storage (chip type dependent) per section.
The area can either be accessed as bytes, 8 + 1 parity
bits or word 16 + 2 parity bits.
5.1.4.1.6.1 M̲e̲c̲h̲a̲n̲i̲c̲a̲l̲ ̲&̲ ̲E̲l̲e̲c̲t̲r̲i̲c̲a̲l̲ ̲S̲p̲e̲c̲i̲f̲i̲c̲a̲t̲i̲o̲n̲s̲
M̲e̲c̲h̲a̲n̲i̲c̲a̲l̲ ̲d̲i̲m̲e̲n̲s̲i̲o̲n̲s̲ ̲o̲f̲ ̲t̲h̲e̲ ̲R̲A̲M̲ ̲m̲o̲d̲u̲l̲e̲:
Height: 412,6 mm ( 10 U crate)
Width: 17,1 mm ( 1 Module)
Depth: 305 mm
The RAM is a front crate mounted module.
P̲o̲w̲e̲r̲ ̲C̲o̲n̲s̲u̲m̲p̲t̲i̲o̲n̲:
+ 5V: 3,5 A
+12V: 1 A
-12V: 10 mA
Identical power connections from both connected transfer
buses are shorted in the module, meaning that the module
must not be used in a Channel Unit with dualized power
supplies.
5.1.4.1.7 T̲h̲e̲ ̲S̲T̲I̲/̲T̲I̲A̲ ̲M̲o̲d̲u̲l̲e̲s̲
Via the STI (Supra-TDX bus Interface) and the TIA (Telecommunication
Interface Adapter), the CR80D system is able to access
an external bus structure, the TDX bus (Telecommunication
Data Exchange bus).
The STI is interfacing directly to the CR80D Channel
Bus while the TIA is the front end towards the TDX
bus. Connection between the two is done by a flat
cable bus called the HI bus (Host Interface Bus, fig.
5.1.4.1.7-1).
Fig. 5.1.4.1.7-1…01…S̲T̲I̲/̲T̲I̲A̲ ̲C̲o̲n̲n̲e̲c̲t̲i̲o̲n̲
Due to the dualized TDX Bus Structure, two TIA modules
are necessary, both controlled by one STI.
5.1.4.1.7.1 T̲h̲e̲ ̲T̲I̲A̲ ̲M̲o̲d̲u̲l̲e̲
A brief introduction to the TDX bus concept will be
given here to ease the understanding of the TIA functions.
The TDX BUS is essentially a high rate digital link
utilizing a communication protocol with high immunity
to interference.
Full packet protocol with error detection and correction
is implemented on the TDX bus for data integrity.
By means of two sets of screened twisted pair cables,
upper and lower bus, it transmits data at a clock rate
of 1.8432 MHz with a maximum throughput of 1.6384 Mbit/sec.
An addressing scheme allows up to 256 devices to share
the TDX bus.
The time division multiplexed serial transfer TDX bus
is clocked and synchronized by a TDX controller. The
controller outputs a continuous bit stream of 1.8432
Mbit/sec. on the lower bus. This stream is divided
into 6400 time-slots of 288 bits per second.
Each time slot (equal to 156,3 microsec.) on the lower
bus contains a standard HDLC frame with control information
(5 bytes), DATA to be transferred (16 bytes), and CCITT-16
(2 bytes) cyclic redundancy check (CRC). The HDLC
frame starts at the beginning of a time slot and takes
up a maximum of 236 bits of the 288 bits in the time
slot, the remaining bits being all "ONES" and from
bit No. 240 all "ZERO'es".
The TDX controller inserts as second byte in the HDLC
frame (fig. 5.1.4.1.7.1-1) on the lower bus a MUX No.
taken from a MUX table (on the controller) that is
scanned according to the speed level assigned to each
device on the TDX bus.
Fig. 5.1.4.1.7.1-1
T̲D̲X̲ ̲B̲u̲s̲ ̲F̲r̲a̲m̲e̲
All devices with their unique device no., set on a
DIL switch, on the TDX BUS look at the MUX No. byte,
and when it coincides with the device No. of a device,
this device has the use of the upper bus, to transmit
data, at the end of the frame on the lower bus, provided
that the lower bus CRC check shows no errors. This
ensures that only one device will transmit on the upper
bus at any time.
If a device instead of recognizing the MUX No. recognizes
the HOST No. or the Device No. it means that data in
the data frame is meant for this device.
One of the devices connected to the TDX BUS is the
TIA, acting as the CR80D front end towards the TDX
BUS.
Fig. 5.1.4.1.7.1-2
The TIA
The TIA, shown on fig. 5.1.4.1.7.1-2, interfaces to
the TDX BUS via tristate drivers and receivers. The
en-/decoder circuit converts the serial data stream
to a number of parallel data bytes. Data coming from
the TIA is converted from parallel to serial code and
synchronized to a clock extracted from the received
data.
Incoming parallel data (bytes) are routed to FIFO1
while the HOST No., Dev. No., MUX No., and CRC are
checked "on the fly" by the state controller.
When HOST-No. is equal to the DIL-switch and no CRC-error
was indicated, the frame is routed to FIFO2 and the
front end control CPU gets an interrupt. Now the front
end control has to move, by DMA, the frame to the buffer
for incoming frames at the same time setting a FULL
flag in a status byte in front of the buffer. This
incoming buffer are located in the input Data RAM area.
If the MUX no. was equal to the DIL-switch and no CRC-error
was indicated, the transmitter will start-up transmission
when bit 241 of received data has been reached. Now
the parallel to serial converter requests for data
bytes which is routed from the output FIFO if it is
not empty.
Once per 156 usec the front end control CPU polls the
output FIFO to see if the content has been transmitted.
If so, a new frame is transferred from the outgoing
buffer located in the output Data RAM to the output
FIFO by the front end control DMA. When no frames
are available in the buffer, no action is taken and
nothing will be transmitted when the parallel to serial
converter requests a new frame.
The TIA Data buffer arbiter selects whether the HI
bus or the TIA gets access to the Data buffer memory.
The arbiter and data buffer memory are designed to
give a maximum wait time of 250 ns in case of conflict.
T̲h̲e̲ ̲i̲n̲p̲u̲t̲/̲o̲u̲t̲p̲u̲t̲ ̲D̲a̲t̲a̲ ̲R̲A̲M̲
This memory is a dual ported 1K x 8 bit RAM used as
buffer memory for ingoing and outgoing frames.
The only path for communication between the TIA and
the STI module goes through this RAM and the HI bus.
5.1.4.1.7.2 T̲h̲e̲ ̲S̲T̲I̲ ̲M̲o̲d̲u̲l̲e̲
The block schematic of the STI is shown on fig. 5.1.4.1.7.2-1.
Fig. 5.1.4.1.7.2-1
The STI Module
M̲a̲i̲n̲ ̲C̲o̲n̲t̲r̲o̲l̲ ̲C̲i̲r̲c̲u̲i̲t̲
This part of the STI, incl. the Channel Bus interface,
provides the connection between the CR80D Channel Bus
and the internal HI bus. Two main functions are handled
by this circuit, namely:
a) the CR80D access to the central RAM
b) the DMA transfer from CR80D to front ends and vice
versa.
H̲I̲ ̲B̲u̲s̲ ̲A̲r̲b̲i̲t̲r̲a̲t̲o̲r̲
This block covers the access to the HI bus. Two Types
of modules are connected to the bus, namely the Master
modules, and the Slave modules.
Master modules:
Channel Bus Interface Circuit
Outgoing processor
Ingoing processor
Slave modules:
Central RAM
Front-ends (TIA input/output DATA RAMs)
The access of the Master modules to the bus is governed
by the HI BUS arbiter, according to a cyclic priority
scheme:
Channel Bus Interface (Central RAM Access)
Channel Bus Interface (Front End DMA)
Outgoing Processor
Channel Bus Interface (Central RAM Access)
Channel Bus Interface (Front End DMA)
Ingoing Processor
Channel Bus Interface (Central RAM Access)
Channel Bus Interface (Front End DMA)
A two-byte transfer between the Central RAM and the
Main Bus Interface takes in this way 2.25 usec.
In order to access the HI bus, each Master module has
its own set of access request (ARQ) and access granted
(BAG) signals.
Two types of slaves exist:
a) Single Byte slaves (front ends) which are designed
to transfer a single byte at a time on the HI BUS.
b) Dual Byte slaves (Central RAM), which only accept
a dual byte access. The dual type of the slave
is indicated to the master by holding a HI-Bus
signal low during the first byte transfer, indicating
that a second byte will/must follow.
I̲n̲g̲o̲i̲n̲g̲ ̲P̲r̲o̲c̲e̲s̲s̲o̲r̲
This processor runs the routines associated with reception
of frames. The ingoing scan routine polls the status
byte of the frame buffer in front of the front-end
input buffer queue until finding the FULL bit set (indicating
that a correctly received frame is available, no CRC
error etc). The incoming processor then uses the frame
CR-ID (Refer to fig. 5.1.4.1.7.1-1) as an entry into
an "Ingoing scan table", resident in the Central RAM,
to get a 2 byte base address for a corresponding "Protocol
descriptor", also in central RAM.
The protocol routine program to run on the Ingoing
processor is selected by the pointer found in the-low-order
byte of the first word in the protocol descriptor.
Execution is initiated by starting the selected program
with the base address found in the "protocol descriptor".
The ingoing processor now, according to protocol, either
discards the frame or sets up a DMA descriptor and
a DMA request which initiates the Main control, based
on the DMA descriptor, to transfer data from the front
end input buffer (resetting the FULL flag) to CR80D
main memory, and also possibly according to protocol
stores a message to CR80D in a CR80D message buffer
(in central RAM), for example in the case of a successfully
received packet.
Finally is returned to the ingoing scan routine for
service of next received frame.
The ingoing scan routine besides polling for a received
frame, also polls a mailbox for time outs detected
by the outgoing scan routine.
O̲u̲t̲g̲o̲i̲n̲g̲ ̲P̲r̲o̲c̲e̲s̲s̲o̲r̲
This processor runs the routines associated with transmission
of frames.
The outgoing scan routine provides an entry into the
"outgoing scan table" (in central RAM) to get a 2 byte
base address of the protocol descriptor to be loaded
from the protocol descriptor buffer.
Based on the contents of the protocol descriptor, it
is decided whether to continue the procedure or not
(Data available or not). If no data are available
for the outgoing process, then the outgoing scan routine
continues to the next entry in the outgoing scan table.
If data are available, then the high order byte of
the first word in the protocol descriptor is used to
select the outgoing protocol routine. This routine
scans a FULL flag in the front end (TIA) outgoing data
buffer. When this flag is not set, indicating a free
outgoing buffer, the outgoing processor sets up a DMA
descriptor and a DMA request, which initiates the Main
Control, based upon the DMA descriptor, to transfer
the data from the CR80D main memory to the front end
outgoing data buffer.
C̲e̲n̲t̲r̲a̲l̲ ̲R̲A̲M̲
The Central RAM is a 32K byte RAM. It can be accessed
by the ingoing processor, the outgoing processor and
a CR80D CPU via the HI bus.
A CR80D CPU loads the Central RAM with the incoming
and outgoing scan table, the protocol descriptors and
data buffer links telling where to put or fetch data
in CR80D main memory.
During operation, the CR80D processes can delete, create
or change protocol descriptors.
To delete a protocol descriptor (close a link) its
base address is removed from the incoming or outgoing
scan table or both.
To create a protocol descriptor (open a link) the descriptor
is loaded to the protocol descriptor buffer area and
its base address within Central RAM is loaded to one
or both scan tables as necessary.
The CR80D processor will only make changes in a protocol
descriptor when its base address is removed from one
or both scan tables, as necessary, in order not to
interfere with ingoing or outgoing processor (concurrent
processing).
Finally the CR80D processor can by issuing a RESET
command, force the incoming and outgoing processor
to remove all entries in their scan tables (closing
all links). The RESET command is utilized during initialization
of the STI/TIA system.
I̲n̲t̲e̲r̲r̲u̲p̲t̲ ̲t̲o̲ ̲C̲R̲8̲0̲D̲
Upon request from Ingoing or Outgoing processor the
Main Control processor is able to issue an interrupt
to the CR80D system, this interrupt can by the CR80D
CPU be read in the MAP.
The interrupt code issued is set on a DIL switch.
5.1.4.1.7.3 M̲e̲c̲h̲a̲n̲i̲c̲a̲l̲ ̲&̲ ̲E̲l̲e̲c̲t̲r̲i̲c̲a̲l̲ ̲S̲p̲e̲c̲i̲f̲i̲c̲a̲t̲i̲o̲n̲s̲
M̲e̲c̲h̲a̲n̲i̲c̲a̲l̲ ̲d̲i̲m̲e̲n̲s̲i̲o̲n̲s̲ ̲o̲f̲ ̲t̲h̲e̲ ̲T̲I̲A̲ ̲m̲o̲d̲u̲l̲e̲
Height: 412,6 mm ( 10 U crate)
Width: 17,1 mm ( 1 Module)
Depth: 160 mm
The TIA is a rear crate mounted module.
P̲o̲w̲e̲r̲ ̲C̲o̲n̲s̲u̲m̲p̲t̲i̲o̲n̲ ̲o̲f̲ ̲t̲h̲e̲ ̲T̲I̲A̲
+ 5V: TBD
-12V: TBD
M̲e̲c̲h̲a̲n̲i̲c̲a̲l̲ ̲d̲i̲m̲e̲n̲s̲i̲o̲n̲s̲ ̲o̲f̲ ̲t̲h̲e̲ ̲S̲T̲I̲
Height: 412,6 mm ( 10 U crate)
Width: 17,1 mm ( 1 Module)
Depth: 305 mm
The STI is a front crate mounted module.
P̲o̲w̲e̲r̲ ̲C̲o̲n̲s̲u̲m̲p̲t̲i̲o̲n̲ ̲o̲f̲ ̲t̲h̲e̲ ̲S̲T̲I̲
+ 5V: 6 A
+12V: 0,3 A
-12V: 10 mA
5.1.4.1.8 T̲h̲e̲ ̲C̲C̲A̲ ̲M̲o̲d̲u̲l̲e̲
This module is part of the SS&C system and will be
treated within the SS&C part of the System Design (sec.
5.4).
5.1.4.1.9 T̲h̲e̲ ̲P̲o̲w̲e̲r̲ ̲S̲u̲p̲p̲l̲y̲
TBD.
5.1.4.2 D̲o̲c̲u̲m̲e̲n̲t̲a̲t̲i̲o̲n̲
TBD.
5.1.4.3 E̲n̲v̲i̲r̲o̲n̲m̲e̲n̲t̲a̲l̲ ̲S̲p̲e̲c̲i̲f̲i̲c̲a̲t̲i̲o̲n̲
TBD.
