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Notes: CPS/TMA/019 (R) (Week 3)
Names: »2700A «
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└─⟦219ec82bd⟧ Bits:30006169 8" Wang WCS floppy, CR 0292A
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!…00……00……00……00…G…0a……00……00…G…0b…G…0d…G…01…G…05…F…09…F…0d…F…00…F F…07…E…0a…E…0e…E…01…E…05…D…09…D…0d…D…00…D D…07…C…0a…C…0d…C…00…C…07…B…0e…B
A…09…A…0f…A…06…@…0b…@
?…0b…?
.…08….…0f…*…07…)…0d…)
#…01…#…07…"…0d…" !…0d…!…02…!…05… …0c…
…1f……0a……1f……0f……1e……08……1e……0e……1e……06……1d……0d……1d… …86…1 …02… …02… …02…
CAMPS Instructor's Manual for
MT/RST Course, Week 3
CPS/TMA/019
CDRL Logistics Support No. 03A
Line Item 8.2.4-B
Niels-Erik Nielsen
Kurt Nybroe-Nielsen
SHAPE (2), NEN, LT, ER[, ALG,
Conf. Mgmt., LU
…0f… ILS Train. Mgmt. 840610
2
840610
Conf.Mgmt. 840610…0e…
2700A/rt …02… CPS/TMA/019
…02……0f… NEN/840610…02…ii
CAMPS INSTRUCTOR'S MANUAL FOR
MT/RST COURSE, WEEK NO. 3…02… Issue 1…02… CAMPS…0e…
821011 All Preliminary Issue
of Document
1 830617 All Completely new update
of
manual
2 840620 All Completely new update
of
the manual in accordance
with CPS Log.No. 1434,
831021.
…0e… 2700A/rt
840610
PU & CU CRATES/PS/FAN UNIT 3:1:1 45
CAMPS…0f…
Describe the physical lay out of
the CU & PU crates and the module positioning
- Describe the mains supply connections
- Describe the PS unit
- Describe the Fan unit
Evaluation of lab. exercises in lesson 3:1:4-6
- The students must have performed the
exercises and filled out the lab work sheets with
the correct results.
- Revision at progress test question 5 and 19
Classroom
L
Black board, 7 OH's
STB II: Section 26
HBK: Section 2.2.2, 3.2, 3.3
HWB: Section 2.1.
…0e… 2700A/rt
840610
CR80 BUS STANDARD 3:1:2 45 CAMPS…0f…
Describe the General data busses
- Processor bus
- Channel bus
- I/0 bus A
- I/O bus B
Describe the main bus terminator (MBT)
Describe the control & power busses.
During evaluation of exercises in lesson 3:1:4-6
- The students must perform the exercise
and the work sheets are checked
during the evaluation
- Revision at progress test questions 1-3 and
18
Classroom
L
Black board, 10 OH's
HBK: Section 3.2.
STB I: Section 8…86…1
…02… …02… …02…
…0e… 2700A/rt
840610
DATA CHANNEL/CIA 3.1.3 45 CAMPS…0f…
- Describe the principles of the
DATA CHANNEL communication
- Describe the CHANNEL INTERFACE ADAPTOR (CIA)
functions
During evaluation of exercises in lesson
3:2:4-6 DAMU EXERCISES
- The students must state the results
of the UM1 command
- Revision at progress test question 4.
Classroom
L
Black board, 6 OH's
HBK: Section 3.7
STB I: Section
…0e… 2700A/rt
840610
PRACTICE PU & CU CRATE 3:1:4-6 3x45 CAMPS…0f…
- Take the PU & CU units apart.
- Disconnect and connect all cables in the PU
and the CU.
- Locate the mains power and DC power
distribution
- Measure on the power distribution busses.
Evaluation of the exercises.
- The students must have filled the work sheets correct
when performed the exercises 1 and 2.
Training room
I, EX, GW, DI
Training System.
Lab. Guide (13 pages).
HWB: Section 2.1
…0e… 2700A/rt
840610
MAP/MIA 3:2:1-2 2x45 CAMPS…0f…
- Describe the MAP/MIA functions
- Describe the address translation principle
- Describe the bootstrap principle
- Describe the interrupt principle
- Describe the MAP/MIA switches and indicators
Evaluation of the exercises in lesson 3:3:4-6
- The students must have performed the
exercise
- Revision at progress test question 6-9, 12 and
14-16
Classroom
L
Black board, 4 OH's
STB I: Section 11 and 12
HBK: Section 2.5
SLM: Section 4.5
…0e… 2700A/rt
840610
DAMU 3:2:3 45 CAMPS…0f…
- Describe the DAMU functions
and use.
- Use the DAMU for bootstrap and
configuration checks.
- Describe the maintenance functions
in the MAP/MIA
Questions during lesson
Evaluation of exercises in lesson 3:3:4-6
- The students must have performed
the exercise.
- Revision at progress test questions 11 and 17.
Classroom
L
Black board, 1 OH.
MPO
…0e… 2700A/rt
840610
PRACTICE DAMU 3:2:4-6 3x45 CAMPS…0f…
- INITIALIZE the system
- ENABLE the I/O MODULES
- SET PARITY in the MODULES
- STATE the response of the UM commands
Evaluation of the exercises
- The students must have performed
the exercise.
Training Room
GW, EX, DI
Training system with VDUs connected to both of the
MIAs.
Lab. Guide (3 pages).
MPO
…0e… 2700A/rt
840610
CPU/CACHE 3:3:1-2 2x45 CAMPS…0f…
- Describe the CPU (main) functions
- Describe the CPU operation principles
- Describe the CACHE principle
- Describe the processor start up routine
Evaluation of the exercises in lesson 3:5:4-6
- The students must have performed the CPU/CACHE
TEST
- Revision at progress test question 6
Classroom
L
Black board, 8 OH's
HBK: Section 2.4
STB I: Section 10
…0e… 2700A/rt
840610
RAM 3:3:3 45 CAMPS…0f…
- Describe the RAM module.
- Select the addressing area of the RAM
module (switch setting)
- check the actual RAM configuration
Evaluation of exercises in lesson 3:4:4-6
- The students must perform the RAM
test exercise
- Revision at progress test questions 10 and 13.
Classroom
L
Black board, 1 OH
SLM: Section 4.5.1
STB I: Section 13…86…1 …02… …02…
…02… …02… …02…
…0e… 2700A/rt
840610
PRACTICE MAP EXERCISES 3:3:4-6 3x45 CAMPS …0f…
- State the FRONT PANEL LEDS of the MAP module
- Use and state the MAINT. MODE COMMAND "M".
Evaluation of the exercises
- The students must have performed
the exercise.
Training Room
GW, EX, DI, I
Training system with VDUs connected to both of the
MIAs.
Lab.Guide (2 pages).
STB I: section 11, datasheet 7-7
…0e… 2700A/rt
840610
LTU/LIA 3:4:1 45 CAMPS…0f…
- Describe the LTU/LIA functions
- Describe the LTU/LIA switch settings
and indicators
- Describe the communication principle
between CPU's and LTU's
Questions during lesson
Evaluation of exercises in lesson 3:5:4-6
- The students must perform the exercise
described in student lab.guide
- Revision of progress test questions 18 and 20.
Classroom
L
Black board, 3 OH's
STB I: Section 15
…0e… 2700A/rt
840610
WATCHDOG 3:4:2 45 CAMPS…0f…
- Describe the WD functions
- Describe the WPU functions
Describe the WCA functions
- Describe the CCBA functions
Evaluation of exercises in lesson 7:1:4-6
- The students must perform the exercise no.1
described in student lab.guide 7:1:4-6
-
Classroom
L
Black board
7 OHs
STB I : section 7
STB II: section 23
…0e… 2700A/rt
840610
CCA & CUCP 3:4:3 2x45 CAMPS…0f…
- Describe the CCA functions
- Describe the CCB communication principle
- Describe the CUCP functions
Evaluation of exercises in lesson 7:1:4-6
- The students must perform the exercises 2 & 3 and
fill in the lab.work sheet for the CUCP exercise
correct
Classroom
L
Black board, 4 OH's
STB II: Section 24 and 27
…0e… 2700A/rt
840610
PRACTICE MAP TEST,RAM TEST 3:4:4-6 3x45 CAMPS…0f…
- Boot and run the MAP TEST
- Boot and run the RAM TEST
Evaluation of the exercises
- The students must have performed
the exercises
Training room
EX, I, GW
- Training System with VDUs connected to both
of the MIAs
- M & D TEST DISK PACK
- M & D TEST FLOPPY DISKETTES
- LAB. GUIDE (2 pages)
SLM.
…0e… 2700A/rt
840610
PROGRESS TEST 3:5:1-3 3x45 CAMPS…0f…
Evaluate his own comprehension of subjects taught in
this week.
The result of this test will be recorded on the "Student's
Progress Report".
Correction of answers
CAMPS Classroom
Progress test.
Test time 60 min.
Progress Test, 4 pages (OH1-4, a copy
for each student)
7 OH's
…86…1 …02… …02… …02…
…02…
…0e… 2700A/rt
840610
PRACTICE CPU/CACHE TEST 3:5:4-6 3x45 CAMPS…0f…
…0e…and LTU TEST…0f…
- Boot and run the CPU/CACHE TEST
- Boot and run the LTU TEST
Evaluation of the exercises
- The students must have performed the exercises.
Training Room
GW, DI, EX
- Training System with VDUs connected to both of
the MIAs.
- M&D TEST DISK PACK
- M&D TEST FLOPPY DISKETTES
- LAB.GUIDE (2 pages)Training System
SLM
…0e… 2700A/rt
840610
WEEKLY PROGRESS TEST 3:5:1-3 3 x 45 CAMPS…0f…
- The results will be used in the student's
final assessment.
The results of this test will be recorded on the
"Student's Progress Report".
Analysis of the test results
CAMPS Classroom
(Good separation required)
Progress Test (20 questions on subject covered during
week 3) Test time 45 min.
3 OH's
…0e… 2700A/rt
840610
PU & CU TROUBLESHOOTING 3:5:4-6 3x45 CAMPS …0f…
- Isolate and remedy system faults
at module level in the processor
unit (PU) and in the channel unit (CU).
- During the practical exercises
- During evaluation of the trouble
shooting exercises. Min.5 faults should be isolated
and remedied.
Training Room
GW, DI, EX
Training System
SLM
…0e… 2700A/rt
MT/RST 3:1:1 840610
PU & CU CRATES L
1 …0f…
OH 1 The PU and CU modules are housed
in 19
inch crates.
Functional PCB modules are inserted
in the front and rear magazines.
64 wire flatcables constitute the
interconnection between the front
and rear magazine modules. To give
access to the interconnection cables
and busses between the front and
rear magazines, the rear magazine
can be tilted backwards.
PU CRATE OH 2 F̲r̲o̲n̲t̲ ̲m̲a̲g̲a̲z̲i̲n̲e̲:̲ 25 slots for mounting
of 2
powers supplies + the main functional
modules. Modules are interconnected
via main
bus motherboards (P & C bus on connector
J1 & J2 respectively).
OH 3 R̲e̲a̲r̲ ̲m̲a̲g̲a̲z̲i̲n̲e̲:̲ 19 stations for mounting
of
adaptor modules. Power is distributed
to
J3 connectors via power bus Motherboard.
CU CRATE OH 4 F̲r̲o̲n̲t̲ ̲m̲a̲g̲a̲z̲i̲n̲e̲:̲ Similar to PU CRATE.
Modules
are interconnected via main bus
motherboards
(I/O bus A & B on connector J1 &
J2 respectively).
OH 5 R̲e̲a̲r̲ ̲m̲a̲g̲a̲z̲i̲n̲e̲:̲ Similar to CU CRATE.
Power is
distributed to J3 connectors via
control
& power bus.
…0e… 2700A/rt
MT/RST 3:1:1
840610
POWER SUPPLY L
2 …0f…
MAINS OH 6 The mains
to the P̲U̲
- DC supply
units are
PU supplied from the filterbox in the
rack,
housing the PU crate. Via power
panels in the rear magazines - which
contain a mains switch, a PWR indicator
(green) and a fuse (5A) - the mains
are led to the two CR 8055 power
supplies in the front magazine which
provide the DC outputs:
DC SUPPLY + 5V
+/-12V
+/-24V (Not used in CAMPS)
The two PS's are connected in parallel
to the P-bus, the C-bus motherboards
and to the J3 power bus in the rear
magazine.
Indicators (green) on the front
panels are ON when power is valid.
CU The mains to the two DC PS's in
the CU is supplied from the PU rack
(rack A & C) filterboxes - separate
supply to each PS via power panels
in the rear magazine.
The pos. 1-4 PS supplies the I/O
bus A and the upper part of the
rear J3 bus.
The pos. 22-25 PS supplies the I/O
bus B and the lower part of the
rear J3 bus.
The supplied DC voltages are:
DC SUPPLY + 5.5V
+/- 12.5V
+/- 24V (Not used in CAMPS)
…0e… 2700A/rt
MT/RST 3:1:1
840610
POWER SUPPLY L
3 …0f…
COMBINE The 0.5V over voltage on the 5 and
12 volts
CIRCUITS compensates the voltage drop of
the combine circuits on the CU modules.
The power combine circuits on the
CU crate
PCB modules protect one supply line
(A or B) against load from the other
by diodes inserted
as follows:
Black
Board 0,5V(f) 0,5V(f)
Ex: +5,5V(A)
+5,5V(B)
+5V to logic
STRAPS By straps on the PS plugs in
the crate, the outputs from the
supply units are selected:
SLM:Fig. PU crate strapping: F to E
4.5.1-8 CU crate strapping: F to H
…0e… 2700A/rt
MT/RST 3:1:1
840610
FAN UNIT L
4 …0f…
Just below each PU and CU crate
a 19" fan unit is placed.
The CR80M FAN UNIT takes air from
the front
AIR FLOW OH 7 side of the rack to cool the front
magazine
and takes air from the rear side
to cool the
rear magazine.
A filter is mounted in the front
intake to
FILTERS prevent particles from outside to
be deposited inside the rack cabinet.
No filter in the rear intake because
the air is taken from inside the
rack cabinet.
The FAN UNIT holds eight fans separated
on two decks with each four fans.
For inspection and replacement of
fans and filters see the SLM Sec.
3.4.1.2.
POWER OH 6 Each deck
is powered
from separate
mains
supplies. If one supply fails, the
four
fans still running are able to provide
sufficient cooling of the crate.
For each deck a mains switch and
fuse are located on the rear side,
and a power ON lamp is located on
the front side.
…0e… 2700A/rt
MT/RST 3:1:2
840610
CR80 BUS STANDARDS L
1…0f…
TYPES - M̲o̲d̲u̲l̲e̲ ̲i̲n̲t̲e̲r̲c̲o̲n̲n̲e̲c̲t̲
̲b̲u̲s̲s̲e̲s̲.
Normally carrying signals between
modules placed in the same crate
(system element)
- S̲y̲s̲t̲e̲m̲ ̲e̲l̲e̲m̲e̲n̲t̲ ̲b̲u̲s̲s̲e̲s̲.
Normally carrying signals between
crates (units) in the total system.
MODULE INTER- G̲e̲n̲e̲r̲a̲l̲ ̲d̲a̲t̲a̲ ̲b̲u̲s̲s̲e̲s̲.
CONNECT Are functionnally different, but
BUSSES compatible concerning mechanical,
electrical and timing characteristics
OH 1 - In the PU's: P Bus (Processor
bus) on the
connectors
J1.
C Bus (Channel
bus) on the
Connectors
J2.
Multilayer PCB's, terminated
in b̲o̲t̲h̲
e̲n̲d̲s̲ with a MBT (main bus terminator)
board.
OH 1 - In the CU: I/0 bus A on the connectors
J1
I/0 bus B on the connectors
J2
Multilayer PCB's, terminated
in
o̲n̲e̲ ̲e̲n̲d̲ with a MBT board, and
in
i̲n̲ ̲t̲h̲e̲ ̲o̲t̲h̲e̲r̲ ̲e̲n̲d̲ by the CIA.
C̲o̲n̲t̲r̲o̲l̲ ̲a̲n̲d̲ ̲p̲o̲w̲e̲r̲ ̲b̲u̲s̲s̲e̲s̲
- In the PU's: Control power
bus for rear
modules on
connectors
J3.
- In the CU: Power bus
for rear
modules
on connector
J3.
…0e… 2700A/rt
MT/RST 3:1:2 840610
CR80 BUS STANDARDS L
2 …0f…
GENERAL The specification for the P-bus
and C-bus in
DATA BUS the PU and the A-bus and C-bus in
the CU are equal except for supply
voltage;
dualized supply via diodes for the
CU, two PS's in parallel for the
PU.
BUS LINES OH 2 DA: 16 bidirectional data lines.
2 x 8 bytes, each with a parity
bit (ODD parity).
UP: Upper byte parity.
LP: Lower byte parity.
OH 3 AD: 16 address lines: A̲D̲O̲ ̲-̲ ̲A̲D̲
̲1̲5̲ ̲addresses
64K words (logical addr's to
MAP).
1 addr line AD16 specifies
program or
data area in logical memory
(each 64k Word).
The total of 20 addr. lines
permits addressing of up to
1 mega word physical memory
(from MAP)
LSO,LS1:
Specifies address destination
("0" = destination is MAIN
MEMORY.)
R/W:"0"= read word in specified
addr.
TRQ,AE,BD,RS: Transfer control signals
between CPU/DMA and MAP.
INR: Interrupt request
INA: Interrupt acknowledge
MC: Master clear. High when power
up or
when issued from the MAP.
2: 8 MHZ system clock
1: 1 MHZ system clock
Miscellaneous PWR & GND lines
…0e… 2700A/rt
MT/RST 3:1:2
840610
CR80 BUS STANDARDS L
3 …0f…
BUS HAND- OH 4 P̲ ̲b̲u̲s̲ ̲&̲ ̲C̲ ̲b̲u̲s̲ ̲i̲n̲ ̲P̲U̲ ̲c̲r̲a̲t̲e̲:̲
SHAKING
1) CPU or DMA (address sourcing
modules)
issues TRQ (L) when addressing
2) MAP returns BD when logical page
(AD10-17) is read. BD must provide
tri-stating of AD10-17 in the
addr.sourcing module.
3) MAP issues AE when the modified
addr. (physical) is valid (AD10-19
issued by MAP).
4) The addressed module responses
with RS when transmitting data,
or when data has been read.
A̲ ̲b̲u̲s̲ ̲&̲ ̲B̲ ̲b̲u̲s̲ ̲i̲n̲ ̲C̲U̲ ̲c̲r̲a̲t̲e̲:̲
1) The address sourcing module issues
TRQ when addressing.
2) The addressed module responses
with RS when transmitting data
or when data has been read.
…0e… 2700A/rt/
MT/RST 3:1:2
840610
CR80 BUS STANDARDS L
4…0f…
HBK: Page 3-80 and 3-81
MODULE OH 5 When peripheral
modules and
C̲b̲u̲s̲ DMA's
INTERRUPT want attention from the CPU they
issue INR
PRINCIPLE (interrupt request) in a 1 period.
In the PU the MAP receives the INR
on the Cbus, decides which CPU is
to be interrupted and notifies this
via the control bus. If the MAP
doesn't want to accept interrupts
from the Cbus it simply pulls the
INR line low.
In the CU the CIA receives and stores
the request until the MIA, in a
polling routine independently of
data transfer, fetches the interrupt.
OH 6 The interrupt code issued on the
INR line
consists of 8 bits:
2 Priority bits P[, P1 (MSB)
6 Module address bits (LSB)
The INR line is an open collector
line,
so if more modules transmit at the
same
time ("L" and "H"), the line will
contain "L".
The INA line which is INR inverted
(in the BTM module) is read by all
interrupt requesting modules and
compared to the issued INR.
As long as INA equals the just issued
INR bit, the module may continue
transmitting the next bit.
In this way only the module which
has majority of "ONES" (from MSB),
will be able
to transmit the complete 8bit INR
word.
In CAMPS the P[, P1 bits are set
to [ in all modules, so that the
priority is determined by the address
alone.
…0e… 2700A/rt/
MT/RST 3:1:2
840610
CR80 BUS STANDARDS L
5 …0f…
MBT All bus signals are normal TTL levels
0-5V.
OH 7 The DA lines and the ADO-19, LSO,
LS1,
R/W lines are tri-state signals,
and
in the MBT module they are pulled
up to logic
"1" (Vcc) when all outputs are disconnected
(high impedance).
The MC, INA, INR and transfer handshake
signals are open collector or tri-state
signals. They are terminated to
ground and Vcc, giving a quiscent
voltage of approx. 2.5V.
INTERRUPT OH 6 The MBT module holds the inverter
logic
SIGNALS for the INR, INA signals.
MOUNTING The MBT module must always be mounted
in the (special) rear slots at the
end of the crate.
POWER The supply voltage in the PU
crate is 5.0 V and in the CU
crate (dual PS) it is 5,5 V.
STRAPS OH 7 Therefore
when the
MBT module
is used in
a CU
strap S̲R̲ ̲2̲ must be placed in pos.
A
to introduce a small voltage drop
(diode
V FORWARD).
The strap SR1 connects - in POS
A - the Address enable (AE) signal
to ground. Therefore, when the MBT
module is used in a CU crate, the
SR1 strap must be placed in pos
A, and when the module is used in
a PU crate, SR1 must be in pos.
B, AE is only generated in a MAP
module.
LED When the +5V is present on the MBT
module the (green) LED is ON.
…0e… 2700A/rt
MT/RST 3:1:2
840610
CR80 BUS STANDARDS L
6 …0f…
CONTROL BUS OH 8-9 The pins A34-43 and B 34-43 of
the J3 connectors in the front magazine
of the PU crate are used by CPU's
and DMA's for interface signals
to the MAP(P and C bus arbitration
and control) via the c̲o̲n̲t̲r̲o̲l̲ ̲b̲u̲s̲.̲
Not a real bus; individual connection
to the CPU and DMA's from the map.
OH 8-10 One module slot (slot 20) is reserved
for the
MAP module. In this slot the J3
connector has 46 control bus connections.
(HBK: Page 3-27)
The PRQ 0-4 Pbus request CPU/MAP
PBG 0-4 Pbus grant MAP/CPU
CRQ 1-4 Cbus request DMA/MAP
CBG 1-4 Cbus grant MAP/DMA
lines, used by the bus arbitrator
to control
the access rights of the main busses,
are parallel bus lines. At each
module pos.- containing a CPU or
DMA - the request and grant connector
pins must be wrapped to the respective
bus line.
The main bus access rights are the
same for
all modules: When a module has just
released its bus control, it have
to wait until all other requesting
modules have finished one control
period.
OH 4 When a module is granted access,
it must issue the TRQ on the bus,
initiating the bus handshaking;
if RS isn't returned within 58
usec's the MAP disables grant, resulting
in a local time out interrupt in
the CPU.
OH 8 When a CPU is granted access it
may issue LBG
and (lock bus grant, common to all CPU's)
which
OH 10 disables the above described time
out function. (For the P-bus only.)
…0e… 2700A/rt
MT/RST 3:1:2
840610
CR80 BUS STANDARDS L
7 …0f…
OH 8 I̲N̲T̲ ̲0̲,̲1̲,̲2̲ with I̲S̲T̲ (L) (interrupt
strobe) is
and notifying the CPU, when it is being
OH 10 interrupted.
OH 10 A̲L̲L̲E̲N̲ (allow enable). The MAP allows
the MIA to issue PUAEN. (From MAP
to MIA). (HBK: Page 3-41):
P̲U̲A̲E̲N̲ (PU adapter enable). Enabling
of adapters (TIA & data channel
I/F in MIA). When LOW, external
I/F's are disabled.
(From MIA to MAP).
E̲C̲L̲ (ext.clear). Input to MAP which
results in master clear on P & C
busses.
P̲F̲L̲ (Power failure look ahead).
Input to MAP from power circuits
when power is going down, which
results in power failure interrupt.
E̲M̲M̲ (ext. maint. mode). Input to
MAP from WD or front panel switch.
…0e… 2700A/rt
MT/RST 3:1:3
840610
DATA CHANNEL L
1…0f…
FUNCTION The data channel is a system element
bus connecting the CU with the PU
and controlled by the MIA.
The bus is a 50 pole twisted pair
flat cable which provides two separate
paths between the units:
OH 1 - Information path (14 lines)
- Interrupt path (3 lines)
(HBK: Page 3-98)
I̲N̲F̲O̲R̲M̲A̲T̲I̲O̲N̲ T̲h̲e̲ ̲I̲n̲f̲o̲r̲m̲a̲t̲i̲o̲n̲ ̲p̲a̲t̲h̲ provides high
speed
P̲A̲T̲H̲ data transfer (1M bytes/sec) in
one byte at a time sequences.
The 40 main bus lines (16 data +
24 addr's) are multiplexed as 5
(times) x 8 bits onto the data channel
like:
OH 2 - Address phase (3 cycles)
- Data phase (2 cycles)
(HBK : Page 3-99)
After each transfer a termination
phase (1 cycle) is entered. (DA:
DATA Acknowledge).
ADDRESS PHASE Addressing may be to a memory location
or to an I/O address in the CU.
The address phase is identified
by the AT (address timing) signal
issued by the MIA in each cycle.
DATA PHASE Always 2 cycles: 1. cycle - lower
byte
2. cycle - upper
byte.
The data phase is identified by
the DT (data timing) signal issued
by the MIA when writing to CU and
by the CIA when reading from CU.
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DATA CHANNEL L
2 …0f…
TERMINATION OH 4 Acknowledge, DA (data ackn.) from
CU, and
PHASE reset of data channel for new
transfer.
W̲r̲i̲t̲e̲ ̲o̲p̲e̲r̲a̲t̲i̲o̲n̲ ̲f̲i̲n̲i̲s̲h̲e̲d̲:̲ DA + error
message (if any error detected)
with DT.
R̲e̲a̲d̲ ̲o̲p̲e̲r̲a̲t̲i̲o̲n̲ ̲f̲i̲n̲i̲s̲h̲e̲d̲:̲ If n̲o̲ ̲e̲r̲r̲o̲r̲s̲
detected, DA transmitted with the
second data cycle.
If error is detected, the data phase
is omitted and DA + error message
with DT is transmitted.
T̲i̲m̲e̲ ̲o̲u̲t̲ ̲t̲e̲r̲m̲i̲n̲a̲t̲i̲o̲n̲:̲ If the addressed
CU doesn't respond within 4 usec,
the MIA issues DA for reset of the
channel.
Example: CIA does never respond
if a parity error is detected in
the addr. phase.
TRANSFER OH 2 HBK: Page 3-99
MODES S̲i̲n̲g̲l̲e̲ ̲t̲r̲a̲n̲s̲f̲e̲r̲ ̲m̲o̲d̲e̲:̲ When only
one word or
byte is to be transferred, all 3
addr. cycles
are traversed.
Termination phase is entered after
o̲n̲e̲ data phase.
OH 3-4 HBK: Page 3-99 and 100
S̲E̲T̲ ̲U̲P̲ ̲a̲n̲d̲ ̲R̲e̲d̲u̲c̲e̲d̲ ̲T̲r̲a̲n̲s̲f̲e̲r̲ ̲m̲o̲d̲e̲:̲
When per-
forming a block transfer (max 64
words), the
address phase is transferred o̲n̲c̲e̲
for s̲e̲t̲t̲i̲n̲g̲ ̲the start addr. in a
address register in the
CIA. A transfer counter (TC) set
up in the
MIA is decremented for each of the
following data phases.
In w̲r̲i̲t̲e̲ operations to memory
locations, the addr. reg. in
the CIA is incremented when the
DA is returned.
In r̲e̲a̲d̲ operations to memory locations,
the addr. reg. is incremented after
each data phase. The termination
phase is entered when the TRANSFER
COUNTER (TC) is zero or when an
error is detected (time out or parity
error when read).
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DATA CHANNEL L
3 …0f…
I̲N̲T̲E̲R̲R̲U̲P̲T̲ OH 1 HBK: Page 3-98
P̲A̲T̲H̲ The CIA receives and stores interrupt
requests from the I/O modules in
the CU crate.
The interrupts are fetched via the
DATA CHANNEL bus interrupt path
by the MIA upon:
1) A MAP command
2) A polling controller in the MIA
addresses the actual CU.
The fetching sequence is like:
1) MIA issues a fetch command in
a 8bit word, specifying the CU
address (+ fetch command). The
word is transmitted as serial
bits on the ID (interrupt data)
line synchroneously with the
IT (interrupt timing) signal.
2) The CIA response is a 8bit serial
word on the ID line synchroneously
with IT as well. The word may
contain the I/O address of a
interrupting device, no interrupt,
or status information.
3) The response is terminated by
the IA (interrupt ackn.) signal
issued synchroneously with the
parity bit of the response word.
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CIA L
4 …0f…
The CU interfacing to the DATA CHANNEL
bus is performed by the CIA module
(channel interface adaptor).
OH 5 Two versions are available:
- one for connection to bus A
- one for connection to bus B
Although physically different they
are functionally equal.
BUS TERMINA- As the DATA CHANNEL bus is designed
for daisy
TIONS chaining of the CU's it has to
be terminated in the last unit
involved. The DTC board (data
channel terminator), therefore,
is placed in the free flat cable
connector on each CIA.
Also the CIA holds the termination
circuits
- in o̲n̲e̲ end - for the A & B busses
in the
CU.
FUNCTIONS The main function of the CIA is
the data transfer between the DATA
CHANNEL bus and the I/O bus.
Towards the DATA CHANNEL bus the
CIA is a slave: The MIA initiates
a transfer by addressing the CIA;
the CIA completes the transfer.
The transfer on the information
path and the interrupt path is explained
as DATA CHANNEL bus functions.
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CIA L
5 …0f…
Towards the I/O bus the CIA is the
master - the only address sourcing
module - and undertakes other support
functions:
- C̲l̲o̲c̲k̲ ̲g̲e̲n̲e̲r̲a̲t̲i̲o̲n̲. The 1 and
2 clocks; 1MHZ and 8 MHZ respectively
are derived from a 16 MHZ crystal
controlled oscillator.
- P̲o̲w̲e̲r̲ ̲s̲u̲p̲e̲r̲v̲i̲s̲i̲o̲n̲. Voltage comperators
monitor the voltages VCC, +12V,
- 12V. A drop in any of these
voltages turns a RED POWER FAIL
INDICATOR on the front panel
ON and cause a PWR failure interrupt
to be issued. The INDICATOR turns
OFF when the MIA has fetched
the interrupt.
BLOCK DIA-
GRAM OH 6 The d̲a̲t̲a̲ ̲c̲h̲a̲n̲n̲e̲l̲ ̲I̲/̲F̲ receives and
transmits the signals on the DATA
CHANNEL bus via t̲r̲a̲n̲s̲f̲o̲r̲m̲e̲r̲ circuits
in order to reduce ground loops
in the system. Dependent on ADDRESS
PHASE or DATA PHASE, the received
bytes are stored in the a̲d̲d̲r̲e̲s̲s̲
̲r̲e̲g̲i̲s̲t̲e̲r̲ or in the i̲n̲t̲e̲r̲m̲e̲d̲i̲a̲t̲e̲
̲d̲a̲t̲a̲ ̲s̲t̲o̲r̲a̲g̲e̲.̲ In SET UP and REDUCED
TRANSFER mode the (first) addr.
is stored in a reduced addr. register
(RAR) which then is incremented
for each data word transferred.
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CIA L
6 …0f…
The d̲a̲t̲a̲ ̲b̲u̲s̲ ̲I̲/̲F̲ controls the traffic
on the I/O bus (as explained under
BUS STANDARDS).
The d̲a̲t̲a̲ ̲b̲u̲s̲ ̲s̲u̲p̲p̲o̲r̲t̲ serves the
power supervision and clock generation
functions.
The i̲n̲t̲e̲r̲r̲u̲p̲t̲ ̲c̲o̲n̲t̲r̲o̲l̲l̲e̲r̲ stores
the interrupt request received from
the I/O bus. Only one INR is stored,
whereupon the INR line is pulled
LOW. When the MIA has polled the
CIA and fetched the interrupt -
without any parity error has been
detected - the INR line is again
released.
SWITCH
SETTING OH 6 The CU No. - SET UP by a DIL switch
- is compared to the CU NO. bits:
- In the first byte received in
all transfer modes on the information
path.
- In the fetch command word on
the interrupt path.
If the bits don't correspond, the
CIA discards the word.
Question How should the switch setting be
on the two CIA modules in the CAMPS
system ?
Answer Black
board…86…1 …02… …02… …02… …02…
…02… …02…
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PRACTICE PU & CU CRATE DI,I,EX,GW
1 …0f…
INTRODUCTION SLG - Describe the lab. exercise for
the students
page (SLG 3:1:4-6).
1-13
SLG - Explain the power and signal
cabling
PAGE
10-13
SLG - Explain how to fill out the WORK
SHEETS:
page The voltages measured on the
different
3-5 busses are noted, and it must
be specified from which PS (R̲i̲g̲h̲t̲
PS = pos 1-4/L̲e̲f̲t̲ PS = pos 22-25)
and from which mains switch (rack
A, B, C) the voltage is sourced.
- Split up into 3 groups:
1 for the CU crate
2 for the PU crates
LAB.WORK - Perform the exercise as described
in the SLG.
- All students must perform STEP 10
and 17. for both a CU crate and
a PU crate.
EVALUATION - Compare the results of the measurements
(Lab.Work Sheets 1-3).
- Discuss the results
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MAP/MIA L
1 …0f…
Functions The MAP/MIA - taken as one unit
- performs most of the essential
PU functions:
- Timing & control
- Authority control of main busses
- Data channel I/F (master)
- Address translation (logical/physical)
- Intra memory DMA (control & mux)
- Interrupt pre-processing
CPU-normal mode
- V24 I/F (MIA)
MAP-maint. mode
- Initialization & Bootstrap
MAP T̲i̲m̲i̲n̲g̲:̲ - The 2 (8MHZ) and 1 (1MHZ)
S̲y̲s̲t̲e̲m̲ ̲c̲l̲o̲c̲k̲s̲ - available for the
PU modules on the main busses -
are generated in a 16 MHZ crystal
controlled oscillator.
- RTC (real time clock) is implemented
as a 47 bit counter, updated
every 1msec
(= approximately 4500 years).
- Fast timer. Every 250 usec all
CPU's are notified (INT lines
= 111 on the control bus) for
decrement of the TMR register
in the CPU (HBK: Page 2-41)
C̲O̲N̲T̲R̲O̲L̲:̲ The M̲C̲(̲M̲a̲s̲t̲e̲r̲ ̲C̲l̲e̲a̲r̲)̲ signal
-
issued on the main busses - is generated
when:
- MC pushbottom on MAP front panel
is activated
- The MAP receives a programmed
CLEAR
- The MAP receives ECL (external
clear) on the control bus
- The +5V has been below 1V. (PWR
OFF/ON)
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MAP/MIA L
2 …0f…
MAP B̲u̲s̲ ̲a̲u̲t̲h̲o̲r̲i̲t̲y̲ ̲&̲ ̲c̲o̲n̲t̲r̲o̲l̲:̲ 5 P-Bus
devices (CPU's) and the Cbus DMA's
may request control of the 2 busses
via the control bus lines PRQ [-4
& CRQ, 1 - 4. The MAP arbitrator
grants the requests cyclically
on the control bus lines PBG [-4
& CBG -4. (Ref. lesson 3:1:1-control
bus).
OH 1 A̲D̲D̲R̲E̲S̲S̲ ̲t̲r̲a̲n̲s̲l̲a̲t̲i̲o̲n̲ ̲(̲M̲A̲P̲P̲I̲N̲G̲)̲;̲
The 16bit CPU
is able to address 64K (2…0e…16…0f… = 65536
64K). This can be either program
or data.
The 2 x 64K "seen" from the CPU
is called a V̲I̲E̲W̲.̲ The address (in
a view) specified from the CPU
is called a l̲o̲g̲i̲c̲a̲l̲ ̲a̲d̲d̲r̲e̲s̲s̲.̲ As
the real (physical) memory capacity
of the CR80 is 16M, a logical to
physical address translation feature
is implemented in the
MAP. The addressing of pages consisting
of 1KWord is translated; addressing
within 1K is direct (physical)
by means of the 10 LSB addr. bits
from a CPU or a DMA.
The memory management part of the
DAMOS in each CPU specifies which
of 64 translation tables in the
MAP has to be used, and the addressing
is performed as follows:
MAP ADDR. - According to the actual view,
the CPU loads its segment register
pair in the MAP with T̲RANSLATION
T̲ABLE (TT) pointers.
- The MAP knows which CPU (or
DMA) is granted bus access;
the respective segment register
pair is used to point out the
TT.
- The logical page (AD 10-15)
specifies the ENTRY in the selected
TT.
- The 14 bit contents of the selected
ENTRY specifies which 1K PAGE
of the entire 16M is to be addressed.
PAGE PROTECTION Each ENTRY of the TRANSLATION
TABLES contents 4 extra bits:
1 parity bit for the lower byte
1 parity bit for the upper byte
2 PAGE PROTECTION bits (PP).
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MAP/MIA L
3 …0f…
The PAGE PROTECTION bits specify
for each 1K PAGE (physical page)
the access rights as:
Protection CPU in CPU
in
Bits System State User
State
(AD17=1) (AD17=0)
̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲
̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲
o̲r̲
̲D̲M̲A̲
̲a̲c̲c̲e̲s̲s̲
0 0 Page absent Page
absent
0 1 Full access Full
access
1 0 Full access Read
only
1 1 Full access No
access
Accessing on absent page generates
a page fault interrupt. This may
be utilized by DAMOS to implement
a "virtual memory":
The interrupt initiates a routine
that rolls any 1K block into memory
from disk.
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MAP/MIA L
4 …0f…
MAP…02……02……02…Drawing on blackboard
ADDR.
TRANSLATION
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MAP L
5 …0f…
IM DMA I̲n̲t̲r̲a̲ ̲m̲e̲m̲o̲r̲y̲
̲D̲M̲A̲:̲ The
CPU may let
the MAP/MIA
transfer
blocks of
data between
memory areas.
F.ex. when
an I/O device
has filled
its memory
area with
incoming
data, the
CPU saves
time by letting
the MAP perform
the transfer
to another
part of memory.
Thus the
I/O device
can continue
receiving
data. The
CPU must
specify data
source and
destination
and set up
translation
tables and
segment registers.
INTERRUPTS I̲n̲t̲e̲r̲r̲u̲p̲t̲ ̲p̲r̲e̲-̲p̲r̲o̲c̲e̲s̲s̲i̲n̲g̲:̲ The MAP
receives and stores interrupts from
the INA bus line in the PU and from
the interrupt scanner (CU interrupts)
in the MIA.
Each interrupt is specified in a
10 bit INTERRUPT VECTOR (IV):
Black 9̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲6̲ ̲ ̲5̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲
̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲[̲
board ̲C̲H̲A̲N̲N̲E̲L̲ ̲U̲N̲I̲T̲ ̲N̲O̲.̲ ̲ ̲ ̲M̲O̲D̲U̲L̲E̲ ̲A̲D̲D̲R̲:̲
̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲
Switch set in CIA Switch set in
I/O modules
Switch set in
CPU's
Part of the MAP RAM area is used
for IV's and tables used in the
interpretion of the vectors. The
tables are accessible by special
privileged interrupt commands during
normal operation and by MAP instructions
(MAINTENANCE COMMANDS) in maintenance
mode.
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MAP L
6 …0f…
Each IV points to a I̲V̲ ̲R̲E̲C̲O̲R̲D̲ specifying
which CPU is to be interrupted (notified)
and the priority of the interrupt.
Black ̲6̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲4̲ ̲ ̲ ̲ ̲3̲ ̲
̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲0̲ ̲ ̲
board IN RECORD: ^̲ ̲C̲P̲U̲ ̲N̲o̲.̲ ̲ ̲^̲ ̲ ̲ ̲ ̲
̲ ̲ ̲ ̲I̲V̲ ̲P̲R̲I̲O̲ ̲ ̲^̲
CPU NO [ - 4 PRIORITY
1-F
CPU NO 7 = COMMON (All CPU's)
A C̲P̲U̲ ̲R̲E̲C̲O̲R̲D̲ is related to each
CPU:
̲4̲ ̲ ̲ ̲ ̲3̲
̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲0̲ ̲
Black CPU RECORD: ^̲ ̲ ̲ ̲^̲ ̲ ̲C̲P̲U̲
̲P̲R̲I̲O̲ ̲ ̲ ̲ ̲ ̲^̲
board
ENABLE/ PRIORITY
0-F
DISABLE
When a CPU has been notified the
MAP sets the CPU PRIO = IV PRIO
and DISABLE. When the CPU is ready
to accept a new interrupt it resets
E/D and loads the current CPU PRIO.
Black
board
INTERRUPT VECTOR IV RECORDS CPU RECORDS
(IV) (IVR) (CPR)
CU MA CPU IV PRIO [[ E/D CPU PRIO
[1
[2
[1 [3
In the interrupt processing the MAP INTERRUPT CONTROL
RAM queues the received IV's and notifies the CPU's
according to the IV priority and the CPU priority (CPU
PRIO must be lower than IV PRIO).
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MAP/MIA L
7 …0f…
INITIALIZATION I̲N̲I̲T̲ ̲&̲ ̲B̲O̲O̲T̲S̲T̲R̲A̲P̲:̲ When MASTER
CLEAR (MC) is generated all modules
enter the self
LED: check routines (BIT). The MAP will
then load
BIT ON all the CPU segment registers
and the transaction tables as
follows:
C̲P̲U̲ ̲S̲E̲G̲M̲E̲N̲T̲ ̲R̲E̲G̲I̲S̲T̲E̲R̲S̲:̲
[ for DATA
1 for PROGRAM
T̲R̲A̲N̲S̲L̲A̲T̲I̲O̲N̲ ̲T̲A̲B̲L̲E̲ ̲N̲O̲.̲ ̲[̲ ̲(̲T̲T̲[̲ ̲ ̲D̲A̲T̲A̲)̲
Logical page [: Phys.page [ A
RAM
module
(ENTRY
no.
0)
with
those
Logical page 63: - - 1 addr's
is
(ENTRY no. 63 required
for
start
up.
T̲R̲A̲N̲S̲L̲A̲T̲I̲O̲N̲ ̲T̲A̲B̲L̲E̲ ̲n̲o̲.̲ ̲1̲ ̲(̲T̲T̲1̲ ̲ ̲P̲R̲O̲G̲R̲A̲M̲
Logical page [-3:Phys.page 3FFC-3FFF 4K
(ENTRY no. [-3) Boot
Strap
Logical page 63: Phys.page 3FFF PROM
in
(ENTRY no. 63) MIA
Then the MAP notifies CPU NO. [
this must be answered within 100
usec, otherwise CPU
No.1 is notified etc.
LED:
NO CPU ON The LED "NO CPU" will be ON until
the first CPU has picked up its
notification descriptor. In this
case IV [. The notified CPU jams
all "one's" onto the address bus
(= highest possible address). This
is via TT1 translated to the highest
physical address
(in the 16M area) which always is
a 4K PROM
in the MIA - containing the DAMOS
BOOTSTRAP LOADER (DAMU).
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MAP/MIA L
8 …0f…
V24 PORT The V̲2̲4̲ ̲I̲/̲O̲ ̲P̲o̲r̲t̲ communicates to
a data terminal in full duplex asynchroneus
mode with a seven bits word length.
The connecting plug is placed on
the MIA front panel (J1).
S1 The baud rate is selectable in a
4bit DIL switch placed on the MIA
(S1).(SCM: Section 4.5.1).
V24 The I/O port may operate in two
modes:
MODES
- NORMAL. The NORM/MAINT. switch
on the MAP front panel in NORMAL.
Communication directly with the
CPU. This is used during BOOTLOAD.
- MAINTENANCE. Switch in MAINT
pos. Communication with the MAP.
(MAP Exerciser program in PROM).
This is used to give commands
to the MAP in OFF line test situations.
DATA T̲h̲e̲ ̲d̲a̲t̲a̲ ̲c̲h̲a̲n̲n̲e̲l̲ ̲I̲/̲F̲ in the MIA
controls the
CHANNEL I/F traffic on the data channel is explained
in lesson 3:1:3.
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MAP/MIA L
9 …0f…
MAP MODULE OH 2 P̲b̲u̲s̲ ̲&̲ ̲C̲b̲u̲s̲ ̲I̲/̲F̲ Buffers/Drivers
to the 2
BLOCK DIAGRAM main busses. The bus communication
is explained in lesson 3:1:1 (BUS
STANDARDS)
M̲E̲M̲O̲R̲Y̲ ̲M̲A̲P̲:̲ Performs the address
translation from logical addresses
received on the main busses to physical
addresses issued on the data channel
via the MIA - or on the Cbus.
D̲M̲A̲ ̲&̲ ̲B̲u̲s̲ ̲I̲/̲F̲:̲ Performs the authority
control of the P & C main busses
via the control bus BUS REQUEST
& BUS GRANT lines. Half of the MAP/MIA
DMA system is placed on the MAP
module, the rest is placed on the
MIA module. When the CPU requests
a block transfer the DMA descriptors,
which specify the source/destination
and block size, is set up, and the
MIA DMA CTRL & data channel I/F
is initiated.
M̲A̲P̲ ̲P̲R̲O̲C̲E̲S̲S̲O̲R̲ ̲(̲M̲P̲)̲:̲ The MP handles
the interrupt processing, DMA set
up, V24 communication, selftest
& start up.
The MP is a 8 bit (bit slice) processor
with uprogram and ucontroller.
A 8 KBYTE RAM is used for temporary
storage
and interrupt processing (IV's etc.).
This RAM is accessible by the CR80
- using special MAP instructions
- as 4KWORD of main memory.
The MP communicates with the MIA
via the bus I/F and the MAP/MIA
bus (MMbus) which is connected to
the lower part of P3 (pins 1-21).
MIA MODULE OH 3 T̲h̲e̲ ̲d̲a̲t̲a̲ ̲c̲h̲a̲n̲n̲e̲l̲ ̲I̲/̲F̲ holds the drivers/
BLOCK DIAGRAM receivers for the 17 bus lines (14
= information path, 3 = interrupt
path). The transfer to the bus is
transformercoupled to provide galvanic
isolation between the system units
(crates). The data & address timing
(DT & AT signals), time out function,
and the data transfer is controlled
by the M̲I̲A̲ ̲C̲T̲R̲L̲ as explained in
lesson 3:1:3 (DATA CHANNEL).
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MAP/MIA L
10 …0f…
T̲h̲e̲ ̲D̲M̲A̲ ̲C̲T̲R̲L̲ is the second half
of the complete MAP/MIA DMA system.
It is used when performing block
transfer (Reduced transfer mode:
Only one address cycle) to/from
the CU. When the address cycle is
finished and the RAR's (reduced
addr. registers in CIA & MIA) are
set up, the transfer is controlled
entirely by the MIA, which releaves
the MAP for other tasks.
I̲n̲t̲e̲r̲r̲u̲p̲t̲ ̲C̲T̲R̲L̲:̲ Performs the polling
of 15 possible interrupting devices
in the CU. When an interrupt request
is picked up the MAP is notified
and the polling stops until the
MAP has read the IMA REGISTER (interupt
module addr.).
P̲R̲O̲M̲:̲ The 4KWORD PROM contains the
system boot load programs (DAMU).
It is addressed on the highest addresses
in the system memory of 16M. Whenever
the MIA detects a PROM address it
issues the DA signal on the channel
bus which resets all modules in
the CU.
S̲I̲O̲ The SIO is the standard serial
V24 I/O interface which provides
the communication between the WD/VDU
and the CR80 or the MAP (MP).
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MAP/MIA L
11 …0f…
MAP OH2 P̲O̲W̲E̲R̲ ̲(̲g̲r̲e̲e̲n̲)̲:̲ Indicates the presence
of
INDICATORS +5V, +/- 12V and that the DC levels
are correct.
T̲E̲S̲T̲ ̲(̲r̲e̲d̲)̲:̲ Indicates that the built-in
test routine is activated. If it
is ON for more than a few seconds
after MC, it indicates an error
in the MAP/MIA modules. Upon successful
execution of all tests, a message
is dumped on the device which is
connected to the V24 port: MAP/BIT:
OK.
If BIT fails - not too serious -
an error code
is printed out.
P̲.̲F̲A̲I̲L̲:̲ Indicates that a power failure
has occured in the PU since the
latest MC.
N̲O̲ ̲C̲P̲U̲:̲ Indicates that NO CPU has
yet answered the notification from
the MAP upon MC. The MAP continues
the notification poll every 100
usec's. In maint.mode the indicator
is undefined.
C̲B̲ ̲D̲M̲A̲:̲ Indicates that the Cbus
DMA in the MAP module is active.
D̲C̲ ̲D̲M̲A̲:̲ Indicates that the DATA
CHANNEL on the MIA module is active.
P̲U̲ ̲D̲I̲S̲ ̲(̲R̲e̲d̲)̲:̲ Indicates that the
adaptor
OH4 modules in the PU are disabled.
I.e. the
TDX bus and the data channel is
disconnected.
The PUAEN signal is LOW.
OH2 IN̲H̲ ̲(̲y̲e̲l̲l̲o̲w̲)̲:̲ Indicates that the
MAP has been
in MAINT. mode since the latest
MC. The maintenance mode sets the
INH (inhibit) signal to prevent
enabling of the PU. However, in
CAMPS, the straps SR1 is mounted,
which makes enabling possible.
H̲A̲L̲T̲ ̲(̲y̲e̲l̲l̲o̲w̲)̲:̲ Indicates that the
Pbus & Cbus are disabled, i.e. no
bus grants will be issued. HALT
is active in MAINT. mode.
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M̲A̲I̲N̲T̲.̲ ̲(̲Y̲e̲l̲l̲o̲w̲)̲:̲ ̲ Indicates that
the MAP is in maintenance mode.
This mode is selected by a front
panel switch, or by the P3 signal
EMM (L).
MIA INDICA- OH3 E̲N̲A̲B̲L̲E̲ ̲(̲Y̲e̲l̲l̲o̲w̲)̲:̲ Indicates - when
ON - that
TORS the PUAEN (High) is enabling the
PU adaptors.
P̲O̲W̲E̲R̲ ̲(̲g̲r̲e̲e̲n̲)̲:̲ Indicates - when
ON - the presence of +5V, +/- 12V.
MAP OH2 D̲I̲S̲/̲E̲N̲ ̲(̲t̲o̲g̲g̲l̲e̲)̲:̲ In the E̲N̲able position
FRONT PANEL and the ALLEN (Allow enable) is HIGH.
Other mo-
SWITCHES OH4 dules may then set PUAEN (PU adaptor
enable).
In the DISable position the PU adaptor
mo-
dules (MIA, TIA) are disabled.
M̲A̲I̲N̲T̲/̲N̲R̲M̲ ̲(̲t̲o̲g̲g̲l̲e̲)̲:̲ In NORMAL position
with the P3 bus signal EMM (enable
maint.mode) High, the MAP operates
with the P & C busses enabled (HALT
LED OFF). (SLM: Section 4.8)
In MAINTENANCE position the MAP
processor enters maint. mode (MAINT.
LED ON) where diagnostic facilities
are available from the V24 Port.
M̲C̲ ̲(̲p̲u̲s̲h̲ ̲b̲u̲t̲t̲o̲n̲)̲:̲ Activates master
Clear. MC on the main busses is
taken LOW and all modules are reset
and execution of BIT's are intiated.
(SLM : Section 4.8)
MIA SWITCH S̲1̲: The ON-BOARD DIL switch selects
the baud
SETTINGS rate for the V24 I/O port.
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DAMU L
1 …0f…
DAMU INIT The DAMOS bootloader program which
is situated in the 4K PROM in the
MIA and activated upon MC in normal
mode, will - as explained in lesson
3:3:1-2, initialization - load the
segment registers with:
[ for DATA
1 for PROGRAM
and the translation tables with:
T̲T̲[̲ ̲(̲D̲A̲T̲A̲)̲
Logical page [: Phys.page [
Logical page 63: Phys.page 1
T̲T̲1̲ ̲(̲P̲R̲O̲G̲R̲A̲M̲)̲
logical page [,1,2,3: Phys.page
3FFC-3FFF
logical page 63: Phys.page
3FFF
QUESTION Where is the data area (phys.addr.)
situated?
Lowest 2K of main memory:
ANSWER Phys.page [ = [-3FF 1K
Phys.page 1 = 3FF - 7FF 1K
QUESTION Where is the program area (phys.addr.)
situated?
ANSWER Highest 4K of the total memory
area
Phys. page [[[[-3FFF = 16K pages
and each PAGE is 1KWORD.
(16x10…0e…3…0f…)x(1x10…0e…3…0f…) = 16x10…0e…6…0f…
DAMU INIT The DAMOS bootloader (with U̲tilities)
- DAMU̲ - contains programs for bootload,
configuration check, and other utilities.
Upon successful BIT in the MAP and
notification of a CPU the DAMU prompts
out on the V24 connected console/VDU:
MAP/BIT:
OK
Black DAMOS BOOTLOADER
(DATE)
Board CPU [
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DAMU L
2
The sign indicates that the DAMU
is ready to execute a command. If
it detects an error in the input
format it prints "?" followed by
an error identification.
Whenever a "ATTN" is sent to DAMU
the currently inputted/executing
command is cancelled - also when
a printout is in progress.
PARITY CHECK To ensure that all memory locations
have the correct parity set it is
recommended always to start with
the SET PARITY program:
ZP CR ;Set parity in PU
(CRATE NO.[)
ZP1 CR ;Set parity in CU
(CRATE NO.1)
The program is n̲o̲n̲ ̲d̲e̲s̲t̲r̲u̲c̲t̲i̲v̲e̲ to
data as long as the checked parity
is correct while:
- # 5555 is written into bad E̲V̲E̲N̲
locations
- # AAAA is written into bad O̲D̲D̲
locations.
The locations with bad parity is
printed out after (each) pass.
UNIT MAPPER UM
The Unit Mapper shows the physical
RAM/PROM memory (4K modules) and
the I/O addresses in a crate.
UM CR (CRATE NO. [)
11111111 11111111/........ .......%
64K RAM 4K PROM
IO:
[1234567 89ABCDEF [1234567 89ABCDFF
........ ......../....1... ......../....
[̲[ - [̲F 1̲[ -
1̲F 2̲[ -
UM 1 CR (CRATE NO.
1)
UM 8 CR (CRATE NO.
8)…86…1 …02…
…02…
…02…
…02…
…02… …02…
…02…
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DAMU L
3 …0f…
I/O COMMANDS OH 1 By means of I/O commands it is possible
to exercise other I/O modules connected
to the system. The "IR" (Input Read)
and "OW" (output Write) commands
have the following format:
IR(CRATE NO.) (MC) (MA) CR
The MODULE COMMANDS (MC) are explained
for the actual module, but for enabling/
disabling of the CU modules the
following is general:
ENABLE MODULE TO I/0 BUS = A…0f…HEX.…0e…
DISABLE MODULE FROM I/O BUS = 8…0f…HEX…0e…
EX:
IR 1A25; ENABLE DISK CTRL #25.
PROGRAMMED The DAMU COMMAND "OC" (OUTPUT CONTROL)
MASTER CLEAR is used as follows:
OC D[[[ [ CR
ADDRESS DATA
IN MAP
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DAMU L
5 …0f…
BOOT After M̲aster C̲lear a boot file which
specifies
COMMANDS and loads the (wanted) program must
be loaded from disk into main memory.
R̲e̲q̲u̲i̲r̲e̲m̲e̲n̲t̲s̲:̲
BFD NO - The B̲F̲D̲ ̲n̲u̲m̲b̲e̲r̲
- found in
the B̲oot
F̲ile D̲irectory
(BFD) for
the disk
- for the
program must
be known.
MODULE - The M̲O̲D̲U̲L̲E̲ ̲A̲D̲D̲R̲E̲S̲S̲ ̲(MA) of the
d̲i̲s̲k̲ ̲c̲o̲n̲t̲r̲o̲l̲l̲e̲r̲
ADDRESS must be known.
CTRL ENABLE - The d̲i̲s̲k̲ ̲c̲o̲n̲t̲r̲o̲l̲l̲e̲r̲ must be e̲n̲a̲b̲l̲e̲d̲
to the I/O bus which is used:
IR 1A (MA) CR
DAMU INFO - Disk data must be specified for
the DAMU. The present specifications
are checked by:
BH BH CR
D̲A̲M̲U̲ ̲D̲E̲F̲A̲U̲L̲T̲:̲
BA ADDR BA 1023 ;CU1 & DEV.23
BU UNIT BU [[[[ ;Drive Unit
NO
BM MEMORY BM [1[[ ;Disk CTRL
memory.
Page 4 =
1[[
(check with
UM)
BT TYPE BT SMD8[ ;Disk type.
Only 2 DISK types are available
for BOOT in the CAMPS system:
SMD 8[; 80 MB
FD500; Floppy disk, 500 sectors.
When the above spec's are correct
the program is boot'ed as follows:
BO BO (BFD NO.) CR ;Load & execute
the
boot file
OR
BE BE (BFD NO.) CR ;Erase memory,
Set
parity
Load & execute
the
boot file.
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MAP MAINTENANCE MODE L
4 …0f…
NRM/MAINT The control bus signal EMM (ext.
maint.mode from Watch Dog) or the
front panel switch NRM/MAINT placed
in the pos. MAINT. will cause:
- All CPU's & STI disabled
- Only active MODULE is MAP DMA.
- HALT, MAINT and INH leds "ON".
- The MAP processor - Map exerciser
(maint. & diagnostic program)
- communicates directly with
the V24 I/O port.
STB I: Section 11, Datasheet 7-7
MAP EXERCISER When the MAP exerciser is initiated,
it prompts "*" on the Maint.Pos.VDU.
Now it is ready for commands.
By means of the MAP exerciser
data may be read/written in memory
locations, I/O devices, segment
registers & translation tables
by the "M" (MOVE) command.
EX:
*M ̲[4 1A25 [[[1
Input read Command One access
Other MAINTENANCE MODE COMMANDS:
* H : HALT
PU
* R : RUN
* S : SINGLE
STEP
* N : NOTIFY
CPU
* C : CPU
SIMULATE
* D : STEP
IN
DMA *
I : IGNORE
(PARITY
&
TIME
OUT)
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DAMU EXERCISES ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ GW,EX,DI
1 …0f…
INTRODUCTION SLG, Describe the lab exercise for the
students
page (SLG 3:2:4-6)
1-3
LAB. WORK Split up into 2 groups. One group
for PU #1 A,
One group for PU # 2.
Perform exercises as described in
the student lab. guide pages 1-3.
EVALUATION Discuss the results of the exercises.
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CPU/CACHE L
1 …0f…
INTRO Extensive use of d̲i̲s̲t̲r̲i̲b̲u̲t̲e̲d̲
̲d̲a̲t̲a̲ ̲p̲r̲o̲c̲e̲s̲s̲i̲n̲g̲ is implemented
in the system:
- All I/O MODULES and DMA MODULES
are intelligent modules, which
perform the time consuming procedures
as handshaking and data exchange
with the peripherals.
- The MAP/MIA modules perform the
time consuming procedures in
the PU:
o Timing and control of the
PU busses
o Data channel communication
o Intra memory DMA.
o Interrupt pre-processing.
This releases the CPU's to perform
"clean processing" in max. possible
time.
CPU's OH 1 Three identical
CPU/CACHE
modules are
included
in the PU.
CPU NO. [ is mounted in slot 13
CPU NO. 1 is mounted in slot 11
CPU NO. 2 is mounted in slot 9
The P bus is reserved for the CPU's,
and a̲l̲l̲ data transfer to/from the
CPU's is via this bus.
The CPU is a general purpose 16
bit (word length) processor with
the ability to address 64 Kword
address or data.
The CPU "looks at" the memory through
the MAP module; i.e. when the CPU
issues a 16 bit (logical) address
on the Pbus. This will be translated
in the MAP to parts of the 16 Mword
physical addresses accessible via
the Cbus and the data channel (This
is handled later on during MAP lesson).
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CPU/CACHE L
2
CPU BLOCK OH 2 C̲P̲U̲: The processing part. Instructions
are
FUNCTIONS fetched from main memory or CACHE
memory
and executed by the CPU.
P̲b̲u̲s̲ ̲I̲/̲F̲:̲ Operates in parallel with
the CPU.
Pbus handshaking is performed
when requested from the CPU.
When bus access is granted the
data transfer to/from MAP/MEMORY
is executed.
C̲A̲C̲H̲E̲: 1 Kword memory containing
copies of
the most recently accessed memory
locations. This to speed up the
system operation because a bus
cycle is avoided whenever the
addressed location is found in
the CACHE.
T̲E̲S̲T̲ ̲M̲E̲M̲O̲R̲Y̲:̲ 4K Prom and 64 words
RAM. The
PROM contains the BIT (built-in
test programs) which are executed
upon MASTER CLEAR. The Pbus I/F
is disabled when the tests are
running.
CPU FUNCTIO- OH 3 D̲a̲t̲a̲ ̲t̲o̲/̲f̲r̲o̲m̲ the CPU is transferred
through
NAL DESCRPT. four unidirectional 16 bit registers:
Writing in AR/ODR is controlled
by the CPU. Writing in the IDR/NINS
is controlled by the CACHE or
the BUS CONTROLLER.
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CPU/CACHE L
3 …0f…
CPU The standard instruction set of
more than
PRINCIPLE 220 instructions is implemented
in approximately 2 KWORD MICROPROGRAM
PROM (each word consists of 64 bits).
Black C̲P̲U̲ ̲P̲R̲I̲N̲C̲I̲P̲L̲E̲:̲
Board
figure
An instruction fetched from the
program area in the memory is via
the input register transferred to
a internal OPCODE register. Here
the operation code (ex: MOV) bits
are used as address pointer to the
uprogram PROM. The execution of
the uprogram is controlled by a
sequencer. The sequencer may change
the initiated sequence (JUMP) when
required from interrupts or feed
back signals resulting from the
program execution.
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CPU/CACHE L
4 …0f…
CPU OH 4 HBK: Section 2.4.4
REGISTERS The CPU contains 8 general purpose
registers
R̲[̲ ̲ ̲R̲7̲ which may be used as
- Accumulators
- Intermediate storage
- Index registers.
Furthermore the CPU contains 9
special regi-
sters, which are described below.
PSW OH 5 P̲R̲O̲C̲E̲S̲S̲O̲R̲ ̲S̲T̲A̲T̲U̲S̲ ̲W̲O̲R̲D̲ ̲R̲E̲G̲I̲S̲T̲E̲R̲
4-7 arithemetic flags set by ALU
8-10 CPU NO (Switch set)
1 Trace flag = trace interrupt.
12 + 14 NOT USED.
EXR OH 4 E̲X̲E̲C̲U̲T̲I̲O̲N̲ ̲R̲E̲G̲I̲S̲T̲E̲R̲:̲
̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲
̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲
BLACK PREVIOUS LEVEL PRIO LEVEL VIEW
BOARD ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲
̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲
LEVEL: To protect process
and program data
against unauthorized
access, all instructions
are divided into
privilege classes:
BLACK USER STATE [ NO Privilege
BOARD 1
. medium Privilege
.
.
SYSTEM STATE 14
15 high Privilege
Level is changed by means of the
MON instruction.
PREVIOUS LEVEL then shows the level
just left.
User or system state is indicated
in bit 11 of the PSW. User state
is application processes.
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CPU/CACHE L
5 …0f…
OH 6 VIEW: Also for protectional reasons
the
memory accessed by the CPU at any
time
is separated in a PROGRAM area and
a PROCESS area (each 64 KWORD).
PROGRAM data is an assembly of instructions
and parameters to perform a certain
task. It is n̲o̲t̲ possible to w̲r̲i̲t̲e̲
into the program area.
PROCESS data is all variables used
during
(description of) program execution.
The VIEW specifies the set of PROGRAM/PROCESS
memory currently used.
PRIO: Indicating the priority of
the current executing process. Most
used for processes in user state;
in system state the LEVEL indicates
the priority. The PRIO is used by
the MAP to decide whether to interrupt
the CPU or not.
BASE OH 4 T̲h̲e̲ ̲B̲A̲S̲E̲ ̲R̲e̲g̲i̲s̲t̲e̲r̲ points to the
first address
OH 7 (the baseline) of the process to
be executed.
All locations in the process are
relative to
the BASE.
MOD OH 4 M̲O̲D̲I̲F̲Y̲ ̲R̲e̲g̲i̲s̲t̲e̲r̲:̲ When an instruction
is
OH 7 preceded by a MOD instruction, the
MOD re-
gister contains a value to be added
to the address references in the
instruction. Most often added to
the BASE register content.
PROG OH 4 P̲R̲O̲G̲R̲A̲M̲ ̲R̲e̲g̲i̲s̲t̲e̲r̲:̲ Points to the
PROGRAM
OH 7 start address, Locations in the
PROGRAM are addressed relative to
PROG.
PRPC OH 4 P̲R̲O̲G̲ ̲+̲ ̲P̲R̲O̲G̲R̲A̲M̲ ̲P̲O̲I̲N̲T̲E̲R̲ ̲R̲e̲g̲i̲s̲t̲e̲r̲:̲
Points to
OH 7 the a̲b̲s̲o̲l̲u̲t̲e̲ (logical) address of
the next
i̲n̲s̲t̲r̲u̲c̲t̲i̲o̲n̲ to be executed.
TMR OH 4 T̲I̲M̲E̲R̲ ̲R̲e̲g̲i̲s̲t̲e̲r̲:̲ The register is
loaded by a
OH 7 load timer instruction (LDT) and
decremented each 250 usec by a fast
timer notification from the MAP.
When it reaches zero and the PSW
timer mask bit is set (bit 15) an
interrupt is generated.
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CPU/CACHE L
6 …0f…
BOUND OH 4 B̲O̲U̲N̲D̲A̲R̲Y̲ ̲R̲e̲g̲i̲s̲t̲e̲r̲:̲
In the privilege
system states
(levels 1 - 15)
the (process)
memory is protected
against writing
for addresses
= BOUND Reg.
Content.
CER OH 4 C̲A̲C̲H̲E̲ ̲E̲R̲R̲O̲R̲ ̲R̲e̲g̲i̲s̲t̲e̲r̲:̲ Updated whenever
a CACHE memory parity error is detected.
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CPU/CACHE L
7 …0f…
CACHE The CACHE principle relies on
the theory that
PRINCIPLE in the program execution one memory
location read by the CPU has a high
probability of being accessed shortly
again. Therefore all access to an
address after the first access don't
have to be done to "the slow main
memory", and don't occupy the main
bus, because it is copied into the
CACHE by the first READ.
CACHE OH 8 The CACHE consisting
of 1 KWORD RAM
is located on
the CPU board.
It is up-
UPDATING dated as "one word at a time" when:
- CPU r̲e̲a̲d̲s̲ a main memory location
which is n̲o̲t̲ ̲y̲e̲t̲ ̲c̲o̲p̲i̲e̲d̲ into
the CACHE.
- CPU w̲r̲i̲t̲e̲s̲ to a main memory location
which i̲s̲ ̲a̲l̲r̲e̲a̲d̲y̲ ̲p̲r̲e̲s̲e̲n̲t̲ in the
CACHE.
- Other CPU's or C-bus DMA's w̲r̲i̲t̲e̲
to a memory location which i̲s̲
̲p̲r̲e̲s̲e̲n̲t̲ in the CACHE. This causes
d̲e̲l̲e̲t̲i̲o̲n̲ of the CACHE copy.
Because the CPU only addresses memory
locations within 2x64K (a view),
the complete CACHE memory has to
be deleted whenever the view is
changed.
TEST Testing of the CPU/CACHE may be
done OFF line
FACILITIES by the BIT (built in test) or on
line by executing disk resident
testprograms.
BIT The built in test (Test memory)
is activated upon master clear:
- The TEST LED (Red) turns ON.
- The Pbus I/F is disabled.
- Test of CPU HW; program control,
data paths, ALU's.
- Test of instruction set. 95%
of program and HW tested.
- Test of Pbus I/F - except tri-state
buffers to Pbus.
- Test of CACHE memory
- Test of CPU clock generator (syncr.
of CACHE, CPU, Pbus I/F).
Any error detected HALTS the CPU,
keeps the TEST led ON, and keeps
the Pbus I/F disabled. Upon success
the TEST led turns OFF.
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CPU/CACHE L
8 …0f…
ON LINE Whenever the CPU reads a CACHE location,
the
TEST (CACHE) CACHE controller checks the parity
on the data. If a (parity) error
is detected, it is signalled to
the CPU (CER register). The CPU
may then disable the CACHE (CACHE
OFF led ON) and perform CACHE testing.
The test sequence is destructive
to data. The CPU may at any time
decide whether to disable the CACHE
or not.
ON LINE When the PU is OFF LINE as regards
the
TEST FROM CAMPS SYSTEM a test program may
be loaded
MAINT.POS. from FD or MMD and run from the
maintenance position. (SLM: Section
4.7.2.1.2)
PROCESSOR M̲A̲S̲T̲E̲R̲ ̲C̲L̲E̲A̲R̲ (MC pushbottom on MAP
module)
START UP causes init. of BIT in all modules.
When the MAP has finished successfully
it "notifies" CPU No [. If this
is N̲O̲T̲ yet ready (= Ackn. to MAP
by fetching the int. vector within
100 Usec) the MAP tries the next
CPU - etc.
The first CPU which answers, jumps
to the highest program area address:
Logical ADDR # EFFF (page 63).
This is a 4K PROM in the
BOOT MIA where the DAMOS BOOT LOADER
(DAMU) is situated.
The DAMU prompts the CPU NO on the
MAINTD.POS.VDU and awaits a command
( ).
OPERATOR C̲O̲M̲M̲A̲N̲D̲S̲:̲
COMMANDS Black ZP; Set parity in PU ([) memory
Board ZP1; - " - CU (1) - "
-
BH; List DAMU default B̲OOT config.
BA 1023 (Disk CTRL A̲DDR.)
BU [[[[ (Disk drive U̲nit NO)
BM [1[[ (Disk CTRL M̲emory addr.)
BT SMD[ (Disk T̲ype.)
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840610
CPU/CACHE L
9 …0f…
Black These values may be changed
Board Ex (CAMPS):
BA 1[25
BM 14[
The disk CTRL must be enabled to the
I/O data bus which is connected to the
testing CPU:
IR 1A25 ;I̲nput R̲ead DEV.
2̲5̲
CPU/CACHE The CPU/CACHE test is started by:
TEST
BO bfd.no.
Or alternative:
BE bfd.no. ;same as BO but
all memory is erased
and parity is reset.
TEST CPU [ 1 2 ;Run test progr.on
all 3 CPU's.
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840610
RAM L
1 …0f…
FUNCTIONS The CR8016 M is a RAM module with
a storage capacity of up to 512
Kword (16 bits + 2 parity bits).
DUAL BUS It interfaces to both the Pbus and
to the
VERSION Cbus in the PU. It must n̲o̲t̲ be used
in the CU because it doesn't contain
the required power combine circuit.
Pipeline registers (data latches)
are implemented to reduce access
time and to provide simultaneous
access from both busses.
BLOCK
DIAGRAM OH 1 I̲n̲p̲u̲t̲ ̲d̲a̲t̲a̲ ̲r̲e̲g̲i̲s̲t̲e̲r̲s̲:̲ 18 bit latches
(16 data + 2 parity) for temporary
storage of data to be written into
the memory. The bus cycle may be
terminated before the data actually
i̲s̲ loaded into the RAM CHIP.
O̲u̲t̲p̲u̲t̲ ̲d̲a̲t̲a̲ ̲r̲e̲g̲i̲s̲t̲e̲r̲s̲:̲ 18 bit latch
with 3-state output. Data is fetched
from the RAM and placed in the latch
at the beginning of a (bus) read
cycle, so that a new access can
be initiated from the other port
before this bus transfer is terminated.
A̲D̲D̲R̲ ̲R̲E̲C̲/̲b̲u̲f̲f̲e̲r̲s̲ ̲&̲ ̲c̲o̲m̲p̲e̲r̲a̲t̲o̲r̲:̲ The
ADDRESS RECEIVERS buffers and latches
the address lines A[-A15. A[ - A6
+ A14 = ROW. A7 A13 + A15 COLUMN).
In a jumper field, straps are set
according to type of memory chips
used. The latch output is then used
for RAM area selection (CAS = column
addr. select). The bus transfer
may be terminated when the address
is latched into the rec/buffers.
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840610
RAM L
2 …0f…
S̲w̲i̲t̲c̲h̲ ̲c̲i̲r̲c̲u̲i̲t̲:̲ 2 DIL switches for
defining the module addr. and upper
& lower limit for disable function.
R̲A̲M̲ ̲c̲o̲n̲t̲r̲o̲l̲:̲The authority control
determines the access to the RAM
from the IN/OUT register at the
Pbus O̲R̲ the Cbus O̲R̲ from the refresh
circuit.
The timing and sequence control
is generating all the strobe and
control signals.
The refresh circuit keeps the dynamic
RAM "alive" by addressing the ROW
(A[-6) every 15 usec.
The timing for the complete board
is derived from a 16 MHZ oscillator.
SWITCH BLACK SLM: Figure 4.5.1-9
SETTING BOARD
The module "START"
address is set
by in the
"S2" switch
DISABLING/ENABLING OF MEMORY PARTS
are performed by the "S1" switch.
In CAMPS no disabling is performed.
MEMORY CONFIG. By means of the DAMOS bootloader
(DAMU) it is
CHECK possible to check the actual
configuration of the PU and the
CU.
UM; The PU config. is written
UM1; The CU - " -
BLACK RAM:
BOARD 11111111 11111111 / ........ ........
Each 4 K Absent or Disabled
64 K
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840610
MAP EXERCISES GW,EX,DI,I
1 …0f…
INTRODUCTION SLG, Describe the lab. exercise for the
students
page (SLG 3:3:4-6)
1-2
Split up into two groups
Group No. 1: PU # 1
Group No. 2: PU # 2
LAB. WORK Perform the exercise as described
in the SLG.
EVALUATION Discuss the observations during
the Lab. exercise in the training
room and after the lab. exercise
in the classroom.
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840610
LTU/LIA L
1 …0f…
LTU FUNCTIONS The L̲ine T̲ermination U̲nit (LTU)
is an interface module between the
CR80 and four V24 communication
lines. In the CAMPS system four
LTU's are placed in the channel
unit (CU). (The LTU is a so called
"I/O MODULE".)
OH 1 Functionally it is separated in
two parts:
1. I/O module ( uprocessor controlled)
2. CR80 memory module; may be placed
anywhere in the 1M CU address
area.
Also included is a bus switch circuit
for switching (both parts) between
I/O bus A and I/O bus B.
Data transfer between the CR80 and
the
uprocessor system is via a shared
RAM memory area.
Black
Board MAIN SYST.
MEMORY RAM PROM
8 K
16K bytes
CR 80
MAIN SHARED uproc.
MEMORY RAM
8K
16K bytes
LTU
Part of the LTU RAM area is hidden
for the CR80; this is containing
the LTU application program ( uprocessor
program).
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LTU/LIA L
2
…0f…
The application program must be
"down loaded" from CR80 upon system
initialization.
DOWNLOAD The usystem controls the download
procedure by means of a bootloader
which is located in a PROM. The
PROM also contains a BUILT-in TEST
(BIT).
The BIT is initiated by POWER UP.
When the LTU is enabled towards
one of the I/O busses and the BIT
has finished successfully, then
the uproc. reports ready to the
CR80.
The CR80 loads the application program
into the shared RAM.
The uproc. checks for transfer errors,
and when OK it moves the program
to the uproc.
SYSTEM RAM.
The uproc. starts from program location
[.
BLOCK
DIAGRAM OH 2 B̲U̲S̲ ̲I̲/̲F̲:̲ The bus I/F's for the I/O
bus A and the I/O bus B are identical
but physically they are separated;
a failure in one port doesn't affect
the other port.
The bus I/F holds the main bus line
drivers/receivers and the LTU is
"disabled" against the bus when
they are in the high impedance state.
During power up/down both bus I/F's
are disabled.
B̲u̲s̲ ̲s̲e̲l̲e̲c̲t̲o̲r̲.̲ Each LTU module must
be assigned an I/O ADDRESS. This
is set up in 6 bits (contact no.
1-6) in the DIL switch S1, and is
compared to the bus address lines
A[-5
S1 (Addr's 0-63). In CAMPS the LTU
addr's are
I/O ADDR. 7,8,B,D. Whenever the LTU receives
an ENABLE/RESET
ENABLE LTU command f̲r̲o̲m̲ ̲o̲n̲e̲ ̲o̲f̲ ̲t̲h̲e̲ ̲I̲/̲O̲ ̲b̲u̲s̲s̲e̲s̲,
the bus I/F against this bus is
enabled. Both bus I/F's can never
be enabled at the same time.
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840610
LTU/LIA L
3
…0f…
I̲/̲F̲ ̲C̲O̲N̲T̲R̲O̲L̲:̲ This block controls
the traffic between the (shared)
RAM memory and the main (I/O) bus-
and holds the interrupt logic.
When the LTU is accessed as a part
of the main memory (shared RAM)
the bus address bits A1[ - A19 are
compared to the switch setting.
S2 & S3 In DIL switch "S2" and "S3":
S2 S3
MEM.ADDR. 1 2 3 4 1 2 3 4 5 6
1K 2K 4K 8K 16K 32K 64K 128K 256K 512K
̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲
̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲
A1[ A19
The switch setting selects the start
address of the 1M memory area in
the CU. In CAMPS 8K (words) shared
RAM's are used, why the three LSB
(in "S2") don't have influence.
S1 The two interrupt priority bits
are set up in
INTERRUPT DIL switch S1 contact no. 7 & 8.
The MODULE
CODE. ADDRESS is set up by contact
no. 1-6.
When addressed, the I/F control
handles the access to the shared
RAM:
- Handshaking between the PU and
the uprocessor.
- Loading and updating the address
counter.
- Parity control.
C̲o̲m̲m̲u̲n̲i̲c̲a̲t̲i̲o̲n̲ ̲R̲A̲M̲ (shared RAM).
Half of the complete LTU RAM area.
In CAMPS 16K x 9 bits ( 8K words
seen from the CR80)
Communication is between CR80 &
uprocessor.
P̲R̲O̲G̲R̲A̲M̲ ̲R̲A̲M̲:̲ (SYSTEM RAM).
Half of the complete LTU RAM area.
16K x 9bits.
All RAM memory is dynamic RAM which
have to be refreshed every 2 msec.
This is handled by the uprocessor.
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840610
LTU/LIA L
4 …0f…
B̲O̲O̲T̲ ̲P̲R̲O̲M̲:̲ Holds the diagnostic
and bootload programs. Initiated
when power up or when a bootload
command is received from the PU.
C̲P̲U̲:̲ Standard zilog Z80 uprocessor.
Controls the communication between
the I/O ports and the shared RAM
memory.
Timer circuitry provides a 4 MHZ
clock and - under software control
- the baud rate control of the I/O
port.
S̲I̲O̲: 2 standard dual ported UARTS.
The four serial I/O ports are via
V24 drivers/receivers (+/-12V),
the P3 connector, a flat cable,
and the L̲ine I̲nterface A̲daptor (LIA)
the communication path's between
peripheral devices and the uprocessor.
P̲I̲O̲:̲ The 8255 PIO has 3 ports x
8 bits for parallel input/output
communication. These ports are used
during internal LTU testing and
to provide more status signals for
the V24 lines (SIO's).
Also, when the LTU is used as the
watch dog processor, the bootload
to the system RAM takes place via
the PIO.
INDICATORS OH 2 P̲O̲W̲E̲R̲ ̲(̲g̲r̲e̲e̲n̲)̲:̲ Indicates - when
ON - the presence of +5V +/-12V.
Power is supplied from both main
busses (Power combine). In case
of a power drop on one bus, the
supply from the other bus is sufficient
for proper operation.
POWER The three voltages are supervised
on the
SUPERVISION board. If one of them drops out
(+5 4,85V) a POWER CLEAR is generated:
The LED turns OFF and both bus I/F's
are disabled.
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840610
LTU/LIA L
5
…0f…
T̲E̲S̲T̲:̲
STEADY ON: BIT is being executed.
FLASHING: An error has been detected
STEADY OFF: No errors detected
B̲U̲S̲ ̲A̲:̲ The bus I/F towards bus A
is enabled.
B̲U̲S̲ ̲B̲:̲ The bus I/F towards bus B
is enabled.
B̲O̲O̲T̲L̲:̲ Indicates bootload mode.
This mode may be entered when;
- A bootload command is received
from the PU.
- A parity error is detected by
the I/F control.
LIA-N OH 3 The L̲ine
I̲nterface
A̲daptor (LIA)
provides
the
FUNCTIONS interface between the LTU V24 I/O
ports and four serial communication
channels - each with a DB25 cannon
connector.
There is no active components on
the LIA board; the communication
lines are distributed from the 64
pole flat cable connector (P1) through
4 strap areas to the back panel
connectors.
STRAPS The strapping for the different
applications in the CAMPS system
is hardwired - so, the LIA modules
must n̲o̲t̲ be interchanged!
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840610
WATCHDOG L
1
…0f…
WD MAIN - Monitoring and control of the
CAMPS
FUNCTIONS system configuration.
OH 1 - Supporting communication between
the PU's and the maintenance
position VDU/MSP.
According to status into which is
collected from the different system
crate assemblies the WD provides:
- switching of the PU systems (Disconnect
active PU/notify stand by PU).
According to commands from the PU
the WD provides:
- switching of the TDX system
- disabling "take ownership" (enable)
from a PU to the CU modules.
Switches on the TDX and CU modules
override the WD control
P.U. OH 1 P̲r̲o̲c̲e̲s̲s̲o̲r̲ ̲U̲n̲i̲t̲ ̲C̲o̲m̲m̲u̲n̲i̲c̲a̲t̲i̲o̲n̲:̲
Both the active and the standby
PU regularly transmits status messages
to the WD via the WDCC bus (watchdog
control channel: V24
WDCC bus channel, 2400 baud).
- The STANDBY PU reflects PU condition
and whether or not it is able
to "take over".
- The ACTIVE PU reflects PU condition
and reports "STILL ALIVE".
- WD supported communication between
the PU and the maint. pos. VDU/MSP
is also via the WDCC bus.
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840610
WATCHDOG L
2
…0f…
CCB OH 1 Via the configuration control bus
(CCB the …02…WD communicates with the
crate configuration adaptors (CCA's)
in the PU, CU and TDX crates.
The bus is a 16 lead twisted pair
flat cable which is daisy chain
connected to all crates in the system.
Due to requirements for galvanic
isolation between the crates, the
signals are transferred via optical
couplers in all modules (except
in the WD connection). The power
(+12V) for the opto drivers is supplied
from the WD.
The bus communication is asynchroneous
(serial) at a speed of 4800 baud;
7 bits words.
PU M & C OH 2 P̲U̲ ̲m̲o̲n̲i̲t̲o̲r̲i̲n̲g̲ ̲&̲ ̲c̲o̲n̲t̲r̲o̲l̲:̲
Black - supervision of DC voltage levels
board - monitoring of ALLOWENABLE (ALLEN)
from MAP
- monitoring of PU ADAPTOR ENABLE
(PUAEN) from MIA
- monitoring of 2 crate temperatures
- command Disable PU (DISPU) to
MIA
- issue of Master clear signal
(ECL) to MAP
- issue of Maint. mode signal (EMM)
to MAP
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840610
WATCHDOG L
3
…0f…
CU M & C OH 3 C̲U̲ ̲m̲o̲n̲i̲t̲o̲r̲i̲n̲g̲ ̲&̲ ̲c̲o̲n̲t̲r̲o̲l̲:̲
- Supervision of dualized power
supply voltages
- Monitoring 2 crate temperatures
- Monitoring of the TAKE OWNERSHIP
AUTO CONTROL (TOA) (ALL FRONT
PANEL SWITCHES of the Channel
Unit Control Panel (CUCP) are
in pos. AUTO.)
- Issue of A bus disable (DISA)
- Issue of B bus disable (DISB)
The two latter commands will only
have effect when the CUCP switches
are in AUTO position.
TDX M & C T̲D̲X̲ ̲C̲r̲a̲t̲e̲ ̲m̲o̲n̲i̲t̲o̲r̲i̲n̲g̲ ̲&̲ ̲c̲o̲n̲t̲r̲o̲l̲:
The CCA on the BSM-X MODULE in the
TDX UNITS has some more functions
than the standard version CCA; a
bus switch function is implemented.
Therefore this module called a BUS
SWITCH MODULE for the TDX system
(BSM-X).
OH 4 A̲l̲l̲ ̲T̲D̲X̲ ̲U̲N̲I̲T̲S̲:̲
- Supervision of the DC voltages
- monitoring of the AUTO/MAN switch
setting
- supervision of the crate temperature
- issue of bus switch command.
A̲d̲d̲i̲t̲i̲o̲n̲a̲l̲ ̲i̲n̲ ̲T̲D̲X̲ ̲U̲N̲I̲T̲S̲ ̲w̲i̲t̲h̲ ̲T̲D̲X̲-̲c̲o̲n̲t̲r̲o̲l̲l̲e̲r̲
- Monitoring of controller status
- monitoring of the bus clock (TS)
- monitoring of the CTRL-bus outlet
power supply (FS).
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840610
WATCHDOG L
4
…0f…
WATCHDOG The WATCHDOG unit consist of three
modules
UNIT housed in a single bus minicrate
with integrated Power supply and
fan unit.
Black T̲h̲e̲ ̲t̲h̲r̲e̲e̲ ̲m̲o̲d̲u̲l̲e̲s̲:̲
board WPU: W̲atchdog CP̲U̲ (= LTU)
OH5 WCA: W̲atchdog C̲PU A̲daptor.
CCBA: C̲rate C̲onfiguration B̲us A̲daptor.
T̲h̲e̲ ̲P̲o̲w̲e̲r̲ ̲s̲u̲p̲p̲l̲y̲:̲
OH 6 The mains supply is fused with 5A
(250V) and the output voltages are
adjusted to:
+ 5,45V (red wire)
+12,7V (green wire)
Ground (blue wire)
WPU The Watchdog CPU is a modified LTU
module. The main bus interfaces
(Bus A I/F & Bus B I/F are not used
in the WD configuration. All communication
is via the PIO and the SIO.
The complete RAM memory is used
for application software (16K).
INIT When initialized (power up/reset)
the BIT - resident in the LTU PROM
- is executed; the TEST led is ON.
Upon a successful pass of the BIT
the boatload program is executed.
BOOTLOAD The bootload procedure differs from
that in the standard LTU version:
- The application program is resident
in a 16K EPROM memory placed
on the WCA board.
- The bootloader addresses the
EPROM via PIO port A, and fetches
the data via PIO port B.
- When the program is loaded successfully
the BOOTL Led turns OFF.
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840610
WATCHDOG L
5
…0f…
WCA W̲A̲T̲C̲H̲D̲O̲G̲ ̲C̲P̲U̲ ̲A̲D̲A̲P̲T̲O̲R̲:̲ The WCA constitutes
the interface between the WPU and:
OH 7 - The WDCC 1 & 2 (WD Control Channels
to the PU's)
- The CCB (config. control bus)
- The Maintenance position VDU
- The Maintenance position printer.
A failsafe circuit always monitors
the WPU "ALIVE" status. The WPU
must update the failsafe circuit
at least every 1 sec; If not, the
CCB is disconnected (tx line)
The WCA holds the WPU software in
a 16K (bytes) EPROM.
The connection to the motherboard
in the crate are only power supply
wires.
From the CCB (optionally a switch
on the CCBA) an external BOOT command
may be received. This is transferred
to the WPU via the control bus.
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840610
WATCHDOG L
6
…0f…
CCBA C̲O̲N̲F̲I̲G̲U̲R̲A̲T̲I̲O̲N̲ ̲C̲O̲N̲T̲R̲O̲L̲ ̲B̲U̲S̲ ̲A̲D̲A̲P̲T̲O̲R̲:̲
The CCBA is a switch unit inserted
between the WCA and the CCB (bus).
Relays on the PCB may disconnect
the WD TX line of the CCB:
- M̲A̲N̲U̲A̲L̲:̲ A panel switch DISABLE/ENABLE
disconnects the TX line in the
disable position. This is a useful
feature to prevent WD interference
when & D programs are executed.
- A̲U̲T̲O̲M̲A̲T̲I̲C̲:̲ When the DISABLE/ENABLE
switch is in the ENABLE position,
ther AUT ENB signal keeps the
TX line connected. The AUT ENB
signal is updated by a 1,43 sec.
one shot on the WCA board.
ENABLE LED Whenever the TX line is enabled
the ENABLE Led on the front panel
is turned ON.
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840610
CCA L
1
…0f…
CCA The C̲rate C̲onfiguration A̲daptor
(CCA) is
FUNCTIONS the monitoring and communicating
module in the watchdog system which
is placed in the PU's and the CU.
It is connected to the Watchdog
unit via the CCB (bus) and is a
slave module of the WPU.
OPERATION Communication with the WD is in
8 bit (serial) words with the speed
of 4800 baud via the CCB (bus).
E̲a̲c̲h̲ communication cycle comprises
four bus
OH 1 bus transmissions:
1. The WD transmits ADDR
(7 Addr.bits + Addr. identifier)
2. The WD transmits COMMAND (7 command
bits + CMMD identifier)
3. The CCA transmits DATA (8 data
bits)
4. The CCA transmits the command
word just received, for check
of transmission (8 status bits).
Minimum three of the above communication
cycles are necessary to access a
CCA:
1. The WD transmits a POINTER; The
5 LSB of the COMMAND word define
the use of the following data
word(s).
2. The WD transmits the actual DATA;
the command word specifies select
A/D input NO, digital input etc.
3. S̲T̲R̲O̲B̲E̲.̲ The COMMAND word (MSB
= 1) loads the DATA into the
"POINTED" register.
AART OH 2 The communication control in the
CCA is provided by an A̲D̲D̲R̲E̲S̲S̲A̲B̲L̲E̲
̲A̲s̲y̲n̲c̲h̲r̲o̲n̲e̲o̲u̲s̲ ̲R̲e̲c̲e̲i̲v̲e̲r̲/̲T̲r̲a̲n̲s̲m̲i̲t̲t̲e̲r̲
(AART). Each time an AART recognizes
its own address - which is set up
in a 6 bit DIL switch (5 bits are
used
S1 max. 32 CCA addr's possible) - it
converts the following word to a
parallel word.
…0e… 2700A/rt
MT/RST 3:4:3
840610
CCA L
2
…0f…
BUSY LED Each time a STROBE is received in
a CCA the
B̲U̲S̲Y̲ ̲L̲E̲D̲ (yellow) on the front panel
is turned ON for about 100 msec's.
POWER LED When +/-12V is supplied to the CCA,
the POWER led (green) on the front
panel is ON.
OH 2 Sixteen analog channels are multiplexed
to the A/D converter input. This
is for sensing the crate voltages.
FRONT PANEL
MEASURING The crate voltages and the reference
voltage
POINTS and offset voltage for the A/D
converter are connected to measuring
points on the CCA front panel.
The U̲r̲e̲f̲ may be adjusted (+10,24V)
by the R33 and R109 potentiometers.
R33 is for course adj.
R109 (front panel accessible) is
for fine adj.
The o̲f̲f̲s̲e̲t̲ may be adjusted by the
R47 potentiometer (V offset = 2,56V).
RESET SWITCH A switch on the front panel will
- in the reset position - set the
CCA to a pre-defined state:
WD monitoring of voltdages and
temperature inputs "seems to
be OK" independently of the actual
situation.
…0e… 2700A/rt
MT/RST 3:4:3
840610
CUCP L
3
…0f…
CUCP The C̲hannel U̲nit C̲ontrol P̲anel (CUCP)
is a
FUNCTIONS switch unit which is placed in the
front magazine of the CU crate.
It controls
OH 3 the bus disable inputs to the I/O
modules in the CU:
ALLOW ENABLE OH 4 If any of the two "DIS/AUTO" switches
are
FROM WD in pos. "AUTO", then a COMMAND SIGNAL
from the WATCHDOG may ALLOW ALL
I/O MODULES (at the same time) to
be ENABLED to the respective I/O
BUS (BUS A or BUS B).
NOT ALLOW If any of the two DIS/AUTO switches
are
ENABLE in pos. "DIS", then the I/O MODULES
FROM WD may n̲o̲t̲ be A̲L̲L̲O̲W̲E̲D̲ to be ENABLED
to the respective I/O Bus (BUS A
or BUS B) by a COMMAND SIGNAL f̲r̲o̲m̲
̲t̲h̲e̲ ̲W̲A̲T̲C̲H̲D̲O̲G̲.
MANUALLY But - if any of the nine "AAEN/AUTO/BAEN"
ALLOW ENABLE switches are in pos. "AAEN" or pos.
"BAEN", then the corresponding I/O
MODULES are ALLOWED to be ENABLED
to the respective I/O Bus (Bus A
and BUS B).
LEDS SLM: TABLE 4.5.2-2
…0e… 2700A/rt
MT/RST 3:4:4-6
840610
M & D TEST MAP & RAM EX,I,GW
1
…0f…
INTRODUCTION SLG, Describe the lab. exercises for
the students
page (SLG 3:4:4-6).
1-2
Split up into two groups
Group No. 1: PU # 1 and SMD
Group No. 2: PU # 2 and FLOPPY DISK
DRIVE
LAB. WORK Perform the lab. exercises as described
in the SLG.
EVALUATION Discuss the observations during
the lab.exercises in the training
room and after the lab. exercises
in the classroom.
…0e… 2700A/rt
MT/RST 3:5:1-3
840610
PROGRESS TEST L
1
…0f…
PROGRESS TEST State before start:
TEST (OH1-4)
Open book test.
Number of questions: 20
Time allowed: 60 min.
ANSWERS TEST Instructor corrects answers.
OH5-7 Answers are presented and explained.
R̲e̲f̲e̲r̲e̲n̲c̲e̲s̲:̲
TEST Q1 : Lesson 3:1:2:OH8-10
Q2 : Lesson 3:1:2:OH8 & 10
Q3 : Lesson 3:1:2:OH6-7
Q4 : Lesson 3:1:3:OH5-6
Q5 : Lesson 3:1:1:OH6
Q6 : Lesson 3:2:1-2:OH1,3:3:1:OH6
Q7 : Lesson 3:2:1-2:OH1
Q8 : Lesson 3:2:1-2:OH1
Q9 : Lesson 3:2:1-2: page
4
Q10: Lesson 3:3:3:OH1
Q11: Lesson 3:2:3:page 1
Q12: Lesson 3:2:1-2: page
4
Q13: Lesson 3:3:3: page 2
Q14: Lesson 3:2:1-2: page
12
Q15: Lesson 3:2:1-2: page
4
Q16: Lesson 3:2:1-2: page
12
Q17: Lesson 3:2:3: page 2
Q18: Lesson 3:1:2:OH6, 3:4:1:page
2-3
Q19: Lesson 3:1:1:OH2
Q20: Lesson 3:4:1: page 1
…0e… 2700A/rt
MT/RST 3:5:4-6
840610
M & D TEST CPU/CACHE & LTU EX,I,GW
1
…0f…
INTRODUCTION SLG, Describe the lab. exercises for
the students
page (SLG 3:5:4-6).
1-2
Split up into two groups
Group No. 1: PU # 1 and FLOPPY DISK
DRIVE
Group No. 2: PU # 2 and SMD
LAB. WORK Perform the lab. exercises as described
in the SLG.
EVALUATION Discuss the observations during
the lab.exercises in the training
room and after the lab. exercises
in the classroom.
2700A 3:1:4-6
NEN/840610
1
STUDENT LABORATORY GUIDE
CAMPS
E̲X̲E̲R̲C̲I̲S̲E̲ ̲N̲O̲.̲ ̲1̲
OBJECTIVE: Enable the students to understand how the
PU-CU crates are built up, how the modules
are placed in the crates, and how the modules
are interconnected. The students will learn
how to check the power supplies.
REFERENCE: Site Level Maintenance Manual (SLM), SLG,
section 3:1:4-6 p. 7-13, and LAB WORK SHEET
1-3, SLG section 3:1:4-6 p. 3-5.
1. Switch OFF mains power to the PU rack.
2. Check the numbering of the cables to the crate
according to (ref. p. 11-13).
3. Disconnect all cables to the PU crate.
4. Check module positioning according to (ref.
p. 7-8).
5. Remove all modules from the PU crate.
6. Remove the PU crate from the rack.
7. Mount the PU crate in the rack.
8. Tilt the rear magazine for access to the back
planes.
9. Connect mains power and switch on the power
supplies.
10. Fill in the LAB WORK SHEETS 1-2.
2700A 3:1:4-6
NEN/840610
2
STUDENT LABORATORY GUIDE
CAMPS
11. Switch OFF mains power to the PU crate.
12. Check the switchsetting of all the dismounted
modules. Ref.: Site Level Maintenance Manual,
section 4.5.1 and 4.5.2.
13. Mount all the modules in the PU crate according
to ref. p. 7-8
14. Connect the cables to the modules as originally
connected. (Ref. p. 11-13).
15. Connect mains power and switch ON the power supplies.
16. Check that the power indicators on all the modules
are ON (green), and that all BIT (built-in-test)
indicators are OFF (red).
17. Fill in the LAB WORK SHEET 3.
2700A 3:1:4-6
NEN/840610
3
STUDENT LABORATORY GUIDE
CAMPS
L̲A̲B̲ ̲W̲O̲R̲K̲ ̲S̲H̲E̲E̲T̲ ̲1̲
D̲C̲ ̲V̲O̲L̲T̲A̲G̲E̲ ̲M̲E̲A̲S̲U̲R̲I̲N̲G̲
P̲U̲ ̲C̲R̲A̲T̲E̲ ̲F̲R̲O̲N̲T̲ ̲M̲A̲G̲A̲Z̲I̲N̲E̲ ̲(̲J̲1̲ ̲&̲ ̲J̲2̲)̲
̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲
̲ ̲ ̲
^ ^ ^ R̲E̲S̲U̲L̲T̲
^
^ VOLTAGE ^ MEAS.POINT ^ P BUS ^ C BUS
^
^̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲^̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲^̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲^̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲
̲ ̲^̲
^ ^ ^ ^
^
^ +5V ^ A40, 41 ^ ^
^
^ ^ B40, 41 ^ ^
^
^ ^ (RED) ^ ^
^
^̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲^̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲^̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲^̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲
̲ ̲^̲
^ ^ ^ ^
^
^ GND (+5V) ^ A42, 43 ^ ^
^
^ ^ B42, 43 ^ ^
^
^ ^ (BLACK) ^ ^
^
^̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲^̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲^̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲^̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲
̲ ̲^̲
^ ^ ^ ^
^
^ +12V ^ A14, B14 ^ ^
^
^ ^ (YELLOW) ^ ^
^
^̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲^̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲^̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲^̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲
̲ ̲^̲
^ ^ ^ ^
^
^ -12V ^ A12, B12 ^ ^
^
^ ^ (GREEN) ^ ^
^
^̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲^̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲^̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲^̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲
̲ ̲^̲
^ ^ ^ ^
^
^ +24V ^ A11 ^ ^
^
^ ^ (WHITE) ^ ^
^
^̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲^̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲^̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲^̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲
̲ ̲^̲
^ ^ ^ ^
^
^ -24V ^ B11 ^ ^
^
^ ^ (ORANGE) ^ ^
^
^̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲^̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲^̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲^̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲
̲ ̲^̲
^ ^ ^ ^
^
^ GND (+12V, ^ A13, B13 ^ ^
^
^ -12V,+24V, ^ (BLUE) ^ ^
^
^ -24V) ^ ^ ^
^
^̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲^̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲^̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲^̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲
̲ ̲^̲
…86…1 …02… …02… …02… …02… …02… …02…
…02… …02… …02…
2700A 3:1:4-6
NEN/840610
4
STUDENT LABORATORY GUIDE
CAMPS
L̲A̲B̲ ̲W̲O̲R̲K̲ ̲S̲H̲E̲E̲T̲ ̲2̲
D̲C̲ ̲V̲O̲L̲T̲A̲G̲E̲ ̲M̲E̲A̲S̲U̲R̲I̲N̲G̲
P̲U̲ ̲C̲R̲A̲T̲E̲ ̲R̲E̲A̲R̲ ̲M̲A̲G̲A̲Z̲I̲N̲E̲ ̲(̲J̲3̲)̲
̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲
̲ ̲ ̲
^ ^ ^
^
^ VOLTAGE ^ MEAS. POINT ^ RESULT
^
^̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲^̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲^̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲
̲ ̲^̲
^ ^ ^
^
^ +5V ^ a 30, 31, 32 (RED) ^
^
^ ^ c 30, 31, 32 ^
^
^̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲^̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲^̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲
̲ ̲^̲
^ ^ ^
^
^ GND (+5V) ^ a 28, 29 (BLACK) ^
^
^ ^ c 28, 29 ^
^
^̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲^̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲^̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲
̲ ̲^̲
^ ^ ^
^
^ +5V ^ a 17, 18, 19 (RED) ^
^
^ ^ c 17, 18, 19 ^
^
^̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲^̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲^̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲
̲ ̲^̲
^ ^ ^
^
^ GND (+5V) ^ a 15, 16 (BLACK) ^
^
^ ^ c 15, 16 ^
^
^̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲^̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲^̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲
̲ ̲^̲
^ ^ ^
^
^ +12V ^ a 27, c 27 (YELLOW) ^
^
^̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲^̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲^̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲
̲ ̲^̲
^ ^ ^
^
^ -12V ^ a 25, c 25 (GREEN) ^
^
^̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲^̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲^̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲
̲ ̲^̲
^ ^ ^
^
^ GND(+/-12V)^ a 26, c 26 (BLUE) ^
^
^̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲^̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲^̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲
̲ ̲^̲
^ ^ ^
^
^ +12V ^ a 14, c 14 (YELLOW) ^
^
^̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲^̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲^̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲
̲ ̲^̲
^ ^ ^
^
^ -12V ^ a 12, c 12 (GREEN) ^
^
^̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲^̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲^̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲
̲ ̲^̲
^ ^ ^
^
^ GND(+/-12V)^ a 13, c 13 (BLUE) ^
^
^̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲^̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲^̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲
̲ ̲^̲
^ ^ ^
^
^ +24V ^ a 24 (WHITE) ^
^
^̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲^̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲^̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲
̲ ̲^̲
^ ^ ^
^
^ -24V ^ a 22 (ORANGE) ^
^
^̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲^̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲^̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲
̲ ̲^̲
^ ^ ^
^
^ GND(+/-24V)^ a 23 (BLUE) ^
^
^̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲^̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲^̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲
̲ ̲^̲
^ ^ ^
^
^ +24V ^ c 24 (WHITE) ^
^
^̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲^̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲^̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲
̲ ̲^̲
^ ^ ^
^
^ -24V ^ c 22 (ORANGE) ^
^
^̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲^̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲^̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲
̲ ̲^̲
^ ^ ^
^
^ GND(+/-24V)^ c 23 (BLUE) ^
^
^̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲^̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲^̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲
̲ ̲^̲
…86…1 …02… …02… …02… …02… …02… …02…
…02… …02… …02…
2700A 3:1:4-6
NEN/840610
5
STUDENT LABORATORY GUIDE
CAMPS
L̲A̲B̲ ̲W̲O̲R̲K̲ ̲S̲H̲E̲E̲T̲ ̲3̲
D̲C̲ ̲V̲O̲L̲T̲A̲G̲E̲ ̲M̲E̲A̲S̲U̲R̲I̲N̲G̲ ̲P̲U̲-̲C̲U̲ ̲C̲R̲A̲T̲E̲
P̲U̲-̲C̲U̲ ̲C̲R̲A̲T̲E̲ ̲R̲E̲A̲R̲ ̲M̲A̲G̲A̲Z̲I̲N̲E̲ ̲O̲N̲ ̲T̲H̲E̲ ̲C̲C̲B̲ ̲M̲O̲D̲U̲L̲E̲
̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲
̲ ̲ ̲
^ ^ ^ ^
^
^̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲^̲ ̲ ̲ ̲ ̲C̲U̲ ̲ ̲ ̲ ̲ ̲ ̲^̲ ̲ ̲ ̲ ̲ ̲P̲U̲#̲1̲ ̲ ̲ ̲ ̲^̲ ̲ ̲ ̲ ̲P̲U̲#̲2̲ ̲
̲ ̲^̲
^ ^ ^ ^
^
^̲ ̲ ̲ ̲+̲2̲4̲V̲A̲ ̲ ̲ ̲ ̲^̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲^̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲^̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲
̲ ̲^̲
^ ^ ^ ^
^
^̲ ̲ ̲ ̲-̲2̲4̲V̲A̲ ̲ ̲ ̲ ̲^̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲^̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲^̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲
̲ ̲^̲
^ ^ ^ ^
^
^̲ ̲ ̲ ̲+̲1̲2̲V̲A̲ ̲ ̲ ̲ ̲^̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲^̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲^̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲
̲ ̲^̲
^ ^ ^ ^
^
^̲ ̲ ̲ ̲-̲1̲2̲V̲A̲ ̲ ̲ ̲ ̲^̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲^̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲^̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲
̲ ̲^̲
^ ^ ^ ^
^
^̲ ̲ ̲ ̲ ̲ ̲5̲V̲A̲ ̲ ̲ ̲ ̲^̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲^̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲^̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲
̲ ̲^̲
^ ^ ^ ^
^
^̲ ̲ ̲ ̲V̲ ̲R̲E̲F̲ ̲ ̲ ̲ ̲^̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲^̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲^̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲
̲ ̲^̲
^ ^ ^ ^
^
^̲ ̲ ̲ ̲+̲2̲4̲V̲B̲ ̲ ̲ ̲ ̲^̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲^̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲^̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲
̲ ̲^̲
^ ^ ^ ^
^
^̲ ̲ ̲ ̲-̲2̲4̲V̲B̲ ̲ ̲ ̲ ̲^̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲^̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲^̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲
̲ ̲^̲
^ ^ ^ ^
^
^̲ ̲ ̲ ̲+̲1̲2̲V̲B̲ ̲ ̲ ̲ ̲^̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲^̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲^̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲
̲ ̲^̲
^ ^ ^ ^
^
^̲ ̲ ̲ ̲-̲1̲2̲V̲B̲ ̲ ̲ ̲ ̲^̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲^̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲^̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲
̲ ̲^̲
^ ^ ^ ^
^
^̲ ̲ ̲ ̲ ̲ ̲5̲V̲B̲ ̲ ̲ ̲ ̲^̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲^̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲^̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲
̲ ̲^̲
^ ^ ^ ^
^
^̲ ̲ ̲O̲F̲F̲S̲E̲T̲ ̲ ̲ ̲ ̲^̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲^̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲^̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲
̲ ̲^̲
…86…1 …02… …02… …02… …02… …02… …02… …02… …02…
…02…
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6
STUDENT LABORATORY GUIDE
CAMPS
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2700A 3:2:4-6
NEN/840610
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STUDENT LABORATORY GUIDE
CAMPS
D̲A̲M̲U̲ ̲E̲X̲E̲R̲C̲I̲S̲E̲S̲:̲
OBJECTIVE: Enable the students to use the most important DAMU
commands.
REFERENCE: CAMPS Site Level Maintenance Manual (SLM).
1. Control the configuration of the Maintenance Position
and change, if necessary.
2. Initialize the system
(SLM: Section 4.8, step 4-7)
3. Set parity in all modules.
(ENABLE COMMAND for I/O MODULES in the CU:
IR 1AXX (XX is the MODULE ADDRESS)
SET PARITY COMMANDS: ZP, ZP1 and ZP8)
4. Check all the memory by the unit mapper
(UNIT MAPPING COMMANDS: UM, UM1 and UM8)
5. Take out the RAM board in slot 16 (0-512K).
6. Init. and try the UM command.
7. Explain the result.
8. Replace the 0-512K RAM board and remove the RAM
board in slot 15.
9. Init. and try the UM command.
2700A 3:2:4-6
NEN/840610
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STUDENT LABORATORY GUIDE
CAMPS
10. Explain the result.
11. Replace the RAM board in slot 15 and remove the
RAM board in slot 6.
12. Try the UM command.
13. Explain the result.
14. Replace the RAM board in slot 6.
15. How will you find the RAM board in slot 6 by use
of the Unit Mapper command?
16. Initialize the system (MC).
17. Give the command IR 1A[7 from the OC (maint.pos.VDU).
18. Check that the LTU in slot 5 in the CU is enabled
to the I/O bus (Yellow lamp Abus or Bbus ON).
19. Give the command UM1.
What is the RAM area?
…0f…
2700A 3:2:4-6
NEN/840610
3
STUDENT LABORATORY GUIDE
CAMPS
…0e…
20. Repeat step 17-19 for the following modules:
Enable LTU slot 6 with command IR 1A[8
Enable LTU slot 7 with command IR 1A[B
Enable LTU slot 8 with command IR 1A[D
Enable DISK CTRL slot 16 with command IR 1A26
Enable DISK CTRL slot 18 with command IR 1A25
Enable DISK CTRL slot 20 with command IR 1A23
Enable FD CTRL slot 14 with command IR 1A[1
21. Disable all the above mentioned modules. Instead
of giving the command IR 1AXX, use the command
IR 18XX.
22. Masterclear the PU from the maintenance position,
by use of the command OC D000 0000.
2700A 3:3:4-6
NEN/840610
1
STUDENT LABORATORY GUIDE
CAMPS
M̲A̲P̲ ̲E̲X̲E̲R̲C̲I̲S̲E̲S̲:
OBJECTIVE: Enable the students to understand the purpose of the
switches and indicators on the front of the MAP module
and enable the students to understand the most important
Maintenance commands.
REFERENCE: CAMPS Site Level Maintenance Manual (SCM)
CAMPS Student Text Book, Vol. I (STB I)
LESSON 3:2:3
1. Switch OFF the power in the PU
2. Remove all the CPU's
3. Switch ON the power in the PU
4. Explain the LED indications on the MAP module.
Ref: SLM, Table 4.5.1-4.
5. Switch to MAINTENANCE mode (Front panel switch
on the MAP module)
6. Explain the LED indications on the MAP module
Ref: SLM, Table 4.5.1-4.
2700A 3:3:4-6
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STUDENT LABORATORY GUIDE
CAMPS
7. Use the following commands and explain what is
happening
Ref.: STB I, Section 11, Datasheet 7-7
7.1 M ̲90 D000 0001 CR
0000
Ref.: SLM, Section 4.8, step 7.
7.2 M ̲00 1A01 0001 CR
Ref.: LESSON 3:2:3, OH 1
7.3 M 80 ̲1A01 0001 CR
0000
8. Switch to NORMAL mode.
(Front panel switch on the MAP module)
2700A 3:4:4-6
NEN/840610
1
STUDENT LABORATORY GUIDE
CAMPS
M̲A̲P̲ ̲T̲E̲S̲T̲:̲
OBJECTIVE: Enable the students to boot and run the MAP test program
from Floppy Diskette and from DISK PACK.
REFERENCE: CAMPS Site Level Maintenance Manual (SLM)
1. Find all the information which is required for
boot of the MAP test program from:
1. Floppy diskette
2. Disk pack
Ref: SLM, Section 4.7.2.1.1, Step 1-8
2. BOOT and RUN the MAP testprogram from Floppy Diskette
Ref: SLM, section 4.7.2.1.3.
3. BOOT and RUN the MAP testprogram from Disk Pack.
Ref: SLM, Section 4.7.2.1.3.
4. Inform the instructor about the result of the test
program.
2700A 3:4:4-6
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STUDENT LABORATORY GUIDE
CAMPS
R̲A̲M̲ ̲T̲E̲S̲T̲:̲
OBJECTIVE: Enable the students to boot and run the RAM test program
from Floppy Diskette and from Disk Pack.
REFERENCE: CAMPS Site Level Maintenance Manual (SLM)
1. Find all the information which is required for
boot of the RAM test program from:
1. Floppy diskette
2. Disk pack
Ref: SLM, Section 4.7.2.1.1, step 1-8
2. BOOT and RUN the RAM testprogram from Floppy Diskette.
Ref: SLM, section 4.7.2.1.4.
3. BOOT and RUN the RAM testprogram from Disk Pack.
Ref: SLM, Section 4.7.2.1.4.
4. Inform the instructor about the result of the test
program.
2700A 3:4:4-6
NEN/840610
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STUDENT LABORATORY GUIDE
CAMPS
BOOT ENTRY FOR TEST PROGRAMS ON SMD DISK
P̲R̲O̲G̲R̲A̲M̲ ̲N̲A̲M̲E̲ B̲O̲O̲T̲ ̲E̲N̲T̲R̲Y̲
CPU [2BD
DISK [2BB
FD [2BA
LTU [2D3
LTU.12 [2C[
LTU.34 [2C1
LTU.5 [2D[
MAP [2BC
PFTP [2BE
RAM [2BF
TDX [2D2
TDX.1 [2C2
TDX.2 [2C3
TDX.3 [2C4
TDX.4 [2C5
TDX.5 [2C6
TDX.6 [2C7
TDX.7 [2C8
TDX.8 [2C9
TDX.9 [2CA
TDX.A [2CB
TDX.B [2CC
TDX.C [2CD
TDX.D [2CE
TDX.E [2CF
TDX.F [2D1
2700A 3:5:4-6
NEN/840610
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STUDENT LABORATORY GUIDE
CAMPS
C̲P̲U̲/̲C̲A̲C̲H̲E̲ ̲T̲E̲S̲T̲
OBJECTIVE: Enable the students to boot and run the CPU/CACHE test
program from Floppy Diskette and from Disk Pack.
REFERENCE: CAMPS Site Level Maintenance Manual (SLM)
1. Find all the information which is required for
boot of the CPU/CACHE test program from:
1. Floppy diskette
2. Disk Pack
Ref: SLM, Section 4.7.2.1.1, Step 1-8
2. BOOT and RUN the CPU/CACHE test program from Floppy
Diskette. Ref: SLM, section 4.7.2.1.2
3. BOOT and RUN the CPU/CACHE test program from Disk
Pack. Ref: SLM, Section 4.7.2.1.2.
2700A 3:5:4-6
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STUDENT LABORATORY GUIDE
CAMPS
L̲T̲U̲ ̲T̲E̲S̲T̲
OBJECTIVE: Enable the students to boot and run the LTU test program
from Floppy Diskettte and from Disk Pack.
REFERENCE: CAMPS Site Level Maintenance Manual (SLM).
1. Find all the information which is required for
boot of the LTU test program from:
1. Floppy diskette
2. Disk Pack
Ref: SLM, Section 4.7.2.1.1, Step 1-8
2. BOOT and run the LTU test program from Floppy Diskette.
Ref: SLM, Section 4.7.2.1.7.
3. BOOT and run the LTU test program from Disk Pack.
Ref: SLM, Section 4.7.2.1.7.
2700A 3:5:1-3
840610 1
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PROGRESS TEST WEEK 3 CAMPS
NAME: ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ SCORE: ̲ ̲
̲ ̲ ̲ ̲ ̲ ̲
1. On which PU bus(ses) are the mainbus arbitration
signals transferred.
(Bus request & bus grant) ?
2. Which module(s) issue(s) the control bus signal
LOCK BUS grant (LBG)?
What happens when it is kept LOW?
3. Describe the purpose(s) of bus termination.
4. Describe the difference between an MBT, when it
is used in a PU, and the same MBT, when used in
a CU.
5. Describe the difference between a CIA-A module
and a CIA-B module (Edge connectors and switch
settings).
2700A 3:5:1-3
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PROGRESS TEST WEEK 3 CAMPS
6. Is it to be expected that the temperature rises
to above the preset alarm level in the rack mounted
temperature sensors if a fan assembly fuse is blown?
7. As the AR (a̲ddress r̲egister) of the CR80 is a 17
bit register (A[-16), how much memory ("K" words)
may the CPU then address?
8. What is the address called, which is issued from
the CPU modules?
9. What is the address called, which is received by
the memory modules?
10. How is it possible for the CPU - with only 17 addr.bits
- to get access to a memory area of 2M words?
11. How much memory ("K" words) is contained in one
RAM module in the CAMPS system?
2700A 3:5:1-3
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PROGRESS TEST WEEK 3 CAMPS
12. Is it necessary to disable any RAM addresses due
to occupation by PROM addresses?
13. How is it possible to check that the switch settings
(addr.area) in the RAM modules are correct - without
removing the modules from the crate?
14. What happens when the MAP front panel switch NRM/MAINT
is in NRM position and the MC pushbuttom is activated?
15. What is the content of the segment registers in
this situation?
16. What happens when the MAP front panel switch NRM/MAINT.
is set in MAINT position and the MC pushbuttom
is activated?
17. How is it possible to distinguish between different
types of memory/no memory in the unit mapper print-out?
What is the smallest memory size that can be indicated?
2700A 3:5:1-3
840610 4
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PROGRESS TEST WEEK 3 CAMPS
18. Which interrupt code is issued from each of the
LTU modules in the CAMPS system?
19. What is the result of the watchdog supervision
if one of the power supplies in the CU fails?
Is it possible to avoid this?
20. Situation:
The CAMPS system is operative with one PU online
and one PU OFF line.
An OFF line LTU communication line is suspected
errorneous.
Describe simple procedures to test:
a) The LTU module
b) The LTU/LIA modules
c) The complete communication line (to f.ex. a
VDU)
2700A 3:5:1-3
840610 1
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ANSWERS TO PROGRESS TEST WEEK 3
CAMPS
1. The MAP controlled bus arbitration for both the
Pbus and the Cbus is communicated via the control
bus:
PBRQ [ - 4, PBG [ - 4
CBRQ 1 - 4, CBG 1-4
2. The LBG is issued by a CPU when it is granted access
to the Pbus (Pbus grant from the MAP).
It is issued (LOW) to keep the Pbus reserved for
the complete data transfer.
No other devices can get access to the bus. The
bus timeout function is disabled.
3. - Bus termination in general: Terminate the bus
lines with the characteristic impedance to
prevent reflections.
- Keep the tri-state driven bus lines at a well-defined
level (High) when no drivers are transmitting.
- Hold the common collector resisters for the
open collector driven bus lines.
4. M̲B̲T̲ ̲i̲n̲ ̲t̲h̲e̲ ̲C̲U̲:̲
- S̲t̲r̲a̲p̲ ̲S̲R̲1̲ ̲i̲n̲ ̲p̲o̲s̲.̲ ̲A̲.̲ The AE (address enable)
signal is grounded. AE is only issued by the
MAP module (Ref.lesson 2:1:1 BUS handshaking).
- S̲t̲r̲a̲p̲ ̲S̲R̲2̲ ̲i̲n̲ ̲P̲o̲s̲ ̲A̲.̲ A voltage drop is introduced
because of the higher supply voltages in the
CU crate (Ref. lesson 2:1:3. Power combine
circuits).
M̲B̲T̲ ̲i̲n̲ ̲a̲ ̲P̲U̲:̲
Both straps in pos. B.
2700A 3:5:1-3
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ANSWERS TO PROGRESS TEST WEEK 3
CAMPS
5. The CIA-A is connected to I/O bus A via a P1 edge
connector.
The CIA-B is connected to I/O bus B via a P2 edge
connector.
The switch setting (DIL switch) is equal.
(Both = crate 1).
6. No, due to the dualized fan unit construction,
four fans will still be running and provide sufficient
cooling to the crate.
7. 17 bits = 128K; This is 64K data and 64K program
(Ref. lesson 2:2:2-2 CPU/CACHE)
8. The LOGICAL address
9. The PHYSICAL address
10. The CPU may select between 16 VIEWS, each view
having its own 128 K of memory. The view is changed
by pointing out another set of Translation tables
in the MAP module (Ref. lesson 2:3:1-2 MAP ADDR.translation)
11. Each module: 128 K words
12. No, the bootstrap PROM addresses are in the highest
4K of the total 16M memory area.
13. Initializing the system (MC) and using the DAMU
unit mapping command ( UM)
14. Master Clear.
Bit is executed in all modules. A CPU is notified.
The bootstrap loader DAMU is initialized; this
is reported via the V24 port on the MIA module.
15. CPU registers: [ for data
1 for Program
DMA registers: undefined
2700A 3:5:1-3
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ANSWERS TO PROGRESS TEST WEEK 3
CAMPS
16. In the MAINT. position the only active module(s)
is the MAP/MIA. The diagnostic program - The MAP
EXERCISER - is active and commands may be given
via the V24 port in the MIA module.
17. RAM memory: 1111
PROM memory: %%%%
No memory: .....
Each unit is indicating 4K.
18. only the address bits (7, 8, B, D respectively)
is issued.
The priority bits in all modules in the CAMPS system
is set to [[.
19. A report on the maintenance position and disabling
of the I/O bus which is connected to the faulty
PS.
The monitoring of errors in the CU is avoided by
the RESET switch on the CCA front panel.
20. a) Bit activated from DAMU or MAP exerciser
b) Run LTU loop back test
c) Run LTU I/O test.
2700A
840610
GENERAL ABBREVIATIONS
Issue 1
CAMPS
DI Discussion
DE Demonstration
L Lecture
GW Group Work
T Test
I Informal Talk
S Self Study
EX Exercise
LG Laboratory Guide
OH Overhead/Handout
2700A
NEN/840610
WEEK SPECIFIC ABBREVIATIONS
WEEK No. 3 Issue 1 CAMPS
HBK CR80 MINI COMPUTER HANDBOOK 82/83.
HWB CPS/SDS/017 (H/W ASSY BREAKDOWN)
MPO CPS/OPM/005 (Maintenance Position Operation
Manual)
SLG CPS/TMA/025 (STUDENT LABORATORY GUIDE)
SLM CPS/TCM/005 (SITE LEVEL MAINTENANCE MANUAL).
STB I CPS/TMA/005 (CAMPS STUDENT TEXT BOOK VOL.
I
STB II CPS/TMA/006 (CAMPS STUDENT TEXT BOOK VOL.
II
STB III CPS/TMA/024 (CAMPS STUDENT TEXT BOOK VOL.
III
PCB PRINTED CIRCUIT BOARD
PWR POWER
PS POWER SUPPLY
2700A
BJR/840403
1
EXERCISE
D̲A̲M̲U̲ ̲E̲X̲E̲R̲C̲I̲S̲E̲S̲:̲
OBJECTIVE: Enable the students to use the most important DAMU
commands.
REFERENCE: DAMOS BOOT LOADER PRODUCT SPECIFICATION.
1. Control the configuration of the Maintenance Position
and change, if necessary.
2. Initialize the system
3. Set parity in all modules
4. Check all the memory by the unit mapper
5. Take out the RAM board in slot 16 (0-512K).
6. Init. and try the UM command.
7. Explain the result.
8. Replace the 0-512K RAM board and take out the RAM
board in slot 15.
9. Init. and try the UM command.
2700A
BJR/840403
2
EXERCISE
10. Explain the result.
11. Replace the RAM board in slot 15 .
12. Try the UM command.
13. Explain the result.
14. How will you find the RAM board in slot 6 by use
of the Unit Mapper command?
15. Initialize the system (MC).
16. Give the command IR 1A[7 from the OC (maint.pos.VDU).
17. Check that the LTU in slot 5 in the CU is enabled
to the I/O bus (Yellow lamp Abus or Bbus ON).
18. Give the command UM1.
What is the RAM area?
…0f…
2700A
BJR/840403
3
EXERCISE
…0e…
19. Repeat step 17-19 for the following modules:
Enable LTU slot 6 with command IR 1A[8
Enable LTU slot 7 with command IR 1A[B
Enable LTU slot 8 with command IR 1A[D
Enable DISK CTRL slot 16 with command IR 1A26
Enable DISK CTRL slot 18 with command IR 1A25
Enable DISK CTRL slot 20 with command IR 1A23
Enable FD CTRL slot 14 with command IR 1A[1
20. Disable all the above mentioned modules. Instead
of giving the command IR 1AXX, use the command
IR 18XX.
21. Masterclear the PU from the maintenance position,
by use of the command OC D000 0000.
2700A 3:5:1-3
830617 1
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PROGRESS TEST WEEK 3 CAMPS
NAME: ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ SCORE: ̲ ̲
̲ ̲ ̲ ̲ ̲ ̲
1. On which PU bus(ses) are the mainbus arbitration
signals transferred.
(Bus request & bus grant) ?
2. What is the difference of the three DAMU commands:
ZP - BE - BO?
What happens when it is kept LOW?
3. Describe the purpose(s) of bus termination.
4. Describe the difference between an MBT, when it
is used in a PU, and the same MBT, when used in
a CU.
5. Describe the difference between a CIA-A module
and a CIA-B module (Edge connectors and switch
settings).
2700A 3:5:1-3
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PROGRESS TEST WEEK 3 CAMPS
6. Is it to be expected that the temperature rises
to above the preset alarm level in the rack mounted
temperature sensors if a fan assembly fuse is blown?
7. As the AR (a̲ddress r̲egister) of the CR80 is a 17
bit register (A[-16), how much memory ("K" words)
may the CPU then address?
8. What is the address called, which is issued from
the CPU modules?
9. What is the address called, which is received by
the memory modules?
10. How is it possible for the CPU - with only 17 addr.bits
- to get access to a memory area of 2M words?
11. How much memory ("K" words) is contained in one
RAM module in the CAMPS system?
2700A 3:5:1-3
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PROGRESS TEST WEEK 3 CAMPS
12. Is it necessary to disable any RAM addresses due
to occupation by PROM addresses?
13. How is it possible to check that the switch settings
(addr.area) in the RAM modules are correct - without
removing the modules from the crate?
14. What happens when the MAP front panel switch NRM/MAINT
is in NRM position and the MC pushbuttom is activated?
15. Write the four commands you will use to enable
the FD controller and the three DISK controllers
1:
2:
3:
4:
16. What happens when the MAP front panel switch NRM/MAINT.
is set in MAINT position and the MC pushbuttom
is activated?
17. How is it possible to distinguish between different
types of memory/no memory in the unit mapper print-out?
What is the smallest memory size that can be indicated?
2700A 3:5:1-3
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PROGRESS TEST WEEK 3 CAMPS
18. Which interrupt code is issued from each of the
LTU modules in the CAMPS system?
19. What is the result of the watchdog supervision
if one of the power supplies in the CU fails?
Is it possible to avoid this?
20. Situation:
The CAMPS system is operative with one PU online
and one PU OFF line.
An OFF line LTU communication line is suspected
errorneous.
Describe simple procedures to test:
a) The LTU module
b) The LTU/LIA modules
c) The complete communication line (to f.ex. a
VDU)
2700A
NEN/840610
WEEK SPECIFIC ABBREVIATIONS
WEEK NO. 3 CAMPS
HBK CR80 Mini Computer Handbook 82/83
HWB CPS/SDS/017 (H/W Assy Breakdown)
MPO CPS/OPM/005 (Maintenance Position Operation
Manual)
SLG CPS/TMA/025 (Student Laboratory Guide)
SLM CPS/TCM/005 Site Level maintenance Manual)
STB I CPS/TMA/005 (student Text Book, Vol. 1)
STB II CPS/TMA/006 (student Text Book, Vol. II)
STB III CPS/TMA/024 (Student Text Book, Vol. III)
PCB Printed Circuit Board
PWR Power
PS Power Supply
