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⟦81e9ca29c⟧ Wang Wps File
Length: 63389 (0xf79d)
Types: Wang Wps File
Notes: CPS/TMA/013 (Week 9)
Names: »2949A «
Derivation
└─⟦974e3658d⟧ Bits:30006161 8" Wang WCS floppy, CR 0241A
└─ ⟦this⟧ »2949A «
WangText
…00……00……00……00……00…6…0a……00……00…6…0b…6…0f…6
6…07…5…0b…5…0f…5
5…07…4…0b…4…0f…4
4…07…3…0b…3…0f…3
3…07…2…0b…2…0f…2
2…07…1…0b…1…0f…1…02…1…06…0…0a…0…0e…0…02…0…06…/…0a……86…1 …02… …02… …02…
…0e… 2949A/rt
JJD/821012
MAP EXERCISES 9:1:1 45
CAMPS…0f…
Check-out the MAP interrupt handling concerning
CPU-to-CPU interrupt,
simulated interrupts and
IVrecord change requests
MAP exercises
CAMPS Training System
GW, H
Whiteboard
MAP: CSD/005/PSP/0037
…0e… 2949A/rt
JJD/821012
MAP EXERCISES 9:1:2 45
CAMPS…0f…
Check-out the MAP interrupt handling concerning
CPU-to-CPU interrupt,
simulated interrupts and
IVrecord change requests
MAP exercises
CAMPS Training System
GW, H
Whiteboard
MAP: CSD/005/PSP/0037
…0e… 2949A/rt
JJD/821012
MAP EXERCISES 9:1:3 45
CAMPS…0f…
Check-out the MAP interrupt handling concerning
CPU-to-CPU interrupt,
simulated interrupts and
IVrecord change requests
MAP exercises
CAMPS Training System
GW, H
Whiteboard
MAP: CSD/005/PSP/0037
…0e… 2949A/rt
JJD/821012
PROCESSOR UNIT BUILT-UP 9:1:4 45
CAMPS…0f…
Disassemble and assemble a processor crate
(skill lesson)
Assembling/disassembling exercise
CAMPS Training System
DE, H
Processor Crate, Avo-Meter
CAMPS Handbook 82/83
Hardware Assembly Break Down Manual
…0e… 2949A/rt
JJD/821012
PROCESSOR UNIT BUILT-UP 9:1:5 45
CAMPS…0f…
Disassemble and assemble a processor crate
(skill lesson)
Assembling/disassembling exercise
CAMPS Training System
H
Processor Crate, Avo-Meter
CAMPS Handbook 82/83
Hardware Assembly Break Down Manual
…0e… 2949A/rt
JJD/821012
SELF-STUDY 9:1:5 45
CAMPS…0f…
Explain the SIO, PIO, CTC and Z80 CPU concerning
blockdiagram, purpose,
mode of operation, input/output
and interrupt handling
Self-study presentation during
Lesson 9:3:2 - 9:3:3
CAMPS Classroom
GW, S, I
Whiteboard
Mostek: Microcomputer components, databook
Zilog: Zilog Data book
Osborne: An introduction to microcomputers,Vol II
…0e… 2949A/rt
JJD/821012
PROCESSOR UNIT BUILT-UP 9:1:6 45
CAMPS…0f…
Disassemble and assemble a processor crate
(skill lesson)
Assembling/disassembling exercise
CAMPS Training System
H
Processor Crate, Avo-Meter
CAMPS Handbook 82/83
Hardware Assembly Break Down Manual
…0e… 2949A/rt
JJD/821012
SELF-STUDY 9:1:6 45
CAMPS…0f…
Explain the SIO, PIO, CTC and Z80 CPU concerning
blockdiagram, purpose,
mode of operation input/output
and interrupt handling
Self-study presentation during
Lesson 9:3:2 - 9:3:3
CAMPS Classroom
GW, S, I
Whiteboard
Mostek: Microcomputer components, databook
Zilog: Zilog Data book
Osborne: An introduction to microcomputers,Vol II
…0e… 2949A/rt
JJD/821012
REVIEW QUIZ 9:2:1 45
CAMPS…0f…
8 out of 10 answers must be correct
CAMPS Classroom
Quiz
As below
Student Textbook
Student Hand-Out
Student Notes
MAP Description CSD/005/PSP/0037
CPU/CACHE Description CSD/005/PSP/0032
…0e… 2949A/rt
JJD/821012
SELF-STUDY 9:2:2 45
CAMPS…0f…
Explain the SIO, PIO, CTS and Z80 CPU
Concerning Blockdiagram,
Purpose, mode of operation
Input/output and interrupt handling
Self-Study Presentation during
Lesson 9:3:2 - 9:3:3
CAMPS Classroom
GW, S, I
Whiteboard
Mostek: Microcomputer components, databook
Zilog: Zilog Data Book
Osborne: An introduction to microcomputers,Vol II
MAP Description CSD/005/PSP/0037
CPU/CACHE Description CSD/005/PSP/0032
…0e… 2949A/rt
JJD/821012
PROCESSOR UNIT BUILT-UP 9:2:2 45
CAMPS…0f…
Disassemble and assemble a processor crate
(Skill Lesson)
Assembling/Disassembling exercise
CAMPS Training System
H
Processor Crate, Avo-Meter
CAMPS Handbook 82/83
Hardware Assembly Break Down Manual
…0e… 2949A/rt
JJD/821012
SELF-STUDY 9:2:3 45
CAMPS…0f…
Explain the SIO, PIO, CTS and Z80 CPU
Concerning Blockdiagram,
Purpose, mode of operation
Input/output and interrupt handling
Self-Study Presentation during
Lesson 9:3:2 - 9:3:3
CAMPS Classroom
GW, S, I
Whiteboard
Mostek: Microcomputer components, databook
Zilog: Zilog Data Book
Osborne: An introduction to microcomputers,Vol II
…0e… 2949A/rt
JJD/821012
PROCESSOR UNIT BUILT-UP 9:2:3 45
CAMPS…0f…
Disassemble and assemble a processor crate
(Skill Lesson)
Assembling/Disassembling exercise
CAMPS Training System
H
Processor Crate, Avo-Meter
CAMPS Handbook 82/83
Hardware Assembly Break Down Manual
…0e… 2949A/rt
JJD/821012
SELF-STUDY 9:2:4 45
CAMPS…0f…
Explain the SIO, PIO, CTS and Z80 CPU
Concerning Blockdiagram,
Purpose, mode of operation
Input/output and interrupt handling
Self-Study Presentation during
Lesson 9:3:2 - 9:3:3
CAMPS Classroom
GW, S, I
Whiteboard
Mostek: Microcomputer components, databook
Zilog: Zilog Data Book
Osborne: An introduction to microcomputers,Vol II
…0e… 2949A/rt
JJD/821012
PROCESSOR UNIT BUILT-UP 9:2:4 45
CAMPS…0f…
Disassemble and assemble a processor crate
(Skill Lesson)
Assembling/Disassembling exercise
CAMPS Training System
H
Processor Crate, Avo-Meter
CAMPS Handbook 82/83
Hardware Assembly Break Down Manual
…0e… 2949A/rt
JJD/821012
PROCESSOR UNIT BUILT-UP 9:2:5 45
CAMPS…0f…
Disassemble and assemble a processor crate
(Skill Lesson)
Assembling/Disassembling exercise
CAMPS Training System
H
Processor Crate, Avo-Meter
CAMPS Handbook 82/83
Hardware Assembly Break Down Manual
…0e… 2949A/rt
JJD/821012
SELF-STUDY 9:2:5 45
CAMPS…0f…
Explain the SIO, PIO, CTS and Z80 CPU
Concerning Blockdiagram,
Purpose, mode of operation
Input/output and interrupt handling
Self-Study Presentation during
Lesson 9:3:2 - 9:3:3
CAMPS Classroom
GW, S, I
Whiteboard
Mostek: Microcomputer components, databook
Zilog: Zilog Data Book
Osborne: An introduction to microcomputers,Vol II
…0e… 2949A/rt
JJD/821012
PROCESSOR UNIT BUILT-UP 9:2:6 45
CAMPS…0f…
Disassemble and assemble a processor crate
(Skill Lesson)
Assembling/Disassembling exercise
CAMPS Training System
H
Processor Crate, Avo-Meter
CAMPS Handbook 82/83
Hardware Assembly Break Down Manual
…0e… 2949A/rt
JJD/821012
REVIEW QUIZ 9:3:1 45
CAMPS…0f…
8 out of 10 answers must be correct
CAMPS Classroom
Quiz
As below
Student Textbook
Student Hand-Out
Student Notes
MAP Description CSD/005/PSP/0037
CPU/CACHE Description CSD/005/PSP/0032
…0e… 2949A/rt
JJD/821012
SELF-STUDY PRESENTATION 9:3:2 45
CAMPS…0f…
Explain the basic principles of the Z80 microprocessor,
the CTC and the SIO
Student Presentation
CAMPS Training
Presentation, DI
Student Materials, Overheads or Hand-outs
Mostek: Microcomputer components, databook
Zilog: Zilog Data Book
Osborne: Introduction to Microcomputers,Vol II
…0e… 2949A/rt
JJD/821012
SELF-STUDY PRESENTATION 9:3:3 45
CAMPS…0f…
Explain the basic principles of a
Z80 microprocessorsystem, including
Z80 CPU
SIO
PIO
CTC
Student Presentation
CAMPS Classroom
Presentation, DI
Student Materials, Overheads or Hand-outs
Mostek: Microcomputer components, databook
Zilog: Zilog Data Book
Osborne: Introduction to Microcomputers,Vol II
…0e… 2949A/rt
JJD/821012
LTU 9:3:4 45
CAMPS…0f…
Explain the CR80 I/0 Module Concept
Describe the purpose of the LTU
Explain the shadow PROM concept
Review Quiz
Situation Questions during the lesson
Questionare at conclusion of lesson
CAMPS Classroom
L
Overheads
Whiteboard
Student Textbook
CSD/005/PSP/0074
…0e… 2949A/rt
JJD/821012
LTU 9:3:5 45
CAMPS…0f…
Explain the LTU Commands and their
use. Describe the purpose of the
blocks shown on the LTU
blockdiagram.
Review Quiz
Situation Questions during the lesson
Questionare at conclusion of lesson
CAMPS Classroom
L, DE
Overheads
Whiteboard
LTU BOARD
Student Textbook
CSD/005/PSP/0074: LTU Description
…0e… 2949A/rt
JJD/821012
LTU BOOTLOAD 9:3:6 45
CAMPS…0f…
Explain the CR80-LTU interface and
Hand-Shake during LTU download
LTU hands-on
Lessons 9:4:1 - 9:4:6
CAMPS Classroom
L,
Overheads
Whiteboard
CSD-MIC/404/PSP/0021
…0e… 2949A/rt
JJD/821012
LTU HANDS-ON 9:4:1 45
CAMPS…0f…
Manually command the LTU to bootload,
clear and send interrupt and verify results,
decode self-test result
Perform a manual bootload of the LTU
and verify result.
LTU exercises
CAMPS Training System
GW
Work Assignment
Student Textbook
CSD-MIC/404/PSP/0021
…0e… 2949A/rt
JJD/821012
LTU HANDS-ON 9:4:2 45
CAMPS…0f…
Manually command the LTU to bootload,
clear and send interrupt and verify results,
decode self-test result
Perform a manual bootload of the LTU
and verify result.
LTU exercises
CAMPS Training System
GW
Work Assignment
Student Textbook
CSD-MIC/404/PSP/0021
…0e… 2949A/rt
JJD/821012
LTU HANDS-ON 9:4:3 45
CAMPS…0f…
Manually command the LTU to bootload,
clear and send interrupt and verify results,
decode self-test result
Perform a manual bootload of the LTU
and verify result.
LTU exercises
CAMPS Training System
GW
Work Assignment
Student Textbook
CSD-MIC/404/PSP/0021
…0e… 2949A/rt
JJD/821012
LTU HANDS-ON 9:4:4 45
CAMPS…0f…
Manually command the LTU to bootload,
clear and send interrupt and verify results,
decode self-test result
Perform a manual bootload of the LTU
and verify result.
LTU exercises
CAMPS Training System
GW
Work Assignment
Student Textbook
CSD-MIC/404/PSP/0021
…0e… 2949A/rt
JJD/821012
LTU HANDS-ON 9:4:5 45
CAMPS…0f…
Manually command the LTU to bootload,
clear and send interrupt and verify results,
decode self-test result
Perform a manual bootload of the LTU
and verify result.
LTU exercises
CAMPS Training System
GW
Work Assignment
Student Textbook
CSD-MIC/404/PSP/0021
…0e… 2949A/rt
JJD/821012
LTU HANDS-ON 9:4:6 45
CAMPS…0f…
Manually command the LTU to bootload,
clear and send interrupt and verify results,
decode self-test result
Perform a manual bootload of the LTU
and verify result.
LTU exercises
CAMPS Training System
GW
Work Assignment
Student Textbook
CSD-MIC/404/PSP/0021
…0e… 2949A/rt
JJD/821012
FLOPPY DISC CONTROLLER 9:5:2 45
CAMPS…0f…
Describe the WD 1791
Understand the floppy disc controller
Blockdiagram
Use the F.D. Controller Commands
Review Quiz
Situation Questions during the
Lesson
CAMPS Classroom
L
Whiteboard
Overhead
Whiteboard
Floppy Disc Controller PCB
…0e… 2949A/rt
JJD/821012
REVIEW QUIZ 9:5:1 45
CAMPS…0f…
8 out of 10 answers must be correct
CAMPS Classroom
Quiz
Student Textbook
Student Hand-out
Student Notes
As Above
…0e… 2949A/rt
JJD/821012
FLOPPY DISC CONTROLLER 9:5:3 45 CAMPS…0f…
Command the Floppy Disc Controller to
Restore, seek, read/write a sector
and verify results
Fetch and interpret status and
additional status.
Exercise
CAMPS Training System
GW, H
Whiteboard
Student Textbook
…0e… 2949A/rt
JJD/821012
FLOPPY DISC CONTROLLER 9:5:5 45
CAMPS…0f…
Command the Floppy Disc Controller to
Restore, seek, read/write a sector
and verify results
Fetch and interpret status and
additional status.
Exercise
CAMPS Training System
GW, H
Whiteboard
Student Textbook
…0e… 2949A/rt
JJD/821012
FLOPPY DISC CONTROLLER 9:5:4 45
CAMPS…0f…
Command the Floppy Disc Controller to
Restore, seek, read/write a sector
and verify results
Fetch and interpret status and
additional status.
Exercise
CAMPS Training System
GW, H
Whiteboard
Student Textbook
…0e… 2949A/rt
JJD/821012
WEEK SUM UP 9:5:6 45
CAMPS…0f…
-
-
CAMPS Classroom
DI, I
-
None
2949A/rt/
9:1:4 JJD/821012
PROCESSOR UNIT BUILT-UP DE,H
Introduction Purpose: 1)Step-by-step integration and
check-out: easy fault recognition
2)Rehearse System Configuration
Demonstration PU disassembled on before hand
Crate dismounted from rack
All wires/cables disconnected
All on-board switches zeroed
Wirecheck Backplane, power
P3 - P1 flatcables
Crate Mounted in rack, mains connected
Fans to fans and r̲e̲a̲r̲ power connectors
Power ON Indicator + fan control
MBTs Configured and inserted
SR1: B SR2: B
First P.S. Check Strap F-H P.U: N̲o̲ ̲s̲t̲r̲a̲p̲
Insert, P.O. check via AVO
Second PS As above
MAP/MIA
(O.C.on V24) Check self-test + print out
CPU DAMU print-out
RAM Configured, DAMU Test
2949A/rt/
9:1:4 JJD/821012
SELF-STUDY L
Introduction
SELF-STUDY Insight, analyse and understand status
Purpose messages
self confidence,
knowledge, further study of TCM or the like
2 types of
CR80 Peripherals The Z80 and the 2901
2901 During floppy disc controller
"Design" Learn two units, interface, next unit, interface
until general Z80 microsystem is "constructed".
G̲e̲n̲e̲r̲a̲l̲ interfacing, n̲o̲t̲ all electrical signals.
Self-Study H.O.1-5 Working papers H.O.1 - H.O.5
2949A/rt/
9:3:2 JJD/821012
SELF-STUDY PRESENTATION DI
Z80 Read/Write MREQ
1 or Q
RD, WR
Wait Stops Z80
Slow Memory or I/O devices
BUSRQ, BUSAK Float the buslines,
(a̲l̲l̲)̲. External control
possible (DMA)
Vectorized INT, NMI
Interrupt
Register Interrupt
̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ V̲e̲c̲t̲o̲r̲ ̲ ̲ ̲
̲ ̲ ̲I̲V̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ Z80 memory
̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲
ADDRESS
̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲
LL
LL
LLLL is the a̲d̲d̲r̲e̲s̲s̲ of the program to be
executed due to the interrupt f̲a̲s̲t̲
Daisy Chain Enable String or daisy chain
+5v
̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲
̲ ̲ ̲
Z80 1 2 3
̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲
̲ ̲ ̲
Interrupt (Common)
Automatic priority!!
2949A/rt/
9:3:2 JJD/821012
SELF-STUDY PRESENTATION DI
Acknowledge M1 + I0RQ: Device outputs vector
Refresh Counter, Row only, 7 bits each
Instruction fetch cycle
CTC Initialization: Reset
Define operation (control
word)
Set-up interrupt vector
Timer Mode Counter Mode
̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲
Divide Incoming Preset Counter
Clocks by a pre- Count down by incoming
determined factor clock
0? interrupt
SIO basicly parallel-serial, serial-parallel
2 channels
synchronous, asynchronous
7 write register for configuration, 3 read
registers for status, polled or interrupts
2949A/rt/
9:3:3 JJD/821012
SELF-STUDY PRESENTATION DI
PIO 4 modes All output
All input
Bidirectional
Control mode (bit mode)
2 Handshake signals: ready, strobe
Initialization 1. select mode
2. set int. control
3. load int.vector (if used)
R̲e̲a̲d̲y̲
Z80
System
Chipselect I/O Address Chipselect
Problem
Solution:
I/O address decoder ROM connected to the
addresslines.
Addresslines I/O
Decoder
̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲
CE
̲C̲T̲C̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲
̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲
CE
̲P̲I̲O̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲
̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲
CE
̲S̲I̲O̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲
2949A/rt/
9:3:4 JJD/821012
LTU L
Cr 80 O.H.1 e.g.Floppy disc controller
I/O Modules
General
Combi
Modules O.H.2 e.g.Disc controller, Tape controller, LTU
Dual
Bus LTU O.H.3 Work-program is R̲A̲M̲!
Dynamically changeable
but also I/O commands
Bootload Moving of program from shared
memory to workprogram memory
(controlled by PROM program)
Memory
Organisation O.H.4 Note: B̲y̲t̲e̲s̲
LTU
Block Diagram O.H.5 General Z80 microcomputer system
+DMA, speed up SIO handling
req Z80 Bus, take over address lines,
Read/Write, interrupt Z80 when the
entire transfer is completed.
̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲
Z80 INT TIMER
3
̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲
BUSRQ ACK EOP
̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲
A REQ
SIO 1 B DMA SIO2
̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲
ACK
2949A/rt/
9:3:4 JJD/821012
LTU L
RAM O.H.1 Access Arbitration, Default Z80
Control Logic CR80 wait max 1 microsecond
Z80 waits if CR80 access
Parity Parity check on in/out data from
Circuit LTU RAM.
Error NMI, bootload, error routing
Led flash (FFFF)
Sequencer RAM timing, started by interface control
Address
Counter + Loaded when memory or I/O access
Comparator +1 to speed up s̲e̲q̲u̲e̲n̲t̲i̲a̲l̲ access.
Interface Command decoding, synchronize LTU to the
Control bus.
Multiplexe the CR80 bus into 16 address
followed by the 16 data lines
active when enabled by an I/O command.
Interrupt Controlled by PIO 1, sends interrupts
Logic on to the e̲n̲a̲b̲l̲e̲d̲ ̲ bus.
2949A/rt/
9:3:4 JJD/821012
LTU L
LTU
Addressing 0.H2
LTU
Commands O.H.3 5555 written into location 00 cause
self-test + interrupt to CR80
enable, disable RAM area
Self-Test O.H.4 built as a mainroutine with testsubroutines
PROMTEST is checksum
RAM is read/write
8253 1/2 is timer test
Error O.H.5 Flash Test LED
Demonstration Remove CTC from socket and decode LED
2949A/rt/
9:3:6 JJD/821012
LTU BOOTLOAD L
LTU
Memory O.H.1 Workprogram is RAM, not accessible
from CR80
Shadow Self-Test and bootload, switched in during
PROM Bootload as L̲T̲U̲ Address 0000-0800
i.e. read from PROM-write into RAM, when
LTU is cleared, shadow PROM is switched out
Shared RAM 0.H2 Togglebit, EOT
CR80 LTU(280)
̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲
AAAA Loads 1)Bytecount
2)Start Address
A̲S̲ ̲S̲E̲E̲N̲ ̲F̲R̲O̲M̲
̲L̲T̲U̲!̲!̲
3)000
Loads 1)Array Start
Address =
where in
workprogram
RAM is the
following is
to be placed
2)Program +
3)Checksum
4)CCCC
1)Calculate Checksum
of the E̲N̲T̲I̲R̲E̲ shared
RAM area, if ok
Clear LTU 2) 0000
i.e. Start LTU
̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲
̲ ̲ ̲ ̲ ̲ ̲ ̲
(Download again) (If not 0002)
2949A/rt/
9:5:2 JJD/821012
FLOPPY DISC CONTROLLER L
FD O.H IBM 3740, single side, single density
Format 1-3 77 tracks, 0 - 76
26 sectors (record), 1 - 26
1 is identified by index mark.
WD 1791 O.H.4 5 registers, 11 commands (via 8 datalines)
Provide the following features:
automatic track seek + verification
read/write a specified sector and
automatic CRC generation/control:
only data is presented7requested on the data
lines.
Status register updated when command is executed.
Automatic restore + verify
F.D.
Controller
Block Diagram O.H.5 Command execution by microroutine jump
I/O Module
Commands O.H.6
Status O.H.7
Additional
Status O.H.8
Operation O.H.9 Seek, Read, Write Sequence
2949A/rt/
9:5:3 JJD/821012
ST. F.D.CONTROLLER GW,H
Exercise H.O.1 Note: The two MSBs in additional status
is a relic from the last datatransfer!
…0f… 2949/rt 9:1:2
JJD/830216
MAP EXERCISES CAMPS…0e…
SWITCH TO MAINTENANCE MODE AND MASTER CLEAR THE P.U.
1) Set-up a CPU-TO-CPU interrupt from CPU 1 to CPU
0. Use the IV = OF
NOTE: CPU 1 does not have to exist!
Verify that CPU 0 get the interrupt by reading
notification descriptor for CPU 0.
Read out INTRQ for CPU 1 and CPU 0 after the interrupt
and explain results.
2) Set-up a simulated interrupt from IV 3F, using
the timer (IV) to CPU 0. The timer must be set
to approx. 30 seconds.
During countdown, set-up the MAP to continuously
read out the notification descriptor belonging
to CPU 0 to verify the sending of the interrupt.
3) Verify that the MAP change the CPU record when
a CPU is notified.
Describe the changes and their purpose
4) Verify the contents of MAP RAM location 89CF following:
a. An attempted access of non-existing RAM (or
I/0) inside the P.U. domain
b. An attempted access of non-existing RAM (or
I/0) in a channel-unit.
Ref. MAP CSD/005/PSP/0037 page 76.
5) Verify the influence of command Ignore on MAP location
8962, and find out the initial value of 8962 (following
a Master Clear).
…0e… 2949A/rt
JJD/821012
CAMPS…0f…
S̲E̲L̲F̲-̲S̲T̲U̲D̲Y̲:̲ ̲Z̲8̲0̲
I̲N̲T̲R̲O̲D̲U̲C̲T̲I̲O̲N̲:̲
Z80 is a standard all-purpose microprocessor used in
several CR80 peripheral modules.
The purpose of this self-study is to f̲a̲m̲i̲l̲i̲a̲r̲i̲z̲e̲ you
with the Z80 characteristics.
Make yourself aquainted with:
READ/WRITE sequence
Wait Concept
BusReq
Bus ACK
Interrupt Handling, including
INT and NMI
Interrupt Concept
Daisy-chain
Interrupt Acknowledge
Refresh
D̲O̲N̲'̲T̲ try to understand Z80 addressing modes or instruction
set!! It is not the scope of this self-study.
…0e… 2949A/rt
JJD/821012
CAMPS…0f…
S̲E̲L̲F̲-̲S̲T̲U̲D̲Y̲:̲ ̲C̲T̲C̲
Produce a block diagram of the CTC, showing only the
block necessary to understand the f̲u̲n̲c̲t̲i̲o̲n̲ of the device.
Prepare a short presentation of the CTC (max. 15 minutes).
The presentation outline c̲o̲u̲l̲d̲ be:
CTC purpose
block diagram
modes of operation incl. initialization
data in/out
interrupt handling
or explain the CTC by going through the CTC signals
and pin assignment
or do it your way!
Note: use pencil for your drawing(s).
…0e… 2949A/rt
JJD/821012
CAMPS…0f…
S̲E̲L̲F̲-̲S̲T̲U̲D̲Y̲:̲ ̲P̲.̲I̲.̲O̲
Produce a block diagram of the P.I.O., showing only
the block necessary to understand the f̲u̲n̲c̲t̲i̲o̲n̲ of the
device.
Prepare a short presentation of the P.I.O. (max. 15
minutes).
The presentation outline c̲o̲u̲l̲d̲ be:
P.I.O.purpose
block diagram
modes of operation incl. initialization
data in/out
interrupt handling
or explain the P.I.O. by going through the P.I.O.
signals and pin assignment
or do it your way!
Note: use pencil for your drawing(s).
…0e… 2949A/rt
JJD/821012
CAMPS…0f…
S̲E̲L̲F̲-̲S̲T̲U̲D̲Y̲:̲ ̲S̲.̲I̲.̲O̲
Produce a block diagram of the S.I.O., showing only
the block necessary to understand the f̲u̲n̲c̲t̲i̲o̲n̲ of the
device.
Prepare a short presentation of the S.I.O. (max. 15
minutes).
The presentation outline c̲o̲u̲l̲d̲ be:
S.I.O.purpose
block diagram
modes of operation incl. initialization
data in/out
interrupt handling
or explain the S.I.O. by going through the S.I.O.
signals and pin assignment
or do it your way!
Note: use pencil for your drawing(s).
…0e… 2949A/rt
SELF-STUDY JJD/821012
MICROPROCESSORS
CAMPS…0f…
"Construct" a microprocessorsystem using the components
from the self-study lessons.
Requirement:
16 address, 8 data bits
4 serial channels, all channels with software controlled
baudrate.
4 8-bits parallel ports, 2 ports must work as input
ports, 2 ports as output.
The system must use vectorized interrupt on the serial
channels (daisy-chain)
A switch must be implemented to force a NMI to the
CPU.
NOTE: Use pencil for your drawing(s).
…0e… 2949A/rt
JJD/821012
REVIEW QUIZ
9:2:1
CAMPS…0f…
1. How is the power failure LED cleared?
2. Can the CPU mask out a power failure interrupt?
explain your answer.
3. Explain the difference between real-time interrupt
and fast timer interrupt.
4. How can an interrupt vector be screened from the
queue-mechanism i.e. not processed by the MAP at
all.
5. Why must the I/O modules in the processorcrate
not use addresses 0-1F?
6. The CPU CACHE writes into main memory. Is the local
CACHE updated?
7. Following a power-up, CPU 0 is notified by the
MAP. Explain CPU reactions.
8. How is the supply voltages in the channel-unit
crate raised 0,5 volts? and why?
9. While the halt signal is active only one device
is granted bus access. Which device?
10. In case of time-out during maintenance mode which
MAP location holds the additional information about
this time-out?
…0e… 2949A/rt
JJD/821012
REVIEW QUIZ
9:3:1
CAMPS…0f…
1. List the events, that will disable CACHE-RAM
2. Explain the major differences between I/O interrupts
and CPU interrupts.
3. List the interrupts that the CPU cannot mask out
4. How is a data channel transfer terminated? why?
5. Can a processor crate contain I/O modules. Explain
your answer
6. Explain the bus arbitration
7. Where is a bus time-out condition d̲e̲t̲e̲c̲t̲e̲d̲?
8. How is the CPU informed about the time-out situation?
9. How is a CPU notified
10. List the conditions which must be fulfilled before
a CPU is notified.
…0e… 2949A/rt
JJD/821012
LTU WORKASSIGNMENT
9:4:1 - 9:4:6
CAMPS…0f…
1. Select a LTU and verify by means of DAMU command
"UM" the RAM enable/disable command.
2. Write by means of MAP exerciser a pattern into
the upper two LTU RAM locations.
Verify by means of DAMU
3. Command by means of MAP exerciser the LTU to perform
a self-test and verify that the LTU interrupt the
CR80 when self-test is completed.
Use MAP RAM and the interrupt queue.
4. Enable the LTU onto one of the databusses and command
the LTU into bootload mode. Perform a step by step
download of the LTU program listed overleaf. During
this download, note the following parameters:
BYTECOUNT, START ADDRESS, CHECKSUM, and LTU STATUS.
Start the LTU execution and check result.
…0e… 2949A/rt
JJD/821012
CAMPS…0f…
LESSON NO: 9:4:1 - 9:4:6
TOPIC: HANDS-ON LTU
This small program will make the LTU flash the
test LED.
813E 73D3 D379 1E71 06FF 1OFF
1DFE F920 CBAF C261 001A E1CB
EA18 A1CB E618
Checksum: 0009…86…1 …02… …02… …02… …02…
…0e… 2949A/rt
JJD/821012
LTU WORKASSIGNMENT
9:4:1 - 9:4:6
CAMPS…0f…
1. Select a LTU and verify by means of DAMU command
"UM" the RAM enable/disable command.
2. Write by means of MAP exerciser a pattern into
the upper two LTU RAM locations.
Verify by means of DAMU
3. Command by means of MAP exerciser the LTU to perform
a self-test and verify that the LTU interrupt the
CR80 when self-test is completed.
Use MAP RAM and the interrupt queue.
4. Enable the LTU onto one of the databusses and command
the LTU into bootload mode. Perform step by step
a download of the LTU program listed overleaf.
During this download, note the following parameters:
BYTECOUNT, START ADDRESS, CHECKSUM, and LTU STATUS.
Start the LTU execution and check result.
…0e… 2949A/rt
JJD/821012
CAMPS…0f…
LESSON NO: 9:4:1 - 9:4:6
TOPIC: HANDS-ON LTU
This small program will make the LTU flash the
test LED.
813E 73D3 D379 1E71 06FF 1OFF
1DFE F920 CBAF C261 001A E1CB
EA18 A1CB E618
Checksum: 0009
…0e… 2949A/rt
JJD/821012
LTU WORKASSIGNMENT
9:4:1 - 9:4:6
CAMPS…0f…
1. Select a LTU and verify by means of DAMU command
"UM" the RAM enable/disable command.
2. Write by means of MAP exerciser a pattern into
the upper two LTU RAM locations.
Verify by means of DAMU
3. Command by means of MAP exerciser the LTU to perform
a self-test and verify that the LTU interrupt the
CR80 when self-test is completed.
Use MAP RAM and the interrupt queue.
4. Enable the LTU onto one of the databusses and command
the LTU into bootload mode. Perform step by step
a download of the LTU program listed overleaf.
During this download, note the following parameters:
BYTECOUNT, START ADDRESS, CHECKSUM, and LTU STATUS.
Start the LTU execution and check result.
…0e… 2949A/rt
JJD/821012
CAMPS…0f…
LESSON NO: 9:4:1 - 9:4:6
TOPIC: HANDS-ON LTU
This small program will make the LTU flash the
test LED.
813E 73D3 D379 1E71 06FF 1OFF
1DFE F920 CBAF C261 001A E1CB
EA18 A1CB E618
Checksum: 0009
…0f… 2949A/rt
JJD/821012
LTU WORKASSIGNMENT
9:4:1 - 9:4:6
CAMPS…0e…
1. Select a LTU and verify by means of DAMU command
"UM" the RAM enable/disable command.
2. Write by means of I̲/̲O̲-commands "12" into LTU RAM
locations 0001 and 0003. Verify by means of m̲e̲m̲o̲r̲y̲
̲r̲e̲a̲d̲ ̲c̲o̲m̲m̲a̲n̲d̲s̲ (use DAMU or MAP Exerciser as you
prefer).
3. Try to write a word (= 2 bytes) into LTU RAM location
3FFF. Dump LTU RAM location 0 and 3FFF and explain
results.
4. Command by means of MAP exerciser the LTU to perform
a self-test and verify that the LTU interrupt the
CR80 when self-test is completed.
Use MAP RAM and the interrupt queue.
5. Enable the LTU onto one of the databusses and command
the LTU into bootload mode. Perform step by step
a download of the LTU program listed overleaf.
During this download, note the following parameters:
BYTECOUNT, START ADDRESS, CHECKSUM, and LTU STATUS.
Start the LTU execution and check result.
…0f… 2949/rt 9:4:1-9:4:6
JJD/830216
CAMPS…0e…
LESSON NO: 9:4:1 - 9:4:6
TOPIC: HANDS-ON LTU
This small program will make the LTU flash the
test LED.
813E 73D3 D379 1E71 06FF 1OFF
1DFE F920 CBAF C261 001A E1CB
EA18 A1CB E618
Checksum: 0009
…0e… 2949A/rt
JJD/821012
LTU WORKASSIGNMENT
9:4:1 - 9:4:6
CAMPS…0f…
1. Select a LTU and verify by means of DAMU command
"UM" the RAM enable/disable command.
2. Write by means of MAP exerciser a pattern into
the upper two LTU RAM locations.
Verify by means of DAMU
3. Command by means of MAP exerciser the LTU to perform
a self-test and verify that the LTU interrupt the
CR80 when self-test is completed.
Use MAP RAM and the interrupt queue.
4. Enable the LTU onto one of the databusses and command
the LTU into bootload mode. Perform step by step
a download of the LTU program listed overleaf.
During this download, note the following parameters:
BYTECOUNT, START ADDRESS, CHECKSUM, and LTU STATUS.
Start the LTU execution and check result.
…0e… 2949A/rt
JJD/821012
CAMPS…0f…
LESSON NO: 9:4:1 - 9:4:6
TOPIC: HANDS-ON LTU
This small program will make the LTU flash the
test LED.
813E 73D3 D379 1E71 06FF 1OFF
1DFE F920 CBAF C261 001A E1CB
EA18 A1CB E618
Checksum: 0009
…0e… 2949A/rt
JJD/821012
LTU WORKASSIGNMENT
9:4:1 - 9:4:6
CAMPS…0f…
1. Select a LTU and verify by means of DAMU command
"UM" the RAM enable/disable command.
2. Write by means of MAP exerciser a pattern into
the upper two LTU RAM locations.
Verify by means of DAMU
3. Command by means of MAP exerciser the LTU to perform
a self-test and verify that the LTU interrupt the
CR80 when self-test is completed.
Use MAP RAM and the interrupt queue.
4. Enable the LTU onto one of the databusses and command
the LTU into bootload mode. Perform step by step
a download of the LTU program listed overleaf.
During this download, note the following parameters:
BYTECOUNT, START ADDRESS, CHECKSUM, and LTU STATUS.
Start the LTU execution and check result.
…0e… 2949A/rt
JJD/821012
CAMPS…0f…
LESSON NO: 9:4:1 - 9:4:6
TOPIC: HANDS-ON LTU
This small program will make the LTU flash the
test LED.
813E 73D3 D379 1E71 06FF 1OFF
1DFE F920 CBAF C261 001A E1CB
EA18 A1CB E618
Checksum: 0009
…0e… 2949A/rt
JJD/821012
REVIEW QUIZ
9:5:1
CAMPS…0f…
1. How will CR80 and the LTU communicate during bootload?
2. Explain the shadow PROM concept
3. What purpose serves the comparator on the LTU blockdiagram?
4. How can CR80 verify that a LTU is alive during
operation?
5. How is LTU program execution started after a successfull
bootload?
6. Is data from LTU shared RAM provided with paritybits
when delivered on to CR80 system bus?
7. Explain two ways of accessing the LTU shared RAM.
8. What will happen if the LTU fails to download the
shared RAM contents into the system RAM?
9. What is the purpose of timer 3 on the LTU blockdiagram?
10. What effect would a NMI have on the LTU?
…0f… 2949A/rt
JJD/830216
FLOPPY DISC CONTROLLER
EXERCISE 9:5:3 - 9:5:5
CAMPS…0e…
1. Enable the floppy disc controller on to the BUS.
Issue a select drive command to one of the drives
and verify result by watching the drive door LED.
NOTE: it is necessary to use the repeater function
in DAMU and MAP EXERCISER to give a clear LED indication.
2. READ OUT status and explain result
3. Insert a discette into the drive and give a seek
track 76 and explain status
4. Clear the floppy controller buffer RAM
5. Write ABBA into the 10 lowest (location 0000 to
0009) RAM Buffer locations
6. Write the buffer RAM into track 10, sector 10
Read out status and explain
7. Write FFFF into the floppy controller
Buffer RAM
Read out status and explain
8. READ track 10, sector 10 back into floppy controller
RAM and dump the content on the console to verify
correct transfer
Read out status and explain
9. Verify the delete record/not delete
10. Verify that the FD sent an interrupt if a not-known
command is received
11. Verify that the MAP timer is reset if the real
interrupt is comming before ????? reach 0
12. Read back 64 words of DAMU that your stored by
floppy dump (done in week No. 8)
…0e… 2949A/rt
JJD/821012
FLOPPY DISC CONTROLLER
EXERCISE 9:5:3 - 9:5:5
CAMPS…0f…
1. Enable the floppy disc controller on to the BUS.
Issue a select drive command to one of the drives
and verify result by watching the drive door LED.
NOTE: it is necessary to use the repeater function
in DAMU and MAP EXERCISER to give a clear LED indication.
2. READ OUT status and explain result
3. Insert a discette into the drive and give a seek
track 76 and explain status
4. Clear the floppy controller buffer RAM
5. Write ABBA into the 10 lowest
RAM Buffer locations
6. Write the buffer RAM into track 10, sector 10
7. Write FFFF into the floppy controller
Buffer RAM
8. READ track 10, sector 10 back into floppy controller
RAM and dump the content on the console to verify
correct transfer.
…0e… 2949A/rt
JJD/821012
FLOPPY DISC CONTROLLER
EXERCISE 9:5:3 - 9:5:5
CAMPS…0f…
1. Enable the floppy disc controller on to the BUS.
Issue a select drive command to one of the drives
and verify result by watching the drive door LED.
NOTE: it is necessary to use the repeater function
in DAMU and MAP EXERCISER to give a clear LED indication.
2. READ OUT status and explain result
3. Insert a discette into the drive and give a seek
track 76 and explain status
4. Clear the floppy controller buffer RAM
5. Write ABBA into the 10 lowest
RAM Buffer locations
6. Write the buffer RAM into track 10, sector 10
7. Write FFFF into the floppy controller
Buffer RAM
8. READ track 10, sector 10 back into floppy controller
RAM and dump the content on the console to verify
correct transfer.
Instructors Manual for
RST Course, Week 9
CPS/TMA/013
Line Item 8.2.4.2
Jesper Jan Damgaard
Kurt Nybroe-Nielsen
SHAPE (3), NCS (1), ORP, PBP, CL, JJD,
BSP, KJA, Conf.Mgmt.
ILS Train.MGT. 821023
Preliminary
821023
…02…CPS/TMA/013
…02…JJD/821023…02……02…
INSTRUCTORS MANUAL FOR RST COURSE,
WEEK 9 …02…CAMPS
821023 All Prelim.Issue of Document
