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SEISMIC DATA
PROCESSING SYSTEM
1982-03-23
Page No. #
1. T̲E̲C̲H̲N̲I̲C̲A̲L̲ ̲S̲U̲M̲M̲A̲R̲Y̲
This note describes a Seismic Data Processing System
for Geophysical Company of Norway A.S.
Main System Functions are:
o Retrieval of data from HDDT
o High speed processing of Seismic data.
o Provision of a Quick Look display of data for monitoring
purposes.
o Generation of 6250 bpi tapes in SEG-D format.
Additionally
o Recording of data onto HDDT
o Retrieval of data from CCT
The technical solution is based on a state-of-the-art
multiprocessor computer system architecture implemented
with the latest technology. Using only few well defined
elements, implemented by standard equipment or microporcessor
units, a flexible modular approach has been chosen.
This results in an architecture with a large built-in
element of re-usability and adaptability for implementing
new processing algorithms and future product improvements.
Care has been taken to provide a reliable architecture
that can continue to function with lessened performance
after one or more basic element failures. Attention
has been paid in the design to the achievement of as
flexible a system as possible without sacrifice to
efficiency. Effective utilization of space has also
been considere and is guaranteed by compact packaging
The Seismic Data Processing System shown in figure
1 is to be considered as a baseline system, composed
of the following elements:
a) High Density Digital Recorders
b) Processing chain with
o File Processor
o Signal Processor(s)
o General Purpose Processor
o I/O Subsystem
c) 6250 bpi CCT recorders
d) Image Display
e) Operator's CRT/Console.
The shown system has comprehensive expansion capabilities,
as well for the processing (additional signal processors)
as for the I/O.
The file Processor performs the high level control
of HDDR retrieval and disk operations.
The signal processor is dedicated to fast Signal Processing.
Data are supplied from the File Processor in adequate
format, processed in the Signal Processor and subsequently
delivered to the General Purpose Processor which takes
care of the formatting and recording onto CCT.
The General Purpose Processor also handles the operator
communication and performs overall system status monitoring
and reporting.
2. S̲Y̲S̲T̲E̲M̲ ̲E̲L̲E̲M̲E̲N̲T̲S̲
2.1 F̲I̲L̲E̲ ̲P̲R̲O̲C̲E̲S̲S̲O̲R̲
The File Processor is shown in fig. 2.
o CPU's can be added as required to meet the performance
requirements.
o RAM modules, each with 128 Kwords can be added
to a maximum of one megaword.
o The STI establishes a fast DMA channel to the other
processors
o The MIA provides the DMA link to the I/O subsystem
o Dualized power supply assures trouble-free operation,
even with one power supply in failure
2.2 S̲I̲G̲N̲A̲L̲ ̲P̲R̲O̲C̲E̲S̲S̲O̲R̲
The signal processor is shown in fig. 3.
o A number of Floating Point Processor modules can
be attached to increase processing capacity
o Additional Signal Processors can be paralleled
on a single Suprabus or several buses in parallel.
2.3 I̲/̲O̲ ̲S̲U̲B̲S̲Y̲S̲T̲E̲M̲
An example of an I/O subsystem is shown in fig. 4.
o Dual-ported disks provides the means for simultaneous
high speed transfer to and from the disk medium.
In addition, disk availability is significantly
improved because most errors can be bypassed.
o The Line Termination Units (LTU) provides microprocessor
controlled termination of lines for oeprators console,
printers and other low to medium speed devices.
o The HDDR is connected through a microporcessor
controlled interface which autonomously perform
- start
- stop
- search for specific time code
- speed/density select
- positioning for read and write
- HDDR status monitoring
o A general-purpose parallel interface convey the
data to or from the HDDR
3. S̲P̲E̲C̲I̲A̲L̲ ̲M̲O̲D̲U̲L̲E̲S̲
3.1 H̲D̲D̲R̲ ̲C̲O̲N̲T̲R̲O̲L̲L̲E̲R̲
- Start
- Stop
- Speed select
- Forward/reverse wind
In addition, positioning based on a separate time code
track is provided. Remote Control is performed by
the dedicated HDDR Controller, located in the I/O Subsystem.
The HDDR controller is basicaly a subset of the controllers
previously delivered by Christian Rovsing A/S delivered
to ESOC and CEMS, Lannion. The controller is microporcessor-controlled
and performs all the basic control functions, and in
addition to this, establishes the interface to the
time code reader.
The controller accepts the following commands:
o R̲E̲A̲D̲ ̲s̲p̲e̲e̲d̲ ̲ The speed is selected and the controller
generates an interrupt when the Correct speed is
reached.
o M̲O̲V̲E̲ ̲d̲i̲s̲t̲a̲n̲c̲e̲,̲ ̲d̲i̲r̲e̲c̲t̲i̲o̲n̲ ̲ - The tape is moved in
the specified direction the specified distance.
The distance is measured by counting pulses, originating
from the capstan tachometer generator. The speed
is set according to the distance taking into account
the acceleration distance, and a stop command is
issued when within the estimated deceleration distance
to the desired point of tape. Tacho-pulses is
continuously tracked, and interaction is performed
if desired point is not rached the first time.
o W̲I̲N̲D̲ - Wind at highest possible speed (no servo
loop control).
o R̲E̲W̲I̲N̲D̲ - As wind, but reverse.
o S̲E̲A̲R̲C̲H̲ ̲T̲i̲m̲e̲ - Position tape at specified time,
using the time code track information. Search
includes the following steps:
a. Determine direction.
Read nearest time code, compare to destination
time code.
b. Determine approximate distance.
Difference in destination and read time code
gives an estimate of the distance. A low speed
is selected if short, highest speed --304.8
cm/sec-- if lkonger than the corresponding
acceleraton distance of approx. 30 meters.
This check is necessary in order to avoid
the situation of passing the destination time
code while the HDDR is accelerating, and thus
not being able to read properly.
c. Read and search for match.
Read and compare read time code to the specified.
When found, stop and count tacho-pulses to
determine deceleration distance.
d. Move back to point of match.
The interpretation of the read time code data takes
into account the possibility of bit errors by utilizing
the knowledge of the sequential nature of the time
code information for validations. The HDDR will stop
and an error message will be given if the specifid
time could not be found.
The error message includes the last validated time
code read on the tape.
The HDDR controller is a CR80D module implemented around
a microprocessor (ref. Figure 6). The microporcessor
executes high level commands issued fom the connected
processor via I/O bus A or B. The time code reader
input is available via a separate channel.
3.2 S̲P̲E̲C̲I̲A̲L̲ ̲F̲L̲O̲A̲T̲I̲N̲G̲ ̲P̲O̲I̲N̲T̲ ̲P̲R̲O̲C̲E̲S̲S̲O̲R̲ ̲
The special Floating Point Processor (SFPP) is a special
CR80D module designed for high speed resampling. It
behaves like an active memory seen from other CR80D
modules in the Image Processor.
The modules architecture, based upon a common internal
bus structure, the FP bus, for the basic elements,
allows for simultaneous processing with a resulting
high performance
As seen in tbe block diagram, Figure 7 the module contains
the following three basic elements:
o Shared Memory (SM)
o Central Processor Unit (CPU)
o Arithmetric Processor Unit (APU)
Communication of data and commands between the active
elements of the SFPP and the CR80D system is performed
via the shared memory. This shared memory contains
two RAM areas. A local 64K words 16-bit accessible
from the Processor bus and from the internal FP bus
as well as a 256 words instruction RAM for the CPU.
The instruction RAM is a mirror of the lowest 256 words
of the local 64K RAM. This means that the access time
to the local 64K RAM from e.g. a CR80D CPU/CACHE via
the Processor bus is not reduced, when the SFPP CPU
performs instruction fetches and visa versa.
The CPU design is absed upon the existing CR80D design
with an instruction set adapted to the application.
The CPU interface to the internal 16-bits bus (FP
bus) is used for instruction, data and address transfer,
while the interface to the CR80D Channel bus is used
for interrupt and SFPP restart.
The CPU operates in parallel with the Arithmetric Processing
Unit (APU). Thus, loading of new data and command
sequences to the APU as well as manipulation of data
in the shared memory can be performed simultaneously
with the arithmetric operations taking place in the
CPU elemnt.
The Arithmetric Processor Unit (APU) performs all floating
point operations based upon commands and data in the
256 x 32 bits RAM. The APU contains three arithmetric
elements, two Arithmetric Logic Unit (ALU) elements,
one for 8-bit exponent operation and one for 24-bit
mantissa operation as well as a 24 x 24 bits multiplier.
These elements are designed with high speed LSI circuits
allowing for a cycle time as low as 375 nsec. The
Arithmetric Controller executes sequences of floating
point instructions in accordance with the command strings
loaded from the CPU into the 256 x 32 bit RAM
Data types:
Real:
S:E7...E0:Fl.............................F23
Integer:
I15 .......................I0
3.3 D̲A̲T̲A̲ ̲D̲E̲M̲U̲L̲T̲I̲P̲L̲E̲X̲E̲R̲
A dedicated Data Demultiplexer module can be designed
to establish the interface between the HDDR and the
Processing System if high speed is a prime requirement.
See figure 8.
