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IDCN - VOLUME II
SYS/83-11-18
TECHNICAL PROPOSAL
Page
2 HARDWARE DESCRIPTION ..........................
2.1 NODE SYSTEM - GENERAL DESCRIPTION ..........
2.1.1 Introduction ...........................
2.1.2 Hardware Architecture ..................
2.1.3 Rack Layout ............................
2.1.4 CR80M Main Processor ...................
2.1.4.1 CR80 General Description ...........
2.1.4.1.1 The Processor Units (PU) .......
2.1.4.1.2 The Channel Units (CU) .........
2.1.4.1.3 Bus Structure ..................
2.1.4.1.4 Watchdog System ................
2.1.4.1.5 The TDX Subsystem ..............
2.1.4.1.5.1 General ....................
2.1.4.1.5.2 TDX Subsystem Description ..
2.1.4.1.5.3 The TDX Bus ................
2.1.4.1.5.4 The Bus Protocols and
Frame Format ...............
2.1.4.1.5.5 The STI/TIA Modules ........
2.1.4.1.5.6 The TDX Crate ..............
2.1.4.1.5.7 The TDX Controller .........
2.1.4.1.5.8 The LTUX-S .................
2.1.4.1.5.9 The BTM-X ..................
2.1.4.1.5.10 The Power Supply ..........
2.2 NODE SYSTEM CONFIGURATION ..................
2.2.1 NODE Processor Units ...................
2.2.2 NODE Channel Units .....................
2.2.3 NODE TDX Units .........................
2.3 PERIPHERAL EQUIPMENT .......................
2.3.1 System Console .........................
2.3.2 Disk Drives, MMD and SMD ...............
2.3.3 Tape Drives ............................
2.4 SCC SYSTEM .................................
2.4.1 Introduction ...........................
2.4.2 Hardware Architecture ..................
2.4.3 Rack Layout ............................
2.4.4.1 SCC Processor Unit .................
2.4.4.2 SCC Channel Unit ...................
2.4.4.3 SCC TDX-Unit .......................
2.4.5 System Console .........................
2.4.6 Disk Drive MMD .........................
2.4.7 Single Floppy Disk Station .............
2 H̲A̲R̲D̲W̲A̲R̲E̲ ̲D̲E̲S̲C̲R̲I̲P̲T̲I̲O̲N̲
2.1 N̲O̲D̲E̲ ̲S̲Y̲S̲T̲E̲M̲ ̲G̲E̲N̲E̲R̲A̲L̲ ̲D̲E̲S̲C̲R̲I̲P̲T̲I̲O̲N̲
2.1.1 I̲n̲t̲r̲o̲d̲u̲c̲t̲i̲o̲n̲
In the following subsections the units of the proposed
system will be described in details. Each functional
module within the units will be identified.
Peripherals and terminals included in the proposed
system are also described in the following subsections.
2.1.2 H̲a̲r̲d̲w̲a̲r̲e̲ ̲A̲r̲c̲h̲i̲t̲e̲c̲t̲u̲r̲e̲
The architecture of the Nodal hardware system proposed
for the Israeli Data Communication Network (IDCN) is
presented in Fig. 2.1.2-1. The NODE is containing the
hardware for the NODE/MEDE functions described in the
system description, chapter 3.
The system is specially tailored to meet the IDCN requirements
using the CR 80 Fault Tolerant Multiprocessor System
(Fatom).
The system includes 2 Processor Units, PU # 1 and PU
#2.
The two PU's are identical, each containing 1 Megaword
Main Memory and 2 CPU's with separate cache memory,
designed to provide a high performance processor unit.
Each PU has interface controllers to the buses connecting
to the two types of input/output - units:
- Channel Units (CU's)
- TDX Units (TU's)
Both Unit types are connected to provide a multiple
unit redundancy design, i.e. each unit is a selfstanding
unit with dual input, but all units of each type are
identically and are providing mutually back-up.
Failures in an CU/TU will not effect the function and
performance of the other units.
Each PU has access to the CU and the TU's. Normally
one PU is active and the other is stand-by, both monitored
and controlled by the Watchdog processor.
In case of failures will the Watchdog processor perform
automatical switch-over to the stand-by processor.
On fig. 2.1.2-1 is indicated how the connectivity requirement
is met by allocating the input/output channels of the
TU's and CU to the various input/output devices.
The CR80 processor system has been developed within
the last 3 years and represents latest state-of-the-art
in technology and is unique in performance and architecture.
The CR80 processors have already been used in many
applications where continous, reliable operation is
required and have proven excellent performance.
2.1.3 R̲a̲c̲k̲ ̲L̲a̲y̲o̲u̲t̲
The proposed Rack Layout is shown on fig. 2.1.3-1.
The units presented in fig. 2.1.2-1 can be identified
as separate physical units placed in the racks.
Each rack has an individual mains switch and the design
of the units - and the racks provides a good, structured
appearance, with good ergonomic features and easy maintenance
access.
The signal cables for external connections are all
terminated on standard connectors on each Input/Output-unit.
The Disk Drive for off-line storage is enclosed in
a separate cabinet.
If however, closer analysis shows that the capacity
can be reduced from the 300 MB proposed to 80 MB it
will be possible to use a drawer-mounted version as
is the case for the two other disk drives.
Figure 2.1.2-1…01…NODAL SYSTEM OVERVIEW; HARDWARE
Figure 2.1.3-1…01…NODE RACK LAYOUT
2.1.4 C̲R̲8̲0̲M̲ ̲M̲a̲i̲n̲ ̲P̲r̲o̲c̲e̲s̲s̲o̲r̲
The processor is constructed based on CR80 system elements.
2.1.4.1 C̲R̲8̲0̲ ̲G̲e̲n̲e̲r̲a̲l̲ ̲D̲e̲s̲c̲r̲i̲p̲t̲i̲o̲n̲
The Main Processor is constructed by means of the modular,
fault-tolerant CR80 computer system by use of various
standard modules (Printed Circuit Boards) organized
in units which are interconnected by galvanic isolated
transfer buses structured as illustrated below, and
shortly described in the following.
The CR80 system units are housed in 19" crates (Card
Magazine) for installation in standard 19" racks as
shown in Fig. 2.1.4.1-1 below.
Fig. 2.1.4.1-1…01…CR80 PROCESSOR UNIT & CHANNEL UNIT
2.1.4.1.1 T̲h̲e̲ ̲P̲r̲o̲c̲e̲s̲s̲o̲r̲ ̲U̲n̲i̲t̲s̲ ̲(̲P̲U̲)̲
The Main Site equipment contains two identical Processor
Units (PUs), see fig. 2.1.4.1-2. The two PUs are placed
in redundant elements in the configuration. One set
of redundant elements is composed of PU #1, Data Channel
A, the Channel Interface Adapter (CIA-A) and I/O Bus
A (including the connected Power module).
The other set of redundant elements is PU #2, Data
Channel B, CIA-B and I/O-Bus B.
FIG. 2.1.4.1-2
PROCESSOR UNIT…86…1 …02… …02… …02… …02…
2.1.4.1.2 T̲h̲e̲ ̲C̲h̲a̲n̲n̲e̲l̲ ̲U̲n̲i̲t̲s̲ ̲(̲C̲U̲)̲
The Channel Units contain the CR80 I/O controller modules
for interfacing towards peripheral equipment, communication
lines etc. The CU has an internal dual transfer bus
structure to ensure that no single failure can stop
operation of more than one I/O controller as shown
in figure, 2.1.4.1-3.
FIG. 2.1.4.1-3
CHANNEL UNIT…86…1 …02… …02… …02… …02…
The transfer buses, data bus A and data bus B, are
connected to two different PU's to ensure continuous
access to the controller modules (CTRL, LTU). The characteristics
of data bus A and data bus B correspond to the internal
buses of the PU.
The CIA-modules constitute the interface between the
word oriented internal transfer buses and the byte
oriented data channels.
The I/O controller modules are all based on the same
principle for interfacing to the channel unit bus structure
and for the external interfaces as illustrated in FIG.
2.1.4.1-4.
FIG. 2.1.4.1-4
CHANNEL UNIT INTERFACE…86…1 …02… …02… …02… …02…
The interface to the CR80 system employs a multiported
RAM memory through which the data is exchanged. The
program for the controller module CPU is resident in
PROM chips.
The physical interface to the peripherals is an adapter
module located at the rear of the CU Crate. As the
internal bus structure is dualized, the power input
is taken from two separate sources to ensure that a
failure in one power source cannot stop the CU Operation.
2.1.4.1.3 B̲u̲s̲ ̲S̲t̲r̲u̲c̲t̲u̲r̲e̲
A CR80 computing system is organized around several
buses, which are described in this section.
A schematic overview showing the interconnection of
the different buses and units are given in FIG. 2.1.4.1-5.
Fig. 2.1.4.1-5…01…CR80 BUS STRUCTURE
Internal in a Processing Unit two buses are available
for data transfer. Electrically and functionally they
are identical, the only differences are related to
the type of module which are connected to them.
To the Processor Bus, the CPU's and Memory are connected,
and to the Channel Bus, DMA modules and memory are
connected.
The two buses are located on each motherboard, mounted
in the back of the PU-Crate.
Internal in a Channel Unit two buses are used for data
transfer, Data Bus A and Data Bus B. The buses are
identically, and further use the same signals as the
Processor and Channel Buses. These two buses are located
on each motherboard, mounted in the back of the CU-crates.
The Data Channel is a flat cable bus connecting one
Processing Bus and one Channel Bus (located in the
same PU) with one or more Data Buses (located in one
or more CU's).
This is done by means of the Data Channel interface
modules (MAP-MIA), CIA-A & CIA-B.
2.1.4.1.4 W̲a̲t̲c̲h̲d̲o̲g̲ ̲S̲y̲s̲t̲e̲m̲
The Watchdog (WD) consists of four parts:
o A WD panel/relay module
o A WD CPU
o A WD Back Panel
o A Operator Console
The interconnection is shown below:
FIG. 2.1.4.1-6
WATCHDOG INTERFACE
2.1.4.1.5 T̲H̲E̲ ̲T̲D̲X̲ ̲S̲U̲B̲S̲Y̲S̲T̲E̲M̲
2.1.4.1.5.1 G̲e̲n̲e̲r̲a̲l̲
This section will provide a description of each of
the functional modules/elements within the TDX.
2.1.4.1.5.2 T̲D̲X̲ ̲S̲u̲b̲s̲y̲s̲t̲e̲m̲ ̲D̲e̲s̲c̲r̲i̲p̲t̲i̲o̲n̲
The TDX consists of:
- The dualized TDX bus, TDX bus#1 and TDX bus#2 each
with two associated TDX controller.
- Interface modules to the Processor Units (STI/TIA)
- TDX Units (TU). The number of TDX Units is determined
by the application.
The TDX Units hold the TDX modules:
- The LTUX-S (TDX Line Termination Unit)
- The BTM-X (TDX Bus Termination module)
Each TDX Unit connected on the TDX bus provides an
output capacity of 32 communication channels in its
max. configuration.
Each channel conforms with the CCITT V24/V28 and the
EIA RS-232C specifications.
The following mechanical dimensions will be referred
to as either standard CR80S module or standard CR80S
19" frame where applicable.
Figure 2.1.4.1.5-1…01…TDX Subsystem Interfaces
2.1.4.1.5.3 T̲h̲e̲ ̲T̲D̲X̲ ̲B̲u̲s̲
The TDX bus, which links the Processor subsystem and
the TDX Units, is essentially a high data rate digital
link. Data is transferred across the link in serial
form at a clock rate of 1.8432 MHz.
Data and clock are transferred on the TDX bus using
the self clocking differential split phase code SPL-D.
The SPL-D code changes the signal level at the start
of each bit-cell, and also in the middle of a bit-cell
if the transmitted data is zero. This is shown in figure
2.1.4.1.5-2. The SPL-D code allows data and clock to
be transmitted on the same line.
Transmitting the clock together with the data on the
TDX bus has several advantages.
The major advantage is that TDX bus delay has no significance
for the correct decoding, because clock and data are
delayed equally. Also, no need exists to synchronize
a receiver to a transmitter.
A second advantage is that the TDX controller clock,
being continuously transmitted on the Lower Bus (explained
later in this para.), is made available to all connected
TDX devices.
All TDX bus activities, such as communication scheduling
and synchronization of connected devices, are governed
by a TDX controller.
Figure 2.1.4.1.5-3 shows schematically the connection
of devices and the controller to the TDX bus. As shown
a TDX bus is physically 2 buses, a Lower Bus and an
Upper Bus. The TDX bus devices (LTUX-S and TIA are
connected with the receiver to the Lower Bus and the
transmitter to the Upper Bus. The TDX controller is
connected with the receiver to the Upper Bus and the
transmitter to the Lower Bus. Thus a transfer of data
between two TDX devices is carried out in two phases:
1) Data is transmitted by the source device and received
by the TDX controller (Upper Bus).
2) Data is retransmitted by the TDX controller on
the Lower Bus and received by the destination device.
Figure 2.1.4.1.5-2…01…The SPL-D Code
Figure 2.1.4.1.5-3…01…TDX Bus Connections
Communication scheduling implies that TDX devices only
can transmit on the Upper Bus when selected to do so.
Selection is carried out by the TDX controller.
A maximum of 255 TDX devices can be connected to the
TDX bus. Among these 255 TDX devices the TIA, which
is the TDX bus interface towards a Processor Unit,
is limited to a maximum of 12.
The LTUX-S interfaces the TDX bus via the BTM-X module.
2.1.4.1.5.4 T̲D̲X̲ ̲B̲u̲s̲ ̲P̲r̲o̲t̲o̲c̲o̲l̲s̲ ̲a̲n̲d̲ ̲F̲r̲a̲m̲e̲ ̲F̲o̲r̲m̲a̲t̲
The software, firmware, and hardware of the TDX may
be divided into 4 levels as shown on fig. 2.1.4.1.5-4.
The Host Computer referenced corresponds to a Processor
Unit within the Processor subsystem and the Host I/F
corresponds to the STI/TIA complex within this Processor
Unit.
Information is transferred across the TDX bus in packets.
Each packet contains one or more frames. A frame is
the smallest information block on the bus. A frame
format is shown on fig. 2.1.4.1.5-5.
The protocol levels are explained as:
L̲e̲v̲e̲l̲ ̲1̲:̲
This level is handled by the Front-Ends in the TDX
devices and by the TDX controller. The Front-End is
the interface between the TDX bus and the TDX-packet
protocol routines.
The controller polls the TDX devices according to a
MUX-table. If a Front-End recognizes its device-number
in the MUX-field of the frame on the Lower Bus, and
a frame containing data is transferred from packet
level to the Front-End, it starts a frame transmission
on the Upper Bus. If no frame is ready, the Front-End
does nothing.
Concerning reception the Front-End compares its device-number
to the device number in the CR-ID field of the frames
on the Lower Bus. If a match is found the frame is
transferred to packet level.
The third and last task of the frame level is to detect
bit errors. This is done through a CRC check. If any
error is detected the frame is discarded in the receiving
Front-End. It is left to the TDX-packet level to recover
from the error.
Figure 2.1.4.1.5-4…01…TDX Protocol Levels
Figure 2.1.4.1.5-5…01…TDX Bus Frame Format
L̲e̲v̲e̲l̲ ̲2̲:̲
The TDX-packet protocol serves communication between
two TDX devices of any type. This can be TIA to TIA,
TIA to LTUX-S or LTUX-S to TIA. Packets may consist
of a variable number of frames less than e.g. 8. The
packet protocol makes use of byte 4 and 5 in the frame
format, which contain communication control, sequence
number and data byte count. A connection between two
TDX devices is always made for transmission in both
directions. The TDX-packet protocol goes only one step
back, which means that only one packet is transmitted
between the reception of two acknowledges (ACKs). In
multiframe packets, frames are numbered sequentially
modulo 8. In this way missing frames are detected,
and by a not-acknowledge (NACK) response, a retransmission
of the erroneous packet is performed. If an error occurs
in the transmission of a single frame packet the missing
response will cause a retransmission. A timer in the
transmitter initiates retransmission of packet N in
case neither ACK nor NACK is received within a specified
time (e.g. lost due to error of the link); transmission
is attempted three times before the protocol gives
up on output.
L̲e̲v̲e̲l̲ ̲3̲:̲
This level serves the I/F between application routines
and the TDX system. This includes set-up and deletion
of TDX channels, change in the assigned TDX-channel
band width, transfer of data buffers and actions upon
unrecoverable transmission errors.
L̲e̲v̲e̲l̲ ̲4̲:̲
Application level which includes all user defined routines
resident in LTUX-S's or in the Processor Subsystem.
2.1.4.1.5.5 T̲h̲e̲ ̲S̲T̲I̲/̲T̲I̲A̲ ̲M̲o̲d̲u̲l̲e̲s̲
Via the STI (Supra-TDX bus Interface) and the TIA (Telecommunication
Interface Adapter), the CR80D system is able to access
an external bus structure, the TDX bus (Telecommunication
Data Exchange bus).
The STI interfaces directly to the CR80D Channel Bus
while the TIA is the front end towards the TDX bus.
Connection between the two is done by a flat cable
bus called the HI bus (Host Interface Bus, fig. 2.1.4.1.5-6).
Fig. 2.1.4.1.5-6…01…STI/TIA CONNECTION
T̲h̲e̲ ̲T̲I̲A̲ ̲M̲o̲d̲u̲l̲e̲
The TIA is acting as the CR80D front end for the TDX
BUS.
The TIA interfaces to the TDX BUS via tristate drivers
and receivers. The encoder/decoder circuit converts
the serial data stream to a number of parallel data
bytes. Data coming from the TIA is converted from
parallel to serial code and synchronized to a clock
extracted from the received data.
T̲h̲e̲ ̲S̲T̲I̲ ̲M̲o̲d̲u̲l̲e̲
The block diagram of the STI is shown on fig. 2.1.4.1.5-7.
Fig. 2.1.4.1.5-7
THE STI MODULE
The Main Control Circuit part of the STI, including
the Channel Bus interface, provides the connection
between the CR80D Channel Bus and the internal HI bus.
Two main functions are handled by this circuit, namely:
a) the CR80D access to the central RAM
b) the DMA transfer from CR80D to front ends and vice
versa.
2.1.4.1.5.6 T̲h̲e̲ ̲T̲D̲X̲ ̲C̲r̲a̲t̲e̲
The TDX modules, the LTUX-S and the BTM-X, are housed
in a standard CR80S 19" frame, the TDX Crate, fig.
2.1.4.1.5-8.
The TDX Crate consists of a front crate and a rear
crate. On the back panel of the front crate is a bus
motherboard (Printed Circuit board) for module interconnection
and also edgeconnectors for the front crate mounted
modules.
Fig. 2.1.4.1.5-9 shows the normal TDX module.
FIG. 2.1.4.1.5-8
CR80S CRATE
FIG. 2.1.4.1.5-9…01…TDX MODULE
2.1.4.1.5.7 T̲h̲e̲ ̲T̲D̲X̲ ̲C̲o̲n̲t̲r̲o̲l̲l̲e̲r̲
The TDX Controller, figure 2.1.4.1.5-10, is the control
device of the TDX bus system. Through it passes all
data between the TDX devices.
The serial TDX bus is clocked and synchronized by the
TDX Controller. The TDX Controller outputs a continuous
bit stream of 1.8432 Mbit/second on the Lower Bus.
This stream is divided into 6400 time slots/second,
each time slot containing 288 bits.
Each time slot on the Lower Bus contains a standard
HDLC frame with control information (5 bytes), DATA
to be transferred (16 bytes), and CCITT-16 Cyclic Redundancy
Check (CRC, 2 bytes). The HDLC frame starts at the
beginning of a time slot and takes up maximally 236
bits of the 288 bits in the time slot.
The controller inserts as the first byte after the
start-FLAG a MUX NO. byte taken from a MUX NO. REGISTER
on the controller. All connected TIAs and LTUX-Ss look
at this byte. If it corresponds to the device number
of a TIA or a LTUX-S this device has the use of the
Upper Bus for data transmission at the end of the frame
(actually at bit count 241) on the Lower Bus. This
ensures that only one device will transmit on the Upper
Bus at any time. If the selected device has no data
to transmit, no frames will be transmitted on the Upper
Bus during that time slot.
The bandwidth assigned to each device at initialization
time by the MUX NO. TABLE is dynamically changeable
in real time, by request from device to controller.
A frame transmitted on the Upper Bus is received by
the TDX Controller. If the destination is not the controller,
the frame is "opened up", MUX NO. added as first byte,
CRC recomputed and the frame is then transmitted with
a one frame delay on the Lower Bus.
If the destination of an Upper Bus frame is the controller
(e.g. request for bandwidth change) or if no frame
is transmitted by the polled device, the controller
can utilize the then free time slot on the Lower Bus
in a "cycle stealing" manner to output device control
information (e.g. acknowledge of bandwidth change request
to a device) or data frames on the Lower Bus. If no
data is awaiting transmission a dummy frame will be
transmitted.
Figure 2.1.4.1.5-10…01…THE TDX CONTROLLER
Transmission is continuous on the Lower Bus, thereby
making it possible to use the highly stable clock of
1.8432 MHz as a master clock for the devices.
2.1.4.1.5.8 T̲h̲e̲ ̲L̲T̲U̲X̲-̲S̲
The LTUX-S provides 4 V24/V28 communication channels.
On the front panel are four switches that can be used
to enable/disable each of the four communication channels.
The LTUX-S is built around a standard microprocessor
using standard microprocessor interface LSIs as interface
between the TDX bus and the user applications.
Communication characteristics can be set individually
for each channel with the exception of communication
speed (Baudrate). This can be set for 2 channels at
a time, i.e. channel 1 and 2 will run at the same baudrate
and so will channel 3 and 4.
TDX Bus Interface
The LTUX-S provides up to 16 full duplex individual
logic channels between the user application and the
TDX bus. The microprocessor supports both application
processing of the TDX interface, TDX protocol and TDX
channel set-up. The sum of bandwidth assigned to the
logic channels through the LTUX-S is dynamically changeable
by request to the TDX Controller.
2.1.4.1.5.9 T̲h̲e̲ ̲B̲T̲M̲-̲X̲
The Bus-Termination Module BTM-X is used for connectting
the TDX-bus to the motherboard in LTUX crates.
Also the BTM-X gives a possibility of distributing
the TDX-bus in a rack with several LTUX-crates.
2.1.4.1.5.10 T̲h̲e̲ ̲P̲o̲w̲e̲r̲ ̲S̲u̲p̲p̲l̲y̲
The TDX Crate power supply is a standard CR80S module.
The Power Supply provides 3 regulated power outputs:
- + 5 Volt
- + 12 Volt
- - 12 Volt
The regulated outputs are galvanic isolated from the
mains supply and frame ground.
The +5 Volt power supply is a 20 KHz push-pull converter
operating directly on the rectified mains voltage.
The +12 Volt and -12 Volt power supplies are fed from
a full wave rectified transformer output.
The +12 Volt power supply is regulated by a conventional
PWM (Pulse Width Modulated) regulator.
The -12 Volt power supply is regulated by a PWM regulator.
P̲o̲w̲e̲r̲ ̲S̲u̲p̲p̲l̲y̲ ̲F̲e̲a̲t̲u̲r̲e̲s̲
- Output maintained during one missing mains supply
cycle
- Efficiency at maximum load better than 72%
- Constant current limit short circuit protection
- Over voltage protection
- Parallelling of more power supplies possible without
derating
- Remote error sensing facility
2.2 N̲O̲D̲E̲ ̲S̲Y̲S̲T̲E̲M̲ ̲C̲O̲N̲F̲I̲G̲U̲R̲A̲T̲I̲O̲N̲ ̲
2.2.1 N̲O̲D̲E̲ ̲P̲r̲o̲c̲e̲s̲s̲o̲r̲ ̲U̲n̲i̲t̲s̲
In section 2.1.4.1 was provided a general description
of the structure of the CR80 fault tolerant processor
system.
Fig. 2.2.1-1 shows the actual configuration of the
two identically equipped NODE Processor Units.
FIG. 2.2.1-1
NODE PROCESSOR UNIT PU#1,2
2.2.2 N̲O̲D̲E̲ ̲C̲h̲a̲n̲n̲e̲l̲ ̲U̲n̲i̲t̲s̲
In section 2.1.4.1 was provided a general description
of the structure of the CR80 fault-tolerant processor
system.
Fig. 2.2.2-1 shows the actual configurations of the
NODE Channel Unit.
FIG. 2.2.2-1
NODE CHANNEL UNIT
CU
2.2.3 N̲O̲D̲E̲ ̲T̲D̲X̲ ̲U̲n̲i̲t̲s̲
In section 2.1.4.1 was provided a general description
of the structure of the CR80 fault tolerant processor
system.
Figs. 2.2.3-1 to 2.2.3-5. show the actual configurations
of the NODE TDX Units.
Figure 2.2.3-1…01…NODE TDX-UNIT #1
Figure 2.2.3-2…01…NODE TDX-UNIT #2
Figure 2.2.3-3…01…NODE TDX-UNIT #3, 4, 5, 6
Figure 2.2.3-4…01…NODE TDX-UNIT #7
Figure 2.2.3-5…01…NODE TDX-UNIT #8
2.3 P̲E̲R̲I̲P̲H̲E̲R̲A̲L̲ ̲E̲Q̲U̲I̲P̲M̲E̲N̲T̲
2.3.1 S̲y̲s̲t̲e̲m̲ ̲C̲o̲n̲s̲o̲l̲e̲
The system console terminal are connected to the Watchdog
Processor.
The system console functions are handled on a Matrix
Printer with Keyboard CR 8391.
If the dualized processor system is split into two
stand-alone systems can the system console terminal
be connected directly to each PU without modifications.
2.3.2 D̲i̲s̲k̲ ̲D̲r̲i̲v̲e̲s̲,̲ ̲M̲M̲D̲ ̲a̲n̲d̲ ̲S̲M̲D̲
a) Two CDC MMDs, type 9730-80, are connected to the
processor system through the Channel Unit.
The two disks are operated as mirrored disk and
are connected to the Channel Unit to support the
completely dualized Processor configuration.
The MMDs are random access storage devices, which
use fixed sealed modules as the storage medium.
b) The two CDC SMDs, type 9766 is connected to the
Processor system.
The two disks are operated as mirrored disk and
are connected to the Channel Unit to support the
completely dualized Processor configuration.
The SMD is a random access rotating memory which
uses removable disk packs as storage media.
2.3.3 T̲A̲P̲E̲ ̲D̲R̲I̲V̲E̲S̲
The two Pertec FT 8000 Tape Stations are connected
to the processor system through the Channel Unit.
2.4 S̲C̲C̲ ̲S̲Y̲S̲T̲E̲M̲
2.4.1 I̲n̲t̲r̲o̲d̲u̲c̲t̲i̲o̲n̲
In the following subsections the units of the proposed
centralized supervision and control system SCC will
be described.
2.4.2 H̲a̲r̲d̲w̲a̲r̲e̲ ̲A̲r̲c̲h̲i̲t̲e̲c̲t̲u̲r̲e̲
The architecture of the SCC hardware proposed is presented
in fig. 2.4.2-1.
The SCC system is a non dualized system with 1 Processor
Unit, PU.
The PU has interface controllers to the buses connecting
the two types of input/output - units:
- Channel to Units (CU's)
- TDX Units (TU's)
On fig. 2.4.2-1 is indicated how the connectivity requirement
is met by allocating the input/output channels of the
TU and the CU to the various input/output devices.
2.4.3 R̲a̲c̲k̲ ̲L̲a̲y̲o̲u̲t̲
The proposed Rack Layout is shown on fig. 2.4.3-1.
The units presented in fig. 2.4.2-1 can be identified
as separate physical units placed in the racks.
FIGURE 2.4.2-1…01…SCC SYSTEM OVERVIEW, HARDWARE
FIGURE 2.4.3-1…01…SCC RACK LAYOUT
2.4.4.1 S̲C̲C̲ ̲P̲r̲o̲c̲e̲s̲s̲o̲r̲ ̲U̲n̲i̲t̲s̲
In section 2.1.4-1 was provided a general description
of the structure of the CR80 fault tolerant processor
system.
Fig. 2.4.1-1 shows the actual configuration of the
equipped SCC Processor Units.
FIGURE 2.4.4.1-1…01…SCC SPROCESSOR UNIT
2.4.4.2 S̲C̲C̲ ̲C̲h̲a̲n̲n̲e̲l̲ ̲U̲n̲i̲t̲s̲
In section 4.2.1.4.1 was provided a general description
of the structure of the CR80 fault-tolerant processor
system.
Figs. 2.4.4.2-1 show the actual configurations of the
SCC Channel Unit.
FIGURE 2.4.4.2-1…01…SCC CHANNEL UNIT
2.4.4.3 S̲C̲C̲ ̲T̲D̲X̲ ̲U̲n̲i̲t̲s̲
In section 2.1.4.1 was provided a general description
of the structure of the CR80 fault tolerant processor
system.
Figs. 2.4.4.3-1 show the actual configurations of the
SCC TDX Unit.
FIGURE 2.4.4.3-1…01…SCC TDX UNIT
2.4.5 S̲y̲s̲t̲e̲m̲ ̲C̲o̲n̲s̲o̲l̲e̲
The system console terminal are connected to the Processor
Unit.
The system console functions are handled on a Matrix
Printer with Keyboard CR 8391. (See section 3.2.5).
The colour TV-monitor mentioned in chapter 3 is not
a part of the proposal.
2.4.6 D̲i̲s̲k̲ ̲D̲r̲i̲v̲e̲s̲,̲ ̲M̲M̲D̲
a) One CDC MMDs, type 9730-80, are connected to the
processor system through the Channel Unit.
The MMDs are random access storage devices, which
use fixed sealed modules as the storage medium.
2.4.7 S̲i̲n̲g̲l̲e̲ ̲F̲l̲o̲p̲p̲y̲ ̲D̲i̲s̲k̲ ̲S̲t̲a̲t̲i̲o̲n̲
One single floppy disk station - type CR8308 - is connected
to the main processors. This station is used mainly
for loading of Maintenance and Diagnostics Software.
