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Notes: CPS/TPR/049
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…02…CPS/TPR/049
FACTORY ACCEPTANCE TEST SPECIFICATION…02…840630…02……02…
AND PROCEDURES, SITE 11
…02……02…CAMPS
T̲A̲B̲L̲E̲ ̲O̲F̲ ̲C̲O̲N̲T̲E̲N̲T̲S̲
1 GENERAL .......................................
1
1.1 PURPOSE ...................................
1
1.2 APPLICABLE DOCUMENTS ......................
1
1.3 LIST OF INSPECTION AND TEST PROCEDURES ....
2
1.4 TERMS AND ABBREVIATIONS ...................
4
2 TEST SPECIFICATION AND EVALUATION .............
6
2.1 TEST SPECIFICATION ........................
6
2.1.1 Test Purpose ..........................
6
2.1.2 Test Object Identification ............
6
2.1.3 Requirements ..........................
6
2.1.4 System Function .......................
7
2.1.5 Test/Function Relationship ............
7
2.1.6 Test Ground Rules .....................
8
2.2 TEST METHODS AND CONSTRAINTS ..............
8
2.2.1 System Test Conditions ................
8
2.2.2 Extent of System Test .................
9
2.2.3 Data Recording ........................
9
2.2.4 System Test Constraints ...............
10
2.2.5 Test Location .........................
10
2.3 TEST EVALUATION ...........................
10
3 TEST DESCRIPTION AND PROCEDURES ...............
11
3.1 TEST GROUP NO. 1 ..........................
11
3.1.1 General Description ...................
11
3.1.2 Verification Cross Reference Index
(VCRI) ................................
11
3.1.3 Test Procedure ........................
11
3.1.3.1 Test Set Up .......................
11
3.1.3.2 Test Initialization ...............
11
3.1.3.3 Test Steps ........................
11
3.2 TEST GROUP NO. 2 ..........................
14
3.2.1 General Description ...................
14
3.2.2 Verification Cross Reference Index
(VCRI) ................................
21
3.2.3 Test Procedures .......................
23
3.2.3.1 Test Procedure 1 ..................
23
3.2.3.1.1 Test Set Up ...................
23
3.2.3.1.2 Test Initialization ...........
28
3.2.3.1.3 Test Steps ....................
29
3.2.3.1.4 Test Termination ..............
71
3.2.3.2 Test Procedure 2 ..................
72
3.2.3.2.1 Test Set Up ...................
72
3.2.3.2.2 Test Initialization ...........
77
3.2.3.2.3 Test Steps ....................
78
3.2.3.2.4 Test Termination ..............
120
3.2.3.3 Test Procedure 3 ..................
121
3.2.3.3.1 Test Set Up ...................
121
3.2.3.3.2 Test Initialization ...........
128
3.2.3.3.3 Test Steps ....................
128
3.2.3.3.4 Test Termination ..............
181
APPENDIX A Test Command Sequence ................
APPENDIX B Test Results .........................
APPENDIX C H/W Checklist.........................
1̲ ̲ ̲G̲E̲N̲E̲R̲A̲L̲
1.1 P̲U̲R̲P̲O̲S̲E̲
The purpose of this document is:
a) to identify:
1) the test object
2) the requirements to be verified
b) to define:
1) the test methods and constraints
2) the test evaluation criteria
3) the detailed procedure for test execution
1.2 A̲P̲P̲L̲I̲C̲A̲B̲L̲E̲ ̲D̲O̲C̲U̲M̲E̲N̲T̲S̲
The following documents are applicable to the extent
specified herein:
a) CAMPS System Requirements Specification,
CPS/210/SYS/0001
b) CAMPS Acceptance Test Specification Overview,
CPS/TSS/001
c) CAMPS Hardware Assembly Breakdown/Hardware Tree
CPS/SDS/017, Issue 3
d) CAMPS System Design Specification
CPS/SDS/001
e) CPU test program product specification
f) MAP test program product specification
g) RAM test program product specification
h) Disk/Floppy Disk/LTU/TDX test program
product specification
i) Watchdog system software Product
specification CSS-MIC/0420/PSP/1010
j) Site Configuration List for Site 9
1.3 L̲I̲S̲T̲ ̲O̲F̲ ̲I̲N̲S̲P̲E̲C̲T̲I̲O̲N̲ ̲A̲N̲D̲ ̲T̲E̲S̲T̲ ̲P̲R̲O̲C̲E̲D̲U̲R̲E̲S̲
U̲S̲E̲D̲ ̲F̲O̲R̲ ̲P̲E̲R̲I̲P̲H̲E̲R̲A̲L̲S̲
1) INSPECTION AND TEST PROCEDURE FOR DELTA DATA TERMINAL
7260TC
CPS/TPR/012 (1) 810910
2) INSPECTION AND TEST PROCEDURE FOR CDC 80Mb SMD
9762
CPS/TPR/013 (1) 810911
3) INSPECTION AND TEST PROCEDURE FOR MICOM 800/2-30
SERIES STAT. MUX.
CPS/TPR/014 (2) 820211
4) INSPECTION AND TEST PROCEDURE FOR VERSITRON FIBER
OPTIC MODEMS
CPS/TPR/015 (1) 811106
5) INSPECTION PROCEDURE FOR EMI EQUIPMENT RACKS
CPS/TPR/016 (1.1) 820311
6) INSPECTION AND TEST PROCEDURE FOR ABACUS FREQUENCY
STABILIZER 1152-3
CPS/TPR/017 (1) 811111
7) INSPECTION AND TEST PROCEDURE FOR ARC V24/V28 L/L
ADAPTERS
CPS/TPR/018 (1) 820210
8) INSPECTION AND TEST PROCEDURE FOR TRACOR MSP MODEL
8000
CPS/TPR/019 (1) 820225
9) INSPECTION AND TEST PROCEDURE FOR VERSITRON ADAPTER
POWER SUPPLY
CPS/TPR/020 (2) 820609
10) INSPECTION PROCEDURE FOR INTERMEDIATE DISTRIBUTION
FILTER AP-7466
CPS/TPR/021 (1) 820609
11) INSPECTION AND TEST PROCEDURE FOR CDC MMD 9730-80F
CPS/TPR/022 (1) 820225
12) INSPECTION PROCEDURE FOR CAPTOR EMI FILTER A-3975A
CPS/TPR/023 (1) 820423
13) INSPECTION PROCEDURE FOR TRANSRACK RACK 0160540/4.44503-00
CPS/TPR/024 (1) 820614
14) INSPECTION PROCEDURE FOR TRANSRACK RACK 0161240/4.44504-00
CPS/TPR/025 (1) 820614
15) INSPECTION AND TEST PROCEDURE FOR RACAL-MILGO MODEM
MPS1223
CPS/TPR/026 (1) 820615
16) INSPECTION AND TEST PROCEDURE FOR CR8308 - FLOPPY
DISK STATION
CPS/TPR/027 (1) 821004
17) INSPECTION AND TEST PROCEDURE FOR EECO/BURROUGHS
PTR/P
CPS/TPR/030 (1) 821203
18) INSPECTION AND TEST PROCEDURE FOR CDC TB216 FIELD
TEST UNIT
CPS/TPR/031 /1) 820927
19) INSPECTION PROCEDURE FOR DYNATECH ANALOQUE PATCH
PANEL 153-120-16VF.
CPS/TPR/032 (1) 830128
20) INSPECTION AND TEST PROCEDURE FOR DYNATECH PATCH
BLOCK DP 12-5.
CPS/TPR/033 (1) 830128
1.4 T̲E̲R̲M̲S̲ ̲A̲N̲D̲ ̲A̲B̲B̲R̲E̲V̲I̲A̲T̲I̲O̲N̲S̲
BPS Bit Per Second
CAMPS Computer Aided Message Processing
System
CCB Configuration Control Bus
CCIS Command & Control Information System
CCITT The International Telegraph and
Telephone Consultative Committee
CIA Data Channel Interface Adapter
CPS CAMPS
CPU Central Processing Unit
CR Carriage Return
CRT Camps Remote Terminals
CU Channel Unit
DCA Disk Control Adaptor
DCB CR80D Control Bus
DCE Data Circuit-terminating Equipment
DMA Direct Memory Access
DMB CR80D Main Bus
DM&T Distribution Monitoring and Test
Equipment
DSMT Development, Software, Maintenance,
Test
DTE Data Terminal Equipment
EDC Error Detection and Correction
EMI-racks Electromagnetic Interference
FW Firmware
HDLC High Level Data Link Control
HW Hardware
ICD Interface Control Document
IDF Intermediate Distribution Frame
IF, I/F Interface
IO, I/O Input/Output
IOS I/O System
ITA International Telegraph Alphabet
LED Light Emitting Diode
LF Line Feed
LIA Line Interface Adaptor
LP Line Printer
LSI Large Scale Integrated Circuits
LSM Low Speed Medium
LSP Low Speed Teleprinter
LTU Line Termination Unit
LTUX Line Termination Unit Wired to the
TDX bus
MAP Memory Mapping Unit
MBT Main Bus Termination Module
MDCO Message Distribution Control Operator
MIA Map Interface Adapter
MIN Minutes
MSO Message Service Operator
MSP Medium Speed Tele Printer
MTBF Mean Time Between Failure
MTTR Mean Time To Repair
M&D Maintenance and Diagnostics
NA Not Applicable
NICS NATO Integrated Communication System
OCR Optical Character Reader
PCB Printed Circuit Board
PROM Programmable Read Only Memory
PSU Power Supply
PTP Paper Tape Puncher
PTR Paper Tape Reader
PU Processor Unit
P-to-P Point to Point
RAM Random Access Memory
RF Radio Frequency
SCARS Status Control, Alerting and Reporting
System
SRS System Requirements Specification
SSC System Status and Control
STI Supra-TDX Bus Interface
SUPV Supervisor
SW Software
TARE Telegraph Automatic Relay Equipment
TBD To Be Defined
TDS Test Drive System
TDX Telecommunication Data Exchange
TIA TDX Bus Interface Adapter
TP Tele Printer
TTY Teletype
VDU Visual Display Unit
WDP Watchdog Processor
X25 Protocol Name
Z80 Zilog 80
2̲ ̲ ̲T̲E̲S̲T̲ ̲S̲P̲E̲C̲I̲F̲I̲C̲A̲T̲I̲O̲N̲ ̲A̲N̲D̲ ̲E̲V̲A̲L̲U̲A̲T̲I̲O̲N̲
2.1 T̲E̲S̲T̲ ̲S̲P̲E̲C̲I̲F̲I̲C̲A̲T̲I̲O̲N̲
2.1.1 T̲e̲s̲t̲ ̲P̲u̲r̲p̲o̲s̲e̲
The purpose of this test is to provide a Factory Acceptance
of each operational site CAMPS hardware.
The acceptance test will consist of:
a) A verification of the equipment configuration.
b) A demonstration of all basic functional hardware
capabilities.
2.1.2 T̲e̲s̲t̲ ̲O̲b̲j̲e̲c̲t̲ ̲I̲d̲e̲n̲t̲i̲f̲i̲c̲a̲t̲i̲o̲n̲
The test and verification will be conducted on each
operational site CAMPS equipment. Each site configuration
are described in CAMPS Hardware Assembly Breakdown/Hardware
Tree (Document C).
2.1.3 R̲e̲q̲u̲i̲r̲e̲m̲e̲n̲t̲s̲
Requirements in SRS which explicitly address hardware
related to
- design and construction
- characteristics
- attributes
these requirements have been qualified during the DSMT
H/W test, ref. CPS/TPR/005.
This test is a verification of the hardware configuration
and a functional test of all basic hardware capabilities.…86…1
…02… …02… …02… …02…
2.1.4 S̲y̲s̲t̲e̲m̲ ̲F̲u̲n̲c̲t̲i̲o̲n̲s̲
To ensure that the hardware will be able to support
all required CAMPS functions, a set of basic functional
capabilities for the hardware have been derived.
The derived functions can be divided into the following
categories:
- CPU
- Memory Mapping, MAP
- Memory, RAM
- Disk I/O
- LTU I/O
- TDX I/O
- Watchdog functions
Special test drive software has been developed for
verification of these functional hardware capabilities.
Reports from CR's incoming inspection of all OEM equipment
contained in each site configuration will be included
in the factory acceptance test report.
2.1.5 T̲e̲s̲t̲/̲F̲u̲n̲c̲t̲i̲o̲n̲s̲ ̲R̲e̲l̲a̲t̲i̲o̲n̲s̲h̲i̲p̲
In order to logically structure the verification activity
of this test it has been subdivided into two testgroups
shown below:
T̲e̲s̲t̲g̲r̲o̲u̲p̲ ̲D̲e̲s̲c̲r̲i̲p̲t̲i̲o̲n̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲N̲o̲.̲
Site Configuration 1
Functional Capabilities 2
2.1.6 T̲e̲s̲t̲ ̲G̲r̲o̲u̲n̲d̲ ̲R̲u̲l̲e̲s̲
The Factory Acceptance Test is based on the sequences
of tests described in the test procedures.
During the test the result of the test is noted in
the test report. If any comments were necessary these
are noted in the test report as well.
If during the test a problem is encountered, the problem
is either categorized as a discrepancy or a defect.
By a discrepancy is meant a mutually agreed issue.
A discrepancy is noted showing an agreed date for clearance
of the issue to be cleared. By a defect is meant a
problem which prevents the acceptance of the test.
Also problems encountered during the test are divided
into two other categories:
Board failures
System level failures
Board failures are corrected immediately by replacement
of the board. System level failures are corrected
after the first test is completed and a retest is performed.
2.2 T̲E̲S̲T̲ ̲M̲E̲T̲H̲O̲D̲S̲ ̲A̲N̲D̲ ̲C̲O̲N̲S̲T̲R̲A̲I̲N̲T̲S̲
2.2.1 S̲y̲s̲t̲e̲m̲ ̲T̲e̲s̲t̲ ̲C̲o̲n̲d̲i̲t̲i̲o̲n̲s̲
This test is a hardware qualification test, and the
verification methods to be applied will consist of:
- examination
- analysis
- demonstration/test
a) Examination
This method is a non-functional verification such
as visual inspection of the physical characteristics
of the item or of the documentation associated with
the item.
b) Analysis
This method is a non-functional verification, such
as reductions or translation of data, review of
analytical data, or review of performances from
a detailed test. Data may be brought forward from
previous tests.
c) Test/Demonstration
This method of testing is to functionally exercise
the equipment such that measurements and observations
of correct operation can be made. Elements not directly
measured or observed are demonstrated by implication.
For each requirement to be verified the verification
method is indicated in the Verification Cross Reference
Index (VCRI). The VCRI is contained in the Test Description
for each individual Testgroup.
2.2.2 E̲x̲t̲e̲n̲t̲ ̲o̲f̲ ̲S̲y̲s̲t̲e̲m̲ ̲T̲e̲s̲t̲
All basic functional hardware capabilities are tested.
2.2.3 D̲a̲t̲a̲ ̲R̲e̲c̲o̲r̲d̲i̲n̲g̲
All test results or indication of compliance with expected
results shall be recorded in a report by CR's test
engineer in charge of test execution.
Test executions must be witnessed by CR's QA and the
purchaser's QAR.
The Test Report shall be signed by CR's test engineer
and the test witnesses.
The original test reference copy will be filed by CR
QA.
2.2.4 S̲y̲s̲t̲e̲m̲ ̲T̲e̲s̲t̲ ̲C̲o̲n̲s̲t̲r̲a̲i̲n̲t̲s̲
The basic functional capabilities of the hardware and
the related system firmware will be verified.
Requirements specifying CAMPS functions provided by
both software, application firmware, and hardware will
be verified during the functional software test.
2.2.5 T̲e̲s̲t̲ ̲L̲o̲c̲a̲t̲i̲o̲n̲
When the CAMPS hardware has been integrated at the
factory, a functional test will be performed. The
location for execution of the test is a CR decision.
2.3 T̲E̲S̲T̲ ̲E̲V̲A̲L̲U̲A̲T̲I̲O̲N̲
Evaluation of the test results will be performed by
comparison of test results with expected results or
by assurance of compliance between requirements and
the referenced documentation.
3̲ ̲T̲E̲S̲T̲ ̲D̲E̲S̲C̲R̲I̲P̲T̲I̲O̲N̲ ̲A̲N̲D̲ ̲P̲R̲O̲C̲E̲D̲U̲R̲E̲S̲
3.1 T̲e̲s̲t̲g̲r̲o̲u̲p̲ ̲N̲o̲.̲ ̲1̲
3.1.1 G̲e̲n̲e̲r̲a̲l̲ ̲D̲e̲s̲c̲r̲i̲p̲t̲i̲o̲n̲
This testgroup will give a verification of the site
configuration.
3.1.2 V̲e̲r̲i̲f̲i̲c̲a̲t̲i̲o̲n̲ ̲C̲r̲o̲s̲s̲ ̲R̲e̲f̲e̲r̲e̲n̲c̲e̲ ̲I̲n̲d̲e̲x̲ ̲(̲V̲C̲R̲I̲)̲
None.
3.1.3 T̲e̲s̲t̲ ̲P̲r̲o̲c̲e̲d̲u̲r̲e̲
3.1.3.1 T̲e̲s̲t̲ ̲S̲e̲t̲u̲p̲
The starting point for execution of this procedure
is that the system is assembled in accordance with
the actual site configuration specified in CAMPS Hardware
Assembly Breakdown/Hardware tree (Document C) and one
copy of document C is present in the testroom.
3.1.3.2 T̲e̲s̲t̲ ̲I̲n̲i̲t̲i̲a̲l̲i̲z̲a̲t̲i̲o̲n̲
The testengineers and testwitnesses are in the testroom
and ready to perform and supervise the test.
3.1.3.3 T̲e̲s̲t̲ ̲S̲t̲e̲p̲s̲
The teststeps for testgroup no. 1 are given in the
following, with an overview description and the teststeps
to follow.
T̲E̲S̲T̲ ̲O̲V̲E̲R̲V̲I̲E̲W̲ T̲E̲S̲T̲ ̲N̲O̲.̲ ̲1̲ ̲ ̲ ̲
F̲U̲N̲C̲T̲I̲O̲N̲:̲ ̲S̲i̲t̲e̲ ̲C̲o̲n̲f̲i̲g̲u̲r̲a̲t̲i̲o̲n̲ ̲
̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲
̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲
Test Case Action SRS Refence
R̲e̲f̲e̲r̲e̲n̲c̲e̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲
̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲
1 Verification of the site N/A
Configuration
T̲E̲S̲T̲ ̲S̲T̲E̲P̲S̲ T̲E̲S̲T̲
̲N̲O̲.̲
̲1̲
F̲U̲N̲C̲T̲I̲O̲N̲:̲ ̲S̲i̲t̲e̲ ̲C̲o̲n̲f̲i̲g̲u̲r̲a̲t̲i̲o̲n̲
S̲P̲S̲ ̲R̲e̲f̲e̲r̲e̲n̲c̲e̲:̲ ̲ ̲N̲/̲A̲
̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲
̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲
Case. Test Action Expected Results
Step no. Station
̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲
̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲
1.1 Verify, for the actual
site to be tested, that
the configuration is in
accordance with that
specified in document C and
J. Use the checklist in
Appendix C, for result
recordings.
Verification
OK
Check Document J to ensure
that all applicable ECOs
have been implemented.
̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲
̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲
COMMENTS:
T̲E̲S̲T̲
̲W̲I̲T̲N̲E̲S̲S̲E̲S̲
TEST
QA
QAR
3.2 T̲E̲S̲T̲G̲R̲O̲U̲P̲ ̲N̲O̲.̲ ̲2̲
3.2.1 G̲e̲n̲e̲r̲a̲l̲ ̲D̲e̲s̲c̲r̲i̲p̲t̲i̲o̲n̲
The purpose of this test group is to verify basic functional
capabilities of the CAMPS hardware.
Functional capabilities to be verified are:
1. CPU
2. Memory Mapping, MAP
3. Memory, RAM
4. Disk I/O
5. Floppy Disk I/O
6. LTU I/O, incl. links to circuits/terminals
7. TDX I/O, incl. links to circuits/terminals *
8. Watchdog functions
Furthermore the following requirements to system security
will be verified during the functional tests:
9. Power Line Filtering (SRS sec. 3.4.5.1.o)
10. CPU instruction set (SRS sec. 3.4.5.7.a.4)
11. Hardware addressing (SRS sec. 3.4.5.7.a.7)
The different communication interfaces will be tested
as follows:
a) T̲e̲r̲m̲i̲n̲a̲l̲s̲ ̲(̲o̲p̲t̲o̲ ̲o̲r̲ ̲V̲2̲4̲/̲V̲2̲8̲(̲L̲/̲L̲)̲)̲
1) Each Opto link to be tested has a VDU or a
MSP connected. The test will be performed for
eight/
four links at a time by sending 24 lines of
alphanumeric characters to the VDU's/MSP's
connected. In case of connected VDU's, a command
setting the VDU's in transmit mode is sent
to the VDU's. The 24 lines previously received
by the VDU's are transmitted back
* One type of LTUX-S will be available for the Factory
Acceptance Test.…86…1 …02… …02… …02… …02…
…02… …02… …02… …02…
to the system. Outputdata and inputdata are
compared for equality. In case of connected
MSP's verification of the transmitted data
are performed by visual inspection of the print
out.
When VDU…08…s and for MSP…08…s are expansions two types
of expansion exist.
The first type is where opto adaptors are connected.
In this case connect a test VDU/MSP to the
adaptor and follow the test described above.
The second type is where adaptors are connected.
In this case plug a test adaptor test into
the actual CTX crate and connect a test VDU/MSP
to the adaptor and follow the test described
above.
2) L̲o̲w̲ ̲S̲p̲e̲e̲d̲ ̲M̲e̲d̲i̲a̲ ̲i̲n̲t̲e̲r̲f̲a̲c̲e̲ ̲(̲V̲2̲4̲/̲V̲2̲8̲(̲L̲/̲L̲)̲)̲
These lines are terminated in the V24 Filter
Box. Each of the links are tested four at a
time using TEST VDU's which are connected to
the actual plug in the filter box. 24 lines
of alphanumeric characters are sent to the
TEST VDU's connected. A command setting the
TEST VDU's in transmit mode is outputted. The
24 lines previously received by the TEST VDU's
are transmitted back to the system. Outputdata
and inputdata are compared for equality.
3) P̲T̲R̲/̲P̲T̲P̲ ̲i̲n̲t̲e̲r̲f̲a̲c̲e̲ ̲(̲V̲2̲4̲/̲V̲2̲8̲(̲L̲/̲L̲)̲)̲
A PTR/PTP is connected to the actual plug in
the V24 Filter Box. The test includes output
of 5 lines of alphanumeric characters which
shall be punched. The punched tape is then
fed back into the PTR part and send back to
the system. Inputdata are dumped on the OC.
4) O̲C̲R̲ ̲i̲n̲t̲e̲r̲f̲a̲c̲e̲ ̲(̲V̲2̲4̲/̲V̲2̲8̲(̲L̲/̲L̲)̲)̲
This test requires an OCR (SHAPE supplied).
If an OCR is not available at the time of the
test, a VDU is used to simulate the OCR. If
an OCR is connected the test is run by inputting
data from the OCR and printing the received
data on the OC. Thus verification is based
upon visual inspection of the OC print out.
If a VDU is connected the test is run as described
in 3.2.1.a.
b) E̲x̲t̲e̲r̲n̲a̲l̲ ̲C̲i̲r̲c̲u̲i̲t̲s̲ ̲(̲V̲2̲4̲/̲V̲2̲8̲(̲L̲/̲L̲)̲)̲
1) A̲C̲C̲I̲S̲/̲S̲C̲A̲R̲S̲I̲I̲ ̲i̲n̲t̲e̲r̲f̲a̲c̲e̲
These lines are terminated in the V24 Filter
Box. Each of the links are tested one at a
time using a TEST VDU which is connected to
the actual plug in the filter box. 24 lines
of alphanumeric characters are send to the
TEST VDU connected. A command setting the TEST
VDU in transmit mode i outputted. The 24 lines
previously received by the TEST VDU is transmitted
back to the system. Outputdata and inputdata
are compared for equality.
2) T̲A̲R̲E̲ ̲i̲n̲t̲e̲r̲f̲a̲c̲e̲
These lines are terminated in the V24 Filter
Box.
Two testconfigurations are defined for this
test:
TEST EQUIPMENT 1 consists of a TEST VDU and
a CRYPTO/MODEM link (The CRYPTO is SHAPE supplied)
and will be used during the test if the CRYPTO
is available at the time of the test. Loading
a CRYPTO key(S) and verification of the CRYPTO
equipment prior to integration with the equipment
and TEST VDU is a SHAPE responsibility.
TEST EQUIPMENT 2 is a TEST VDU and will be
used during the test if the CRYPTO equipment
is unavailable at the time of the test. 24
lines of alphanumeric characters are send to
the TESTCONFIGURATION connected. A command
setting the TESTCONFIGURATION in transmit mode
is outputted. The 24 lines previously received
by the TESTCONFIGURATION is transmitted back
to the system. Outputdata and inputdata are
compared for equality.
c) C̲o̲n̲n̲e̲c̲t̲i̲o̲n̲ ̲o̲f̲ ̲T̲e̲r̲m̲i̲n̲a̲l̲s̲ ̲a̲n̲d̲ ̲E̲x̲t̲e̲r̲n̲a̲l̲ ̲C̲i̲r̲c̲u̲i̲t̲s̲
To ease identification of terminals connected
to the TDX system via signal adapters and LTUX-Ss,
each terminal and the link between the terminal
and the signal adapter is given a three digit
identifier. Each digit is a hexadecimal number.
The format of the identifier is …08…XYZ…08… and the
terminal having this identification is connected
via link (opto or V24) XYZ to channel Z (1-4)
of LTUX-S X (1-2) in TDX Unit (TU) Y (1-E).
E.g.: a MSP has
the identifier 2A3 that the MSP is connected
via link 2A3 to channel 3 of LTUX-S no. 2 in
TDX Unit 10.
An external circuit is identified similar to
terminals with the crate identifier being zero
(identifying the Channel Unit): Thus an external
circuit connected to LTU/LIA-N NO. 3 channel
2 and the associated V24 link is identified
as 032.
V24 links enters/leaves the system via Filtered
CANNON D-connectors in the V24 Filter Box (ref.
fig. 3.2.1-1). These connectors are numbered
consecutively from J1 to J53. A cross-reference
between filterbox connectors and V24 link identifiers
for each individual site is given in fig. 3.2.1-2.).
F̲i̲g̲u̲r̲e̲ ̲3̲.̲2̲.̲1̲-̲1̲ ̲V̲2̲4̲ ̲F̲i̲l̲t̲e̲r̲ ̲B̲o̲x̲,̲ ̲p̲l̲u̲g̲ ̲l̲o̲c̲a̲t̲i̲o̲n̲s̲
I̲d̲e̲n̲t̲i̲f̲i̲e̲r̲ F̲i̲l̲t̲e̲r̲ ̲B̲o̲x̲ ̲C̲o̲n̲n̲e̲c̲t̲o̲r F̲u̲n̲c̲t̲i̲o̲n D̲e̲v̲i̲c̲e̲ ̲I̲D̲*
N̲o̲t̲e̲s̲
011 J30 CCIS
021 J31 SCARS
031 J26 TARE
032 J27 TARE
111 N/A VDU Opto
112 N/A VDU Opto
113 N/A VDU Opto
114 N/A VDU Opto
211 N/A VDU Opto
212 N/A VDU Opto
213 N/A VDU Opto
214 N/A VDU Opto
121 N/A VDU Opto
122 N/A VDU Opto
123 N/A VDU Opto
124 N/A VDU Opto
221 N/A VDU Opto
222 N/A VDU Opto
223 N/A VDU Opto
224 N/A VDU Opto
131 N/A VDU Opto
132 N/A (VDU)
133 N/A (VDU)
134 N/A (VDU)
231 N/A (OCR)
141 N/A MSP Opto
142 N/A MSP Opto
143 N/A MSP Opto
144 N/A MSP Opto
241 N/A MSP Opto
242 N/A MSP Opto
243 N/A MSP Opto
244 N/A (MSP)
A CROSS-REFERENCE BETWEEN FILTER BOX
CONNECTORS AND V24 LINK IDENTIFIERS
FIGURE 3.2.1-2
I̲d̲e̲n̲t̲i̲f̲i̲e̲r̲ F̲i̲l̲t̲e̲r̲ ̲B̲o̲x̲ ̲C̲o̲n̲n̲e̲c̲t̲o̲r F̲u̲n̲c̲t̲i̲o̲n
D̲e̲v̲i̲c̲e̲ ̲I̲D̲* N̲o̲t̲e̲s̲
151 J1 LSM(TTY)
152 J2 LSM
153 J3 LSM
154 J4 LSM
251 J5 LSM
252
253
254 J25 PTP/PTR
171 N/A (.OCR)
271 N/A (.OCR)
1B1 N/A CRT/VDU
1B2 N/A CRT/VDU
1B3 N/A CRT/VDU
1B4 N/A CRT/VDU
2B1 N/A CRT/MSP
2B2 N/A CRT/MSP
2B3 N/A CRT/MSP
2B4 N/A CRT/MSP
A CROSS-REFERENCE BETWEEN FILTER BOX
CONNECTORS AND V24 LINK IDENTIFIERS
FIGURE 3.2.1-2
3.2.2 V̲e̲r̲i̲f̲i̲c̲a̲t̲i̲o̲n̲ ̲C̲r̲o̲s̲s̲ ̲R̲e̲f̲e̲r̲e̲n̲c̲e̲ ̲I̲n̲d̲e̲x̲ ̲(̲V̲C̲R̲I̲)̲
The VCRI, table 3.2.2-1, identifies functional capabilities
to be verified along with the verification method.
REQUIREMENT VERIFICATION
METHOD
N/A EXAM.
ANAL.
TEST
----------------------------------------------------------------
F FUNCTIONAL CAPABILITIES
F.1 PU#1/CU/TDX#1 FUNCTIONAL TEST
F.1.1 CPU#0/#1/#2 Test X
F.1.2 MAP/MIA Test X
F.1.3 RAM Test X
F.1.4 Disk Ctrl/DCA/Disk#1/#2/
#3/ Test X
F.1.5 LTU/LIA-N/LINK#1/#2/#3
Test X
F.1.6 Floppy Ctrl/SFA/Floppy Disk
Test X
F.1.7 I/O Bus load Test X
F.1.8 STI/TIA#1/TIA#2 Test X
F.1.9 TDX Ctrl#1 Test X
F.1.10 BSM-X Test X
F.1.11 LTUX-S Test X
F.2 PU#2/CU/TDX#2 FUNCTIONAL TEST
F.2.1 CPU#0/#1/#2 Test X
F.2.2 MAP/MIA Test X
F.2.3 RAM Test X
F.2.4 Disk Ctrl/DCA/Disk#1/#2/
#3/ Test X
F.2.5 LTU/LIA-N/LINK#1/#2/#3
Test X
F.2.6 Floppy Ctrl/SFA/Floppy Disk
Test X
F.2.7 I/O Bus load Test X
F.2.8 STI/TIA#1/TIA#2 Test X
F.2.9 TDX Ctrl#2 Test X
F.2.10 BSM-X Test X
F.2.11 LTUX-S Test
F.3 WDP FUNCTIONAL TEST X
F.3.1 LTU/WCA Test X
F.3.2 CCA Test X
F.3.3 BSM-X Test X
F.3.4 CUCP Test X
F.3.5 CCBA Test X
TABLE 3.2.2-1
3.2.3 T̲e̲s̲t̲ ̲P̲r̲o̲c̲e̲d̲u̲r̲e̲s̲
3.2.3.1 T̲e̲s̲t̲ ̲P̲r̲o̲c̲e̲d̲u̲r̲e̲ ̲1̲
This testprocedure serves to verify functional capabilities
of PU#1, the associated part of the CU and the connected
TDX#1 system as identified in the VCRI.
3.2.3.1.1 T̲e̲s̲t̲ ̲S̲e̲t̲ ̲U̲p̲
The test is performed via an Operator Console (OC)
which is a printer and keyboard.
The OC is connected to the system as follows:
1. Substitute the leftmost OPTO transceiver in
the rack C Adapter crate with a V24/V28(L/L)
adapter (1 channel), and connect the OC to
the V24 connector on the front panel of the
adaptor.
2. Remove the two V24 cables from J1 and J3 located
on the front panel of the WCA (rear crate of
the Watchdog Processor crate).
3. Connect the two V24 cables.
The OC is now connected to the V24 port on the MIA
in the rear crate of PU#1 (ref. fig. 3.2.3.1.1-1).
Carry out/control the following:
a) OC Set up:
The communication part of the OC is set to:
1) Asynchronous communication
2) 7 bit character length
3) Even parity check/generation
4) 1 stop bit
5) 1200 Baud communication speed
FIGURE 3.2.3.1.1-1
C̲o̲n̲n̲e̲c̲t̲i̲o̲n̲ ̲o̲f̲ ̲t̲h̲e̲ ̲O̲p̲e̲r̲a̲t̲o̲r̲ ̲C̲o̲n̲s̲o̲l̲e̲
b) Switch settings in PU#1 and PU#2 front crate modules:
1) The NRM/MAIN switch on the MAP module front
panel is set to NRM.
2) The EN/DIS switch on the MAP module front panel
is set to EN.
c) Switch settings in PU#1 and PU#2 rear crate modules:
1) The Baudrate select switches 1-4 (S1) on the
MAP Interface Adapter (MIA) Printed Circuit
Board (PCB) is set to #7 which corresponds
to a transmission speed of 1200 Baud:
Switch 1: OPEN
Switch 2: OPEN
Switch 3: OPEN
Switch 4: CLOSED
2) The RESET switch on the Configuration Control
Adaptor (CCA) front panel is set to RESET.
d) Switch settings in CU front crate modules:
1) Switches on the Channel Unit Control Panel
(CUCP) front panel is set as:
a) The CU Bus A Switch DIS/AUTO is set to
AUTO
b) The CU Bus B switch DIS/AUTO is set to
AUTO
c) The Disk Ctrl. No. 1 switch AAEN/AUTO/BAEN
is set to AUTO
d) The Disk Ctrl. No. 2 switch AAEN/AUTO/BAEN
is set to AUTO
e) The Disk Ctrl. No. 3 switch AAEN/AUTO/BAEN
is set to AUTO
f) The LTU No. 1 switch AAEN/AUTO/BAEN is
set to AUTO
g) The LTU No. 2 switch AAEN/AUTO/BAEN is
set to AUTO
h) The LTU No. 3 switch AAEN/AUTO/BAEN is
set to AUTO
i) The LTU No. 4 switch AAEN/AUTO/BAEN is
set to AUTO
k) The LTU No. 5 switch AAEN/AUTO/BAEN is
set to AUTO
l) The SD.FD.CTRL switch AAEN/AUTO/BAEN is
set to AUTO
e) Switch settings in CU rear crate modules:
1) The Reset switch on the CCA module front panel
is set to Reset
f) Switch settings in TU modules
1) All BSM-Xs:
a) The AUTO/MAN/OFF switch is set to MAN
b) The BUS 1/Bus 2 switch is set to BUS 1.
2) All LTUX-Ss:
a) The CH 1 switch ON/OFF is set to ON
b) The CH 2 switch ON/OFF is set to ON
c) The CH 3 switch ON/OFF is set to ON
d) The CH 4 switch ON/OFF is set to ON
g) Switch settings on frequency stabilizer rack:
1) The input power switch on all three stabilizers
are set to off.
2) The three rotary switches on the By-Pass panel
are all set to the Frequency Stabilizer position.
h) Setting of power switches in Computer racks:
1) Power switch (2) on each Mains switch is set
to OFF.
2) Power switch (2) on the Disk Drive rear panel
is set to "ON"
3) Power switch (1) on the Floppy Disk Drive rear
panel is set to "ON".
4) Power switch (1) on the Watchdog Processor
Unit rear panel is set to "OFF".
5) Power switch (2) in the rear crate of PU#1
is set to "ON"
6) Power switch (2) in the rear crate of the CU
is set to "ON"
7) Power switch (2) in the rear crate of the PU#2
is set to "ON".
8) Power switch (2) in the rear panel of each
80D fan unit is set to "ON".
9) Power switch (2) in the rear crate of the Adaptor
Crate is set to "ON"
10) Power switch (1) in the rear panel of the 80S
Blower Unit is set to "ON"
11) Power switch (1) on each CR80D Power supply
(6 front crate mounted modules) is set to "ON".
i) Setting of Power Switches in Line Termination racks:
1) Power Switch (2) on each Mains Switch is set
to "OFF".
2) Power Switch (1) on the rear panel of each
80S Fan Unit is set to "ON".
3) Power Switch (2) in the rear crate of each
TU is set to "ON".
4) Power Switch (1) on each CR80S Power Supply
(1 in the front crate of each TU) is set to
"ON".
3.2.3.1.2 T̲e̲s̲t̲ ̲I̲n̲i̲t̲i̲a̲l̲i̲z̲a̲t̲i̲o̲n̲
The testengineers and testwitnesses are in the testroom
and ready to perform and supervise the test.
Power Up the System as follows :
a) Power Up all connected terminals i.e. VDUs, MSPs,
OC, PTP/PTR, OCR as applicable.
b) The input Power Switch on the front panel of each
Frequency Stabilizer is set to "ON".
c) The power switch (2) on Mains switch no. 1 is set
to "ON" wait 15 secs.
d) The power switch (2) on each of the remaining Mains
Switches is set to "ON".
e) Mount a Disk Pack with the test software in Disk
Drive no. 2, close the lid and push the drive back
in rack B.
f) Activate "START" push button on Disk Drive No.
2 and wait until the "READY" indicator stays "ON".
g) Insert a scratch Floppy Disk in each of the two
drives in the Floppy Disk drive of rack B, and
close the lids.
3.2.3.1.3 T̲e̲s̲t̲ ̲S̲t̲e̲p̲s̲
The teststeps for testgroup no. 2, testprocedure no.
1 (2/1), are given in the following preceded by a testoverview.
T̲E̲S̲T̲ ̲O̲V̲E̲R̲V̲I̲E̲W̲ T̲E̲S̲T̲ ̲N̲O̲.̲:̲ ̲2̲/̲1̲
F̲U̲N̲C̲T̲I̲O̲N̲:̲ ̲ ̲F̲u̲n̲c̲t̲i̲o̲n̲a̲l̲ ̲C̲a̲p̲a̲b̲i̲l̲i̲t̲i̲e̲s̲
̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲
̲ ̲ ̲ ̲
Test Case/
Reference Action SRS Reference
̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲
̲ ̲ ̲ ̲
1. CPU test N/A
2. MAP test N/A
3. RAM test N/A
4. Disk/Floppy Disk N/A
test
5.1 LTU #1 N/A
5.2 LTU #2 N/A
5.3 LTU #3 N/A
6. Load Test N/A
7.2 LTUX-S Link 11x-21x N/A
7.3 LTUX-S Link 12x-22x N/A
7.4 LTUX-S Link 13x-23x N/A
7.5 LTUX-S Link 14x-24x N/A
7.6 LTUX-S Link 15x N/A
7.7 LTUX-S Link 25x N/A
/Continued....…86…1
…02… …02…
T̲E̲S̲T̲ ̲O̲V̲E̲R̲V̲I̲E̲W̲ T̲E̲S̲T̲ ̲N̲O̲.̲:̲ ̲2̲/̲1̲
F̲U̲N̲C̲T̲I̲O̲N̲:̲ ̲ ̲F̲u̲n̲c̲t̲i̲o̲n̲a̲l̲ ̲C̲a̲p̲a̲b̲i̲l̲i̲t̲i̲e̲s̲ (Continued)
̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲
̲ ̲ ̲ ̲
Test Case/
Reference Action SRS Reference
̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲
̲ ̲ ̲ ̲
7.8 LTUX-S TELETYPE TEST N/A
7.9 LTUX-S Link 254 N/A
7.10 LTUX-S Link 231 N/A
7.11 LTUX-S Link 171, 271 N/A
7.12 LTUX-S Link 1B-2B, N/A
Resyne Module Test
All Power line filtering sec. 3.4.5.1.o
All CPU instruction set sec. 3.4.5.7.a.4
All Hardware addressing sec. 3.4.5.7.a.7
T̲E̲S̲T̲ ̲S̲T̲E̲P̲S̲ T̲E̲S̲T̲
̲N̲O̲.̲:̲
̲2̲/̲1̲
F̲U̲N̲C̲T̲I̲O̲N̲:̲ ̲ ̲P̲U̲#̲1̲/̲C̲U̲/̲T̲D̲X̲#̲1̲ ̲F̲u̲n̲c̲t̲i̲o̲n̲a̲l̲ ̲T̲e̲s̲t̲
S̲R̲S̲ ̲R̲E̲F̲E̲R̲E̲N̲C̲E̲:̲ ̲ ̲S̲e̲c̲s̲.̲3̲.̲4̲.̲5̲.̲1̲.̲o̲,̲ ̲3̲.̲4̲.̲5̲.̲7̲.̲a̲.̲4̲,̲ ̲3̲.̲4̲.̲5̲.̲7̲.̲a̲.̲7̲ ̲ ̲ ̲
̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲
Case Test
Step No. Station Action Expected Results
̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲
̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲
1.1 OC Examine printout on OC Refer to Appendix
B sec. 1.1
1.2 OC Boot the CPU test pro-
gram as follows:
Enter from the OC:
BA 1025(CR)
BM 140(CR)
BO 621(CR) Refer to Appendix
B sec. 1.2
1.3 OC Enter from the OC
REPORTLEVEL = 0(CR)
ACTIVATE CPU 0(CR)
ACTIVATE CPU 1(CR)
ACTIVATE CPU 2(CR)
TEST CPU 0 1 2(CR) Refer to Appendix
B section 1.3.
1.4 OC Quit the CPU test by en-
tering from the OC:
QUIT(CR) Refer to Appendix
B section 1.4
̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲
̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲
Comments:
̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲
̲ ̲
T̲E̲S̲T̲ ̲W̲I̲T̲N̲E̲S̲S̲E̲S̲
TEST QA QAR
T̲E̲S̲T̲ ̲S̲T̲E̲P̲S̲ T̲E̲S̲T̲
̲N̲O̲.̲:̲
̲2̲/̲1̲
F̲U̲N̲C̲T̲I̲O̲N̲:̲ ̲ ̲P̲U̲#̲1̲/̲C̲U̲/̲T̲D̲X̲#̲1̲ ̲F̲u̲n̲c̲t̲i̲o̲n̲a̲l̲ ̲T̲e̲s̲t̲
S̲R̲S̲ ̲R̲E̲F̲E̲R̲E̲N̲C̲E̲:̲ ̲ ̲S̲e̲c̲s̲.̲ ̲3̲.̲4̲.̲5̲.̲1̲.̲o̲,̲ ̲3̲.̲4̲.̲5̲.̲7̲.̲a̲.̲4̲,̲ ̲3̲.̲4̲.̲5̲.̲7̲.̲a̲.̲7̲ ̲ ̲
̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲
Case Test
Step No. Station Action Expected Results
̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲
̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲
2.1 OC Boot the MAP test pro-
gram as follows:
Enter from the OC:
BA 1025(CR)
BM 140(CR)
BO 61F(CR) Refer to Appendix
B sec. 2.1
2.2 OC Enter from the OC:
REPORTLEVEL = 0(CR)
TEST ALL(CR) Refer to Appendix
B section 2.2
2.3 OC Quit the MAP test by en-
tering from the OC:
QUIT(CR) Refer to Appendix
B section 1.4
̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲
̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲
Comments:
̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲
̲ ̲
T̲E̲S̲T̲ ̲W̲I̲T̲N̲E̲S̲S̲E̲S̲
TEST QA QAR
T̲E̲S̲T̲ ̲S̲T̲E̲P̲S̲ T̲E̲S̲T̲
̲N̲O̲.̲:̲
̲2̲/̲1̲
F̲U̲N̲C̲T̲I̲O̲N̲:̲ ̲ ̲P̲U̲#̲1̲/̲C̲U̲/̲T̲D̲X̲#̲1̲ ̲F̲u̲n̲c̲t̲i̲o̲n̲a̲l̲ ̲T̲e̲s̲t̲
S̲R̲S̲ ̲R̲E̲F̲E̲R̲E̲N̲C̲E̲:̲ ̲ ̲S̲e̲c̲s̲.̲ ̲3̲.̲4̲.̲5̲.̲1̲.̲o̲,̲ ̲3̲.̲4̲.̲5̲.̲7̲.̲a̲.̲4̲,̲ ̲3̲.̲4̲.̲5̲.̲7̲.̲a̲.̲7̲ ̲ ̲
̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲
Case Test
Step No. Station Action Expected Results
̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲
̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲
3.1 OC Boot the RAM test pro-
gram as follows:
Enter from the OC:
BA 1025(CR)
BM 140(CR)
BO 620(CR) Refer to Appendix
B sec. 3.1
3.2 OC Enter from the OC:
REPORTLEVEL = 0(CR)
TEST ALL(CR) Refer to Appendix
B section 3.2
3.3 OC Quit the RAM test by en-
tering from the OC:
QUIT(CR) Refer to Appendix
B section 3.3
̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲
̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲
Comments:
̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲
̲ ̲
T̲E̲S̲T̲ ̲W̲I̲T̲N̲E̲S̲S̲E̲S̲
TEST QA QAR
T̲E̲S̲T̲ ̲S̲T̲E̲P̲S̲ T̲E̲S̲T̲
̲N̲O̲.̲:̲
̲2̲/̲1̲
F̲U̲N̲C̲T̲I̲O̲N̲:̲ ̲ ̲P̲U̲#̲1̲/̲C̲U̲/̲T̲D̲X̲#̲1̲ ̲F̲u̲n̲c̲t̲i̲o̲n̲a̲l̲ ̲T̲e̲s̲t̲
S̲R̲S̲ ̲R̲E̲F̲E̲R̲E̲N̲C̲E̲:̲ ̲ ̲S̲e̲c̲s̲.̲ ̲3̲.̲4̲.̲5̲.̲1̲.̲o̲,̲ ̲3̲.̲4̲.̲5̲.̲7̲.̲a̲.̲4̲,̲ ̲3̲.̲4̲.̲5̲.̲7̲.̲a̲.̲7̲ ̲ ̲
̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲
Case Test
Step No. Station Action Expected Results
̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲
̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲
3.4 OC Enter from the OC:
IR 1A23(CR)
IR 1A25(CR)
IR 1A26(CR)
IR 1A07(CR)
IR 1A08(CR)
IR 1A0B(CR)
Refer to Appendix
B
section 3.4
3.5 OC Enter from the OC:
ZP(CR) Either:
ZP
Or:
ZP
Parity error(s)
X
̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲
̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲
Comments:
̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲
̲ ̲
T̲E̲S̲T̲ ̲W̲I̲T̲N̲E̲S̲S̲E̲S̲
TEST QA QAR
T̲E̲S̲T̲ ̲S̲T̲E̲P̲S̲ T̲E̲S̲T̲
̲N̲O̲.̲:̲
̲2̲/̲1̲
F̲U̲N̲C̲T̲I̲O̲N̲:̲ ̲ ̲P̲U̲#̲1̲/̲C̲U̲/̲T̲D̲X̲#̲1̲ ̲F̲u̲n̲c̲t̲i̲o̲n̲a̲l̲ ̲T̲e̲s̲t̲
S̲R̲S̲ ̲R̲E̲F̲E̲R̲E̲N̲C̲E̲:̲ ̲ ̲S̲e̲c̲s̲.̲ ̲3̲.̲4̲.̲5̲.̲1̲.̲o̲,̲ ̲3̲.̲4̲.̲5̲.̲7̲.̲a̲.̲4̲,̲ ̲3̲.̲4̲.̲5̲.̲7̲.̲a̲.̲7̲ ̲ ̲
̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲
Case Test
Step No. Station Action Expected Results
̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲
̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲
3.6 OC Enter from the OC:
ZP1(CR) Either:
ZP1
ZP8(CR) Or:
ZP1
Parity error(s)
X
3.7 OC Enter from the OC:
IR 1823(CR)
IR 1825(CR)
IR 1826(CR)
IR 1807(CR)
IR 1808(CR)
IR 180B(CR)
Refer to Appendix
B
section 3.5
The steps from 3.4
to 3.7 incl. have reset
possible parity errors
in the CU memories
̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲
̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲
Comments:
̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲
̲ ̲
T̲E̲S̲T̲ ̲W̲I̲T̲N̲E̲S̲S̲E̲S̲
TEST QA QAR
T̲E̲S̲T̲ ̲S̲T̲E̲P̲S̲ T̲E̲S̲T̲
̲N̲O̲.̲:̲
̲2̲/̲1̲
F̲U̲N̲C̲T̲I̲O̲N̲:̲ ̲ ̲P̲U̲#̲1̲/̲C̲U̲/̲T̲D̲X̲#̲1̲ ̲F̲u̲n̲c̲t̲i̲o̲n̲a̲l̲ ̲T̲e̲s̲t̲
S̲R̲S̲ ̲R̲E̲F̲E̲R̲E̲N̲C̲E̲:̲ ̲ ̲S̲e̲c̲s̲.̲ ̲3̲.̲4̲.̲5̲.̲1̲.̲o̲,̲ ̲3̲.̲4̲.̲5̲.̲7̲.̲a̲.̲4̲,̲ ̲3̲.̲4̲.̲5̲.̲7̲.̲a̲.̲7̲ ̲ ̲
̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲
Case Test
Step No. Station Action Expected Results
̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲
̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲
4.1 OC Boot the Disk test-
program as follows:
Enter from the OC:
BA 1025(CR)
BM 140(CR)
BO 634(CR) Refer to Appendix
B
sec. 4.1
4.2 N/A Depress the "START" N/A.
pushbutton on disk
drive #2 and wait un-
til the "START"and
"READY" indicators are
"OFF". Replace the test
software disk pack in
Disk Drive # 2 with a
scratch disk pack.
Push the drive back
into rack B.
Activate the "START"
pushbutton on Drive #2
and wait until the
"READY"indicator stays
"ON". Depress the
WRITE PROTECT push-
button. (WRITE PROTECT
indicator is 'OFF')
̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲
̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲
Comments:
̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲
̲ ̲
T̲E̲S̲T̲ ̲W̲I̲T̲N̲E̲S̲S̲E̲S̲
TEST QA QAR
T̲E̲S̲T̲ ̲S̲T̲E̲P̲S̲ T̲E̲S̲T̲
̲N̲O̲.̲:̲
̲2̲/̲1̲
F̲U̲N̲C̲T̲I̲O̲N̲:̲ ̲ ̲P̲U̲#̲1̲/̲C̲U̲/̲T̲D̲X̲#̲1̲ ̲F̲u̲n̲c̲t̲i̲o̲n̲a̲l̲ ̲T̲e̲s̲t̲
S̲R̲S̲ ̲R̲E̲F̲E̲R̲E̲N̲C̲E̲:̲ ̲ ̲S̲e̲c̲s̲.̲ ̲3̲.̲4̲.̲5̲.̲1̲.̲o̲,̲ ̲3̲.̲4̲.̲5̲.̲7̲.̲a̲.̲4̲,̲ ̲3̲.̲4̲.̲5̲.̲7̲.̲a̲.̲7̲ ̲ ̲
̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲
Case Test
Step No. Station Action Expected Results
̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲
̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲
4.3 OC Activate the Disk test
as follows:
Enter from the OC: Refer to Appendix
B
DO TEST sec. 4.2
(Appendix A, sec. 2.1)
4.4 OC Quit the Disk test
by entering from the OC: Refer to Appendix
B
QUIT(CR) sec. 1.4
4.5 N/A Depress the "START" N/A.
pushbutton on disk
drive #2 and wait un-
til the "START"and
"READY" indicators are
"OFF". Replace the
scratch disk pack in
Disk Drive # 2 with the
test software disk pack.
Push the drive back
into rack B.
Activate the "START"
pushbutton on Drive #2
and wait until the
"READY"indicator stays
"ON". Activate the WRITE
PROTECT pushbutton.
(WRITE PROTECT indicator 'ON')
̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲
̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲
Comments:
̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲
̲ ̲
T̲E̲S̲T̲ ̲W̲I̲T̲N̲E̲S̲S̲E̲S̲
TEST QA QAR
T̲E̲S̲T̲ ̲S̲T̲E̲P̲S̲ T̲E̲S̲T̲
̲N̲O̲.̲:̲
̲2̲/̲1̲
F̲U̲N̲C̲T̲I̲O̲N̲:̲ ̲ ̲P̲U̲#̲1̲/̲C̲U̲/̲T̲D̲X̲#̲1̲ ̲F̲u̲n̲c̲t̲i̲o̲n̲a̲l̲ ̲T̲e̲s̲t̲
S̲R̲S̲ ̲R̲E̲F̲E̲R̲E̲N̲C̲E̲:̲ ̲ ̲S̲e̲c̲s̲.̲ ̲3̲.̲4̲.̲5̲.̲1̲.̲o̲,̲ ̲3̲.̲4̲.̲5̲.̲7̲.̲a̲.̲4̲,̲ ̲3̲.̲4̲.̲5̲.̲7̲.̲a̲.̲7̲ ̲ ̲
̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲
Case Test
Step No. Station Action Expected Results
̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲
̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲
5.1.1 OC Boot the LTU test-
program as follows:
Enter from the OC:
BA 1025(CR)
BM 140(CR) Refer to Appendix
B
BO 635(CR) sec. 5.1
5.1.2 N/A Connect the TEST VDU N/A
to J30 in the V24 fil-
ter box via testcable A.
5.1.3 OC Activate the LTU#1
channel 1 test as follows:
Enter from the OC: Refer to Appendix
B
DO LTU11(CR) sec. 5.2
(Appendix A, sec. 3.1)
5.2.1 N/A Connect the TEST VDU N/A
to J31 in the V24 fil-
ter box via testcable A.
5.2.2 OC Activate the LTU#2
channel 1 test as follows:
Enter from the OC: Refer to Appendix
B
DO LTU21(CR) sec. 5.3
(Appendix A, sec. 3.2)
̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲
̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲
Comments:
̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲
̲ ̲
T̲E̲S̲T̲ ̲W̲I̲T̲N̲E̲S̲S̲E̲S̲
TEST QA QAR
T̲E̲S̲T̲ ̲S̲T̲E̲P̲S̲ T̲E̲S̲T̲
̲N̲O̲.̲:̲
̲2̲/̲1̲
F̲U̲N̲C̲T̲I̲O̲N̲:̲ ̲ ̲P̲U̲#̲1̲/̲C̲U̲/̲T̲D̲X̲#̲1̲ ̲F̲u̲n̲c̲t̲i̲o̲n̲a̲l̲ ̲T̲e̲s̲t̲
S̲R̲S̲ ̲R̲E̲F̲E̲R̲E̲N̲C̲E̲:̲ ̲ ̲S̲e̲c̲s̲.̲ ̲3̲.̲4̲.̲5̲.̲1̲.̲o̲,̲ ̲3̲.̲4̲.̲5̲.̲7̲.̲a̲.̲4̲,̲ ̲3̲.̲4̲.̲5̲.̲7̲.̲a̲.̲7̲ ̲ ̲
̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲
Case Test
Step No. Station Action Expected Results
̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲
̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲
5.2.3 OCA Quit the LTU test pro-
gram by entering from Refer to Appendix
B
OC: QUIT(CR) section 3.3
5.3.1 Connect 4 loop-back
connectors in LIA-N #3,
J1 to J4. Insert LTU64
test in the floppy disk
drive 0.
̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲
̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲
Comments:
̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲
̲ ̲
T̲E̲S̲T̲ ̲W̲I̲T̲N̲E̲S̲S̲E̲S̲
TEST QA QAR
…06…1 …02… …02… …02…
T̲E̲S̲T̲ ̲S̲T̲E̲P̲S̲ T̲E̲S̲T̲ ̲N̲O̲.̲:̲ ̲2̲/̲1̲
F̲U̲N̲C̲T̲I̲O̲N̲:̲ ̲ ̲P̲U̲#̲1̲/̲C̲U̲/̲T̲D̲X̲#̲1̲ ̲F̲u̲n̲c̲t̲i̲o̲n̲a̲l̲ ̲T̲e̲s̲t̲
S̲R̲S̲ ̲R̲E̲F̲E̲R̲E̲N̲C̲E̲:̲ ̲ ̲S̲e̲c̲s̲.̲ ̲3̲.̲4̲.̲5̲.̲1̲.̲o̲,̲ ̲3̲.̲4̲.̲5̲.̲7̲.̲a̲.̲4̲,̲ ̲3̲.̲4̲.̲5̲.̲7̲.̲a̲.̲7̲ ̲ ̲
̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲
Case Test
Step No. Station Action Expected
Results
̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲
̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲
5.3.2 OC Boot the 64K test program
as follows. Enter from the
OC:
BA 1001(CR)
BT FD500(CR) Refer
to
Appendix
B
BE (CR) sec. 5.4.
5.3.3 OC Enter from OC:
REPORTLEVEL = 2(CR)
LTU.LOOP ̲BACK ̲TEST
(#100B #420 2400 Refer
Appendix
B
1 1 1 1)(CR) sec.
5.5
5.3.4 OC Quit the LTU 64K test
by entering from the OC: Refer
Appendix
B
QUIT(CR) sec.
3.3.
̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲
̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲
Comments:
̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲
T̲E̲S̲T̲ ̲W̲I̲T̲N̲E̲S̲S̲E̲S̲
TEST QA QAR
T̲E̲S̲T̲ ̲S̲T̲E̲P̲S̲ T̲E̲S̲T̲
̲N̲O̲.̲:̲
̲2̲/̲1̲
F̲U̲N̲C̲T̲I̲O̲N̲:̲ ̲ ̲P̲U̲#̲1̲/̲C̲U̲/̲T̲D̲X̲#̲1̲ ̲F̲u̲n̲c̲t̲i̲o̲n̲a̲l̲ ̲T̲e̲s̲t̲
S̲R̲S̲ ̲R̲E̲F̲E̲R̲E̲N̲C̲E̲:̲ ̲ ̲S̲e̲c̲s̲.̲ ̲3̲.̲4̲.̲5̲.̲1̲.̲o̲,̲ ̲3̲.̲4̲.̲5̲.̲7̲.̲a̲.̲4̲,̲ ̲3̲.̲4̲.̲5̲.̲7̲.̲a̲.̲7̲ ̲ ̲
̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲
Case Test
Step No. Station Action Expected Results
̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲
̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲
6.1 N/A Connect a TEST VDU N/A
via testcable A to
J30 (LTU#11) in the
filter box. VDU set-up:
9600 Baud
Echo Mode
6.2 N/A Swop Disk Controllers in N/A
CU pos. 18 and 20
6.3 Push the Master Clear Refer to Appendix
B sec. 1.1
6.3.1 Depress the WRITE PROTECT
push button on Drive#2
(WRITE PROTECT indicator
is 'OFF')
6.4 OC Enter from the OC: OC print out:
IR1A23 (CR) IR1A23
FFFF
ZP ZP
Parity error(s)
X
ZP1 ZP1
ZP8(CR) Parity error(s)
X
6.5 OC BO 610 Refer to Appendix
B sec. 6.1
̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲
̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲
Comments:
̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲
̲ ̲
T̲E̲S̲T̲ ̲W̲I̲T̲N̲E̲S̲S̲E̲S̲
TEST QA QAR
T̲E̲S̲T̲ ̲S̲T̲E̲P̲S̲ T̲E̲S̲T̲
̲N̲O̲.̲:̲
̲2̲/̲1̲
F̲U̲N̲C̲T̲I̲O̲N̲:̲ ̲ ̲P̲U̲#̲1̲/̲C̲U̲/̲T̲D̲X̲#̲1̲ ̲F̲u̲n̲c̲t̲i̲o̲n̲a̲l̲ ̲T̲e̲s̲t̲
S̲R̲S̲ ̲R̲E̲F̲E̲R̲E̲N̲C̲E̲:̲ ̲ ̲S̲e̲c̲s̲.̲ ̲3̲.̲4̲.̲5̲.̲1̲.̲o̲,̲ ̲3̲.̲4̲.̲5̲.̲7̲.̲a̲.̲4̲,̲ ̲3̲.̲4̲.̲5̲.̲7̲.̲a̲.̲7̲ ̲ ̲
̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲
Case Test
Step No. Station Action Expected Results
̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲
̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲
6.6 OC Enter time and date Refer to Appendix
B sec. 6.2
6.7 OC Enter from the OC
OPEN SYS Refer to Appendix
B
DO CONFIG1 sec. 6.3
6.8 OC Enter from the OC:
PRINTER ̲TASK L: Y
P: TMS*TERM0(CR) Refer to Appendix
B sec 6.4
6.9 OC Enter from the OC:
PRINT PRI Refer to Appendix
B sec. 6.5
6.10 OC Enter from the OC:
DO HCLF20 Refer to Appendix
B sec. 6.6
6.11 OC To terminate the
test enter
from the OC:
KILL SYS00(CR).
If not terminated the Refer to Appendix
B
test runs app. 1/2 hour. sec. 6.7
̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲
̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲
Comments:
̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲
̲ ̲
T̲E̲S̲T̲ ̲W̲I̲T̲N̲E̲S̲S̲E̲S̲
TEST QA QAR
T̲E̲S̲T̲ ̲S̲T̲E̲P̲S̲ T̲E̲S̲T̲
̲N̲O̲.̲:̲
̲2̲/̲1̲
F̲U̲N̲C̲T̲I̲O̲N̲:̲ ̲ ̲P̲U̲#̲1̲/̲C̲U̲/̲T̲D̲X̲#̲1̲ ̲F̲u̲n̲c̲t̲i̲o̲n̲a̲l̲ ̲T̲e̲s̲t̲
S̲R̲S̲ ̲R̲E̲F̲E̲R̲E̲N̲C̲E̲:̲ ̲ ̲S̲e̲c̲s̲.̲ ̲3̲.̲4̲.̲5̲.̲1̲.̲o̲,̲ ̲3̲.̲4̲.̲5̲.̲7̲.̲a̲.̲4̲,̲ ̲3̲.̲4̲.̲5̲.̲7̲.̲a̲.̲7̲ ̲ ̲
̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲
Case Test
Step No. Station Action Expected Results
̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲
̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲
6.12 OC To terminate the
system s/w enter Refer to Appendix
B
from the OC: sec. 6.8
CLOSE(CR)
6.13 N/A Swop the Disk Control- N/A lers
in
CU
pos.18
and
20.
6.14 N/A Activate Master Clear Refer to Appendix
B Sec. 1.1
6.15 OC Enter from the OC OC print out
IR1A25 IR1A25
FFFF
ZP1 ZP1
Parity error(s)
X
̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲
̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲
Comments:
̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲
̲ ̲
T̲E̲S̲T̲ ̲W̲I̲T̲N̲E̲S̲S̲E̲S̲
TEST QA QAR
T̲E̲S̲T̲ ̲S̲T̲E̲P̲S̲ T̲E̲S̲T̲
̲N̲O̲.̲:̲
̲2̲/̲1̲
F̲U̲N̲C̲T̲I̲O̲N̲:̲ ̲ ̲P̲U̲#̲1̲/̲C̲U̲/̲T̲D̲X̲#̲1̲ ̲F̲u̲n̲c̲t̲i̲o̲n̲a̲l̲ ̲T̲e̲s̲t̲
S̲R̲S̲ ̲R̲E̲F̲E̲R̲E̲N̲C̲E̲:̲ ̲ ̲S̲e̲c̲s̲.̲ ̲3̲.̲4̲.̲5̲.̲1̲.̲o̲,̲ ̲3̲.̲4̲.̲5̲.̲7̲.̲a̲.̲4̲,̲ ̲3̲.̲4̲.̲5̲.̲7̲.̲a̲.̲7̲ ̲ ̲
̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲
Case Test
Step No. Station Action Expected Results
̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲
̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲
6.16 N/A Activate the N/A
WRITE PROTECT push-
button on Drive#2.
(WRITE PROTECT indica-
tor is 'ON')
6.17 N/A Activate Master Clear. Refer to Appendix
B sec. 1.1
̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲
̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲
Comments:
̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲
̲ ̲
T̲E̲S̲T̲ ̲W̲I̲T̲N̲E̲S̲S̲E̲S̲
TEST QA QAR
T̲E̲S̲T̲ ̲S̲T̲E̲P̲S̲ T̲E̲S̲T̲
̲N̲O̲.̲:̲
̲2̲/̲1̲
F̲U̲N̲C̲T̲I̲O̲N̲:̲ ̲ ̲P̲U̲#̲1̲/̲C̲U̲/̲T̲D̲X̲#̲1̲ ̲F̲u̲n̲c̲t̲i̲o̲n̲a̲l̲ ̲T̲e̲s̲t̲
S̲R̲S̲ ̲R̲E̲F̲E̲R̲E̲N̲C̲E̲:̲ ̲ ̲S̲e̲c̲s̲.̲ ̲3̲.̲4̲.̲5̲.̲1̲.̲o̲,̲ ̲3̲.̲4̲.̲5̲.̲7̲.̲a̲.̲4̲,̲ ̲3̲.̲4̲.̲5̲.̲7̲.̲a̲.̲7̲ ̲ ̲
̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲
Case Test
Step No. Station Action Expected Results
̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲
̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲
7.1 OC Boot the TDX1 test pro-
gram as follows:
BA 1025(CR)
BM 140(CR) Refer to Appendix
B
BO 62F(CR) sec 7.1
7.2 OC Activate the link 11x-21x
LTUX-S test as fol-
lows:
Enter from the OC:
DO OPEN1(CR)
(Appendix A, sec. 4.7a)
DO VDU8(CR)
(Appendix A, sec. 4.1) OC print out
as
DO CLOSE1(CR) specified in
appen-
(Appendix A, sec. 4.7b) dix B, sec. 7.2
7.3 OC Activate the link 12x-22x
LTUX-S test as fol-
lows:
Enter from the OC:
DO OPEN2(CR)
(Appendix A, sec. 4.8a)
DO VDU8(CR)
(Appendix A, sec. 4.1) OC print out
as
DO CLOSE2(CR) specified in
appen-
(Appendix A, sec. 4.8b) dix B, sec. 7.3
̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲
̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲
Comments:
̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲
̲ ̲
T̲E̲S̲T̲ ̲W̲I̲T̲N̲E̲S̲S̲E̲S̲
TEST QA QAR
T̲E̲S̲T̲ ̲S̲T̲E̲P̲S̲ T̲E̲S̲T̲
̲N̲O̲.̲:̲
̲2̲/̲1̲
F̲U̲N̲C̲T̲I̲O̲N̲:̲ ̲ ̲P̲U̲#̲1̲/̲C̲U̲/̲T̲D̲X̲#̲1̲ ̲F̲u̲n̲c̲t̲i̲o̲n̲a̲l̲ ̲T̲e̲s̲t̲
S̲R̲S̲ ̲R̲E̲F̲E̲R̲E̲N̲C̲E̲:̲ ̲ ̲S̲e̲c̲s̲.̲ ̲3̲.̲4̲.̲5̲.̲1̲.̲o̲,̲ ̲3̲.̲4̲.̲5̲.̲7̲.̲a̲.̲4̲,̲ ̲3̲.̲4̲.̲5̲.̲7̲.̲a̲.̲7̲ ̲ ̲
̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲
Case Test
Step No. Station Action Expected Results
̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲
̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲
7.4.1 Powerdown TU#3 N/A
Connect 3 test VDU's
to J32 in the CRT-A
V24 filterbox and to
J32, J28 in the CRT-B
filterbox. All via
testcable A
Power up TU#3
7.4.2 OC Activate the link 13x
LTUX-S test as fol-
lows:
Enter from the OC:
DO OPEN13(CR)
(Appendix A, sec. 4.9a)
DO VDU4(CR)
(Appendix A, sec. 4.2) OC print out
as
DO CLOSE13(CR) specified in
Appen-
(Appendix A, sec. 4.9b) dix B, sec. 7.4
̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲
̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲
Comments:
̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲
̲ ̲
T̲E̲S̲T̲ ̲W̲I̲T̲N̲E̲S̲S̲E̲S̲
TEST QA QAR
T̲E̲S̲T̲ ̲S̲T̲E̲P̲S̲ T̲E̲S̲T̲
̲N̲O̲.̲:̲
̲2̲/̲1̲
F̲U̲N̲C̲T̲I̲O̲N̲:̲ ̲ ̲P̲U̲#̲1̲/̲C̲U̲/̲T̲D̲X̲#̲1̲ ̲F̲u̲n̲c̲t̲i̲o̲n̲a̲l̲ ̲T̲e̲s̲t̲
S̲R̲S̲ ̲R̲E̲F̲E̲R̲E̲N̲C̲E̲:̲ ̲ ̲S̲e̲c̲s̲.̲ ̲3̲.̲4̲.̲5̲.̲1̲.̲o̲,̲ ̲3̲.̲4̲.̲5̲.̲7̲.̲a̲.̲4̲,̲ ̲3̲.̲4̲.̲5̲.̲7̲.̲a̲.̲7̲ ̲ ̲
̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲
Case Test
Step No. Station Action Expected Results
̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲
̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲
7.5.1 N/A Power down TU#4 N/A
N/A Connect 1 test MSP to N/A
J31 in the CRT-A
filterbox
Power up TU#4
7.5.2 OC Activate the link 14x
LTUX-S test as fol-
lows:
Enter from the OC:
DO OPEN14(CR) MSP 14X print
out
(Appendix A, sec. 4.12a) as specified
in ap-
DO MSP (CR) pendix B, sec.8.1
(Appendix A, sec.4.3)
DO CLOSE14(CR) OC print out
as
(Appendix A, sec. 4.12b) specified in
Appen-
dix B, sec. 7.6
̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲
̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲
Comments:
̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲
̲ ̲
T̲E̲S̲T̲ ̲W̲I̲T̲N̲E̲S̲S̲E̲S̲
TEST QA QAR
T̲E̲S̲T̲ ̲S̲T̲E̲P̲S̲ T̲E̲S̲T̲
̲N̲O̲.̲:̲
̲2̲/̲1̲
F̲U̲N̲C̲T̲I̲O̲N̲:̲ ̲ ̲P̲U̲#̲1̲/̲C̲U̲/̲T̲D̲X̲#̲1̲ ̲F̲u̲n̲c̲t̲i̲o̲n̲a̲l̲ ̲T̲e̲s̲t̲
S̲R̲S̲ ̲R̲E̲F̲E̲R̲E̲N̲C̲E̲:̲ ̲ ̲S̲e̲c̲s̲.̲ ̲3̲.̲4̲.̲5̲.̲1̲.̲o̲,̲ ̲3̲.̲4̲.̲5̲.̲7̲.̲a̲.̲4̲,̲ ̲3̲.̲4̲.̲5̲.̲7̲.̲a̲.̲7̲ ̲ ̲
̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲
Case Test
Step No. Station Action Expected Results
̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲
̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲
7.5.3 OC Activate the link 24x
LTUX-S test as fol-
lows:
Enter from the OC:
DO OPEN24(CR) MSP24X print
out as
(Appendix A, sec. 4.13a) specified in
appen-
DO MSP (CR) dix B, sec. 8.1
(Appendix A, sec. 4.3)
DO CLOSE24(CR) OC print out
as
(Appendix A, sec. 4.13b) specified in
Appen-
dix B, sec. 7.7
7.5.4 N/A Power down TU#4. N/A
Disconnect test MSP
Power up TU#4
7.5.5 Quit the test program
by entering from the
OC: QUIT(CR) Refer to Appendix
A sec. 1.4
7.6 Boot the TDX2 test
program as follows:
BA 1025 (CR)
BM 140 (CR) Refer to Appendix
B
BO 630 sec. 7.8
̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲
̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲
Comments:
̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲
̲ ̲
T̲E̲S̲T̲ ̲W̲I̲T̲N̲E̲S̲S̲E̲S̲
TEST QA QAR
T̲E̲S̲T̲ ̲S̲T̲E̲P̲S̲ T̲E̲S̲T̲
̲N̲O̲.̲:̲
̲2̲/̲1̲
F̲U̲N̲C̲T̲I̲O̲N̲:̲ ̲ ̲P̲U̲#̲1̲/̲C̲U̲/̲T̲D̲X̲#̲1̲ ̲F̲u̲n̲c̲t̲i̲o̲n̲a̲l̲ ̲T̲e̲s̲t̲
S̲R̲S̲ ̲R̲E̲F̲E̲R̲E̲N̲C̲E̲:̲ ̲ ̲S̲e̲c̲s̲.̲ ̲3̲.̲4̲.̲5̲.̲1̲.̲o̲,̲ ̲3̲.̲4̲.̲5̲.̲7̲.̲a̲.̲4̲,̲ ̲3̲.̲4̲.̲5̲.̲7̲.̲a̲.̲7̲ ̲ ̲
̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲
Case Test
Step No. Station Action Expected Results
̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲
̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲
7.6.1 N/A Power down TU#5 N/A
Connect the 4 test VDUs
to J1-4 in the V24 fil-
ter box via test cables.
Power up TU#5
7.6.2 OC Activate the link 15x
LTUX-S test as fol-
lows:
Enter from the OC: OC print out
as
DO OPEN15(CR) specified in
appen-
(Appendix A, sec.4.14a) dix B sec. 7.9
DO VDU4 (CR)
(Appendix A, sec.4.2)
DO CLOSE15(CR)
(Appendix A, sec.4.14b)
7.7.1 N/A Power down TU#5 N/A
Disconnect 2 test
VDU's from J1 and 4 in the
V24 filter box and connect
the 2 test VDU's to J5 and
via test cable A to J25.
Disconnect W202 and W203
from ch 2 and 3 on the V24
L/L in pos. 7 and connect
then to ch 2 and 3 respectively
on the V24 L/L pos 15
Power up TU#5
̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲
̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲
Comments:
̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲
̲ ̲
T̲E̲S̲T̲ ̲W̲I̲T̲N̲E̲S̲S̲E̲S̲
TEST QA QAR
T̲E̲S̲T̲ ̲S̲T̲E̲P̲S̲ T̲E̲S̲T̲
̲N̲O̲.̲:̲
̲2̲/̲1̲
F̲U̲N̲C̲T̲I̲O̲N̲:̲ ̲ ̲P̲U̲#̲1̲/̲C̲U̲/̲T̲D̲X̲#̲1̲ ̲F̲u̲n̲c̲t̲i̲o̲n̲a̲l̲ ̲T̲e̲s̲t̲
S̲R̲S̲ ̲R̲E̲F̲E̲R̲E̲N̲C̲E̲:̲ ̲ ̲S̲e̲c̲s̲.̲ ̲3̲.̲4̲.̲5̲.̲1̲.̲o̲,̲ ̲3̲.̲4̲.̲5̲.̲7̲.̲a̲.̲4̲,̲ ̲3̲.̲4̲.̲5̲.̲7̲.̲a̲.̲7̲ ̲ ̲
̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲
Case Test
Step No. Station Action Expected Results
̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲
̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲
7.7.2 OC Activate the link 25x
LTUX-S test as fol-
lows:
Enter from the OC: OC print out
as
DO OPEN25(CR) specified in
appen-
(Appendix A, sec. 4.15a) dix B sec. 7.10
DO VDU4 (CR)
(Appendix A, sec. 4.2)
DO CLOSE25(CR)
(Appendix A, sec. 4.15b)
7.7.3 N/A Power down TU#5 N/A
Disconnect the 4 test
VDU's from J5, J2, J3 and
J25 in the V24 filter box.
Power up TU#5
̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲
̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲
Comments:
̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲
̲ ̲
T̲E̲S̲T̲ ̲W̲I̲T̲N̲E̲S̲S̲E̲S̲
TEST QA QAR
T̲E̲S̲T̲ ̲S̲T̲E̲P̲S̲ T̲E̲S̲T̲
̲N̲O̲.̲:̲
̲2̲/̲1̲
F̲U̲N̲C̲T̲I̲O̲N̲:̲ ̲ ̲P̲U̲#̲1̲/̲C̲U̲/̲T̲D̲X̲#̲1̲ ̲F̲u̲n̲c̲t̲i̲o̲n̲a̲l̲ ̲T̲e̲s̲t̲
S̲R̲S̲ ̲R̲E̲F̲E̲R̲E̲N̲C̲E̲:̲ ̲ ̲S̲e̲c̲s̲.̲ ̲3̲.̲4̲.̲5̲.̲1̲.̲o̲,̲ ̲3̲.̲4̲.̲5̲.̲7̲.̲a̲.̲4̲,̲ ̲3̲.̲4̲.̲5̲.̲7̲.̲a̲.̲7̲ ̲ ̲
̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲
Case Test
Step No. Station Action Expected Results
̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲
̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲
7.7.4 OC Quit the TDX2 test by
entering from the OC: Refer to Appendix
B
QUIT(CR) sec. 1.4
̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲
̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲
Comments:
̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲
̲ ̲
T̲E̲S̲T̲ ̲W̲I̲T̲N̲E̲S̲S̲E̲S̲
TEST QA QAR
T̲E̲S̲T̲ ̲S̲T̲E̲P̲S̲ T̲E̲S̲T̲
̲N̲O̲.̲:̲
̲2̲/̲1̲
F̲U̲N̲C̲T̲I̲O̲N̲:̲ ̲ ̲P̲U̲#̲1̲/̲C̲U̲/̲T̲D̲X̲#̲1̲ ̲F̲u̲n̲c̲t̲i̲o̲n̲a̲l̲ ̲T̲e̲s̲t̲
S̲R̲S̲ ̲R̲E̲F̲E̲R̲E̲N̲C̲E̲:̲ ̲ ̲S̲e̲c̲s̲.̲ ̲3̲.̲4̲.̲5̲.̲1̲.̲o̲,̲ ̲3̲.̲4̲.̲5̲.̲7̲.̲a̲.̲4̲,̲ ̲3̲.̲4̲.̲5̲.̲7̲.̲a̲.̲7̲ ̲ ̲
̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲
Case Test
Step No. Station Action Expected Results
̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲
̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲
7.8 Boot the TDX5 test as
follows:
BA 1025(CR)
BM 140(CR) Refer to Appendix
BO 633(CR) B sec. 7.21
̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲
̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲
Comments:
̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲
̲ ̲
T̲E̲S̲T̲ ̲W̲I̲T̲N̲E̲S̲S̲E̲S̲
TEST QA QAR
T̲E̲S̲T̲ ̲S̲T̲E̲P̲S̲ T̲E̲S̲T̲
̲N̲O̲.̲:̲
̲2̲/̲1̲
F̲U̲N̲C̲T̲I̲O̲N̲:̲ ̲ ̲P̲U̲#̲1̲/̲C̲U̲/̲T̲D̲X̲#̲1̲ ̲F̲u̲n̲c̲t̲i̲o̲n̲a̲l̲ ̲T̲e̲s̲t̲
S̲R̲S̲ ̲R̲E̲F̲E̲R̲E̲N̲C̲E̲:̲ ̲ ̲S̲e̲c̲s̲.̲ ̲3̲.̲4̲.̲5̲.̲1̲.̲o̲,̲ ̲3̲.̲4̲.̲5̲.̲7̲.̲a̲.̲4̲,̲ ̲3̲.̲4̲.̲5̲.̲7̲.̲a̲.̲7̲ ̲ ̲
̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲
Case Test
Step No. Station Action Expected Results
̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲
̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲
7.8.1 N/A Power down TU#5
Connect the TTY to J1
in the V24 filter box.
Set switch S2 on LTUX-S
#15 to:
1: CLOSED
2: OPEN
3: OPEN
4: OPEN
Power up TU#5 N/A
7.8.2 OC Activate the link 151
LTUX-S test as follows:
Enter from the OC: OC print out
as
DO OPEN151(CR) specified in
appen-
(Appendix A, sec.4.40a) dix B sec. 7.22.
DO TTY(CR) TTY print out
(Appendix A, sec.4.6) as specified
in ap-
DO CLOSE151(CR) pendix B, sec.8.2
(Appendix A,sec.4.40b)
7.8.3 N/A Power down TU#5. Set N/A
switch S2 on LTUX-S
#15 to:
1: CLOSED
2: CLOSED
3: CLOSED
4: CLOSED
Power up to TU#5
̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲
̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲
Comments:
̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲
̲ ̲
T̲E̲S̲T̲ ̲W̲I̲T̲N̲E̲S̲S̲E̲S̲
TEST QA QAR
T̲E̲S̲T̲ ̲S̲T̲E̲P̲S̲ T̲E̲S̲T̲
̲N̲O̲.̲:̲
̲2̲/̲1̲
F̲U̲N̲C̲T̲I̲O̲N̲:̲ ̲ ̲P̲U̲#̲1̲/̲C̲U̲/̲T̲D̲X̲#̲1̲ ̲F̲u̲n̲c̲t̲i̲o̲n̲a̲l̲ ̲T̲e̲s̲t̲
S̲R̲S̲ ̲R̲E̲F̲E̲R̲E̲N̲C̲E̲:̲ ̲ ̲S̲e̲c̲s̲.̲ ̲3̲.̲4̲.̲5̲.̲1̲.̲o̲,̲ ̲3̲.̲4̲.̲5̲.̲7̲.̲a̲.̲4̲,̲ ̲3̲.̲4̲.̲5̲.̲7̲.̲a̲.̲7̲ ̲ ̲
̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲
Case Test
Step No. Station Action Expected Results
̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲
̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲
7.8.4 OC Quit the TDX test by
entering from the OC: Refer to Appendix
QUIT(CR) B, sec. 1.4
7.9 OC Boot the TDX4 test
program as follows Refer to Appendix
BA 1025(CR) B, sec. 7.18
BM 140(CR)
BO 632(CR)
̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲
̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲
Comments:
̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲
̲ ̲
T̲E̲S̲T̲ ̲W̲I̲T̲N̲E̲S̲S̲E̲S̲
TEST QA QAR
T̲E̲S̲T̲ ̲S̲T̲E̲P̲S̲ T̲E̲S̲T̲
̲N̲O̲.̲:̲
̲2̲/̲1̲
F̲U̲N̲C̲T̲I̲O̲N̲:̲ ̲ ̲P̲U̲#̲1̲/̲C̲U̲/̲T̲D̲X̲#̲1̲ ̲F̲u̲n̲c̲t̲i̲o̲n̲a̲l̲ ̲T̲e̲s̲t̲
S̲R̲S̲ ̲R̲E̲F̲E̲R̲E̲N̲C̲E̲:̲ ̲ ̲S̲e̲c̲s̲.̲ ̲3̲.̲4̲.̲5̲.̲1̲.̲o̲,̲ ̲3̲.̲4̲.̲5̲.̲7̲.̲a̲.̲4̲,̲ ̲3̲.̲4̲.̲5̲.̲7̲.̲a̲.̲7̲ ̲ ̲
̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲
Case Test
Step No. Station Action Expected Results
̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲
̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲
7.9.1 N/A Powerdown PU#5
Connect the PTP/R to N/A
J25 in the V24 fil-
ter box. Set switch S2
on LTUX-S #25 to:
1: Closed
2: Closed
3: Open
4: Closed
Power up TU#5.
7.9.2 OC Activate the link 254
LTUX-S test as follows:
Enter from the OC:
DO OPEN254(CR)
(Appendix A, sec.4.36a)
DO PTP(CR) A piece of tape
is
(Appendix A, sec.4.4a) punched. Tear
it off and feed
it into the
reader with the
reader switch
load/run in position
load.
̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲
̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲
Comments:
̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲
̲ ̲
T̲E̲S̲T̲ ̲W̲I̲T̲N̲E̲S̲S̲E̲S̲
TEST QA QAR
T̲E̲S̲T̲ ̲S̲T̲E̲P̲S̲ T̲E̲S̲T̲
̲N̲O̲.̲:̲
̲2̲/̲1̲
F̲U̲N̲C̲T̲I̲O̲N̲:̲ ̲ ̲P̲U̲#̲1̲/̲C̲U̲/̲T̲D̲X̲#̲1̲ ̲F̲u̲n̲c̲t̲i̲o̲n̲a̲l̲ ̲T̲e̲s̲t̲
S̲R̲S̲ ̲R̲E̲F̲E̲R̲E̲N̲C̲E̲:̲ ̲ ̲S̲e̲c̲s̲.̲ ̲3̲.̲4̲.̲5̲.̲1̲.̲o̲,̲ ̲3̲.̲4̲.̲5̲.̲7̲.̲a̲.̲4̲,̲ ̲3̲.̲4̲.̲5̲.̲7̲.̲a̲.̲7̲ ̲ ̲
̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲
Case Test
Step No. Station Action Expected Results
̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲
̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲
7.9.3 OC Enter from the OC:
cont.
DO PTR(CR) The load/run
switch
(Appendix A, sec. 4.4b) is set to run.
OC print out
as specified
in app. B sec.
7.20
DO CLOSE 254(CR)
Appendix A, sec. 4.36b)
7.9.4 N/A Power down TU#5.
Remove PTP/R from J25.
Set switch S2 on LTUX-S
#25 to 1: CLOSED
2: CLOSED
3: CLOSED
4: CLOSED
Power up TU#5.
̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲
̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲
Comments:
̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲
̲ ̲
T̲E̲S̲T̲ ̲W̲I̲T̲N̲E̲S̲S̲E̲S̲
TEST QA QAR
T̲E̲S̲T̲ ̲S̲T̲E̲P̲S̲ T̲E̲S̲T̲
̲N̲O̲.̲:̲
̲2̲/̲1̲
F̲U̲N̲C̲T̲I̲O̲N̲:̲ ̲ ̲P̲U̲#̲1̲/̲C̲U̲/̲T̲D̲X̲#̲1̲ ̲F̲u̲n̲c̲t̲i̲o̲n̲a̲l̲ ̲T̲e̲s̲t̲
S̲R̲S̲ ̲R̲E̲F̲E̲R̲E̲N̲C̲E̲:̲ ̲ ̲S̲e̲c̲s̲.̲ ̲3̲.̲4̲.̲5̲.̲1̲.̲o̲,̲ ̲3̲.̲4̲.̲5̲.̲7̲.̲a̲.̲4̲,̲ ̲3̲.̲4̲.̲5̲.̲7̲.̲a̲.̲7̲ ̲ ̲
̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲
Case Test
Step No. Station Action Expected Results
̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲
̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲
7.10.1 N/A Power down TU#3 N/A
Connect the test VDU to
J32in the V24 filter box
via test cable A.
Test VDU set up:
2400 Baud
even parity check/generation
1 stop bit
7 bit character length
Power up TU#3
7.10.2 OC Activate the Link 231
LTUX-S test as follows:
Enter from the OC:
DO OPEN231(CR)
(Appendix A, sec.4.30a)
DO OCR(CR)
(Appendix A, sec.4.5) OC print out
as
DO CLOSE231(CR) specified in
appen-
(Appendix A, sec.4.30b) dix B, sec.7.19
a
7.10.3 N/A Power down TU#3 N/A
Disconnect the test VDU
from J32 in the V24 filter
box.
̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲
̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲
Comments:
̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲
̲ ̲
T̲E̲S̲T̲ ̲W̲I̲T̲N̲E̲S̲S̲E̲S̲
TEST QA QAR
T̲E̲S̲T̲ ̲S̲T̲E̲P̲S̲ T̲E̲S̲T̲
̲N̲O̲.̲:̲
̲2̲/̲1̲
F̲U̲N̲C̲T̲I̲O̲N̲:̲ ̲ ̲P̲U̲#̲1̲/̲C̲U̲/̲T̲D̲X̲#̲1̲ ̲F̲u̲n̲c̲t̲i̲o̲n̲a̲l̲ ̲T̲e̲s̲t̲
S̲R̲S̲ ̲R̲E̲F̲E̲R̲E̲N̲C̲E̲:̲ ̲ ̲S̲e̲c̲s̲.̲ ̲3̲.̲4̲.̲5̲.̲1̲.̲o̲,̲ ̲3̲.̲4̲.̲5̲.̲7̲.̲a̲.̲4̲,̲ ̲3̲.̲4̲.̲5̲.̲7̲.̲a̲.̲7̲ ̲ ̲
̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲
Case Test
Step No. Station Action Expected Results
̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲
̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲
7.11.1 N/A Power down TU#7 N/A
Connect 2 test VDU's via
test cable A to J27 in
RCT-A and J27 in RCT-B
V24 filterbox
Test VDU set up:
2400 Baud
even parity check/generation
1 stop bit
7 bit character length
Power up TU#7
7.11.2 OC Activate the Link 171
LTUX-S test as follows:
Enter from the OC:
DO OPEN171(CR)
(Appendix A, sec.4.33a)
DO OCR(CR)
(Appendix A, sec.4.5) OC print out
as
DO CLOSE171(CR) specified in
appen-
(Appendix A, sec.4.33b) dix B, sec.7.19
B
̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲
̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲
Comments:
̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲
̲ ̲
T̲E̲S̲T̲ ̲W̲I̲T̲N̲E̲S̲S̲E̲S̲
TEST QA QAR
T̲E̲S̲T̲ ̲S̲T̲E̲P̲S̲ T̲E̲S̲T̲
̲N̲O̲.̲:̲
̲2̲/̲1̲
F̲U̲N̲C̲T̲I̲O̲N̲:̲ ̲ ̲P̲U̲#̲1̲/̲C̲U̲/̲T̲D̲X̲#̲1̲ ̲F̲u̲n̲c̲t̲i̲o̲n̲a̲l̲ ̲T̲e̲s̲t̲
S̲R̲S̲ ̲R̲E̲F̲E̲R̲E̲N̲C̲E̲:̲ ̲ ̲S̲e̲c̲s̲.̲ ̲3̲.̲4̲.̲5̲.̲1̲.̲o̲,̲ ̲3̲.̲4̲.̲5̲.̲7̲.̲a̲.̲4̲,̲ ̲3̲.̲4̲.̲5̲.̲7̲.̲a̲.̲7̲ ̲ ̲
̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲
Case Test
Step No. Station Action Expected Results
̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲
̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲
7.11.3 OC Activate the Link 271
LTUX-S test as follows:
Enter from the OC:
DO OPEN271(CR)
(Appendix A, sec.4.34a)
DO OCR(CR)
(Appendix A, sec.4.5) OC print out
as
DO CLOSE271(CR) specified in
appen-
(Appendix A, sec.4.34b) dix B, sec.7.19
C
7.11.4 N/A Power down TU#7 N/A
Disconnect test VDU's
from J27 in RCT-A and
RCT-B V24 filterbowex.
Power up TU#7.
7.11.5 OC Quit the test entering
from the OC:
QUIT(CR)
̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲
̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲
Comments:
̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲
̲ ̲
T̲E̲S̲T̲ ̲W̲I̲T̲N̲E̲S̲S̲E̲S̲
TEST QA QAR
T̲E̲S̲T̲ ̲S̲T̲E̲P̲S̲ T̲E̲S̲T̲
̲N̲O̲.̲:̲
̲2̲/̲1̲
F̲U̲N̲C̲T̲I̲O̲N̲:̲ ̲ ̲P̲U̲#̲1̲/̲C̲U̲/̲T̲D̲X̲#̲1̲ ̲F̲u̲n̲c̲t̲i̲o̲n̲a̲l̲ ̲T̲e̲s̲t̲
S̲R̲S̲ ̲R̲E̲F̲E̲R̲E̲N̲C̲E̲:̲ ̲ ̲S̲e̲c̲s̲.̲ ̲3̲.̲4̲.̲5̲.̲1̲.̲o̲,̲ ̲3̲.̲4̲.̲5̲.̲7̲.̲a̲.̲4̲,̲ ̲3̲.̲4̲.̲5̲.̲7̲.̲a̲.̲7̲ ̲ ̲
̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲
Case Test
Step No. Station Action Expected Results
̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲
̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲
7.12.1 OC Boot the TDX3 test as
follows:
BA 1025(CR)
BM 140(CR) Refer to Appendix
B
BO 631(CR) sec. 7.14
7.12.2 N/A Power down the main site N/A
stat. mux.#1
and Remote site A stat.
mux.
Remove the testcable be-
tween the main site fil-
terbox J33 and the Remo-
te site A filterbox J40.
On the main site A and the
Remote site A stat. mux.
set S1 and S2 on the ba-
se board switch group 2
to the CLOSED position
(extern clock). Power up
the main site stat.mux #1
and Remote site A
stat. mux.
7.12.3 N/A Connect the CRYPTO/MODEM N/A
link between main site
filterbox J33 and Remo-
te site A filterbox J40.
̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲
̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲
Comments:
̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲
̲ ̲
T̲E̲S̲T̲ ̲W̲I̲T̲N̲E̲S̲S̲E̲S̲
TEST QA QAR
T̲E̲S̲T̲ ̲S̲T̲E̲P̲S̲ T̲E̲S̲T̲
̲N̲O̲.̲:̲
̲2̲/̲1̲
F̲U̲N̲C̲T̲I̲O̲N̲:̲ ̲ ̲P̲U̲#̲1̲/̲C̲U̲/̲T̲D̲X̲#̲1̲ ̲F̲u̲n̲c̲t̲i̲o̲n̲a̲l̲ ̲T̲e̲s̲t̲
S̲R̲S̲ ̲R̲E̲F̲E̲R̲E̲N̲C̲E̲:̲ ̲ ̲S̲e̲c̲s̲.̲ ̲3̲.̲4̲.̲5̲.̲1̲.̲o̲,̲ ̲3̲.̲4̲.̲5̲.̲7̲.̲a̲.̲4̲,̲ ̲3̲.̲4̲.̲5̲.̲7̲.̲a̲.̲7̲ ̲ ̲
̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲
Case Test
Step No. Station Action Expected Results
̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲
̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲
7.12.4 N/A Power up both MODEMs and N/A
CRYPTOs. If identical
keystores on both CRYPTOs
are on then proceed from
7.24.5 else load the
cryptokey into keystore 1
on both cryptos.
7.12.5 N/A CRYPTO synchronization CRYPTOs are
should be initiated. If synchronized
not CH1.ERR on the
RESYNC MODULE is on.
Activate the RESET push-
button on the RESYNC MO-
DULE.
7.12.6 N/A Set switch S1 on the RTS on the main
MODEM link to OFF site modem goes
off
(MODEM link open circuit) for 1.5 secs
and then on again
for 3 secs.
When RTS on the main site CRYPTOS synchronize.
goes off the second time
set switch S1 to ON.
̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲
̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲
Comments:
̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲
̲ ̲
T̲E̲S̲T̲ ̲W̲I̲T̲N̲E̲S̲S̲E̲S̲
TEST QA QAR
T̲E̲S̲T̲ ̲S̲T̲E̲P̲S̲ T̲E̲S̲T̲
̲N̲O̲.̲:̲
̲2̲/̲1̲
F̲U̲N̲C̲T̲I̲O̲N̲:̲ ̲ ̲P̲U̲#̲1̲/̲C̲U̲/̲T̲D̲X̲#̲1̲ ̲F̲u̲n̲c̲t̲i̲o̲n̲a̲l̲ ̲T̲e̲s̲t̲
S̲R̲S̲ ̲R̲E̲F̲E̲R̲E̲N̲C̲E̲:̲ ̲ ̲S̲e̲c̲s̲.̲ ̲3̲.̲4̲.̲5̲.̲1̲.̲o̲,̲ ̲3̲.̲4̲.̲5̲.̲7̲.̲a̲.̲4̲,̲ ̲3̲.̲4̲.̲5̲.̲7̲.̲a̲.̲7̲ ̲ ̲
̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲
Case Test
Step No. Station Action Expected Results
̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲
̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲
7.12.7 N/A Set switch S1 to OFF After 13.5 secs.
the CH1.ERR indicator
goes on
Set switch S1 to ON No synchronization
is initiated
7.12.8 N/A Activate the RESET push- After 1.5secs
the
button on the RESYNC CRYPTOS synchronize.
MODULE
7.12.9 N/A Set switch S2 on the RTS on the main
MODEM link to OFF site modem goes
off
(MODEM link open circuit) for 1.5 secs
and then on again
for 3 secs.
When RTS on the main site CRYPTOS synchronize.
goes off the second time
set switch S2 to ON.
7.12.10 N/A Set switch S2 to OFF After 13.5 secs.
the CH1.ERR indicator
goes on
Set switch S2 to ON No synchronization
is initiated
̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲
̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲
Comments:
̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲
̲ ̲
T̲E̲S̲T̲ ̲W̲I̲T̲N̲E̲S̲S̲E̲S̲
TEST QA QAR
T̲E̲S̲T̲ ̲S̲T̲E̲P̲S̲ T̲E̲S̲T̲
̲N̲O̲.̲:̲
̲2̲/̲1̲
F̲U̲N̲C̲T̲I̲O̲N̲:̲ ̲ ̲P̲U̲#̲1̲/̲C̲U̲/̲T̲D̲X̲#̲1̲ ̲F̲u̲n̲c̲t̲i̲o̲n̲a̲l̲ ̲T̲e̲s̲t̲
S̲R̲S̲ ̲R̲E̲F̲E̲R̲E̲N̲C̲E̲:̲ ̲ ̲S̲e̲c̲s̲.̲ ̲3̲.̲4̲.̲5̲.̲1̲.̲o̲,̲ ̲3̲.̲4̲.̲5̲.̲7̲.̲a̲.̲4̲,̲ ̲3̲.̲4̲.̲5̲.̲7̲.̲a̲.̲7̲ ̲ ̲
̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲
Case Test
Step No. Station Action Expected Results
̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲
̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲
7.12.11 N/A Activate the RESET push- After 1.5secs
the
button on the RESYNC CRYPTOS synchronize.
MODULE
7.12.12 OC Activate the link 1BX
LTUX-S test as fol-
lows:
Enter from the OC:
DO OPEN1B(CR)
(Appendix A,sec. 4.24a)
DO VDU4(CR)
(Appendix A, sec.4.2)
When a couple of lines Output stops.
have been transmitted to
the remote VDUs set switch
S1 to OFF.
̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲
̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲
Comments:
̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲
̲ ̲
T̲E̲S̲T̲ ̲W̲I̲T̲N̲E̲S̲S̲E̲S̲
TEST QA QAR
T̲E̲S̲T̲ ̲S̲T̲E̲P̲S̲ T̲E̲S̲T̲
̲N̲O̲.̲:̲
̲2̲/̲1̲
F̲U̲N̲C̲T̲I̲O̲N̲:̲ ̲ ̲P̲U̲#̲1̲/̲C̲U̲/̲T̲D̲X̲#̲1̲ ̲F̲u̲n̲c̲t̲i̲o̲n̲a̲l̲ ̲T̲e̲s̲t̲
S̲R̲S̲ ̲R̲E̲F̲E̲R̲E̲N̲C̲E̲:̲ ̲ ̲S̲e̲c̲s̲.̲ ̲3̲.̲4̲.̲5̲.̲1̲.̲o̲,̲ ̲3̲.̲4̲.̲5̲.̲7̲.̲a̲.̲4̲,̲ ̲3̲.̲4̲.̲5̲.̲7̲.̲a̲.̲7̲ ̲ ̲
̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲
Case Test
Step No. Station Action Expected Results
̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲
̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲
7.12.13 N/A When the CH1.ERR. indica- CRYPTOs synchronize
tor goes on set S1 to ON and output is
resumed.
and activate the RESET OC print out
as speci-
pushbutton on the RESYNC fied in appendix
B,
module. Let the testse- sec. 7.23
quence finish normally
7.12.14 OC Enter from the OC:
DO VDU4(CR)
(Appendix A, sec.4.2)
When a couple of lines Output stops.
have been transmitted to
the remote VDUs set switch
S2 to OFF.
7.12.15 N/A When the CH1.ERR. indica- CRYPTOs synchronize
tor goes on set S2 to ON and output is
resumed.
and activate the RESET OC print out
as speci-
pushbutton on the RESYNC fied in appendix
B,
module. Let the testse- sec. 7.23
quence finish normally
Enter from the OC:
DO CLOSE1B (CR)
(Appendix A, sec.4.24b)
̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲
̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲
Comments:
̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲
̲ ̲
T̲E̲S̲T̲ ̲W̲I̲T̲N̲E̲S̲S̲E̲S̲
TEST QA QAR
T̲E̲S̲T̲ ̲S̲T̲E̲P̲S̲ T̲E̲S̲T̲
̲N̲O̲.̲:̲
̲2̲/̲1̲
F̲U̲N̲C̲T̲I̲O̲N̲:̲ ̲ ̲P̲U̲#̲1̲/̲C̲U̲/̲T̲D̲X̲#̲1̲ ̲F̲u̲n̲c̲t̲i̲o̲n̲a̲l̲ ̲T̲e̲s̲t̲
S̲R̲S̲ ̲R̲E̲F̲E̲R̲E̲N̲C̲E̲:̲ ̲ ̲S̲e̲c̲s̲.̲ ̲3̲.̲4̲.̲5̲.̲1̲.̲o̲,̲ ̲3̲.̲4̲.̲5̲.̲7̲.̲a̲.̲4̲,̲ ̲3̲.̲4̲.̲5̲.̲7̲.̲a̲.̲7̲ ̲ ̲
̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲
Case Test
Step No. Station Action Expected Results
̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲
̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲
Power down the main site
stat. max. 1, stat. max. 2
and PU#B. Disconnect
W233, W234, W238, W239 on
the desync. module.
Conect W233 to J4, W234
to J2, W238 to J3 and
W239 to J1.
Power up the main site
stat. max. 1, stat. max. 2
and PU#B.
7.12.15 N/A CRYPTO synchronization CRYPTOs are
should be initiated. If synchronized
not CH1.ERR on the
RESYNC MODULE is on.
Activate the RESET push-
button on the RESYNC MO-
DULE.
7.12.16 N/A Set switch S1 on the RTS on the main
MODEM link to OFF site modem goes
off
(MODEM link open circuit) for 1.5 secs
and then on again
for 3 secs.
When RTS on the main site CRYPTOS synchronize.
goes off the second time
set switch S1 to ON.
̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲
̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲
Comments:
̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲
̲ ̲
T̲E̲S̲T̲ ̲W̲I̲T̲N̲E̲S̲S̲E̲S̲
TEST QA QAR
T̲E̲S̲T̲ ̲S̲T̲E̲P̲S̲ T̲E̲S̲T̲
̲N̲O̲.̲:̲
̲2̲/̲1̲
F̲U̲N̲C̲T̲I̲O̲N̲:̲ ̲ ̲P̲U̲#̲1̲/̲C̲U̲/̲T̲D̲X̲#̲1̲ ̲F̲u̲n̲c̲t̲i̲o̲n̲a̲l̲ ̲T̲e̲s̲t̲
S̲R̲S̲ ̲R̲E̲F̲E̲R̲E̲N̲C̲E̲:̲ ̲ ̲S̲e̲c̲s̲.̲ ̲3̲.̲4̲.̲5̲.̲1̲.̲o̲,̲ ̲3̲.̲4̲.̲5̲.̲7̲.̲a̲.̲4̲,̲ ̲3̲.̲4̲.̲5̲.̲7̲.̲a̲.̲7̲ ̲ ̲
̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲
Case Test
Step No. Station Action Expected Results
̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲
̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲
7.12.18 N/A Set switch S1 to OFF After 13.5 secs.
the CH1.ERR indicator
goes on
Set switch S1 to ON No synchronization
is initiated
7.12.19 N/A Activate the RESET push- After 1.5secs
the
button on the RESYNC CRYPTOS synchronize.
MODULE
7.12.20 N/A Set switch S2 on the RTS on the main
MODEM link to OFF site modem goes
off
(MODEM link open circuit) for 1.5 secs
and then on again
for 3 secs.
When RTS on the main site CRYPTOS synchronize.
goes off the second time
set switch S2 to ON.
7.12.21 N/A Set switch S2 to OFF After 13.5 secs.
the CH1.ERR indicator
goes on
Set switch S2 to ON No synchronization
is initiated
̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲
̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲
Comments:
̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲
̲ ̲
T̲E̲S̲T̲ ̲W̲I̲T̲N̲E̲S̲S̲E̲S̲
TEST QA QAR
T̲E̲S̲T̲ ̲S̲T̲E̲P̲S̲ T̲E̲S̲T̲
̲N̲O̲.̲:̲
̲2̲/̲1̲
F̲U̲N̲C̲T̲I̲O̲N̲:̲ ̲ ̲P̲U̲#̲1̲/̲C̲U̲/̲T̲D̲X̲#̲1̲ ̲F̲u̲n̲c̲t̲i̲o̲n̲a̲l̲ ̲T̲e̲s̲t̲
S̲R̲S̲ ̲R̲E̲F̲E̲R̲E̲N̲C̲E̲:̲ ̲ ̲S̲e̲c̲s̲.̲ ̲3̲.̲4̲.̲5̲.̲1̲.̲o̲,̲ ̲3̲.̲4̲.̲5̲.̲7̲.̲a̲.̲4̲,̲ ̲3̲.̲4̲.̲5̲.̲7̲.̲a̲.̲7̲ ̲ ̲
̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲
Case Test
Step No. Station Action Expected Results
̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲
̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲
7.12.22 N/A Activate the RESET push- After 1.5secs
the
button on the RESYNC CRYPTOS synchronize.
MODULE
7.12.23 OC Activate the link 1BX
LTUX-S test as fol-
lows:
Enter from the OC:
DO OPEN2B(CR)
(Appendix A,sec. 4.25a)
DO MSP(CR)
(Appendix A, sec.4.3)
When a couple of lines Output stops.
have been transmitted to
the remote MSPs set switch
S1 to OFF.
̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲
̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲
Comments:
̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲
̲ ̲
T̲E̲S̲T̲ ̲W̲I̲T̲N̲E̲S̲S̲E̲S̲
TEST QA QAR
T̲E̲S̲T̲ ̲S̲T̲E̲P̲S̲ T̲E̲S̲T̲
̲N̲O̲.̲:̲
̲2̲/̲1̲
F̲U̲N̲C̲T̲I̲O̲N̲:̲ ̲ ̲P̲U̲#̲1̲/̲C̲U̲/̲T̲D̲X̲#̲1̲ ̲F̲u̲n̲c̲t̲i̲o̲n̲a̲l̲ ̲T̲e̲s̲t̲
S̲R̲S̲ ̲R̲E̲F̲E̲R̲E̲N̲C̲E̲:̲ ̲ ̲S̲e̲c̲s̲.̲ ̲3̲.̲4̲.̲5̲.̲1̲.̲o̲,̲ ̲3̲.̲4̲.̲5̲.̲7̲.̲a̲.̲4̲,̲ ̲3̲.̲4̲.̲5̲.̲7̲.̲a̲.̲7̲ ̲ ̲
̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲
Case Test
Step No. Station Action Expected Results
̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲
̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲
7.12.24 N/A When the CH1.ERR. indica- CRYPTOs synchronize
tor goes on set S1 to ON and output is
resumed.
and activate the RESET OC print out
as speci-
pushbutton on the RESYNC fied in appendix
B,
module. Let the testse- sec. 7.24
quence finish normally
7.12.25 OC Enter from the OC:
DO MSP(CR)
(Appendix A, sec.4.3)
When a couple of lines Output stops.
have been transmitted to
the remote VDUs set switch
S2 to OFF.
7.12.26 N/A When the CH1.ERR. indica- CRYPTOs synchronize
tor goes on set S2 to ON and output is
resumed.
and activate the RESET OC print out
as speci-
pushbutton on the RESYNC fied in appendix
B,
module. Let the testse- sec. 7.24
quence finish normally
Enter from the OC:
DO CLOSE2B (CR)
(Appendix A, sec.4.25b)
̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲
̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲
Comments:
̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲
̲ ̲
T̲E̲S̲T̲ ̲W̲I̲T̲N̲E̲S̲S̲E̲S̲
TEST QA QAR
T̲E̲S̲T̲ ̲S̲T̲E̲P̲S̲ T̲E̲S̲T̲
̲N̲O̲.̲:̲
̲2̲/̲1̲
F̲U̲N̲C̲T̲I̲O̲N̲:̲ ̲ ̲P̲U̲#̲1̲/̲C̲U̲/̲T̲D̲X̲#̲1̲ ̲F̲u̲n̲c̲t̲i̲o̲n̲a̲l̲ ̲T̲e̲s̲t̲
S̲R̲S̲ ̲R̲E̲F̲E̲R̲E̲N̲C̲E̲:̲ ̲ ̲S̲e̲c̲s̲.̲ ̲3̲.̲4̲.̲5̲.̲1̲.̲o̲,̲ ̲3̲.̲4̲.̲5̲.̲7̲.̲a̲.̲4̲,̲ ̲3̲.̲4̲.̲5̲.̲7̲.̲a̲.̲7̲ ̲ ̲
̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲
Case Test
Step No. Station Action Expected Results
̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲
̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲
7.12.27 N/A Power down the CRYPTOs, N/A
the MODEMs and the main
site stat. mux #1
and Remote site A stat.
mux. Remove the CRYPTO/
MODEM link. Connect the
testcable between J33 in
the main site filterbox
and J40 in the Remote site A
filterbox.
On the main site stat.mux #1
and the Remote site A stat. mux.
set S1 on the ba-
se board switch group 2
to the OPEN position
(intern clock). Power up
the main site stat.mux #1
and Remote site A stat. mux.
̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲
̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲
Comments:
̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲
̲ ̲
T̲E̲S̲T̲ ̲W̲I̲T̲N̲E̲S̲S̲E̲S̲
TEST QA QAR
3.2.3.1.4 T̲e̲s̲t̲ ̲T̲e̲r̲m̲i̲n̲a̲t̲i̲o̲n̲
Power Down the system as Follows:
a) Depress "START" push button on Disk Drive # 2 and
wait until the "START" and "READY" indicators are
"OFF".
b) Remove the Disk Pack from Disk Drive # 2, close
the lid and push the drive back in rack B
c) The two scratch Floppy Disks are removed from the
Floppy Disk drive in rack C. Close the lids.
d) The Power Switch (2) on each Mains Switch is set
to "OFF".
e) The input power switch on each Frequency Stabilizer
is set to "OFF"
f) Power Down all connected Terminals i.e. VDUs, MSPs,
OC, PTP/PTR, as applicable.
g) Disconnect the OC from the leftmost V24/V28(L/L)
adaptor in the Adaptor crate of rack C, and replace
this adaptor with the originally mounted OPTO transceiver.
h) Disconnect the two V24 cables (at the WDP rear
crate), remove the short extension cable and reconnect
the two cables to J1 and J3 respectively.
