OctetView
0x00000…00100 (0, 0, 0) Sector 02484130323438 ┆ HA0248A ┆
0x00100…00200 (0, 0, 1) Sector 00000000000000 ┆ ┆
0x00200…00300 (0, 0, 2) Sector ff00f8f8ffffff ┆ xx ┆
0x00300…00306 (0, 0, 3) WangDocument {d00=0x29, d01=0x38, d02=0x41, ptr=(26,0, 0), d05=0x00}
0x00306…0030c WangDocument {d00=0x29, d01=0x39, d02=0x41, ptr=(46,0, 8), d05=0x00}
0x0030c…00320 29 39 41 2e 08 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ┆)9A. ┆
0x00320…00340 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ┆ ┆
[…0x5…]
0x003e0…00400 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 0c ┆ ┆
0x00400…00500 (0, 0, 4) Sector 00000000000000 ┆ ┆
0x00500…00600 (0, 0, 5) Sector 02484130323438 ┆ HA0248A ┆
0x00600…00700 (0, 0, 6) Sector 421c402600415b ┆B @& A[' = X% % PO P ; ' A C g x g V W O : 2793A g < {C < { ; 3 ;g ┆
0x00700…00800 (0, 0, 7) Sector 00000000000000 ┆ ┆
[…0x8…]
0x01000…01100 (1, 0, 0) WangDocumentBody
[…0x4…]
0x01500…01600 (1, 0, 5) Sector 00000000000000 ┆ ┆
[…0x2…]
0x01800…01900 (1, 0, 8) WangDocumentBody
[…0x4…]
0x01d00…01e00 (1, 0, 13) Sector 010eff00293941 ┆ )9Ane Tagblock 2 = Neutral Tagblock 3 = Ground 8.9 INSTALLATION OF SIGNAL CABLES a) The H/N delivered V24 digital cables and the VF analog line cables coming from the main distributuion frame are inserted through the metallic conduit into th┆
0x01e00…01f00 (1, 0, 14) Sector 010fff00293941 ┆ )9Ae Tare rack. b) The V24 digital cables coming from the Crypto equipment are terminated and connected to the V24 BPJF J2 (See ATBB drawing 146). For pin assignment, see ATBB doc. page 5.4. c) The VF analog line cables coming from the main distr┆
0x01f00…02000 (1, 0, 15) Sector 01005c00293941 ┆ \ )9Aibution frame are terminated and connected to the VF BPJF J2 (See ATBB drawing 146). gements will be discussed and finalized during the site verification meetings. 0 AUXILLIARIES 1 54x32x61 1 10 0.09 2 10┆
0x02000…02100 (2, 0, 0) WangDocumentBody
[…0x17f…]
0x1a000…1a100 (26, 0, 0) WangDocumentHead {hdr=WangSectHead {next=(26,0, 1), len=0xff, h3=41293841}, f00=»2938A «, f01=»CPS/AUX/033 (ff - 5.8) «, f02=»ktd «, f03=»HAU «, f04=»INSTALL.PROC. Site 6 «, f05=18-10-82 14:00, f06=» 3 «, f07=»23 «, f08=» 9509 «, f09=28-12-82 14:30, f10=» «, f11=»03 «, f12=» 60 «, f13=16-12-82 13:50, f14=14-09-83 15:42, f15=»0248A «, f16=» 80 «, f17=» 8 «, f18=»02 «, f19=» 1164 «, f20=» 17493 «, f21=» «, f22=» 0 «, f99=930003100010052710110490aaca15050000000000000142037501df}
0x1a100…1a200 (26, 0, 1) WangDocumentBody
[…0x146…]
0x2e800…2e900 (46, 0, 8) WangDocumentHead {hdr=WangSectHead {next=(46,0, 9), len=0xff, h3=41293941}, f00=»2939A «, f01=»CPS/AUX/033 (5.9 - op) «, f02=»ktd «, f03=»HAU «, f04=»INSTALL.PROC. Site 6 «, f05=18-10-82 14:01, f06=» 5 «, f07=»11 «, f08=» 13709 «, f09=17-12-82 09:49, f10=» «, f11=»01 «, f12=» 22 «, f13=17-12-82 09:41, f14=14-09-83 15:43, f15=»0248A «, f16=» 73 «, f17=» 8 «, f18=»11 «, f19=» 1128 «, f20=» 19035 «, f21=» «, f22=» 0 «, f99=131020000110052710110490aaca15050000000000000142036501df}
0x2e900…2ea00 (46, 0, 9) WangDocumentBody
[…0x6…]
0x2f000…2f100 (47, 0, 0) Sector 2f01ff00279341 ┆/ ' A 1 1 2793A/rt 4:5:4-6 NEN/840620 2 STUDENT LABORATORY GUIDE CAMPS 1 ┆
0x2f100…2f200 (47, 0, 1) Sector 2f02ff00279341 ┆/ ' A CRATE CABLING OBJECTIVES: ENABLE the STUDENT to identify all cables and cable connections in the TDX SYSTEM. REFERENCES: CAMPS HARDWARE ASSEMBLY BREAKDOWN/HARDWARE TREE (CPS/SDS/017). OH 4 & 5 of th┆
0x2f200…2f300 (47, 0, 2) Sector 2f03ff00279341 ┆/ ' Ae LESSON 4:4:2. EXERCISE GUIDE: Switch OFF the MAINS POWER to the TDX CRATES. Check all TDX CABLE CONNECTIONS according to this LAB.GUIDE, page 3-7. Check the INTERNAL CABLE CONNECTIONS according the OH4 & 5 of the LESSON 4:4:2. INSERT/CO┆
0x2f300…2f400 (47, 0, 3) Sector 00005e00279341 ┆ ^ ' ANNECT the MODULES/CABLES if any are REMOVED/DISCONNECTED. Switch ON the MAINS POWER. HE VDU: SECTION 4.7.2.2, POINT g.4 ERROR CODES SLM: AND MESSAGES: SECTION 4.7.2.2, POINTS g.8 and g.9 E [ or 1. 6.2 Perform the BOOT COMMANDS ac┆
0x2f400…2f500 (47, 0, 4) Sector 2f05ff00293941 ┆/ )9A circuit exists between the safety group (cabinets) and the lines of circuit no. 1 through 9 and 1a through 3a. b) Remount the lids of the power line filters by the 30 screws. c) Start the powering up in the below sequence, starting at the CAMPS┆
0x2f500…2f600 (47, 0, 5) Sector 2f06d900293941 ┆/ Y )9A power distribution board (PDB): 5.9.2 CAMPS PDB TURN ON: Main circuit breaker TURN ON: Miniature circuit breakers CHECKOUT: No fuses in the CAMPS PDB blown due to short circuit in the installation. $<6 !&<6 Mc&! "(=6 E '<M% ! "2<┆
0x2f600…2f700 (47, 0, 6) Sector 2f07ff00293941 ┆/ )9A 1 5.9.3 Frequency Stabilizers and Disk Drives To examine that the 3 disk drives are supplied from 3 separate phases via the frequency stabilizers proceed in the below sequence: a)┆
0x2f700…2f800 (47, 0, 7) Sector 2e08ff00293941 ┆. )9A Frequency Stabilizer #1/Disk #1 (MMD) RACK A 1) TURN ON: Input power switch on front of the stabilizer (A1A3)(see CAMPS H/W Breakdown page 214). Set the rotary switch on the by-pass panel to position "frequency stabilizer". 2) CHECK: ┆
0x2f800…2f900 (47, 0, 8) Sector 2f09ff00279341 ┆/ ' A 1 1 2793A/rt 4:4:4-6 NEN/840620 2 STUDENT LABORATORY GUIDE CAMPS 1 ┆
0x2f900…2fa00 (47, 0, 9) Sector 2f0aff00279341 ┆/ ' A TDX LOOP TEST OBJECTIVES: ENABLE the STUDENT to - STATE the TDX DEVICES, ADAPTORS, and PERIPHERALS, which are ACCESSED by the TEST - DESCRIBE the FUNCTION of the TEST - BOOT UP the TEST PROGRAM┆
0x2fa00…2fb00 (47, 0, 10) Sector 2f0bff00279341 ┆/ ' A - FULLFIL an ERROR FREE TEST - STATE the RESPONSE appearing on the VDU - STATE the ERROR CODES and MESSAGES REFERENCE : CAMPS SITE LEVEL MAINTENANCE MANUAL, CPS/TCM/005 EXERCISE SLM: GUIDE: SECTION 4.7.2.1.8, STEP 19-22 ┆
0x2fb00…2fc00 (47, 0, 11) Sector 2f0cdd00279341 ┆/ ] ' ANOTE! LOOP "NO." is the respective LINE PORT ID. (See 4:1:1:OH5-7) RESPONSE ON SLM: THE VDU: SECTION 4.7.2.2, POINT g.6 ERROR CODES SLM: AND MESSAGES: SECTION 4.7.2.2, POINTS g.8 and g.9 ┆
0x2fc00…2fd00 (47, 0, 12) Sector 2f0dff00279341 ┆/ ' A 1 1 2793A/rt 4:5:4-6 NEN/840620 1 STUDENT LABORATORY GUIDE CAMPS 1 ┆
0x2fd00…2fe00 (47, 0, 13) Sector 2f0eff00279341 ┆/ ' A TDX VDU I/O TEST OBJECTIVES: ENABLE the STUDENT to - STATE the TDX DEVICES which are ACCESSED by the TEST - DESCRIBE the FUNCTION of the TEST - BOOT UP the TEST PROGRAM - FULLFIL an ERROR FR┆
0x2fe00…2ff00 (47, 0, 14) Sector 2f0fff00279341 ┆/ ' AEE TEST - STATE the RESPONSE appearing on the VDU - STATE the ERROR CODES and MESSAGES REFERENCE : CAMPS SITE LEVEL MAINTENANCE MANUAL, CPS/TCM/005 EXERCISE SLM: GUIDE: SECTION 4.7.2.1.8, STEP 23-26 NOTE! IO "NO." is the res┆
0x2ff00…30000 (47, 0, 15) Sector 2f00c200279341 ┆/ B ' Apective LINE PORT ID. (See 4:1:1:OH5-7) RESPONSE ON SLM: THE VDU: SECTION 4.7.2.2, POINT g.7 ERROR CODES SLM: AND MESSAGES: SECTION 4.7.2.2, POINTS g.8 and g.9 he CU. COMMAND: ENTO ^ENTER^ 5. ENABLE the resp┆
0x30000…30100 (48, 0, 0) Sector 3001ff00279341 ┆0 ' A 1 1 2793A/rt 4:3:4-6 NEN/840229 2 STUDENT LABORATORY GUIDE CAMPS 1 ┆
0x30100…30200 (48, 0, 1) Sector 3002ff00279341 ┆0 ' A LTUX STATUS TEST OBJECTIVES: ENABLE the STUDENT to - STATE the TDX DEVICES which are ACCESSED by the TEST - DESCRIBE the FUNCTION of the TEST - BOOT UP the TEST PROGRAM - FULLFIL an ERROR FR┆
0x30200…30300 (48, 0, 2) Sector 3003ff00279341 ┆0 ' AEE TEST - STATE the RESPONSE appearing on the VDU - STATE the ERROR CODES and MESSAGES REFERENCE : CAMPS SITE LEVEL MAINTENANCE MANUAL, CPS/TCM/005 EXERCISE SLM: GUIDE: SECTION 4.7.2.1.8, STEP 11-14 NOTE! The LTUX STATUS "┆
0x30300…30400 (48, 0, 3) Sector 3004d100279341 ┆0 Q ' ANO." is the respective LTUX-S PORT ID. (See 4:1:1:OH5-7) RESPONSE ON SLM: THE VDU: SECTION 4.7.2.2, POINT g.4 ERROR CODES SLM: AND MESSAGES: SECTION 4.7.2.2, POINTS g.8 and g.9 E [ or 1. 6.2 Perform the BOOT COMMANDS ac┆
0x30400…30500 (48, 0, 4) Sector 3005ff00279341 ┆0 ' A 1 1 2793A/rt 4:4:4-6 NEN/840620 1 STUDENT LABORATORY GUIDE CAMPS 1 ┆
0x30500…30600 (48, 0, 5) Sector 3006ff00279341 ┆0 ' A TDX LTUX TEST OBJECTIVES: ENABLE the STUDENT to - STATE the TDX DEVICES which are ACCESSED by the TEST - DESCRIBE the FUNCTION of the TEST - BOOT UP the TEST PROGRAM - FULLFIL an ERROR FREE ┆
0x30600…30700 (48, 0, 6) Sector 3007ff00279341 ┆0 ' ATEST - STATE the RESPONSE appearing on the VDU - STATE the ERROR CODES and MESSAGES REFERENCE : CAMPS SITE LEVEL MAINTENANCE MANUAL, CPS/TCM/005 EXERCISE SLM: GUIDE: SECTION 4.7.2.1.8, STEP 15-18 NOTE! OPEN "NO." is the resp┆
0x30700…30800 (48, 0, 7) Sector 2f08c100279341 ┆/ A ' Aective LINE PORT ID. (See 4:1:1:OH5-7) RESPONSE ON SLM: THE VDU: SECTION 4.7.2.2, POINT g.5 ERROR CODES SLM: AND MESSAGES: SECTION 4.7.2.2, POINTS g.8 and g.9 ABORATORY GUIDE CAMPS 1 ┆
0x30800…30900 (48, 0, 8) Sector 3009ff00279341 ┆0 ' A 1 1 2793A/rt 4:2:4-6 NEN/840620 4 STUDENT LABORATORY GUIDE CAMPS 1 ┆
0x30900…30a00 (48, 0, 9) Sector 300aff00279341 ┆0 ' A STI TEST OBJECTIVES: ENABLE the STUDENT to - STATE the TDX DEVICES which are ACCESSED by the TEST - DESCRIBE the FUNCTION of the TEST - BOOT UP the TEST PROGRAM - FULLFIL an ERROR FREE TEST ┆
0x30a00…30b00 (48, 0, 10) Sector 300bff00279341 ┆0 ' A - STATE the RESPONSE appearing on the VDU - STATE the ERROR CODES and MESSAGES REFERENCE: CAMPS SITE LEVEL MAINTENANCE MANUAL, CPS/TCM/005 EXERCISE SLM: GUIDE: SECTION 4.7.2.1.8, STEP 2-5 RESPONSE ON SLM: THE VDU: ┆
0x30b00…30c00 (48, 0, 11) Sector 300c7000279341 ┆0 p ' A SECTION 4.7.2.2, POINT g.2 ERROR CODES SLM: AND MESSAGES: SECTION 4.7.2.2, POINTS g.8 and g.9 ee 4:1:1:OH5-7)4:5:1-3 840209 2 of 2 ┆
0x30c00…30d00 (48, 0, 12) Sector 300dff00279341 ┆0 ' A 1 1 2793A/rt 4:3:4-6 NEN/840620 1 STUDENT LABORATORY GUIDE CAMPS 1 ┆
0x30d00…30e00 (48, 0, 13) Sector 300eff00279341 ┆0 ' A TDX BUS TEST OBJECTIVES: ENABLE the STUDENT to - STATE the TDX DEVICES which are ACCESSED by the TEST - DESCRIBE the FUNCTION of the TEST - BOOT UP the TEST PROGRAM - FULLFIL an ERROR FREE T┆
0x30e00…30f00 (48, 0, 14) Sector 300fff00279341 ┆0 ' AEST - STATE the RESPONSE appearing on the VDU - STATE the ERROR CODES and MESSAGES REFERENCE: CAMPS SITE LEVEL MAINTENANCE MANUAL, CPS/TCM/005 EXERCISE SLM: GUIDE: SECTION 4.7.2.1.8, STEP 6-10 RESPONSE ON SLM: TH┆
0x30f00…31000 (48, 0, 15) Sector 30007800279341 ┆0 x ' AE VDU: SECTION 4.7.2.2, POINT g.3 ERROR CODES SLM: AND MESSAGES: SECTION 4.7.2.2, POINTS g.8 and g.9 4. ENABLE the "TAKE OWNERSHIP" possibility of the respective I/O Bus in the CU. COMMAND: ENTO ^ENTER^ 5. ENABLE the resp┆
0x31000…31100 (49, 0, 0) Sector 31016200279341 ┆1 b ' Aective DISK CONTROLLER. COMMAND: IR 1A .. ^CR^ MODULE ADDRESS (MA) 840620 GENERAL ABBREVIATIONS CAMPS 1 ┆
0x31100…31200 (49, 0, 1) Sector 3102ff00279341 ┆1 ' A 1 1 2793A/rt 4:2:4-6 NEN/840620 3 STUDENT LABORATORY GUIDE CAMPS 1 ┆
0x31200…31300 (49, 0, 2) Sector 3103ff00279341 ┆1 ' A 6. BOOT UP from FLOPPY DRIVE (FD) 1 NOTE! The TEST PROGRAMS concerning the LTUX-S MODULES associated one TDX UNIT are stored in the resp┆
0x31300…31400 (49, 0, 3) Sector 3104ff00279341 ┆1 ' Aective DISKETTE labeled with the TDX UNIT NO. Each of these DISKETTES are also containing the STI TEST PROGRAM and the TDX BUS TEST PROGRAM. 6.1 INSERT the selected DISKETTE in FLOPPY DISK DRIVE [ or 1. 6.2 Perform the BOOT COMMANDS ac┆
0x31400…31500 (49, 0, 4) Sector 3105ff00279341 ┆1 ' Acording to SLM, SECTION 4.7.2.1.8, STEP [. 7. BOOT UP from STORAGE MODULE DRIVE (SMD). NOTE! The TEST PROGRAMS concerning the LTUX-S MODULES associated one TDX UNIT are stored in the FILE numbered with the BFD NO. according to the table b┆
0x31500…31600 (49, 0, 5) Sector 3106ff00279341 ┆1 ' Aelow. Each of these FILES are also containing the STI TEST PROGRAM and the TDX BUS TEST PROGRAM. TDX SYSTEM TEST PROGRAMS STORED ON THE DISK PACK: ^ TDX UNIT NO. ^ BFD NO. ^ ┆
0x31600…31700 (49, 0, 6) Sector 3107ff00279341 ┆1 ' A ^ ^ ^ ^ 1-5 ^ 2E6 ^ ^ 6-A ^ 2E7 ^ ^ B-F ^ 2E8 ^ ^ ^ ^ 7.1 INSTALL the DISK PACK in the SMD, 7.2 Perform t┆
0x31700…31800 (49, 0, 7) Sector 30084900279341 ┆0 I ' Ahe BOOT COMMANDS according to SLM, SECTION 4.7.2.1.8, STEP [. 1 2793A/rt 4:2:4-6 NEN/840620 1 STUDENT LABORATORY GUIDE CAMPS 1 ┆
0x31800…31900 (49, 0, 8) Sector 3109ff00279341 ┆1 ' A TDX SYSTEM STATUS TEST OBJECTIVES: ENABLE the STUDENT to - CONFIGURATE a VDU for TDX-CONTROLLER CONNECTION - STATE the RELATIONSHIP of DEVICE ADDRESS and LOCATION in the TDX UNITS - STA┆
0x31900…31a00 (49, 0, 9) Sector 310aff00279341 ┆1 ' ATE the DIFFERENCE between M&D TDX SYSTEM TESTS and TDX SYSTEM STATUS TEST - DESCRIBE the BSM-X BUS SWITCHING - DESCRIBE the RELATIONSHIP OF BSM-X, TDX-BUS, and TDX CONTROLLER REFERENCE: CAMPS SITE LEVEL MAINTENANCE MANUAL, CPS/TCM/005 ┆
0x31a00…31b00 (49, 0, 10) Sector 310bff00279341 ┆1 ' A EXERCISE SLM: GUIDE: SECTION 4.3.3.4, FIGURE 4.3.3.4-2 1 NOTE! This TEST PROGRAM is part of the APPLICATION SOFTWARE stored in the TDX CONTROLLER MEMORY. RESPO┆
0x31b00…31c00 (49, 0, 11) Sector 310c7f00279341 ┆1 ' ANSE ON SLM: THE VDU: SECTION 4.3.3.4, FIGURE 4.3.3.4-2 NOTE! "DEVICE NO." is DECIMAL NO. (See 4:1:1:OH5-7)4:5:1-3 840209 2 of 2 ┆
0x31c00…31d00 (49, 0, 12) Sector 310dff00279341 ┆1 ' A 1 1 2793A/rt 4:2:4-6 NEN/840620 2 STUDENT LABORATORY GUIDE CAMPS 1 ┆
0x31d00…31e00 (49, 0, 13) Sector 310eff00279341 ┆1 ' A BOOT UP PROCEDURES for the M&D TDX SYSTEM TEST PROGRAMS OBJECTIVES: Enable the STUDENTS to BOOT UP the M&D TDX SYSTEM TEST PROGRAMS from - FLOPPY DRIVE (FD) - STORAGE MODULE DRIVE (SMD) REFER┆
0x31e00…31f00 (49, 0, 14) Sector 310fff00279341 ┆1 ' AENCE: CAMPS SITE LEVEL MAINTENANCE MANUAL, CPS/TCM/005 EXERCISE GUIDE: The following COMMANDS will be entered from the MAINTENANCE POSITION l. SELECT an OFF-LINE PU COMMAND: PU#1 ^ENTER^ or PU#2 ^ENTER^ 2. RE┆
0x31f00…32000 (49, 0, 15) Sector 3100ff00279341 ┆1 ' ASET the selected PU COMMAND: RSET ^ENTER^ 3. ENABLE the selected PU COMMAND: ENPU ^ENTER^ 4. ENABLE the "TAKE OWNERSHIP" possibility of the respective I/O Bus in the CU. COMMAND: ENTO ^ENTER^ 5. ENABLE the resp┆
0x32000…32100 (50, 0, 0) Sector 00005e00279341 ┆ ^ ' ANNECT the MODULES/CABLES if any are REMOVED/DISCONNECTED. Switch ON the MAINS POWER. HE VDU: SECTION 4.7.2.2, POINT g.4 ERROR CODES SLM: AND MESSAGES: SECTION 4.7.2.2, POINTS g.8 and g.9 E [ or 1. 6.2 Perform the BOOT COMMANDS ac┆
0x32100…32200 (50, 0, 1) Sector 3202d200279341 ┆2 R ' A DI Discussion DE Demonstration L Lecture GW Group Work T Test I Informal Talk S Self Study EX Exercise LG Laboratory Guide OH Overhead/Handout for signal adaption to/from the CTRL/DEVICES ┆
0x32200…32300 (50, 0, 2) Sector 3203ff00279341 ┆2 ' A 1 2793A 840620 WEEK SPECIFIC ABBREVIATIONS ┆
0x32300…32400 (50, 0, 3) Sector 3204ff00279341 ┆2 ' A WEEK NO 4 CAMPS 1 HBK CR80 MINICOMPUTER HANDBOOK 82/83 SLM CPS/TCM/005 (SITE LEVEL MAINTENANCE MANUAL) HWB CP┆
0x32400…32500 (50, 0, 4) Sector 32052a00279341 ┆2 * ' AS/SDS/017 (HARDW. ASSY BREAKDOWN) pacitors) to a high impedance input differential receiver. Supply Voltage: Two +5V lines which are fused on the TDX device module supply the outlet box circutry with power. gem hertiland back panel type 8 (B┆
0x32500…32600 (50, 0, 5) Sector 3206ff00279341 ┆2 ' A 1 1 2793A/rt 4:1:4-6 NEN/840620 1 STUDENT LABORATORY GUIDE CAMPS 1 ┆
0x32600…32700 (50, 0, 6) Sector 3207f800279341 ┆2 x ' A No exercise in Lesson 4:1:4-6 but Instructor Guided practice subjects as follows: - TDX SYSTEM INTRODUCTION & DEMONSTRATION - INTRODUCTION OF THE TDX RELATED SECTIONS OF THE SLM & HWB. ber opt┆
0x32700…32800 (50, 0, 7) Sector 3108ff00279341 ┆1 ' A 1 1 2793A/rt 4:2:4-6 NEN/840620 1 STUDENT LABORATORY GUIDE CAMPS 1 ┆
0x32800…32900 (50, 0, 8) Sector 3209dd00279341 ┆2 ] ' ANOTE! LOOP "NO." is the respective LINE PORT ID. (See 4:1:1:OH5-7) RESPONSE ON SLM: THE VDU: SECTION 4.7.2.2, POINT g.6 ERROR CODES SLM: AND MESSAGES: SECTION 4.7.2.2, POINTS g.8 and g.9 ┆
0x32900…32a00 (50, 0, 9) Sector 320aff00279341 ┆2 ' A 1 1 2793A/rt 4:5:4-6 NEN/840620 1 STUDENT LABORATORY GUIDE CAMPS 1 ┆
0x32a00…32b00 (50, 0, 10) Sector 320bff00279341 ┆2 ' A TDX VDU I/O TEST OBJECTIVES: ENABLE the STUDENT to - STATE the TDX DEVICES which are ACCESSED by the TEST - DESCRIBE the FUNCTION of the TEST - BOOT UP the TEST PROGRAM - FULLFIL an ERROR FR┆
0x32b00…32c00 (50, 0, 11) Sector 320cff00279341 ┆2 ' AEE TEST - STATE the RESPONSE appearing on the VDU - STATE the ERROR CODES and MESSAGES REFERENCE : CAMPS SITE LEVEL MAINTENANCE MANUAL, CPS/TCM/005 EXERCISE SLM: GUIDE: SECTION 4.7.2.1.8, STEP 23-26 NOTE! IO "NO." is the res┆
0x32c00…32d00 (50, 0, 12) Sector 320dc200279341 ┆2 B ' Apective LINE PORT ID. (See 4:1:1:OH5-7) RESPONSE ON SLM: THE VDU: SECTION 4.7.2.2, POINT g.7 ERROR CODES SLM: AND MESSAGES: SECTION 4.7.2.2, POINTS g.8 and g.9 he CU. COMMAND: ENTO ^ENTER^ 5. ENABLE the resp┆
0x32d00…32e00 (50, 0, 13) Sector 320eff00279341 ┆2 ' A 1 1 2793A/rt 4:5:4-6 NEN/840620 2 STUDENT LABORATORY GUIDE CAMPS 1 ┆
0x32e00…32f00 (50, 0, 14) Sector 320fff00279341 ┆2 ' A CRATE CABLING OBJECTIVES: ENABLE the STUDENT to identify all cables and cable connections in the TDX SYSTEM. REFERENCES: CAMPS HARDWARE ASSEMBLY BREAKDOWN/HARDWARE TREE (CPS/SDS/017). OH 4 & 5 of th┆
0x32f00…33000 (50, 0, 15) Sector 3200ff00279341 ┆2 ' Ae LESSON 4:4:2. EXERCISE GUIDE: Switch OFF the MAINS POWER to the TDX CRATES. Check all TDX CABLE CONNECTIONS according to this LAB.GUIDE, page 3-7. Check the INTERNAL CABLE CONNECTIONS according the OH4 & 5 of the LESSON 4:4:2. INSERT/CO┆
0x33000…33100 (51, 0, 0) Sector 3301d100279341 ┆3 Q ' ANO." is the respective LTUX-S PORT ID. (See 4:1:1:OH5-7) RESPONSE ON SLM: THE VDU: SECTION 4.7.2.2, POINT g.4 ERROR CODES SLM: AND MESSAGES: SECTION 4.7.2.2, POINTS g.8 and g.9 E [ or 1. 6.2 Perform the BOOT COMMANDS ac┆
0x33100…33200 (51, 0, 1) Sector 3302ff00279341 ┆3 ' A 1 1 2793A/rt 4:4:4-6 NEN/840620 1 STUDENT LABORATORY GUIDE CAMPS 1 ┆
0x33200…33300 (51, 0, 2) Sector 3303ff00279341 ┆3 ' A TDX LTUX TEST OBJECTIVES: ENABLE the STUDENT to - STATE the TDX DEVICES which are ACCESSED by the TEST - DESCRIBE the FUNCTION of the TEST - BOOT UP the TEST PROGRAM - FULLFIL an ERROR FREE ┆
0x33300…33400 (51, 0, 3) Sector 3304ff00279341 ┆3 ' ATEST - STATE the RESPONSE appearing on the VDU - STATE the ERROR CODES and MESSAGES REFERENCE : CAMPS SITE LEVEL MAINTENANCE MANUAL, CPS/TCM/005 EXERCISE SLM: GUIDE: SECTION 4.7.2.1.8, STEP 15-18 NOTE! OPEN "NO." is the resp┆
0x33400…33500 (51, 0, 4) Sector 3305c100279341 ┆3 A ' Aective LINE PORT ID. (See 4:1:1:OH5-7) RESPONSE ON SLM: THE VDU: SECTION 4.7.2.2, POINT g.5 ERROR CODES SLM: AND MESSAGES: SECTION 4.7.2.2, POINTS g.8 and g.9 ABORATORY GUIDE CAMPS 1 ┆
0x33500…33600 (51, 0, 5) Sector 3306ff00279341 ┆3 ' A 1 1 2793A/rt 4:4:4-6 NEN/840620 2 STUDENT LABORATORY GUIDE CAMPS 1 ┆
0x33600…33700 (51, 0, 6) Sector 3307ff00279341 ┆3 ' A TDX LOOP TEST OBJECTIVES: ENABLE the STUDENT to - STATE the TDX DEVICES, ADAPTORS, and PERIPHERALS, which are ACCESSED by the TEST - DESCRIBE the FUNCTION of the TEST - BOOT UP the TEST PROGRAM┆
0x33700…33800 (51, 0, 7) Sector 3208ff00279341 ┆2 ' A - FULLFIL an ERROR FREE TEST - STATE the RESPONSE appearing on the VDU - STATE the ERROR CODES and MESSAGES REFERENCE : CAMPS SITE LEVEL MAINTENANCE MANUAL, CPS/TCM/005 EXERCISE SLM: GUIDE: SECTION 4.7.2.1.8, STEP 19-22 ┆
0x33800…33900 (51, 0, 8) Sector 33097000279341 ┆3 p ' A SECTION 4.7.2.2, POINT g.2 ERROR CODES SLM: AND MESSAGES: SECTION 4.7.2.2, POINTS g.8 and g.9 ee 4:1:1:OH5-7)4:5:1-3 840209 2 of 2 ┆
0x33900…33a00 (51, 0, 9) Sector 330aff00279341 ┆3 ' A 1 1 2793A/rt 4:3:4-6 NEN/840620 1 STUDENT LABORATORY GUIDE CAMPS 1 ┆
0x33a00…33b00 (51, 0, 10) Sector 330bff00279341 ┆3 ' A TDX BUS TEST OBJECTIVES: ENABLE the STUDENT to - STATE the TDX DEVICES which are ACCESSED by the TEST - DESCRIBE the FUNCTION of the TEST - BOOT UP the TEST PROGRAM - FULLFIL an ERROR FREE T┆
0x33b00…33c00 (51, 0, 11) Sector 330cff00279341 ┆3 ' AEST - STATE the RESPONSE appearing on the VDU - STATE the ERROR CODES and MESSAGES REFERENCE: CAMPS SITE LEVEL MAINTENANCE MANUAL, CPS/TCM/005 EXERCISE SLM: GUIDE: SECTION 4.7.2.1.8, STEP 6-10 RESPONSE ON SLM: TH┆
0x33c00…33d00 (51, 0, 12) Sector 330d7800279341 ┆3 x ' AE VDU: SECTION 4.7.2.2, POINT g.3 ERROR CODES SLM: AND MESSAGES: SECTION 4.7.2.2, POINTS g.8 and g.9 4. ENABLE the "TAKE OWNERSHIP" possibility of the respective I/O Bus in the CU. COMMAND: ENTO ^ENTER^ 5. ENABLE the resp┆
0x33d00…33e00 (51, 0, 13) Sector 330eff00279341 ┆3 ' A 1 1 2793A/rt 4:3:4-6 NEN/840229 2 STUDENT LABORATORY GUIDE CAMPS 1 ┆
0x33e00…33f00 (51, 0, 14) Sector 330fff00279341 ┆3 ' A LTUX STATUS TEST OBJECTIVES: ENABLE the STUDENT to - STATE the TDX DEVICES which are ACCESSED by the TEST - DESCRIBE the FUNCTION of the TEST - BOOT UP the TEST PROGRAM - FULLFIL an ERROR FR┆
0x33f00…34000 (51, 0, 15) Sector 3300ff00279341 ┆3 ' AEE TEST - STATE the RESPONSE appearing on the VDU - STATE the ERROR CODES and MESSAGES REFERENCE : CAMPS SITE LEVEL MAINTENANCE MANUAL, CPS/TCM/005 EXERCISE SLM: GUIDE: SECTION 4.7.2.1.8, STEP 11-14 NOTE! The LTUX STATUS "┆
0x34000…34100 (52, 0, 0) Sector 3401ff00279341 ┆4 ' Aective DISKETTE labeled with the TDX UNIT NO. Each of these DISKETTES are also containing the STI TEST PROGRAM and the TDX BUS TEST PROGRAM. 6.1 INSERT the selected DISKETTE in FLOPPY DISK DRIVE [ or 1. 6.2 Perform the BOOT COMMANDS ac┆
0x34100…34200 (52, 0, 1) Sector 3402ff00279341 ┆4 ' Acording to SLM, SECTION 4.7.2.1.8, STEP [. 7. BOOT UP from STORAGE MODULE DRIVE (SMD). NOTE! The TEST PROGRAMS concerning the LTUX-S MODULES associated one TDX UNIT are stored in the FILE numbered with the BFD NO. according to the table b┆
0x34200…34300 (52, 0, 2) Sector 3403ff00279341 ┆4 ' Aelow. Each of these FILES are also containing the STI TEST PROGRAM and the TDX BUS TEST PROGRAM. TDX SYSTEM TEST PROGRAMS STORED ON THE DISK PACK: ^ TDX UNIT NO. ^ BFD NO. ^ ┆
0x34300…34400 (52, 0, 3) Sector 3404ff00279341 ┆4 ' A ^ ^ ^ ^ 1-5 ^ 2E6 ^ ^ 6-A ^ 2E7 ^ ^ B-F ^ 2E8 ^ ^ ^ ^ 7.1 INSTALL the DISK PACK in the SMD, 7.2 Perform t┆
0x34400…34500 (52, 0, 4) Sector 34054900279341 ┆4 I ' Ahe BOOT COMMANDS according to SLM, SECTION 4.7.2.1.8, STEP [. 1 2793A/rt 4:2:4-6 NEN/840620 1 STUDENT LABORATORY GUIDE CAMPS 1 ┆
0x34500…34600 (52, 0, 5) Sector 3406ff00279341 ┆4 ' A 1 1 2793A/rt 4:2:4-6 NEN/840620 4 STUDENT LABORATORY GUIDE CAMPS 1 ┆
0x34600…34700 (52, 0, 6) Sector 3407ff00279341 ┆4 ' A STI TEST OBJECTIVES: ENABLE the STUDENT to - STATE the TDX DEVICES which are ACCESSED by the TEST - DESCRIBE the FUNCTION of the TEST - BOOT UP the TEST PROGRAM - FULLFIL an ERROR FREE TEST ┆
0x34700…34800 (52, 0, 7) Sector 3308ff00279341 ┆3 ' A - STATE the RESPONSE appearing on the VDU - STATE the ERROR CODES and MESSAGES REFERENCE: CAMPS SITE LEVEL MAINTENANCE MANUAL, CPS/TCM/005 EXERCISE SLM: GUIDE: SECTION 4.7.2.1.8, STEP 2-5 RESPONSE ON SLM: THE VDU: ┆
0x34800…34900 (52, 0, 8) Sector 34097f00279341 ┆4 ' ANSE ON SLM: THE VDU: SECTION 4.3.3.4, FIGURE 4.3.3.4-2 NOTE! "DEVICE NO." is DECIMAL NO. (See 4:1:1:OH5-7)4:5:1-3 840209 2 of 2 ┆
0x34900…34a00 (52, 0, 9) Sector 340aff00279341 ┆4 ' A 1 1 2793A/rt 4:2:4-6 NEN/840620 2 STUDENT LABORATORY GUIDE CAMPS 1 ┆
0x34a00…34b00 (52, 0, 10) Sector 340bff00279341 ┆4 ' A BOOT UP PROCEDURES for the M&D TDX SYSTEM TEST PROGRAMS OBJECTIVES: Enable the STUDENTS to BOOT UP the M&D TDX SYSTEM TEST PROGRAMS from - FLOPPY DRIVE (FD) - STORAGE MODULE DRIVE (SMD) REFER┆
0x34b00…34c00 (52, 0, 11) Sector 340cff00279341 ┆4 ' AENCE: CAMPS SITE LEVEL MAINTENANCE MANUAL, CPS/TCM/005 EXERCISE GUIDE: The following COMMANDS will be entered from the MAINTENANCE POSITION l. SELECT an OFF-LINE PU COMMAND: PU#1 ^ENTER^ or PU#2 ^ENTER^ 2. RE┆
0x34c00…34d00 (52, 0, 12) Sector 340dff00279341 ┆4 ' ASET the selected PU COMMAND: RSET ^ENTER^ 3. ENABLE the selected PU COMMAND: ENPU ^ENTER^ 4. ENABLE the "TAKE OWNERSHIP" possibility of the respective I/O Bus in the CU. COMMAND: ENTO ^ENTER^ 5. ENABLE the resp┆
0x34d00…34e00 (52, 0, 13) Sector 340e6200279341 ┆4 b ' Aective DISK CONTROLLER. COMMAND: IR 1A .. ^CR^ MODULE ADDRESS (MA) 840620 GENERAL ABBREVIATIONS CAMPS 1 ┆
0x34e00…34f00 (52, 0, 14) Sector 340fff00279341 ┆4 ' A 1 1 2793A/rt 4:2:4-6 NEN/840620 3 STUDENT LABORATORY GUIDE CAMPS 1 ┆
0x34f00…35000 (52, 0, 15) Sector 3400ff00279341 ┆4 ' A 6. BOOT UP from FLOPPY DRIVE (FD) 1 NOTE! The TEST PROGRAMS concerning the LTUX-S MODULES associated one TDX UNIT are stored in the resp┆
0x35000…35100 (53, 0, 0) Sector 3501ff00279341 ┆5 ' A WEEK NO. 4 CAMPS 1 HBK CR80 MINICOMPUTER HANDBOOK 82/83 SLM CPS/TCM/005 (SITE LEVEL MAINTENANCE MANUAL) HWB CP┆
0x35100…35200 (53, 0, 1) Sector 3502ee00279341 ┆5 n ' AS/SDS/017 (HARDWARE ASSY BREAKDOWN) STB I CPS/TMA/005 (STUDENT TEXT BOOK, VOL. I) STB II CPS/TMA/006 (STUDENT TEXT BOOK, VOL.II) STB III CPS/TMA/024 (STUDENT TEXT BOOK, VOL. III) SLG CPS/TMA/025 (STUDENT LABORATORY GUIDE) k panel type 8 (B┆
0x35200…35300 (53, 0, 2) Sector 3503ff00279341 ┆5 ' A 1 1 2793A/rt 4:1:4-6 NEN/840620 1 STUDENT LABORATORY GUIDE CAMPS 1 ┆
0x35300…35400 (53, 0, 3) Sector 3504f800279341 ┆5 x ' A No exercise in Lesson 4:1:4-6 but Instructor Guided practice subjects as follows: - TDX SYSTEM INTRODUCTION & DEMONSTRATION - INTRODUCTION OF THE TDX RELATED SECTIONS OF THE SLM & HWB. ber opt┆
0x35400…35500 (53, 0, 4) Sector 3505ff00279341 ┆5 ' A 1 1 2793A/rt 4:2:4-6 NEN/840620 1 STUDENT LABORATORY GUIDE CAMPS 1 ┆
0x35500…35600 (53, 0, 5) Sector 3506ff00279341 ┆5 ' A TDX SYSTEM STATUS TEST OBJECTIVES: ENABLE the STUDENT to - CONFIGURATE a VDU for TDX-CONTROLLER CONNECTION - STATE the RELATIONSHIP of DEVICE ADDRESS and LOCATION in the TDX UNITS - STA┆
0x35600…35700 (53, 0, 6) Sector 3507ff00279341 ┆5 ' ATE the DIFFERENCE between M&D TDX SYSTEM TESTS and TDX SYSTEM STATUS TEST - DESCRIBE the BSM-X BUS SWITCHING - DESCRIBE the RELATIONSHIP OF BSM-X, TDX-BUS, and TDX CONTROLLER REFERENCE: CAMPS SITE LEVEL MAINTENANCE MANUAL, CPS/TCM/005 ┆
0x35700…35800 (53, 0, 7) Sector 3408ff00279341 ┆4 ' A EXERCISE SLM: GUIDE: SECTION 4.3.3.4, FIGURE 4.3.3.4-2 1 NOTE! This TEST PROGRAM is part of the APPLICATION SOFTWARE stored in the TDX CONTROLLER MEMORY. RESPO┆
0x35800…35900 (53, 0, 8) Sector 3509ff00279341 ┆5 ' A 1 2793A 4:5:1-3 840209 2 of 2 ┆
0x35900…35a00 (53, 0, 9) Sector 350aff00279341 ┆5 ' A PROGRESS TEST WEEK 4 CAMPS 1 7 Describe the main difference between the HDLC FRAME format when TRANSMITTING on the LOWER TDX BUS and the UPP┆
0x35a00…35b00 (53, 0, 10) Sector 350bff00279341 ┆5 ' AER TDX BUS, respectively. 8 How does the WATCH DOG supervise the TDX CONTROLLER? 9 How is the TDX BUS connected to the TDX CONTROLLER? 10 How is the TDX BUS connected to the LTUX-S MODULES? 11 The STI indicates P.ERR! What is wro┆
0x35b00…35c00 (53, 0, 11) Sector 350cff00279341 ┆5 ' Ang? 12 Describe an easy method to check the correct switchsetting (S2) in the STI without removing the module from the crate. 13 Describe the main performances of the LOW LEVEL ADAPTOR modules. 14 Describe the main difference between ┆
0x35c00…35d00 (53, 0, 12) Sector 350d2d00279341 ┆5 - ' ATYP 1 and TYP 2 LOW LEVEL ADAPTOR. 2793A/rt MT/RST 4:4:1-2 840620 CTX-CRATES ┆
0x35d00…35e00 (53, 0, 13) Sector 350eff00279341 ┆5 ' A 1 2793A/rt 840620 GENERAL ABBREVIATIONS CAMPS 1 ┆
0x35e00…35f00 (53, 0, 14) Sector 350fd200279341 ┆5 R ' A DI Discussion DE Demonstration L Lecture GW Group Work T Test I Informal Talk S Self Study EX Exercise LG Laboratory Guide OH Overhead/Handout for signal adaption to/from the CTRL/DEVICES ┆
0x35f00…36000 (53, 0, 15) Sector 3500ff00279341 ┆5 ' A 1 2793A 840620 WEEK SPECIFIC ABBREVIATIONS ┆
0x36000…36100 (54, 0, 0) Sector 3601ff00279341 ┆6 ' Ao the TDX bus via tri-state, balanced (differential) galvanically isolated (trafo) power drivers. The DISAB (tri-state) signal controls the driver to be in the high impedance condition. The RX part: The SPL-D coded receive data is transferred fro┆
0x36100…36200 (54, 0, 1) Sector 3602e700279341 ┆6 g ' Am the bus via galvanic isolators (capacitors) to a high impedance input differential receiver. Supply Voltage: Two +5V lines which are fused on the TDX device module supply the outlet box circutry with power. gem hertiland back panel type 8 (B┆
0x36200…36300 (54, 0, 2) Sector 3603ff00279341 ┆6 ' A 1 2793A/rt MT/RST 4:4:3 840620 POWER SUPPLIES/BP8 ┆
0x36300…36400 (54, 0, 3) Sector 3604ff00279341 ┆6 ' A L 1 1 ADAPTOR PS OH 1 CTX crates which contain adaptor modules (L/L adaptor TYP 1 & 2 and fiber opt┆
0x36400…36500 (54, 0, 4) Sector 3605ff00279341 ┆6 ' Aic modems TYP OM-2) are equipped with a power supply which provides the 18V AC to the modules. The 18V AC is led to the modules via the CTX motherboard. TDX PS The TDX modules in the CTX crate (LTUX, BSM, CTRL) are supplied with DC power (+5V, +/-┆
0x36500…36600 (54, 0, 5) Sector 3606ff00279341 ┆6 ' A12V) from a power supply PS Type CR8022. The DC voltages are distributed to the modules via the CTX motherboard. Characteristics: +5V (max 32 A) Potmeter adj. to 4.5-5.8V +12V (max 2.8 A) -12V (max 1.2 A) not adjustable - All output┆
0x36600…36700 (54, 0, 6) Sector 3607ff00279341 ┆6 ' As are short circuit protected (constant current limiter) - Overvoltage on the output results in immediate shutdown - +5V fused (primary) 3.15 A +/-12V fused (primary) 0.63 A - Presence of outputs is indicated on LEDs on the front panel. ┆
0x36700…36800 (54, 0, 7) Sector 3508cc00279341 ┆5 L ' A PB 8 FUNCTIONS OH 2 The back panel type 8 interconnects any V24/V28 communicating devices. One panel serves 4 channels. By means of ON-board straps, the lines can be interchanged or disconnected. TDX bus is a two core screened RF cable (type T (m┆
0x36800…36900 (54, 0, 8) Sector 3609ff00279341 ┆6 ' A) 3078) with a char. impedance of 100 Ohm. One cable (two cores) is used as lower bus, and one cable is used as upper bus. TERMINATION To prevent reflections on the bus, all cables must be terminated in both ends with a 100 Ohm resistor. SCREE┆
0x36900…36a00 (54, 0, 9) Sector 360aff00279341 ┆6 ' AN To prevent ground loops, the screen must only GROUNDING be connected to ground in one rack; normally the CPU rack. TDX OUTLET OH 7 Connects ONE TDX bus - both upper and lower FUNCTIONS (bus) - to the modules which communicate via the TDX bus. ┆
0x36a00…36b00 (54, 0, 10) Sector 360bff00279341 ┆6 ' AIn the CAMPS system, 2 outlets are connected to each BSM-X module but ONE outlet is connected to each CTRL, and ONE outlet is connected to each HOST I/F (TIA) The termination of the bus cables and the grounding of the screens are made directly on┆
0x36b00…36c00 (54, 0, 11) Sector 360c2e00279341 ┆6 . ' A the terminal block of the outlet box. LSB MSB STRAPS SETTINGS ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ PIN BLOCK NO. ^ 1┆
0x36c00…36d00 (54, 0, 12) Sector 360dff00279341 ┆6 ' A 1 2793A/rt MT/RST 4:4:1-2 840620 CTX-CRATES ┆
0x36d00…36e00 (54, 0, 13) Sector 360eff00279341 ┆6 ' A L 4 1 OUTLET The bus cable connection on the terminal block CONNECTIONS is like: ┆
0x36e00…36f00 (54, 0, 14) Sector 360fff00279341 ┆6 ' A TX 1 & 2 RX 1 & 2 CTRL OUTLET LOWER BUS UPPER BUS OTHER OUTLETS UPPER BUS LOWER BUS (Blackboard) The outlet box contains circuits for signal adaption to/from the CTRL/DEVICES ┆
0x36f00…37000 (54, 0, 15) Sector 3600ff00279341 ┆6 ' Aand provides galvanic isolation between the bus cable and the communicating module, i.e. between the different racks which contain TDX equipment. BLOCK OH 8 The TX part: The SPL-D coded data from the PRINCIPLE transmitting module is transferred t┆
0x37000…37100 (55, 0, 0) Sector 3701ff00279341 ┆7 ' Athe I/O area. - power distributuion from the front side PS to the TDX modules and the adaptor modules (+5V +/-12V) - communication lines between the BSM-X and LTUX-S's - power distribution from the rear side PS to the adaptor modules (9V AC┆
0x37100…37200 (55, 0, 1) Sector 3702ff00279341 ┆7 ' A) BACK POSITIONS In the rear of the CTX crate, the following are to be mounted: OH 3 - Main power panel for mains supply HWB: Fig. (mains filter, fuse) 3.1-3 - Adaptor power supply (2x9V AC) - V24/V28 back panels and back panel type 8 (B┆
0x37200…37300 (55, 0, 2) Sector 37034100279341 ┆7 A ' AP8) - TSA panel (Temp. Sense Adaptor) - BSM-X panel BACK PLANE CONNECTION PIN LAY OUT for the UPPER CONNECTOR: 1 ^ 64 POL. C┆
0x37300…37400 (55, 0, 3) Sector 3704ff00279341 ┆7 ' A 1 2793A/rt MT/RST 4:4:1-2 840620 CTX-CRATES ┆
0x37400…37500 (55, 0, 4) Sector 3705ff00279341 ┆7 ' A L 2 1 INTERNAL OH 4 Internal cable connections HWB: Page 87 ADAPTOR CRATE OH 5 Housing only LOW┆
0x37500…37600 (55, 0, 5) Sector 3706d100279341 ┆7 Q ' A LEVEL Adaptors and back HWB: Fig. panels (BP8) 3.1-13 (sheet 1) Only one power supply unit, the 18V AC adaptor PS in the rear side. OH 6 Internal cable connections HWB: Fig. 3.1-13 (sheet 2) LSB MSB I/O ADDRESS: (See┆
0x37600…37700 (55, 0, 6) Sector 3707ff00279341 ┆7 ' A 1 2793A/rt MT/RST 4:4:1-2 840620 CTX-CRATES ┆
0x37700…37800 (55, 0, 7) Sector 3608ff00279341 ┆6 ' A L 3 1 TDX CABLES OH 7 The cable type used as the TDX bus is a two core screened RF cable (type T (m┆
0x37800…37900 (55, 0, 8) Sector 3709ff00279341 ┆7 ' A8, PU#1 ^ 1 ^ 1 ^ 0 ^ 0 ^ 0 ^ 1 ^ 0 ^ 0 ^ ^ Front Slot 18, PU#2 ^ 1 ^ 1 ^ 0 ^ 0 ^ 0 ^ 1 ^ 0 ^ 0 ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ LSB MSB ^ LSB MSB ^ ┆
0x37900…37a00 (55, 0, 9) Sector 370aff00279341 ┆7 ' A ^ LOWER 4 BIT ^ UPPER 4 BIT ^ STRAPS SETTINGS ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ PIN BLOCK NO. ^ 1 ^ 2 ^ 3 ^ 4 ^ 5 ^ 6 ^ 7 ^ 8 ^ 9 ^ 10┆
0x37a00…37b00 (55, 0, 10) Sector 370bb600279341 ┆7 6 ' A^ 11^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ STRAP LOCATION ^ B ^ B ^ B ^ B ^ X ^ X ^ A ^ Y ^ X ^ X ^ B ^ X = "DO NOT CARE" Y = FIXED MOUNTED 0 ^ 0 ^ 0 ^ ^ Rear Slot 14, PU#2 (SPARE) ^ 0 ^ 0 ^ 0 ^ 0 ^ ^ ┆
0x37b00…37c00 (55, 0, 11) Sector 370c4c00279341 ┆7 L ' A 1 LSB MSB STRAPS SETTINGS ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ PIN BLOCK NO. ^ 1┆
0x37c00…37d00 (55, 0, 12) Sector 370dff00279341 ┆7 ' A 1 1 skal gemmes 2793A/rt MT/RST ┆
0x37d00…37e00 (55, 0, 13) Sector 370eff00279341 ┆7 ' A 4:4:1-2 840620 CTX-CRATES L 1 1 CRATE┆
0x37e00…37f00 (55, 0, 14) Sector 370fff00279341 ┆7 ' A FUNCTIONS The CTX crate houses 25 stations in the FRONT POSITIONS front side the following modules: TDX modules: TDX Controller BSM-X LTUX-S OH 1 ADAPTOR modules: HWB: Fig. 3.1-3 L/L Adaptors type 1 (4 channels) L/L Adaptors type┆
0x37f00…38000 (55, 0, 15) Sector 3700ff00279341 ┆7 ' A 2 (1 channel) OPTO Transceivers (1 channel) 1 Power supply for the TDX modules. MOTHERBORD OH 2 The modules are plugged into a CTX CTX: Fig. motherboard which provides: 4.2-1 - interconnection between the LTUX.S and adaptor modules via ┆
0x38000…38100 (56, 0, 0) Sector 3801a800279341 ┆8 ( ' A = CR80 CHANNEL BUS ^ ^ GND 27 GND ^ ^ A8 28 A9 ^ ^ A10 29 ┆
0x38100…38200 (56, 0, 1) Sector 3802ff00279341 ┆8 ' A W BACK PLANE CONNECTION PIN LAYOUT For the LOWER CONNECTOR: HI-BUS ┆
0x38200…38300 (56, 0, 2) Sector 38032200279341 ┆8 " ' A 64 pol. flatcable BACK PLANE CONNECTION PIN LAY OUT for the UPPER CONNECTOR: 1 ^ 64 POL. C┆
0x38300…38400 (56, 0, 3) Sector 3804ff00279341 ┆8 ' A 1 SWITCH SETTING DEVICE ADDRESS: (DEVICE NO. in the TDX SYSTEM) DIP SWITCH "S1" CONTACT NO. ^ 1 ^ 2 ^ 3 ^ 4 ^ ┆
0x38400…38500 (56, 0, 4) Sector 3805ff00279341 ┆8 ' A OPEN OPEN = "1" (PRESS DOWN) ^ CONTACT NO. ^ ^ ^ ^ ^ ^ STI LOCATION ^ 1 ^ 2 ^ 3 ^ 4 ^ ^ ┆
0x38500…38600 (56, 0, 5) Sector 3806ff00279341 ┆8 ' A ^ ^ ^ ^ ^ ^ Front Slot 18, PU#1 ^ 1 ^ 0 ^ 0 ^ 0 ^ ^ Front Slot 18, PU#2 ^ 1 ^ 0 ^ 0 ^ 0 ^ ^ ^ ^ ^ ^ ^ LSB MSB I/O ADDRESS: (See┆
0x38600…38700 (56, 0, 6) Sector 3807ff00279341 ┆8 ' An from the CR80) DIP SWITCH "S2" CONTACT NO. ^ 1 ^ 2 ^ 3 ^ 4 ^ 5 ^ 6 ^ 7 ^ 8 ^ OPEN OPEN = "1" (PRESS DOWN) ┆
0x38700…38800 (56, 0, 7) Sector 3708ff00279341 ┆7 ' A ^ CONTACT NO.^ ^ ^ ^ ^ ^ ^ ^ ^ ^STI LOCATION ^ 1 ^ 2 ^ 3 ^ 4 ^ 5 ^ 6 ^ 7 ^ 8 ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ Front Slot 1┆
0x38800…38900 (56, 0, 8) Sector 3809ff00279341 ┆8 ' A 1 SWITCH SETTING BASE ADDRESS of the SHARED MEMORY seen from the STI MODULE: DIP SWITCH "S1" CONTACT NO. ^ 1 ^ 2 ^ 3 ^ 4 ^┆
0x38900…38a00 (56, 0, 9) Sector 380aff00279341 ┆8 ' A OPEN OPEN = "1" (PRESS DOWN) ^ CONTACT NO. ^ ^ ^ ^ ^ ^ TIA LOCATION ^ 1 ^ 2 ^ 3 ^ 4 ^ ^ ┆
0x38a00…38b00 (56, 0, 10) Sector 380bff00279341 ┆8 ' A ^ ^ ^ ^ ^ ^ Rear Slot 16, PU#1 ^ 0 ^ 0 ^ 0 ^ 0 ^ ^ Rear Slot 14, PU#1 (SPARE) ^ 0 ^ 0 ^ 0 ^ 0 ^ ^ Rear Slot 16, PU#2 ^ 0 ^ 0 ^ 0 ^ 0 ^ ^ Rear Slot 14, PU#2 (SPARE) ^ 0 ^ 0 ^ 0 ^ 0 ^ ^ ┆
0x38b00…38c00 (56, 0, 11) Sector 380cff00279341 ┆8 ' A ^ ^ ^ ^ ^ LSB MSB STRAPS SETTINGS ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ PIN BLOCK NO. ^ 1┆
0x38c00…38d00 (56, 0, 12) Sector 380d9400279341 ┆8 ' A ^ 2 ^ 3 ^ 4 ^ 5 ^ 6 ^ 7 ^ 8 ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ STRAP LOCATION ^ A ^ A ^ B ^ B ^ B ^ A ^ B ^ A ^ ^ 64 POL. FLATC┆
0x38d00…38e00 (56, 0, 13) Sector 380e6f00279341 ┆8 o ' A W Her inds`ttes tegning ^ ^ GND 2 GND ^ ^ 3 ^ ^ 4 ^ ^ 5 ^ ^ RX-STA┆
0x38e00…38f00 (56, 0, 14) Sector 380f6f00279341 ┆8 o ' A W Her inds`ttes tegning R/W ^ ^ TEST 10 DATI ^ ^ PWI 11 DACP ^ ^ 12 FB ^ ^ GND 13 [1 ^ ^┆
0x38f00…39000 (56, 0, 15) Sector 3800ff00279341 ┆8 ' A W BACK PLANE CONNECTION PIN LAYOUT for the MIDDLE CONNECTOR: STI MAIN BUS ┆
0x39000…39100 (57, 0, 0) Sector 3901ff00279341 ┆9 ' A ^ ^ GND 22 GND ^ ^ A0 23 A1 ^ ^ A2 24 A3 ^ ^ A4 25 A5 ^ ^ A6 26 A7 ^ ^ GND 27 GND ^ ^ A8 28 A9 ^ ^ A10 29 ┆
0x39100…39200 (57, 0, 1) Sector 39029400279341 ┆9 ' A A11 ^ ^ A12 30 A13 ^ ^ A14 31 A15 ^ ^ GND 32 GND ^ ^ ^ RAME is then converted BYTE by BYTE from SERIAL to PARALLEL and routed to FIFO 1. During this transfer the┆
0x39200…39300 (57, 0, 2) Sector 3903ff00279341 ┆9 ' A W BACK PLANE CONNECTION PIN LAY OUT for the UPPER CONNECTOR: 1 ^ 64 POL. C┆
0x39300…39400 (57, 0, 3) Sector 3904ff00279341 ┆9 ' AONNECTOR ^ ^ c ^ a ^ ^ ^ ^ 1 ^ ^ 2 ^ ^ 3 ^ ^ 4 ^ ^ 5 ^ ^ 6 ┆
0x39400…39500 (57, 0, 4) Sector 3905ff00279341 ┆9 ' A ^ ^ 7 ^ ^ 8 ^ ^ 9 ^ ^ 10 ^ ^ 11 ^ ^ 12 ^ ^ 13 ^ ^ 14 ┆
0x39500…39600 (57, 0, 5) Sector 3906ff00279341 ┆9 ' A ^ ^ 15 ^ ^ 16 ^ ^ 17 ^ ^ 18 ^ ^ 19 ^ ^ 20 ^ ^ 21 ^ ^ -24V (2) 22 -┆
0x39600…39700 (57, 0, 6) Sector 3907ff00279341 ┆9 ' A24V (1) ^ ^ GND 23 GND ^ ^ +24V (2) 24 +24V (1) ^ ^ -12V 25 -12V ^ ^ GND 26 GND ^ ^ +12V 27 +12V ^ ^ GND 28 GND ^ ^ GND 29 GND ^ ^ +5V 30 +5┆
0x39700…39800 (57, 0, 7) Sector 38087500279341 ┆8 u ' AV ^ ^ +5V 31 +5V ^ ^ +5V 32 +5V ^ ^ ^ ^ ^ 6 DISAB+ 1 19 GND ^ ^ ┆
0x39800…39900 (57, 0, 8) Sector 3909ff00279341 ┆9 ' A ^ ^ 7 GND 20 TXDAT- 1 ^ ^ ^ ^ 8 TXDAT+ 1 21 GND ^ ^ ^ ^ 9 ┆
0x39900…39a00 (57, 0, 9) Sector 390aff00279341 ┆9 ' A GND 22 RXDAT- 2 ^ ^ ^ ^ 10 RXDAT+ 2 23 TXDAT- 2 ^ ^ ^ ^ 11 TXDAT+ 2 ┆
0x39a00…39b00 (57, 0, 10) Sector 390bff00279341 ┆9 ' A 24 RXDAT- 1 ^ ^ ^ ^ 12 RXDAT+ 1 25 DISAB- 2 ^ ^ ^ ^ 13 DISAB+ 2 ┆
0x39b00…39c00 (57, 0, 11) Sector 390c5100279341 ┆9 Q ' A ^ ^ ^ n) present the LED will be illuminated. "TEST" LED If the TIA MODULE is not initialized by the (red) STI MODULE the "TEST" LED will be illuminated. TIA OH7 NONE! FRO┆
0x39c00…39d00 (57, 0, 12) Sector 390dff00279341 ┆9 ' A 1 BACK PLANE CONNECTION PIN LAY OUT for the LOWER CONNECTOR: 1 ^ 64 POL. FLATC┆
0x39d00…39e00 (57, 0, 13) Sector 390eff00279341 ┆9 ' AABLE, HI-BUS ^ ^ c ^ a ^ ^ ^ ^ GND 1 GND ^ ^ GND 2 GND ^ ^ 3 ^ ^ 4 ^ ^ 5 ^ ^ RX-STA┆
0x39e00…39f00 (57, 0, 14) Sector 390fff00279341 ┆9 ' ATUS 6 ERROR ^ ^ EX-INT 7 RESTART ^ ^ 8 MRQ ^ ^ 9 R/W ^ ^ TEST 10 DATI ^ ^ PWI 11 DACP ^ ^ 12 FB ^ ^ GND 13 [1 ^ ^┆
0x39f00…3a000 (57, 0, 15) Sector 3900ff00279341 ┆9 ' A GND 14 [2 ^ ^ H0 15 H1 ^ ^ H2 16 H3 ^ ^ GND 17 GND ^ ^ D0 18 D1 ^ ^ D2 19 D3 ^ ^ D4 20 D5 ^ ^ D6 21 D7 ┆
0x3a000…3a100 (58, 0, 0) Sector 3a01ff00279341 ┆: ' A SET UP by the DIP SWITCH named "S1". The STRAPS SETTINGS provide the APPLICATION of the STI MODULE to a UNIQUE PERFORMANCE. The CAMPS APPLICATION is shown. BUILD-IN TEST CHECK SUM TEST in EPROM. READ/WRITE TEST in RAM. TEST FRAMES a┆
0x3a100…3a200 (58, 0, 1) Sector 3a024900279341 ┆: I ' Are TRANSMITTED and RECEIVED by the TIA MODULE when starting up. t to be RECEIVED the FLAGS are deleted by the MPCC. The REST of the HDLC FRAME is then converted BYTE by BYTE from SERIAL to PARALLEL and routed to FIFO 1. During this transfer the┆
0x3a200…3a300 (58, 0, 2) Sector 3a037500279341 ┆: u ' A 1 Her inds`ttes tegning ) is carried out. From FIFO 1 the contents are transferred to FIFO 2 from which the FRONT END PROCESSOR will move the "DATA BYTES" of the┆
0x3a300…3a400 (58, 0, 3) Sector 3a047300279341 ┆: s ' A 1 Her inds`ttes tegning as been activated, an outgoing HDLC FRAME will be transferred BYTE by BYTE from FIFO 3 and converted from PARALLEL to SERIAL by the MPCC tog┆
0x3a400…3a500 (58, 0, 4) Sector 3a05ff00279341 ┆: ' A 1 FRONT PANEL CONNECTION PIN LAY OUT for the TDX BUS CONNECTOR: ^ PIN SIGNAL PIN SIGNAL ┆
0x3a500…3a600 (58, 0, 5) Sector 3a06ff00279341 ┆: ' A^ ^ ^ ^ 1 Logic one 14 same as 1 ^ ^ ^ ^ 2 Logic one 15 same as 2 ^ ^ ┆
0x3a600…3a700 (58, 0, 6) Sector 3a07ff00279341 ┆: ' A ^ ^ 3 GND 16 GND ^ ^ ^ ^ 4 GND 17 GND ^ ^ ┆
0x3a700…3a800 (58, 0, 7) Sector 3908ff00279341 ┆9 ' A ^ ^ 5 GND 18 DISAB- 1 ^ ^ ^ ^ 6 DISAB+ 1 19 GND ^ ^ ┆
0x3a800…3a900 (58, 0, 8) Sector 3a09ff00279341 ┆: ' AIA) L 11 1 TIA OH7 This MEMORY is SHARED by the SHARED MEMORY FRONT END PROCESSO┆
0x3a900…3aa00 (58, 0, 9) Sector 3a0aff00279341 ┆: ' AR of the TIA MODULE and the (RAM) INGOING and the OUTGOING PROCESSOR of the STI MODULE. An ARBITOR which is attached to the SHARED MEMORY makes this MEMORY DUAL PORTED. It directs whether the TIA or the HI-BUS has access to the SHARED MEMORY. ┆
0x3aa00…3ab00 (58, 0, 10) Sector 3a0bff00279341 ┆: ' A DMA CONTROLLER This circuit performs the data transfer from the DATA BUFFER (FIFO 2) to the SHARED MEMORY as well as the data transfer from the SHARED MEMORY to the DATA BUFFER (FIFO 3) FRONT PANEL OH7 Two LEDS are available in the FRONT PANE┆
0x3ab00…3ac00 (58, 0, 11) Sector 3a0cff00279341 ┆: ' AL. LEDS "POWER" LED When both of the SUPPLIES (+ 5V, - 12V) are (green) present the LED will be illuminated. "TEST" LED If the TIA MODULE is not initialized by the (red) STI MODULE the "TEST" LED will be illuminated. TIA OH7 NONE! FRO┆
0x3ac00…3ad00 (58, 0, 12) Sector 3a0d9f00279341 ┆: ' ANT PANEL SWITCHES FRONT PANEL OH7 The connection to one TDX BUS is obtained CONNECTION OH8 through a STANDARD 25 PIN CANNON CONNECTOR named "J1". PARALLEL conversion of each byte. When TRANSMITTING HDLC FRAMES the MPCC performs: - PA┆
0x3ad00…3ae00 (58, 0, 13) Sector 3a0eff00279341 ┆: ' A 1 2793A/rt MT/RST 4:2:3 840620 HOST I/F (STI/T┆
0x3ae00…3af00 (58, 0, 14) Sector 3a0fff00279341 ┆: ' AIA) L 12 1 BACK PANEL OH7 The connection to the STI MODULE is CONNECTIONS OH9 perf┆
0x3af00…3b000 (58, 0, 15) Sector 3a00ff00279341 ┆: ' Aormed by a FLAT CABLE via the LOWER BACK PANEL CONNECTOR. OH7 The POWER DISTRIBUTION is performed by a OH10 BACK PLANE MOTHERBOARD through the UPPER CONNECTOR. TIA OH7 The BASE ADDRESS of the SHARED MEMORY seen SET UP from the STI MODULE is┆
0x3b000…3b100 (59, 0, 0) Sector 3b01ff00279341 ┆; ' AIA) L 10 1 TIA OH7 FIRST IN FIRST OUT registers DATA BUFFER 3 FIFO registers are ┆
0x3b100…3b200 (59, 0, 1) Sector 3b02ff00279341 ┆; ' Aavailable for ROUTING the HDLC FRAMES. When a HDLC FRAME is about to be RECEIVED the FLAGS are deleted by the MPCC. The REST of the HDLC FRAME is then converted BYTE by BYTE from SERIAL to PARALLEL and routed to FIFO 1. During this transfer the┆
0x3b200…3b300 (59, 0, 2) Sector 3b03ff00279341 ┆; ' A MUX. No. and the CHANNEL ROUTING IDENTIFIER (CR-ID) are checked. Furthermore the CYCLIC REDUNDANCY CHECK (CRC) is carried out. From FIFO 1 the contents are transferred to FIFO 2 from which the FRONT END PROCESSOR will move the "DATA BYTES" of the┆
0x3b300…3b400 (59, 0, 3) Sector 3b04ff00279341 ┆; ' A HDLC FRAME to an "INGOING BUFFER" in the SHARED MEMORY. When the TRANSMITTER function of the STI MODULE has been activated, an outgoing HDLC FRAME will be transferred BYTE by BYTE from FIFO 3 and converted from PARALLEL to SERIAL by the MPCC tog┆
0x3b400…3b500 (59, 0, 4) Sector 3b05ff00279341 ┆; ' Aether with the execution of the remaining MPCC functions. The contents of FIFO 3 are at an earlier stage moved from an "OUTGOING BUFFER" in the SHARED MEMORY to FIFO 3. FRONT END PROCESSOR This is a standard ZILOG 80 MICRO PROCESSOR which exec┆
0x3b500…3b600 (59, 0, 5) Sector 3b06ff00279341 ┆; ' Autes the APPLICATION PROGRAM of the TIA MODULE. The APPLICATION PROGRAM is stored in an associated EPROM containing the TDX INTERFACE TASK and the TASK for the ACTIVATION and CONTROLLING of the DMA transfer between the DATA BUFFER and the SHARED MEM┆
0x3b600…3b700 (59, 0, 6) Sector 3b070e00279341 ┆; ' AORY. ows: RS-422 The DATA and CONTROL LINES to/from the TDX DRIVERS/RECEIVERS BUS are differential lines, which are in accordance with the RS-422 recommendations. DECODER A MESSAGE to a CR80 HOST COMPUTER via the & ENCODER TDX CONTROL┆
0x3b700…3b800 (59, 0, 7) Sector 3a08ff00279341 ┆: ' A 1 2793A/rt MT/RST 4:2:3 840620 HOST I/F (STI/T┆
0x3b800…3b900 (59, 0, 8) Sector 3b09ff00279341 ┆; ' A CODE in DATA and CLOCK. When the TIA MODULE is TRANSMITTING HDLC FRAMES, the ENCODER LOGIC on the MODULE will CODE the OUTGOING DATA with the 1.8432 MHz CLOCK and TRANSMIT the SPL-D CODED DATA STREAM to the UPPER TDX BUS. The CLOCK used by the ┆
0x3b900…3ba00 (59, 0, 9) Sector 3b0a8200279341 ┆; ' AENCODER LOGIC is derived from the DECODER LOGIC. In this way the MESSAGE HANDLING is SYNCRONIZED by the TDX CONTROLLER. STI SET UP OH2 Two DIP SWITCHES are available on the STI OH5 MODULE: ┆
0x3ba00…3bb00 (59, 0, 10) Sector 3b0bff00279341 ┆; ' A 1 2793A/rt MT/RST 4:2:3 840620 HOST I/F (STI/T┆
0x3bb00…3bc00 (59, 0, 11) Sector 3b0cff00279341 ┆; ' AIA) L 9 1 TIA OH7 MULTI PROTOCOL COMMUNICATION CONTROLLER. MPCC On RECEIVED HD┆
0x3bc00…3bd00 (59, 0, 12) Sector 3b0dff00279341 ┆; ' ALC FRAMES the MPCC performs: - Deletion of FLAG BYTES. - Deletion of ZEROES from the BITSTUFFING - CYCLIC REDUNDANCY CHECK (CRC). - SERIAL to PARALLEL conversion of each byte. When TRANSMITTING HDLC FRAMES the MPCC performs: - PA┆
0x3bd00…3be00 (59, 0, 13) Sector 3b0eff00279341 ┆; ' ARALLEL to SERIAL conversion of each byte. - BITSTUFFING (insertion of ZEROES). - CRC BYTE generation. - Insertion of FLAG BYTES and ABORT BYTE. STATE This functional block CONTROLS the ROUTING CONTROLLER of the HDLC FRAMES in the DAT┆
0x3be00…3bf00 (59, 0, 14) Sector 3b0f5800279341 ┆; X ' AA BUFFER. The LOGIC STATE CONTROLLER LOGIC also CONTROLS the MPCC functions. 2793A/rt MT/RST 4:2:3 840620 HOST I/F (STI/T┆
0x3bf00…3c000 (59, 0, 15) Sector 3b00ff00279341 ┆; ' A 1 2793A/rt MT/RST 4:2:3 840620 HOST I/F (STI/T┆
0x3c000…3c100 (60, 0, 0) Sector 3c01ff00279341 ┆< ' A16. PERFORMANCE The TIA MODULE is an INTELLIGENT FRONT END MODULE with the application as a SLAVE MODULE to the STI MODULE. The data exchanges between the STI MODULE and the TDX BUS passes via an onboard SHARED MEMORY (RAM), shared by the TIA MO┆
0x3c100…3c200 (60, 0, 1) Sector 3c02ff00279341 ┆< ' ADULE and the STI MODULE. The MAIN PERFORMANCES of the TIA MODULE are as follows: - DECODING and ENCODING of the SPL-D CODE by which the DATA STREAM is transferred on the TDX BUS. - SERIAL/PARALLEL and PARALLEL/SERIAL conversion of the DATA ┆
0x3c200…3c300 (60, 0, 2) Sector 3c03ff00279341 ┆< ' ASTREAM. - Serves the HDLC FRAME CHECK. - Routes the DATA to and from the onboard SHARED MEMORY (RAM). The HDLC FRAMES are RECEIVED from the LOWER BUS and TRANSMITTED to the UPPER BUS. The connection to the TDX BUS is obtained through a 25 ┆
0x3c300…3c400 (60, 0, 3) Sector 3c04a400279341 ┆< $ ' Apins connector in the FRONT PANEL of the TIA MODULE via WALL OUTLET. Connection to the STI MODULE is performed by a FLAT CABLE via a BACK PANEL CONNECTOR. 4:2:3 840620 HOST I/F (STI/T┆
0x3c400…3c500 (60, 0, 4) Sector 3c05ff00279341 ┆< ' A 1 2793A/rt MT/RST 4:2:3 840620 HOST I/F (S┆
0x3c500…3c600 (60, 0, 5) Sector 3c06ff00279341 ┆< ' ATI/TIA) L 8 1 TIA OH7 The BLOCK DIAGRAM of the TIA MODULE BLOCK DIAGRAM described┆
0x3c600…3c700 (60, 0, 6) Sector 3c07ff00279341 ┆< ' A as follows: RS-422 The DATA and CONTROL LINES to/from the TDX DRIVERS/RECEIVERS BUS are differential lines, which are in accordance with the RS-422 recommendations. DECODER A MESSAGE to a CR80 HOST COMPUTER via the & ENCODER TDX CONTROL┆
0x3c700…3c800 (60, 0, 7) Sector 3b08ff00279341 ┆; ' ALER will be RECEIVED by the destined TIA MODULE from the LOWER TDX BUS. This SERIAL DATA STREAM, consisting of the HDLC FRAMES, is coded with the 1.8432 MHz CLOCK by the TDX CONTROLLER in the SPL-D CODE. The DECODER LOGIC will SEPARATE the SPL-D┆
0x3c800…3c900 (60, 0, 8) Sector 3c09ff00279341 ┆< ' A 1 2793A/rt MT/RST 4:2:3 840620 HOST I/F (STI/T┆
0x3c900…3ca00 (60, 0, 9) Sector 3c0aff00279341 ┆< ' AIA) L 6 1 STI SET UP OH2 Two DIP SWITCHES are available on the STI OH5 MODULE: ┆
0x3ca00…3cb00 (60, 0, 10) Sector 3c0bff00279341 ┆< ' A - DIP SWITCH "S1" DEVICE ADDRESS (DEVICE NO. in the TDX SYSTEM) - DIP SWITCH "S2" I/O ADDRESS (MODULE ADDRESS seen from the CR80) The DEVICE ADDRESS of the STI MODULE identifies a unique DEVICE NO. in the TDX SYSTEM. It is SE┆
0x3cb00…3cc00 (60, 0, 11) Sector 3c0cff00279341 ┆< ' AT UP by means of the DIP SWITCH named "S1". NOTE! The "S1" SET UP is ignored by the CAMPS APPLICATION SOFTWARE. The INPUT/OUTPUT ADDRESS seen from the CR80 COMPUTER is SET UP by means of the DIP SWITCH named "S2". By using the DAM┆
0x3cc00…3cd00 (60, 0, 12) Sector 3c0dff00279341 ┆< ' AU UNIT MAPPING COMMAND "UM" it is possible to check, if the "SL" SWITCH SETTING is correct. The STRAPS SETTINGS provide the APPLICATION of the STI MODULE to a UNIQUE PERFORMANCE. CAMPS APPLICATION is shown. BUILD-IN INITIALIZATION to th┆
0x3cd00…3ce00 (60, 0, 13) Sector 3c0e1c00279341 ┆< ' Ae TIA MODULE. TEST L 4 1 "TEST" LED During the execution of the BUILD-IN TEST (red) (BIT), the ┆
0x3ce00…3cf00 (60, 0, 14) Sector 3c0fff00279341 ┆< ' A 1 2793A/rt MT/RST 4:2:3 840620 HOST I/F (STI/T┆
0x3cf00…3d000 (60, 0, 15) Sector 3c00ff00279341 ┆< ' AIA) L 7 1 TIA OH6 In every PROCESSOR UNIT (PU) in REAR SLOT MODULE POSITION No. ┆
0x3d000…3d100 (61, 0, 0) Sector 3d01ff00279341 ┆= ' AP.ERROR" OH2 If a drop in the SUPPLIES (+5V, +12V, -12V) LED (red) has occurred since the latest MASTER CLEAR, the "P.ERROR" LED will be illuminated to indicate an intermediate POWER ERROR. "C.ERROR" LED If TIME-OUT or PARITY ERROR has been ┆
0x3d100…3d200 (61, 0, 1) Sector 3d02ff00279341 ┆= ' Adetected (red) during a DMA transfer on the MAIN BUS, the "C.ERROR" LED will be illuminated. "M.ERROR" LED If TIME-OUT or PARITY ERROR has been detected (red) during a DMA transfer on the internal HI-BUS, the "M.ERROR" LED will be illuminate┆
0x3d200…3d300 (61, 0, 2) Sector 3d030a00279341 ┆= ' Ad. vides the access from the CR80 to the CENTRAL RAM. - DIRECT MEMORY ACCESS (DMA) from the CR80 MAIN MEMORY to the TIA MEMORY and vice versa. - Derives the HI-BUS CLOCK from the CR80 MAIN BUS CLOCK. - Exchanges INTERRUPTS between INGOING ┆
0x3d300…3d400 (61, 0, 3) Sector 3d04ff00279341 ┆= ' A 1 2793A/rt MT/RST 4:2:3 840620 HOST I/F (STI/T┆
0x3d400…3d500 (61, 0, 4) Sector 3d05ff00279341 ┆= ' AIA) L 5 1 "RX.STATE" LED When the STI MODULE via the TIA MODULE does (yellow) n┆
0x3d500…3d600 (61, 0, 5) Sector 3d06ff00279341 ┆= ' Aot receive the 1.8432 MHz SYNCHRONIZATION CLOCK from the SPL-D CODE, the "RX.STATE" LED will be illuminated. STI FRONT OH2 NONE! PANEL SWITCHES FRONT PANEL OH2 NONE! CONNECTIONS BACK PLANE OH2 The UPPER CONNECTOR (P1) is used for the CON┆
0x3d600…3d700 (61, 0, 6) Sector 3d07ff00279341 ┆= ' ANECTIONS POWER SUPPLY only (equal to the POWER CONNECTION on the MIDDLE CONNECTOR). OH2 The MIDDLE CONNECTOR (P2) performs the OH3 connection to the CR80 CHANNEL BUS. OH2 The LOWER CONNECTOR (P3) performs the OH4 connection to the TIA MODULE┆
0x3d700…3d800 (61, 0, 7) Sector 3c081c00279341 ┆< ' A via a FLAT CABLE. L 3 1 OUTGOING OUTGOING DATA is data from CR80 to TIA PROCESSOR MODULE. ┆
0x3d800…3d900 (61, 0, 8) Sector 3d09ff00279341 ┆= ' AThe Processor is a standard ZILOG 80 MICRO PROCESSOR containing the TDX PACKET PROTOCOL TASK for the OUTGOING HDLC FRAMES. The OUTGOING PROCESSOR also SETS UP the PARAMETER (SOURCE and DESTINATION) used by the MBIF for the DMA DATA TRANSFER from ┆
0x3d900…3da00 (61, 0, 9) Sector 3d0aff00279341 ┆= ' Athe CR80 MAIN MEMORY to the SHARED MEMORY on the TIA MODULE. CENTRAL RAM The CENTRAL RAM is a 32K BYTE RAM which is accessed via the HOST INTERFACE BUS (HI-BUS). It contains INFORMATION about the DMA ADDRESSES. HI-BUS ARBITOR This functional┆
0x3da00…3db00 (61, 0, 10) Sector 3d0bff00279341 ┆= ' A block directs the access to the HI-BUS where the INTERNAL DATA TRANSFER as well as the DATA TRANSFER between the CR80 CHANNEL BUS and the STI MODULE are routed. STI FRONT OH2 Eight LEDs are available in the FRONT PANEL. PANEL LEDS "POWER" L┆
0x3db00…3dc00 (61, 0, 11) Sector 3d0c6c00279341 ┆= l ' AED When all the three supplies (+5V, +12V, (green) -12V) are present, the LED will be illuminated. 1 STI MODULE OH1 In every PROCESSOR UNIT (PU) in FRONT SLOT POSITION N┆
0x3dc00…3dd00 (61, 0, 12) Sector 3d0dff00279341 ┆= ' A 1 2793A/rt MT/RST 4:2:3 840620 HOST I/F (STI/T┆
0x3dd00…3de00 (61, 0, 13) Sector 3d0eff00279341 ┆= ' AIA) L 4 1 "TEST" LED During the execution of the BUILD-IN TEST (red) (BIT), the ┆
0x3de00…3df00 (61, 0, 14) Sector 3d0fff00279341 ┆= ' A"TEST" LED will be illuminated for a few seconds. When the BUILD-IN TEST is fulfilled successfully (no error), the "TEST" LED will be extinguished. If the BUILD-IN TEST detects an ERROR, the "TEST" LED will show CONSTANT LIGHT. "BUSY" LED ┆
0x3df00…3e000 (61, 0, 15) Sector 3d00ff00279341 ┆= ' ADuring a DIRECT MEMORY ACCESS (DMA)transfer (yellow) on the MAIN BUS, the "BUSY" LED will be illuminated. "H.I. DMA" During a DIRECT MEMORY ACCESS (DMA) transfer (yellow) on the internal HI-BUS, the "H.I. DMA" LED will be illuminated. STI"┆
0x3e000…3e100 (62, 0, 0) Sector 3e01ff00279341 ┆> ' AIA) L 2 1 STI MODULE OH2 STI BLOCK DIAGRAM described as follows: BLOCK DIAGRAM ┆
0x3e100…3e200 (62, 0, 1) Sector 3e02ff00279341 ┆> ' AMBIF: (MAIN BUS INTERFACE) The MBIF provides the connection between the CR80 MAIN BUS and the internal HI-BUS. This functionally block contains a HIGH SPEED BIT SLICE MICROPROCESSOR and a DMA CONTROLLER. It performs the functions as follows: -┆
0x3e200…3e300 (62, 0, 2) Sector 3e03ff00279341 ┆> ' A Provides the access from the CR80 to the CENTRAL RAM. - DIRECT MEMORY ACCESS (DMA) from the CR80 MAIN MEMORY to the TIA MEMORY and vice versa. - Derives the HI-BUS CLOCK from the CR80 MAIN BUS CLOCK. - Exchanges INTERRUPTS between INGOING ┆
0x3e300…3e400 (62, 0, 3) Sector 3e04ff00279341 ┆> ' APROCESSOR, OUTGOING PROCESSOR, and CR80. - Supervises the three POWER SOURCES (+5V, +12V, -12V). - Displays STATUS of the STI MODULE. STI INGOING OH2 INGOING DATA is data from TIA MODULE to CR80 PROCESSOR The PROCESSOR is a standard ZIL┆
0x3e400…3e500 (62, 0, 4) Sector 3e05ff00279341 ┆> ' AOG 80 MICRO PROCESSOR containing the TDX PACKET PROTOCOL TASK for the INGOING HDLC FRAMES. The INGOING PROCESSOR also SETS UP the PARAMETERS (SOURCE and DESTINATION) used by the MBIF for the DMA DATA TRANSFER from the SHARED MEMORY on the TIA MOD┆
0x3e500…3e600 (62, 0, 5) Sector 3e062300279341 ┆> # ' AULE to the CR80 MAIN MEMORY. 2793A/rt MT/RST 4:2:1-2 840620 TDX CONTROLLER ┆
0x3e600…3e700 (62, 0, 6) Sector 3e07ff00279341 ┆> ' A 1 2793A/rt MT/RST 4:2:3 840620 HOST I/F (STI/T┆
0x3e700…3e800 (62, 0, 7) Sector 3d08ff00279341 ┆= ' AIA) L 3 1 OUTGOING OUTGOING DATA is data from CR80 to TIA PROCESSOR MODULE. ┆
0x3e800…3e900 (62, 0, 8) Sector 3e09ff00279341 ┆> ' A STRAP LOCATION ^ A ^ B ^ B ^ C ^ B ^ B ^ C ^ B ^ B ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ PIN BLOCK NO. ^ 11^ 12^ 13^ 14^ 15^ 16^ 17^ 18^ 19^ ^ ^ ^ ┆
0x3e900…3ea00 (62, 0, 9) Sector 3e0a5d00279341 ┆> ] ' A^ ^ ^ ^ ^ ^ ^ ^ ^ STRAP LOCATION ^ A ^ A ^ B ^ B ^ A ^ A ^ B ^ B ^ B ^ ected to both RECEIVER CHANNELS on the other TDX CONTROLLER. Therefore, the LED is insignificant in the CAMPS. HDLC FRAMES in the DATA BUFFER. The LOGIC STATE ┆
0x3ea00…3eb00 (62, 0, 10) Sector 3e0bff00279341 ┆> ' A 1 2793A/rt 4:2:3 840620 MT/RST L┆
0x3eb00…3ec00 (62, 0, 11) Sector 3e0cff00279341 ┆> ' A HOST I/F (STI/TIA) 1 1 STI MODULE OH1 In every PROCESSOR UNIT (PU) in FRONT SLOT POSITION N┆
0x3ec00…3ed00 (62, 0, 12) Sector 3e0dff00279341 ┆> ' Ao. 18. PERFORMANCE The STI MODULE is an INTELLIGENT INTERFACE MODULE associated the TDX SYSTEM for the COMMUNICATION between the CR80 COMPUTER and one TDX BUS via the TELECOMMUNICATION INTERFACE ADAPTOR MODULE (TIA). The MAIN PERFORMANCES of ┆
0x3ed00…3ee00 (62, 0, 13) Sector 3e0eff00279341 ┆> ' Athe STI MODULE are as follows: - Responds to CR80 access to the STI MODULE - CONTROL of the CR80 access to the STI MODULE - DIRECT MEMORY ACCESS (DMA) transfer from CR80 MAIN MEMORY to TIA MEMORY and vice versa - Establishes VIRTUAL CHAN┆
0x3ee00…3ef00 (62, 0, 14) Sector 3e0ff300279341 ┆> s ' ANELS for COMMUNICATION between STI MODULE and LTUX-S MODULES - Serves the TDX PACKET PROTOCOL - HIGH BANDWIDTH - Connection to the CR80 CHANNEL BUS via BACK PLANE MOTHERBOARD and connection to the TIA MODULE via a FLAT CABLE n connector ┆
0x3ef00…3f000 (62, 0, 15) Sector 3e00ff00279341 ┆> ' A 1 2793A/rt MT/RST 4:2:3 840620 HOST I/F (STI/T┆
0x3f000…3f100 (63, 0, 0) Sector 3f01ff00279341 ┆? ' A 1 2793A/rt MT/RST 4:2:1-2 840620 TDX CONTROLLER ┆
0x3f100…3f200 (63, 0, 1) Sector 3f02ff00279341 ┆? ' A L 7 1 BACK PLANE OH2 The PIN LAY OUT of the BACK PLANE CONNECTION CONNECTION┆
0x3f200…3f300 (63, 0, 2) Sector 3f03ff00279341 ┆? ' AS OH6 to the TDX CONTROLLER. This connection is used for the POWER SUPPLY (+5V, +12V, -12V). SET UP OH2 The DEVICE ADDRESS of the TDX CONTROLLER OH7 identifies a unique DEVICE No. in the TDX SYSTEM. The ADDRESS SETTING is a FIXED SET UP ┆
0x3f300…3f400 (63, 0, 3) Sector 3f04ff00279341 ┆? ' A (DIP SWITCH "S1" not used). TDX CONTROLLER DEVICE ADDRESS = [[ (always). The STRAPS SETTINGS provide the APPLICATION of the TDX CONTROLLER to a UNIQUE PERFORMANCE. CAMPS APPLICATION is shown. BUILD-IN TEST CHECK SUM TEST in EPROM. ┆
0x3f400…3f500 (63, 0, 4) Sector 3f051f00279341 ┆? ' AREAD/WRITE TEST in RAM. 2793A/rt MT/RST 4:2:1-2 840620 TDX CONTROL┆
0x3f500…3f600 (63, 0, 5) Sector 3f06ff00279341 ┆? ' A 1 2793A/rt MT/RST 4:2:1-2 840620 TDX CONTROLLER ┆
0x3f600…3f700 (63, 0, 6) Sector 3f07ff00279341 ┆? ' A L 8 1 SWITCH SETTING NONE! The DEVICE ADDRESS is FIXED SET UP = [[ ┆
0x3f700…3f800 (63, 0, 7) Sector 3e08ff00279341 ┆> ' A STRAPS SETTINGS ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ PIN BLOCK NO. ^ 2 ^ 3 ^ 4 ^ 5 ^ 6 ^ 7 ^ 8 ^ 9 ^ 10^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^┆
0x3f800…3f900 (63, 0, 8) Sector 3f09ff00279341 ┆? ' ACTED" the LED will be illuminated. On the other hand when the TDX CONTROLLER STATUS is "UPPER BUS #2 SELECTED" the LED will be extinguished. However, in the CAMPS a TDX CONTROLLER is used for each of the two TDX BUSSES. The UPPER BUS #1 is connect┆
0x3f900…3fa00 (63, 0, 9) Sector 3f0acd00279341 ┆? M ' Aed to both RECEIVER CHANNELS on one of the TDX CONTROLLERS and the UPPER BUS #2 is connected to both RECEIVER CHANNELS on the other TDX CONTROLLER. Therefore, the LED is insignificant in the CAMPS. HDLC FRAMES in the DATA BUFFER. The LOGIC STATE ┆
0x3fa00…3fb00 (63, 0, 10) Sector 3f0bff00279341 ┆? ' A 1 2793A/rt 4:2:1-2 840620 MT/RST TDX CONTROLLER ┆
0x3fb00…3fc00 (63, 0, 11) Sector 3f0cff00279341 ┆? ' A L 6 1 "TR.ST." LED ERROR detected in the TRANSMITTED SPL-D code (red) wi┆
0x3fc00…3fd00 (63, 0, 12) Sector 3f0dff00279341 ┆? ' All cause the "TR.ST." LED to be illuminated. "FUSE" LED ERROR in one or both of the SUPPLIES (red) (V cc 1, V cc 2) or in the FUSES for the associated WALL OUTLET will cause the "FUSE" LED to be illuminated. FRONT PANEL OH2 N┆
0x3fd00…3fe00 (63, 0, 13) Sector 3f0eff00279341 ┆? ' AONE! SWITCHES FRONT PANEL OH2 A BNC connector and two 25 pin connectors CONNECTIONS are available in the FRONT PANEL. The BNC connector named "EXT. CLK" is used for EXTERNAL 1.8432 MHz CLOCK SIGNAL. OH2 The 25 pin connector named "TDX BUS"┆
0x3fe00…3ff00 (63, 0, 14) Sector 3f0fff00279341 ┆? ' A is used OH3 for the connection of the TDX CONTROLLER to the respective TDX BUS via WALL OUTLET. OH2 The 25 pin connector named "WATCH DOG" is OH4 used for the connection of the TDX OH5 CONTROLLER to the WATCH DOG via the 25 pin connector ┆
0x3ff00…40000 (63, 0, 15) Sector 3f00d800279341 ┆? X ' Aon the BSM-X and further on through the CONFIGURATION CONTROL BUS. OH2 As another application it is possible to OH4 connect a TEST TERMINAL (VDU) to the "WATCH DOG" connector for TDX SYSTEM STATUS TEST. ONOUS RECEIVER TRANSMITTER The USA┆
0x40000…40100 (64, 0, 0) Sector 4001ff00279341 ┆@ ' ART handles the SERIAL COMMUNICATION to/from a TEST TERMINAL (VDU) via the 24V DRIVERS/RECEIVERS. The BAUD RATE is 300 BAUD. V24 RECEIVERS Standard V24 RECEIVERS/DRIVERS are /DRIVERS OH2 associated the USART ports to obtain a standardized conn┆
0x40100…40200 (64, 0, 1) Sector 4002ff00279341 ┆@ ' Aection to the TEST TERMINAL (VDU). WATCH DOG The WATCH DOG LOGIC is MONITORING the TDX LOGIC CONTROLLER STATUS and the STATUS of the POWER supplied to the WALL OUTLETS. The LOGIC is equipped with 5 drivers and 3 receivers for SIGNAL EXCHANG┆
0x40200…40300 (64, 0, 2) Sector 4003ff00279341 ┆@ ' AE through the "WATCH DOG" connector via the BSM-X and the CONFIGURATION CONTROL BUS to the WATCH DOG PROCESSOR UNIT. CLOCK This circuit consists of a 1.8432 Mhz GENERATOR oscillator. The CLOCK PULSES are used in the ENCODER logic where the SERIA┆
0x40300…40400 (64, 0, 3) Sector 40045500279341 ┆@ U ' AL DATA is coded with the CLOCK (SPL-D code) and transmitted on the LOWER BUS. imultaniously on the LOWER BUS a in so-called SPL-D CODE. The ENCODER LOGIC codes the OUTGOING SERIAL DATA with the CLOCK. The DECODER LOGIC will decode the DATA STRE┆
0x40400…40500 (64, 0, 4) Sector 4005ff00279341 ┆@ ' A 1 2793A/rt MT/RST 4:2:1-2 840620 TDX CONTROL┆
0x40500…40600 (64, 0, 5) Sector 4006ff00279341 ┆@ ' ALER L 5 1 FRONT PANEL OH2 Five LEDS are available in the FRONT PANEL. LEDS ┆
0x40600…40700 (64, 0, 6) Sector 4007ff00279341 ┆@ ' A"POWER" LED If all the 3 SUPPLIES (+ 5V, + 12V, - 12V) (green) are present the LED will be illuminated. "TEST" LED During the execution of the BUILD-IN TEST (red) (BIT) the "TEST" LED will be illuminated for a few seconds. When th┆
0x40700…40800 (64, 0, 7) Sector 3f08ff00279341 ┆? ' Ae BUILD-IN TEST is fulfilled successfully (no error) the "TEST" LED will be extinguished. If the BUILD-IN TEST detects an ERROR the "TEST" LED will show SLOW FLASH. "REC.ST." LED When the TDX CONTROLLER STATUS is "UPPER (yellow) BUS#1 SELE┆
0x40800…40900 (64, 0, 8) Sector 4009ff00279341 ┆@ ' AAMES the MPCC performs: - Deletion of ABORT byte and FLAG bytes - Deletion of ZEROES from the BITSTUFFING - CYCLIC REDUNDANCY CHECK (CRC) - SERIAL to PARALLEL conversion of each byte When TRANSMITTING HDLC FRAMES the MPCC performs: - P┆
0x40900…40a00 (64, 0, 9) Sector 400aff00279341 ┆@ ' AARALLEL to SERIAL conversion of each byte - BITSTUFFING (Insertion of ZEROES) - CRC byte generation - FLAGE bytes insertion STATE This functional block CONTROLS the ROUTING CONTROLLER of the HDLC FRAMES in the DATA BUFFER. The LOGIC STATE ┆
0x40a00…40b00 (64, 0, 10) Sector 400bff00279341 ┆@ ' ACONTROLLER LOGIC also CONTROLS the MPCC functions. DATA BUFFER FIRST IN FIRST OUT registers. 4 FIFO registers are available for ROUTING the HDLC FRAMES. The CHANNEL ROUTING IDENTIFIER (CR-ID) in the HDLC FRAMES contents the INFORMATION of DE┆
0x40b00…40c00 (64, 0, 11) Sector 400cff00279341 ┆@ ' ASTINATION of the respective FRAMES. If the FRAME is destined for the TDX CONTROLLER itself ("HOST NO. = [["), the DATA INFORMATION will be used informally by the CPU. If the "HOST NO." in the received FRAME is not equal to "[[", a MUX. NO. will be┆
0x40c00…40d00 (64, 0, 12) Sector 400d6f00279341 ┆@ o ' A inserted in the FRAME and the FRAME will be transmitted to the DEVICE which is IDENTIFIED in the CR-ID. cording to a predefinded MUX. TABLE in the TDX CONTROLLER. How often a certain DEVICE (LTUX-S or STI MODULE) is allowed to send MESSAGES on t┆
0x40d00…40e00 (64, 0, 13) Sector 400eff00279341 ┆@ ' A 1 2793A/rt MT/RST 4:2:1-2 840620 TDX CONTROL┆
0x40e00…40f00 (64, 0, 14) Sector 400fff00279341 ┆@ ' ALER L 4 1 CPU/MEMORY The CPU is a standard Z80 microprocessor. Together with┆
0x40f00…41000 (64, 0, 15) Sector 4000ff00279341 ┆@ ' A the MEMORY and part of the DATA BUFFER, the CPU constitutes the MICRO COMPUTER PART of the TDX CONTROLLER. It handles the MUX. TABLE and diagnostics the communication. USART UNIVERSAL SYNCHRONOUS ASYNCHRONOUS RECEIVER TRANSMITTER The USA┆
0x41000…41100 (65, 0, 0) Sector 4101ff00279341 ┆A ' ALER L 2 1 MESSAGE FORMAT, CODE FORMAT, and DATA COMMUNICATION. (See Lesson 4┆
0x41100…41200 (65, 0, 1) Sector 4102ff00279341 ┆A ' A:1:2 & 4:1:3). Because of a REDUNDANT SYSTEM two TDX CONTROLLERS are incorporated. The AUTOMATICALLY ENABLING of one of these TDX CONTROLLERS and the DISABLING of the other one is performed by the WATCH DOG according to the STATUS of the TDX CON┆
0x41200…41300 (65, 0, 2) Sector 4103ff00279341 ┆A ' ATROLLERS, and the STATUS of the PROCESSOR UNITS. BLOCK DIAGRAM OH2 The TDX BLOCK DIAGRAM described as follows: RS-422 The DATA and CONTROL LINES from/to the RECEIVER/DRIVER TDX BUS are differential lines in accordance with the RS-422 recommen┆
0x41300…41400 (65, 0, 3) Sector 4104ff00279341 ┆A ' Adations. ENCODER & DECODER The DATA and the 1.8432 MHz CLOCK are transmitted simultaniously on the LOWER BUS a in so-called SPL-D CODE. The ENCODER LOGIC codes the OUTGOING SERIAL DATA with the CLOCK. The DECODER LOGIC will decode the DATA STRE┆
0x41400…41500 (65, 0, 4) Sector 4105ff00279341 ┆A ' AAM being RECEIVED, that means separating the SPL-D CODE in the DATA and the CLOCK. OH2 The advantages of the SPL-D CODE are: - SOURCE and DESTINATION are SYNCRONIZED - Correct decoding in spite of delay in cable The TDX CONTROLLER TRANSMI┆
0x41500…41600 (65, 0, 5) Sector 41068700279341 ┆A ' ATS on the LOWER BUS and RECEIVES on the UPPER BUS. Each BUS consists of a TWISTED PAIR CABLE. UPPER BUS + LOWER BUS = TDX BUS. ADAPTORS Show the location of L/L ADAPTOR, OPTO T/R, & PANELS BP8, TSP and BSM-X panel and explain the relation to o┆
0x41600…41700 (65, 0, 6) Sector 4107ff00279341 ┆A ' A 1 2793A/rt MT/RST 4:2:1-2 840620 TDX CONTROL┆
0x41700…41800 (65, 0, 7) Sector 4008ff00279341 ┆@ ' ALER L 3 1 MPCC MULTI PROTOCOL COMMUNICATION CONTROLLER On RECEIVED HDLC FR┆
0x41800…41900 (65, 0, 8) Sector 41099200279341 ┆A ' Aduce SLM: Section 4.5.4 INTRODUCT. Section 4.5.4 Section 4.7.2.1.8 Section 4.7.2.2 HWB HWB Introduce HWB: Section 3 INTRODUCT. xt lower speed level dependent on the state of the FF, which is complemented by each test. The MUX-table show┆
0x41900…41a00 (65, 0, 9) Sector 410aff00279341 ┆A ' A 1 2793A/rt MT/RST 4:2:1-2 840620 TDX CONTROL┆
0x41a00…41b00 (65, 0, 10) Sector 410bff00279341 ┆A ' ALER L 1 1 MODULE OH1 The TDX CONTROLLER for the TDX BUS #1 is POSITI┆
0x41b00…41c00 (65, 0, 11) Sector 410cff00279341 ┆A ' AON placed in TDX UNIT No. 1, FRONT SLOT No. 1 The TDX CONTROLLER for the TDX BUS #2 is placed in TDX UNIT No. 4, FRONT SLOT No. 1. PERFORMANCE CONTROLS and SYNCHRONIZES the DATA- COMMUNICATION between the STI MODULE in the PROCESSOR UNIT (P┆
0x41c00…41d00 (65, 0, 12) Sector 410dff00279341 ┆A ' AU) and the LTUX-S MODULES in the TDX UNITS (TU). The CONTROL of the DATA COMMUNICATION is performed according to a predefinded MUX. TABLE in the TDX CONTROLLER. How often a certain DEVICE (LTUX-S or STI MODULE) is allowed to send MESSAGES on t┆
0x41d00…41e00 (65, 0, 13) Sector 410eff00279341 ┆A ' Ahe TDX BUS is called BANDWIDTH. The BANDWIDTH depends on how often the DEVICE No. is represented in the MUX. TABLE. The SYNCHRONIZING of the DATA COMMUNICATION by the TDX CONTROLLER is due to a continious BIT STREAM of 1.8432 Mbit/sec. which the┆
0x41e00…41f00 (65, 0, 14) Sector 410fd100279341 ┆A Q ' A TDX CONTROLLER clocks and synchronizes on the LOWER TDX BUS. This BIT STREAM is divided into 6400 TIME SLOTS of 288 bits each. In each TIME SLOT a DATA MESSAGE or a DUMMY MESSAGE can be transmitted. EVICE transmit on the TDX BUS, then the ENCODE┆
0x41f00…42000 (65, 0, 15) Sector 4100ff00279341 ┆A ' A 1 2793A/rt MT/RST 4:2:1-2 840620 TDX CONTROL┆
0x42000…42100 (66, 0, 0) Sector 4201ec00279341 ┆B l ' AR. contains the TDX SYSTEM CLOCK GENERATOR (1.8432 MHz). The clock used by the LTUX-S and TIA, when transmitting, is derived from the respective DECODER LOGIC. In this way MESSAGE HANDLING in the TDX SYSTEM is SYNCHRONIZED. ne frame on the TDX┆
0x42100…42200 (66, 0, 1) Sector 4202ff00279341 ┆B ' A 1 2793A/rt MT/RST 4:1:4-6 840620 DEMONSTRATION OF THE TDX SYS┆
0x42200…42300 (66, 0, 2) Sector 4203ff00279341 ┆B ' ATEM, SLM, and HWB DE, I, DI 1 1 TDX UNITS Show all the TDX UNITS related to the TDX UNIT "NO.s"┆
0x42300…42400 (66, 0, 3) Sector 4204ff00279341 ┆B ' A. TDX BUSSES Show the location of the two TDX CONTROLLERS. Follow the cable from the "TDX BUS" connector on the front panel of the TDX CONTROLLER to the respective WALL OUTLET and then follow the TDX BUS from TDX UNIT to TDX UNIT and PU. Exp┆
0x42400…42500 (66, 0, 4) Sector 4205ff00279341 ┆B ' Alain the relation between the BSM-X "MODULE NO.s" and TDX UNIT "NO.s". TDX DEVICES Show the location of the LTUX-S modules and the STI/TIA modules. Explain the relation between the LTUX-S "DEVICE NO.s" and the TDX UNIT "NO.s". Take out a LTU┆
0x42500…42600 (66, 0, 5) Sector 4206ff00279341 ┆B ' AX-S module from a TDX CRATE and show a DIP SWITCH. NOTE! - Always POWER OFF when removing or inserting MODULES in TDX CRATES. ADAPTORS Show the location of L/L ADAPTOR, OPTO T/R, & PANELS BP8, TSP and BSM-X panel and explain the relation to o┆
0x42600…42700 (66, 0, 6) Sector 4207ff00279341 ┆B ' Ather TDX modules, BUSSES and PERIPHERALS. PS Show the location of the PS and explain the application of PS in front magazine and PS in rear magazines. PORT ID Go to the SUPERVISOR POSITION and SIGN ON to ENGINEERING FUNCTION. Perform the command┆
0x42700…42800 (66, 0, 7) Sector 4108ff00279341 ┆A ' A "PCON" and print out "ALL" the configuration list of the TDX SYSTEM DEVICES and PERIPHERALS. 4:1:1 Explain the relation between the LINE PORT ID OH5-7 and the corresponding LTUX-S, ADAPTOR, BP8, I/O CHANNEL (LINE), and PERIPHERAL. SLM SLM Intro┆
0x42800…42900 (66, 0, 8) Sector 4209ff00279341 ┆B ' A the last "ADD" in the speed level chain - one of two possibilities: the first "ADD" in the highest speed level or the first "ADD" in the next lower speed level dependent on the state of the FF, which is complemented by each test. The MUX-table show┆
0x42900…42a00 (66, 0, 9) Sector 420a7900279341 ┆B y ' An on OH 1 will give following bandwidth-allocation (please notice that not used speed levels are not encountered). ted in the COMMUNICATION byte. The bytecount and the continous frame count is detected in the CONTROL BYTE (SEQ. NO. + NO. OF DATA BYT┆
0x42a00…42b00 (66, 0, 10) Sector 420bff00279341 ┆B ' A 1 2793A/rt MT/RST 4:1:3 840620 TDX TRANSMISSION ┆
0x42b00…42c00 (66, 0, 11) Sector 420cff00279341 ┆B ' A L 4 1 1 BLACK AB - ABC - ┆
0x42c00…42d00 (66, 0, 12) Sector 420dff00279341 ┆B ' AAB - ABCD - AB - ABC - AB - ABCDEFG BOARD AB - ABC - AB - ABCD - AB - ABC - AB - ABCDEFGH AB - ABC - AB - ABCD - AB - ABC - AB - ABCDEFG AB - ABC - AB - ABCD - AB - ABC - AB - ABCDEFGH (DUMMY) This gives a rela┆
0x42d00…42e00 (66, 0, 13) Sector 420eff00279341 ┆B ' Ative bandwidth on following: 1 BLACK Address Relative Bandwidth BOARD A, B 32 C 16 D 8 E, F, G 4 H 2 I, DUMMY 1 This entire cyclus is repeated c┆
0x42e00…42f00 (66, 0, 14) Sector 420fff00279341 ┆B ' Aontinuously and is called a scancyclus. DECODER, On the TDX CONTR., on the LTUX-S, and on the ENCODER STI/TIA a DECODER and an ENCODER is build and in. SPL-D CODE OH2 When the above mentioned TDX DEVICE transmit on the TDX BUS, then the ENCODE┆
0x42f00…43000 (66, 0, 15) Sector 4200ff00279341 ┆B ' AR will CODE the OUTGOING bits with the CLOCK SIGNAL (1.8432 MHz) in a so-called SPL-D CODE (self clocking differential split phase code). When receiving from the TDX BUS the DECODER will SEPARATE the SPL-DS CODE in bits and clock. The TDX CONT┆
0x43000…43100 (67, 0, 0) Sector 4301ff00279341 ┆C ' A The HOST INTERFACE transfers data in logical data units (LDUs) which are a number of datapackets. At LEVEL 3 the LDUs are chopped into packets. Retransmission may be requested for frames or packets, not for LDUs. BANDWIDTH As one frame on the TDX┆
0x43100…43200 (67, 0, 1) Sector 4302e700279341 ┆C g ' A BUS transfers max. (BW) 128 data bits (16 bytes x 8 bits) and a transfer from a DEVICE only occurs when the DEVICE NO. equals the MUX NO., then the bandwidth of a DEVICE is directly related to the frequence of the MUX NO. TDX TRANSMISSION ┆
0x43200…43300 (67, 0, 2) Sector 4303ff00279341 ┆C ' A 1 2793A/rt MT/RST 4:1:3 840620 TDX TRANSMISSION ┆
0x43300…43400 (67, 0, 3) Sector 4304ff00279341 ┆C ' A L 3 1 All the DEVICES in a specific system configuration are allocated a certain BW which is prep┆
0x43400…43500 (67, 0, 4) Sector 4305ff00279341 ┆C ' Arogrammed in the MUX table of the TDX CONTROLLER firmware (PROM). The MUX. NO. of a high BW device is written more frequently than a MUX. NO. of a low BW device. QUESTION What is the max. BW (theoretically) of the TDX BUS? ANSWER (16 data bytes ┆
0x43500…43600 (67, 0, 5) Sector 4306ff00279341 ┆C ' Ax 8 bits x 6400 time slots/sec = 819200 baud BW SPEED LEVEL MUX TABLE . . . . . . (EXPLAIN) Only MUX. NO.s for DEVICES appended to the bus (status READY) will be inserted in the lower b┆
0x43600…43700 (67, 0, 6) Sector 4307ff00279341 ┆C ' Aus frames. BANDWIDTH OH 1 The bandwidth allocated to each device ALLOCATION in the TDX system is determined by the MUX-table. This table is configured as shwon on OH 1 with 14 speed levels. (HBK, Section 8.2.2.1) Each time a frame is transmitt┆
0x43700…43800 (67, 0, 7) Sector 4208ff00279341 ┆B ' Aed on the lower bus, a device-address is read from the MUX-table in the location given by the "pointer to next ADD" and used as MUX-No. The "pointer to next ADD" is updated to the next "ADD", which is either the next in the chain or - in case it was┆
0x43800…43900 (67, 0, 8) Sector 4309ff00279341 ┆C ' Arms the frame EN/DE-capsulation and the error detection and correction on packet level. 4:1:2 A packet is one or more frames transferred page 3 between two devices. Any device which has received a packet must return ACK/NACK. Frames are received┆
0x43900…43a00 (67, 0, 9) Sector 430aff00279341 ┆C ' A errorfree from LEVEL 1 and accumulated into packets at LEVEL 2. The first and the last frame in a packet is indicated in the COMMUNICATION byte. The bytecount and the continous frame count is detected in the CONTROL BYTE (SEQ. NO. + NO. OF DATA BYT┆
0x43a00…43b00 (67, 0, 10) Sector 430b7700279341 ┆C w ' AES). Any errors detected results in rejection of the packet and request for a retransmission by returning NACK. 2793A/rt MT/RST 840620 TDX SYST┆
0x43b00…43c00 (67, 0, 11) Sector 430cff00279341 ┆C ' A 1 2793A/rt MT/RST 4:1:3 840620 TDX TRANSMISSION ┆
0x43c00…43d00 (67, 0, 12) Sector 430dff00279341 ┆C ' A L 2 1 LEVEL 3 At LEVEL 3, the ingoing packets are routed through VIRTUAL CHANNELS to the applicati┆
0x43d00…43e00 (67, 0, 13) Sector 430eff00279341 ┆C ' Aon routines in LTUX-S and the TDX HANDLER in the HOST INTERFACE (STI). CHANNELS 4:1:2 A VIRTUAL CHANNEL for a LTUX-S (10 channels) OH 4 is identified in the DATA TYPE byte (4 bits) of the frame. A VIRTUAL for a HOST I/F is a combination of the ┆
0x43e00…43f00 (67, 0, 14) Sector 430fff00279341 ┆C ' ADATA TYPE and DEV. NO. (12 bits = 4096 channels). VIRTUAL channel 0 and 1 are used entirely for datagram messages such as diagnostics and commands to OPEN and CLOSE channels. An OPEN channel is a channel with information at LEVEL 3 about the R┆
0x43f00…44000 (67, 0, 15) Sector 4300ff00279341 ┆C ' AEMOTE CHANNEL (= CR ID). Transfer of data can take place between any two channels when opened. The TDX handler opens and closes (creates and dismantles loglines) the channels through which datastreams may flow. Such is performed at LEVEL 3. ┆
0x44000…44100 (68, 0, 0) Sector 44018300279341 ┆D ' A A device allocated a higher bandwidth on the bus is represented more frequently in the table than lower bandwidth devices. ^ ^ ^ ^ 1 ^ DATAGRAM to TDX CONTROLLER ^ ^ ^ ┆
0x44100…44200 (68, 0, 1) Sector 4402ff00279341 ┆D ' A 1 2793A/rt MT/RST 4:1:3 840620 TDX TRANSMISSION ┆
0x44200…44300 (68, 0, 2) Sector 4403ff00279341 ┆D ' A L 1 1 PROTOCOL Black 3 Protocol Levels: board 1: Physical level - Frame level ┆
0x44300…44400 (68, 0, 3) Sector 4404ff00279341 ┆D ' A All TDX 2: Link level - Packet level DEVICES 3: Network level - LDU level (only via HOST) APPLICATION level (LTUX-S) (LDU = LOGICAL DATA UNIT (HBK,section 8.2.2)) LEVEL 1 Transmission of fram┆
0x44400…44500 (68, 0, 4) Sector 4405ff00279341 ┆D ' Aes between TDX DEVICES: - The FRONT END part of a TDX DEVICE performs (for each frame): Bit stuffing, CRC byte generation, ABORT and FLAG byte insertion, parallel/serial conversion, and SPL-D coding. - Bus drivers transmit on UPPER BUS. - Bus┆
0x44500…44600 (68, 0, 5) Sector 4406ff00279341 ┆D ' A receivers on the TDX CONTROLLER then transfer the frame to the MPCC which, decodes SPL-D, converts serial/parallel, removes ABORT and FLAG, deletes bit (stuffing), checks CRC, reads DEV. NO., and inserts MUX. NO., bitstuffing, CRC byte, flags, par.┆
0x44600…44700 (68, 0, 6) Sector 4407ff00279341 ┆D ' A/ser. conv., SPL-D coding with internal clock. - Bus drivers transmit on lower bus. - The TDX DEVICES receive and perform SPL-D decoding, ser./par. conversion, bitstuff deletions, flags removal, CRC check, reads MUX. NO. and DEV. NO. The DEVICE ┆
0x44700…44800 (68, 0, 7) Sector 4308ff00279341 ┆C ' Awhich recognizes the MUX. NO. is allowed to transmit on upper bus. The DEVICE which recogn. DEV. NO. transfers the frame to the link level. LEVEL 2 Transferred data packets are chopped into HDLC frames. The firmware in the TDX DEVICE perfo┆
0x44800…44900 (68, 0, 8) Sector 4409ff00279341 ┆D ' A ^ ^ACK/NACK ^ ^FRAME NO ^[[=NO BYTES^ ^ + ^ ^IN PACKET^[1-1[ HEX ^ ^FLOW CONTROL ^ ^ BYTES ^(RETURN TO ^=1-16 DEC ^ ^SENDER ^"PIGGY-BACK") ^1 x 01 ^=FIRST FRAME IN PACKET ^1 x 10 ^=LAST FRAME ^1 x 1┆
0x44900…44a00 (68, 0, 9) Sector 440a6300279341 ┆D c ' A1 ^=FIRST and LAST (only ^ ^ one) ^x 1 xx ^=BETWEEN FIRST and LAST FRAME 2793A/rt MT/RST 4:1:1 840620 TDX SYSTEM STRUCTURE ┆
0x44a00…44b00 (68, 0, 10) Sector 440bff00279341 ┆D ' A 1 2793A/rt MT/RST 840620 TDX SYST┆
0x44b00…44c00 (68, 0, 11) Sector 440cff00279341 ┆D ' AEM THEORY L 4 1 UPPER BUS OH3 & 4 ABORT BYTE: Dummy byte, No. MUX NO. in upper bus f┆
0x44c00…44d00 (68, 0, 12) Sector 440dff00279341 ┆D ' Arames because all the frames are to the TDX CTRL, and the MUX.NO. is generated in the TDX CTRL. The rest of the frame is equal to the lower bus frame format. COMMUNICA- ONE CYCLE: The TDX CTRL outputs a frame on the LOWER TION bus. MUX.NO. ind┆
0x44d00…44e00 (68, 0, 13) Sector 440eff00279341 ┆D ' Aicates the device, which is allowed to transmit on the upper bus. All devices "look" at the MUX.NO. and the CR-ID. The device which recognizes its addr. in the HOST/MODE or DEV. NO. fetches the frame. Only the TDX CTRL receives the frame on the up┆
0x44e00…44f00 (68, 0, 14) Sector 440fff00279341 ┆D ' Aper bus. If the HOST/MODE is [ the controller fetches the frame (This might be a request for change of bandwidth from a device) and transmits a dummy frame on the lower bus (f.ex. diagnostic frame). Change of BANDWIDTH is not used in CAMPS. Wh┆
0x44f00…45000 (68, 0, 15) Sector 4400ff00279341 ┆D ' Aenever the frame is not destined for the TDX CTRL, a MUX.NO. is inserted and the frame is - without any further change - transmitted on the lower bus in the next time slot. DEVICE The MUX.NO. is fetched from the MUX.table in POLLING the TDX CTRL.┆
0x45000…45100 (69, 0, 0) Sector 4501ff00279341 ┆E ' ATION ^ Board ^CHANNEL NO. ^ ^ ^ [ ^ DATAGRAM between LTUX-s and STI^ ^ ^ ^ ^ 1 ^ DATAGRAM to TDX CONTROLLER ^ ^ ^ ┆
0x45100…45200 (69, 0, 1) Sector 4502ff00279341 ┆E ' A ^ ^ 2-5 ^ 4 physical SERIAL I/O CHANNELS ^ ^ ^ ^ ^ 6-9 ^ Not used in CAMPS ^ ^ ^ ^ 1 ┆
0x45200…45300 (69, 0, 2) Sector 4503b800279341 ┆E 8 ' A HOST/MODE & DEVICE NO.: Describing the SOURCE and DESTINATION DEVICES - for the actual FRAME of DATA. LOWER BUS. MUX.TABLE OH1 The MUX. TABLE on the TDX CONTROLLER is a DE┆
0x45300…45400 (69, 0, 3) Sector 4504ff00279341 ┆E ' A 1 2793A/rt MT/RST 4:1:2 840620 TDX SY┆
0x45400…45500 (69, 0, 4) Sector 4505ff00279341 ┆E ' ASTEM THEORY L 4 1 COMMUNICATION BYTE: Used for information in a packet transmissio┆
0x45500…45600 (69, 0, 5) Sector 4506ff00279341 ┆E ' An (Packet=one or more frames between two open (logical) channels) f.ex. First/last frame in a packet. CONTROL BYTE: Frame sequence no. + no. of data bytes in frame FRAME SEQ.NO.: In a packet transmission the frames are sequentially numbered (s┆
0x45600…45700 (69, 0, 6) Sector 4507ff00279341 ┆E ' Aeq.no.). If the receiving device detects a jump in seq.no.s, the frame is discarded and retransmission is requested. NO. OF DATA BYTES: The actual number of data bytes (max.16) in this frame. 1 ┆
0x45700…45800 (69, 0, 7) Sector 4408ff00279341 ┆D ' A Black PART OF ^ COMMUNICATION BYTE ^ FRAME ^ NUMBER OF ^ Board FRAME: ^ MSB ^ LSB ^ SEQ.NO. ^ DATABYTES ^ ^ ^ ^ ^ ^ ^ S^S^S^S ^ S^S^S^S ^ Z^Z^Z ^ W^W^W^W^W ^ ^ ^ ^ ^ ┆
0x45800…45900 (69, 0, 8) Sector 4509ff00279341 ┆E ' Ao 236 bits (max) due to "bitstuffing" (or each five "1"'s an extra "0" is inserted). This is used as an error detection feature. One HDLC frame contains a total of 25 bytes of 8 bits: 2 Flag bytes (01111110) 5 communication control bytes 16┆
0x45900…45a00 (69, 0, 9) Sector 450a3b00279341 ┆E ; ' A data bytes 2 CRC bytes (Cyclic Redundancy Check) 2793A/rt MT/RST 4:1:1 840620 TDX SYSTEM STRUCTURE ┆
0x45a00…45b00 (69, 0, 10) Sector 450bff00279341 ┆E ' A 1 skal der ikke v`re en side 1? 2793A/rt MT/RST 4:1:2 840620 TDX SYST┆
0x45b00…45c00 (69, 0, 11) Sector 450cff00279341 ┆E ' AEM THEORY L 2 1 LOWER BUS OH2 & 4 START Flag (1 byte) FRAME FORMAT MUX.NO. (┆
0x45c00…45d00 (69, 0, 12) Sector 450dff00279341 ┆E ' A1 byte): The MUX.NO. is a DEVICE NO., which is generated in the controller - it is taken from the MUX.TABLE. It indicates which device is allowed to transmit data on the upper bus in the next timeslot. All devices "look" at the MUX.NO., and the DEVI┆
0x45d00…45e00 (69, 0, 13) Sector 450eff00279341 ┆E ' ACE which recognizes its own NO. (= device addr.) starts the transmission on the upper bus, when having received bit 241 of the present timeslot: CR-ID (Channel & Routing Identifier) 2 bytes concerning DATA TYPE, HOST/MODE, and DEVICE NO as fol┆
0x45e00…45f00 (69, 0, 14) Sector 450fff00279341 ┆E ' Alows. DATA TYPE: Identifying virtual channel NO. through which the data must be routed. It does not necessarily correlate with f.ex. the (four) physical channels in a LTUX. It merely points to a specific application. Each LTUX-S MODULE is a┆
0x45f00…46000 (69, 0, 15) Sector 4500ff00279341 ┆E ' Able to separate 10 VIRTUAL CHANNELS as follows: 1 ^ ^ ^ Black ^VIRTUAL ^ FUNC┆
0x46000…46100 (70, 0, 0) Sector 4601ff00279341 ┆F ' A 1 2793A/rt MT/RST 4:1:2 840620 TDX DATA COMMUNICATION ┆
0x46100…46200 (70, 0, 1) Sector 4602ff00279341 ┆F ' A L 1 1 TDX BUSSES OH1 Each TDX BUS consists of an UPPER BUS (TWISTED PAIR CABLE) and a LOWER BUS (T┆
0x46200…46300 (70, 0, 2) Sector 4603ff00279341 ┆F ' AWISTED PAIR CABLE). The STI/TIA and LTUX-S MODULES transmit on the UPPER BUS and receive from the LOWER BUS. The TDX CONTROLLER receives from UPPER BUS and transmits on the LOWER BUS. MUX.TABLE OH1 The MUX. TABLE on the TDX CONTROLLER is a DE┆
0x46300…46400 (70, 0, 3) Sector 4604ff00279341 ┆F ' AVICE POLLING TABLE, the contents of which are the DEVICE NO.'s of the TDX SYSTEM. By the POLLING SEQUENCE these DEVICE NO.s (named MUX.NO.s) in the row they are set up will represent, which LTUX-S or STI/TIA is allowed to transmit DATA. MASTER OH┆
0x46400…46500 (70, 0, 4) Sector 4605ff00279341 ┆F ' A1 The TDX CONTROLLER contains the MASTER CLOCK CLOCK GENERATOR of the TDX SYSTEM. The frequency is 1.8432 MHZ. SYNCHRONIZATION FROM CONTROLLER: Contineous data stream on lower bus: 1.8432 Mbits/sec divided into 6400 timeslots of 288 bits. ┆
0x46500…46600 (70, 0, 5) Sector 46062b00279341 ┆F + ' ABlack One Timeslot: Board BSM-X MODULE is a BUS SWITCHING MODULE MODULE and a MONITORING MODULE. TDX UNITS OH 3 Max. 15 TDX UNITS (TU) per. TDX SYSTEM. (TDX UNIT = TDX CRATE) The BSM-X MODULE is the "HEAD GATE" of the TU (BSM-X MODUL┆
0x46600…46700 (70, 0, 6) Sector 4607ff00279341 ┆F ' A 1 2793A/rt MT/RST 4:1:2 840620 TDX DATA COMMUNICATION ┆
0x46700…46800 (70, 0, 7) Sector 4508ff00279341 ┆E ' A L 2 1 HDLC FRAME The HDLC (High Level Date Link Control) frame length may differ from 200 bits (min) t┆
0x46800…46900 (70, 0, 8) Sector 46092c00279341 ┆F , ' Ahich is located in the REAR MAGAZINE. 2793A/aml ANSWERS TO PROGRESS TEST WEEK 4 830928 1 of 1 LESSON: 4:5:1-3 ┆
0x46900…46a00 (70, 0, 9) Sector 460aff00279341 ┆F ' A 1 2793A/rt MT/RST 4:1:1 840620 TDX SYSTEM STRUCTURE ┆
0x46a00…46b00 (70, 0, 10) Sector 460bff00279341 ┆F ' A L 2 1 TSP The TEMPERATURE SENSOR (ADAPTOR) PANEL is located in the REAR MAGAZINE. POWER OH 3 The P┆
0x46b00…46c00 (70, 0, 11) Sector 460cff00279341 ┆F ' AS in the FRONT MAGAZINE is used for the SUPPLIES POWER to the TDX CONTROLLER, BSM-X MODULE, and LTUX-S MODULE(s). OH 3-4 The PS in the REAR MAGAZINE is used for the POWER to the LOW LEVEL ADAPTORS and OPTIC FIBER MODEM located in the FRONT MAGAZ┆
0x46c00…46d00 (70, 0, 12) Sector 460dff00279341 ┆F ' AINE. DEVICE NO. 3 Each TDX DEVICE has a unique DEVICE ADDRESS (DEVICE ADDR.) (Device No.) in the TDX SYSTEM as follows: 1 ┆
0x46d00…46e00 (70, 0, 13) Sector 460eff00279341 ┆F ' ABlack ^ TDX DEVICE ^ ADDR.AREA ^ Board ^ ^ (HEX. NO.s) ^ ^ TDX CONTROLLER ^ [[ ^ ^ ^ ^ ^ STI/(TIA) ^ [1 - [C ^ ^ ^ ^ ^ ┆
0x46e00…46f00 (70, 0, 14) Sector 460fff00279341 ┆F ' A LTUX-S ^ [D - FE ^ ^ ^ ^ ^ DUMMY ^ FF ^ ^ ^ ^ OH 5-7 The DEVICE ADDRESSES (DEVICE NO.s) used in the CAMPS are shown (DECIMAL & HEXADECIMAL) fo┆
0x46f00…47000 (70, 0, 15) Sector 46002a00279341 ┆F * ' Ar the LTUX-S modules in TU NO. 1-9. CAMPS 1 - Isolate and remedy TDX system faults at module level - During evaluation of the troubleshooting T┆
0x47000…47100 (71, 0, 0) Sector 47014000279341 ┆G @ ' Araining room GW, DI, EX Training System nected to the TDX SYSTEM? 3. When does a TDX DEVICE transmit? 4. How can you get information about the TDX system status? Does this action disturb the normal function? 5. What┆
0x47100…47200 (71, 0, 1) Sector 4702ff00279341 ┆G ' A 1 2793A/rt MT/RST 4:1:1 840620 TDX SYSTEM STRUCTURE ┆
0x47200…47300 (71, 0, 2) Sector 4703ff00279341 ┆G ' AL 1 1 General TDX: Telecommunication Data Exchange A unique element of the CAMPS is the TDX SYSTEM. In┆
0x47300…47400 (71, 0, 3) Sector 4704ff00279341 ┆G ' A essence, the TDX SYSTEM handles nearly entire complex of terminals and communication lines with a minimum attention by the central processor in increased processor throughput. The TDX SYSTEM as a hole is a STAND ALONE SYSTEM taking care of the da┆
0x47400…47500 (71, 0, 4) Sector 4705ff00279341 ┆G ' Ata communication between the MAIN MEMORY of the CR80 and the USER/OPERATOR POSITIONS (PERIPHERALS). STRUCTURE and OH1-2 STB I, Section 5. PERFORMANCE DEVICES OH1-2 TDX DEVICES: - TDX CONTROLLER (1 per. TDX BUS) - STI/TIA (1 per. PU) - LTUX-┆
0x47500…47600 (71, 0, 5) Sector 4706ff00279341 ┆G ' AS (max. 2 per TU) BUS SWITCH OH1 The BSM-X MODULE is a BUS SWITCHING MODULE MODULE and a MONITORING MODULE. TDX UNITS OH 3 Max. 15 TDX UNITS (TU) per. TDX SYSTEM. (TDX UNIT = TDX CRATE) The BSM-X MODULE is the "HEAD GATE" of the TU (BSM-X MODUL┆
0x47600…47700 (71, 0, 6) Sector 4707ff00279341 ┆G ' AE NO.). TDX CONTROLLER One TDX CONTROLLER is asssigned to TDX BUS # LOCATION 1; the other TDX CONTROLLER is assigned to TDX Bus # 2. The two TDX CONTROLLERS are located in TV # 1 and TU # 4 respectively. ADAPTORS OH3 4 serial V24 I/O CHANNELS p┆
0x47700…47800 (71, 0, 7) Sector 4608ff00279341 ┆F ' Aer. LTUX-S. LOW LEVEL ADAPTORS and OPTIC FIBER MODEM for the I/O CHANNELS ARE located in OH4 the FRONT MAGAZINE or BP8 BACK PANELS are located in the REAR MAGAZINE. BSM-X Connections to the two TDX BUSSES and the CCB PANEL via the BSM-X PANEL, w┆
0x47800…47900 (71, 0, 8) Sector 4709ff00279341 ┆G ' A 1 2793A/aml ANSWERS TO PROGRESS TEST WEEK 4 830928 1 of 1 LESSON: 4:5:1-3 ┆
0x47900…47a00 (71, 0, 9) Sector 470aff00279341 ┆G ' A CAMPS 1 1. 2. 2. WATCH DOG is connected by the CCB BUS to BSMX-S. 3. When MUX NO. on LOWER BUS hit DEVICE N┆
0x47a00…47b00 (71, 0, 10) Sector 470bff00279341 ┆G ' AO. 4. Connect a VDU set to 30 Baud to TDX CONTROLLER and type S and CR. No. 5. 1 2 2 LTUX-S No. in TDX CRATE CHANNEL No. of LTUX-S. 6. Yes. 7. Through STI/TIA module. 8. IO m┆
0x47b00…47c00 (71, 0, 11) Sector 470cff00279341 ┆G ' Aodule in PU CRATE, which is the STI module. 9. By doing loop test. A loop is mounted on the OPTO MODEM. 10. TDX CONTROLLER. 11. 1.8432 MHz. 12. It connects the device to TDX BUS. 13. The twisted pair are terminated by 100 ohm. 14. A┆
0x47c00…47d00 (71, 0, 12) Sector 470dff00279341 ┆G ' After 16 scan of MUX TABLE, 3 scan sending out test frame and then if no respons the DEVICE is skiped on the MUX TABLE. 15. No, from DEVICE. 16. Two sets of twisted pair, each pair shieldet. 17. The DEVICE is asked to retransmit. 18. I┆
0x47d00…47e00 (71, 0, 13) Sector 470e6f00279341 ┆G o ' At indicates the start of a FRAME. 19. 4. 20. No. There is only 2 TDX CONTROLLERs, one per TDX BUS. CK - M&D TEST FLOPPY DISKETTES - SLM: Section 4.7.2.1.8, 4.7.2.2 - 4:1:1:OH5-7 TDX CRATES┆
0x47e00…47f00 (71, 0, 14) Sector 470fff00279341 ┆G ' A 1 2793A/rt 840620 TROUBLESHO┆
0x47f00…48000 (71, 0, 15) Sector 4700ff00279341 ┆G ' AOTING 4:5:4-6 3 x 45 CAMPS 1 - Isolate and remedy TDX system faults at module level - During evaluation of the troubleshooting T┆
0x48000…48100 (72, 0, 0) Sector 4801ff00279341 ┆H ' Ae located in a TDX CRATE? 2. How is the WATCH DOG connected to the TDX SYSTEM? 3. When does a TDX DEVICE transmit? 4. How can you get information about the TDX system status? Does this action disturb the normal function? 5. What┆
0x48100…48200 (72, 0, 1) Sector 4802ff00279341 ┆H ' A does the number 122 in the command DO TDX VDU IO122 refer to? 6. Can you exchange TDX CONTROLLERS without changing anything else? 7. How is the TDX SYSTEM connected to the PROCESSOR? 8. What is the 5th line in the UMO indicating? ┆
0x48200…48300 (72, 0, 2) Sector 48034f00279341 ┆H O ' A 9. How can you check that an OPTO MODEM is functioning correctly? scribed in SLG 7:1:4-6 Classroom L 12 OHs Black board SLM: Section 4.5.4 840620 TDX HOST I┆
0x48300…48400 (72, 0, 3) Sector 4804ff00279341 ┆H ' A 1 2793A/aml 4:5:1-3 830928 2 of 2 PROGRESS TEST WEEK 4 ┆
0x48400…48500 (72, 0, 4) Sector 4805ff00279341 ┆H ' A CAMPS 1 10. Which TDX DEVICE transmits on the LOWER BUS? 11. What is the BITRATE of the signal on the TDX BU┆
0x48500…48600 (72, 0, 5) Sector 4806ff00279341 ┆H ' ASSES? 12. What is the function of the WALL OUTLET? 13. What is done to the TDX BUS to prevent reflection? 14. What happens if a DEVICE does not respond to its MUX NO.? 15. Does the WALL OUTLET get power from the TDX BUS? 16. W┆
0x48600…48700 (72, 0, 6) Sector 4807ff00279341 ┆H ' Ahat is the physical structure of a TDX BUS? 17. What happens if a DEVICE makes a transmission error? 18. What is the purpose of the FLAG in TDX FRAME? 19. How many OPTO MODEMS can be connected to an ADAPTOR POWER SUPPLY? 20. Is th┆
0x48700…48800 (72, 0, 7) Sector 47083200279341 ┆G 2 ' Aere a TDX CONTROLLER in every TDX CRATE? 2793A/rt 840620 PROGRES┆
0x48800…48900 (72, 0, 8) Sector 4809ff00279341 ┆H ' AS TEST 4:5:1-3 3x45 CAMPS 1 Evaluate his own comprehension of subjects taught in this week. The result of this test will be recorded in the "STU┆
0x48900…48a00 (72, 0, 9) Sector 480ad800279341 ┆H X ' ADENT's PROGRESS REPORT". Correction of answers Classroom Progress test, duration 60 min. Progress test, 4 pages (OH1-4, a copy for each student). 6 OHs STBI, II & III SLM PACK and M&D TEST FLOPPY - DISKETTES ┆
0x48a00…48b00 (72, 0, 10) Sector 480bff00279341 ┆H ' A 1 2793A/rt 840620 M&D TDX┆
0x48b00…48c00 (72, 0, 11) Sector 480cff00279341 ┆H ' A SYSTEM TEST 4:5:4-6 3x45 CAMPS 1 - Fullfill an ERROR FREE "TDX VDU I/O TEST" (See OBJECTIVES, SLG 4:5:4-6: page 1). ┆
0x48c00…48d00 (72, 0, 12) Sector 480dff00279341 ┆H ' A - During practical exercise. - During evaluation of the exercise. - The students must have performed all exercises. Training room GW, DI, EX -┆
0x48d00…48e00 (72, 0, 13) Sector 480ef000279341 ┆H p ' A SLG 4:5:4-6 (2 pages) - Training system with VDUs connected to both of the MIAs - M&D TEST DISK PACK - M&D TEST FLOPPY DISKETTES - SLM: Section 4.7.2.1.8, 4.7.2.2 - 4:1:1:OH5-7 TDX CRATES┆
0x48e00…48f00 (72, 0, 14) Sector 480fff00279341 ┆H ' A 1 - 2793A/aml 4:5:1-3 830928 1 of 2 PROGRESS TEST WEEK 4 ┆
0x48f00…49000 (72, 0, 15) Sector 4800ff00279341 ┆H ' A CAMPS 1 NAME: SCORE: 1. How many LTUX-S DEVICES can b┆
0x49000…49100 (73, 0, 0) Sector 4901ff00279341 ┆I ' A 1 2793A/rt 840620 CCA FUNCTIO┆
0x49100…49200 (73, 0, 1) Sector 4902ff00279341 ┆I ' ANS OF THE BSM-X 4:4:3 45 CAMPS 1 - Describe the CCB communication principles - Recognize the CCA functions of the BSM-X Evaluation at exercises┆
0x49200…49300 (73, 0, 2) Sector 4903b700279341 ┆I 7 ' A in Lesson 7:1:4-6 - The students must perform the exercise No. 2, described in SLG 7:1:4-6 Classroom L 12 OHs Black board SLM: Section 4.5.4 840620 TDX HOST I┆
0x49300…49400 (73, 0, 3) Sector 4904ff00279341 ┆I ' A 1 2793A/rt 840620 M&D TDX SY┆
0x49400…49500 (73, 0, 4) Sector 4905ff00279341 ┆I ' ASTEM TEST 4:4:4-6 3x45 CAMPS 1 - Fullfill an ERROR FREE "TDX LTUX TEST" (See OBJECTIVES, SLG 4:4:4-6: page 1). - Fullfill an ERROR FREE "TDX LOOP TE┆
0x49500…49600 (73, 0, 5) Sector 4906ff00279341 ┆I ' AST" (See OBJECTIVES, SLG 4:4:4-6: page 2) - During practical exercise. - During evaluation of the exercise. - The students must have performed all exercises. Training room GW, DI, EX - Traini┆
0x49600…49700 (73, 0, 6) Sector 4907dc00279341 ┆I \ ' Ang system with VDUs connected to both of the MIAs - M&D TEST DISK PACK & - LOOP BACK CONNECTOR FOR V24 L/L ADAPTOR & OPTO - T/R - SLG 4:4:4-6 (2 pages) - SLM: Section 4.7.2.1.8, 4.7.2.2 - 4:1:1:OH5-7 M&D TDX┆
0x49700…49800 (73, 0, 7) Sector 4808ff00279341 ┆H ' A 1 2793A/rt 840620 PROGRES┆
0x49800…49900 (73, 0, 8) Sector 4909ff00279341 ┆I ' AATUS TEST" (See OBJECTIVES, SLG 4:3:4-6: page 2) - During practical exercise. - During evaluation of the exercise. - The students must have performed all exercises. Training room GW, DI, EX -┆
0x49900…49a00 (73, 0, 9) Sector 490ad000279341 ┆I P ' A SLG 4:3:4-6 (2 pages) - Training system with VDUs connected to both of the MIAs - M&D TEST DISK PACK - M&D TEST FLOPPY DISKETTES - SLM: Section 4.7.2.1.8, 4.7.2.2 & 4.7.2.2. - 4:1:1:OH5-7 EST DISK PACK and M&D TEST FLOPPY - DISKETTES ┆
0x49a00…49b00 (73, 0, 10) Sector 490bff00279341 ┆I ' A 1 2793A/rt 840620 POWER ┆
0x49b00…49c00 (73, 0, 11) Sector 490cff00279341 ┆I ' ASUPPLIES, BP8 & TSP 4:4:1 45 CAMPS 1 Describe the TDX power supplies and the power distribution in the TDX crate Describe the BP8 (Back Panel type 8) f┆
0x49c00…49d00 (73, 0, 12) Sector 490ddb00279341 ┆I [ ' Aunctions Describe the TSP (Temperature Sensor Panel) No format check Current questions Classroom L Black board, 2 OHs -SLM: Section 4.5.4 & 4.5.5 -STB II: Section 26 & 29 State the front panel LEDs State th┆
0x49d00…49e00 (73, 0, 13) Sector 490eff00279341 ┆I ' A 1 2793A/rt 840620 TDX CRATES┆
0x49e00…49f00 (73, 0, 14) Sector 490fff00279341 ┆I ' A, WALL OUTLETS 4:4:2 45 CAMPS 1 - Describe the TDX Crate functions - Describe the TDX CABLES - Describe all cable connections and the module positionin┆
0x49f00…4a000 (73, 0, 15) Sector 4900cc00279341 ┆I L ' Ag in the TTX crates - Describe the WALL OUTLET functions No formal check Current questions Classroom L Black board, 8 OH's SLM: Section 4.5.4 HWB: Section 3 LT┆
0x4a000…4a100 (74, 0, 0) Sector 4a01ff00279341 ┆J ' AUX-S 4:3:2 45 CAMPS 1 State the MODULE LOCATION Describe the performance Recognize the block diagram State the front panel LEDs State the┆
0x4a100…4a200 (74, 0, 1) Sector 4a02ff00279341 ┆J ' A function of the front panel switches State the front panel connections State the back plane connections Perform the MODULE SET UP Describe the BIT. Evaluation at the lab. exercises in lesson 4:3:4-6. Revision at progress test, question ┆
0x4a200…4a300 (74, 0, 2) Sector 4a034b00279341 ┆J K ' A10 Classroom L 5 OHs STB II: Section 22 2793A/rt 840620 TDX HOST I┆
0x4a300…4a400 (74, 0, 3) Sector 4a04ff00279341 ┆J ' A 1 2793A/rt 840620 L/L ADA┆
0x4a400…4a500 (74, 0, 4) Sector 4a05ff00279341 ┆J ' APTORS & OPTO T/R 4:3:3 45 CAMPS 1 Describe the L/L ADAPTORS & OPTO T/R - Performance - Main functions - Applications State the front panel LEDs ┆
0x4a500…4a600 (74, 0, 5) Sector 4a06cc00279341 ┆J L ' A Evaluation at the lab. exercises in lesson 4:4:4-6 & 4:5.4-6 Revision at progress test, question 13 & 14 Classroom L 5 OHs -LESSON 6:3:1-2 -SLM: Section 4.5.5 TDX DATA C┆
0x4a600…4a700 (74, 0, 6) Sector 4a07ff00279341 ┆J ' A 1 2793A/rt 840620 M&D TDX┆
0x4a700…4a800 (74, 0, 7) Sector 4908ff00279341 ┆I ' A SYSTEM TEST 4:3:4-6 3x45 CAMPS 1 - Fullfill an ERROR FREE "TDX BUS TEST" (See OBJECTIVES, SLG 4:3:4-6: page 1). - Fullfill an ERROR FREE "LTUX-S ST┆
0x4a800…4a900 (74, 0, 8) Sector 4a09ff00279341 ┆J ' A - Perform the M&D TEST "BOOT UP PROCEDURES (See OBJECTIVES, SLG 4:2:4-6: page 2) - Fullfill an ERROR FREE "STI TEST" (See OBJECTIVES, SCG 4:2:4-6: page 4) - During practical exercise. - During evaluation of the┆
0x4a900…4aa00 (74, 0, 9) Sector 4a0aff00279341 ┆J ' A exercise. - The students must have performed all exercises. Training room GW, DI, EX - Training system with VDUs connected to both of the MIAs - TDX CONTROLLER CABLE - M&D TEST DISK PACK and M&D TEST FLOPPY - DISKETTES ┆
0x4aa00…4ab00 (74, 0, 10) Sector 4a0b6000279341 ┆J ` ' A - SLG 4:2:4-6 (4 pages) - SLM: Section 4.3.3.4, 4.7.2.1.8 & 4.7.2.2. - 4:1:1:OH5-7 : Section 6 -! <6 C{-! <6 M1' Z -C7-:!<~ B -!/=6'C*-:!<~ B%-!/=6WC*-!/=6)M2&*/=MM, > I!e=6 !Z="(=e*$<kas#r 9x2"<! <6 M8)I:^=~ B#.!#<6 ! <6 M&&:!<~ J#.:!<2.=M2┆
0x4ab00…4ac00 (74, 0, 11) Sector 4a0cff00279341 ┆J ' A 1 2793A/rt 840620 BS┆
0x4ac00…4ad00 (74, 0, 12) Sector 4a0dff00279341 ┆J ' AM-X 4:3:1 45 CAMPS 1 State the MODULE LOCATION Describe the performance Recognize the block diagram State the front panel LEDs State th┆
0x4ad00…4ae00 (74, 0, 13) Sector 4a0eff00279341 ┆J ' Ae function of the front panel switches State the front panel connections State the back plane connections Perform the MODULE SET UP Evaluation at the lab. exercises in lesson 4:3:4-6 & 4:4:4-6 Revision at progress test, question 10 ┆
0x4ae00…4af00 (74, 0, 14) Sector 4a0f4200279341 ┆J B ' A Classroom L 6 OHs STB II: Section 21 2793A/rt 840620 TDX CONTRO┆
0x4af00…4b000 (74, 0, 15) Sector 4a00ff00279341 ┆J ' A 1 2793A/rt 840620 LT┆
0x4b000…4b100 (75, 0, 0) Sector 4b01ff00279341 ┆K ' A State the front panel connections State the back panel connections Perform the MODULE SET UP Describe the BIT Evaluation at the lab. exercises in lesson 4:2:4-6 (TDX SYSTEM STATUS TEST) Revision at pr┆
0x4b100…4b200 (75, 0, 1) Sector 4b026a00279341 ┆K j ' Aogress test question 8 & 9. Classroom L 7 OHs STB II: Section 20 Mj ~ B 4:g=~ J 4Cq5M")IMy,M1' R 4 'M, CV4:g=~ Bg4M73~ B)4Cq5! ="(=*(=N#FMC 2.=M ':>=V V u:A=!>= AH1 R^4 ]M, C 4:>=2A=Ms!:g=~ Jr4Mj2:g=~ B}4C75! ┆
0x4b200…4b300 (75, 0, 2) Sector 4b03ff00279341 ┆K ' A 1 2793A/rt 840620 TDX HOST I┆
0x4b300…4b400 (75, 0, 3) Sector 4b04ff00279341 ┆K ' A/F (STI/TIA) 4:2:3 45 CAMPS 1 State the Location of the MODULES Describe the performance of the MODULES Recognize the block diagrams State the front┆
0x4b400…4b500 (75, 0, 4) Sector 4b05ff00279341 ┆K ' A panel LEDs State the function of the front panel switches State the front panel connections State the back plane connections Perform the MODULE SET UP Describe the BIT Evaluation at the lab. exercises in lesson 4:2:4-6 (STI TEST) Revi┆
0x4b500…4b600 (75, 0, 5) Sector 4b067a00279341 ┆K z ' Asion at progress test, question 11 & 12. Classroom L 11 OHs STB II: Section 18 & 19 2793A/rt 840620 TDX DATA C┆
0x4b600…4b700 (75, 0, 6) Sector 4b07ff00279341 ┆K ' A 1 2793A/rt 840620 TDX SYSTEM S┆
0x4b700…4b800 (75, 0, 7) Sector 4a08ff00279341 ┆J ' ATATUS TEST, 4:2:4-6 3x45 CAMPS BOOT UP PROCEED. & STI TEST 1 - Fullfill an ERROR FREE "TDX SYSTEM STATUS TEST" (See OBJECTIVES, SLG 4:2:4-6: page 1) ┆
0x4b800…4b900 (75, 0, 8) Sector 4b09ff00279341 ┆K ' A 1 2793A/rt 840620 TDX TRANSM┆
0x4b900…4ba00 (75, 0, 9) Sector 4b0aff00279341 ┆K ' AISSION 4:1:3 45 CAMPS 1 Recognize the 3 protocol levels Describe the SPL-D CODE FORMAT Revision of progress test, question 2 & 4 ┆
0x4ba00…4bb00 (75, 0, 10) Sector 4b0b6c00279341 ┆K l ' A Classroom L Blackboard, 2 OHs HBK: Section 8.2.2 & 8.3 STB I: Section 6 -! <6 C{-! <6 M1' Z -C7-:!<~ B -!/=6'C*-:!<~ B%-!/=6WC*-!/=6)M2&*/=MM, > I!e=6 !Z="(=e*$<kas#r 9x2"<! <6 M8)I:^=~ B#.!#<6 ! <6 M&&:!<~ J#.:!<2.=M2┆
0x4bb00…4bc00 (75, 0, 11) Sector 4b0cff00279341 ┆K ' A 1 2793A/rt 840620 DEMONSTRAT┆
0x4bc00…4bd00 (75, 0, 12) Sector 4b0dff00279341 ┆K ' AION OF THE 4:1:4-6 3x45 CAMPS TDX SYSTEM,SLM & HWB 1 Locate all TDX SYSTEM MODULES and POWER SUPPLIES. Find the TDX SYSTEM related sections in t┆
0x4bd00…4be00 (75, 0, 13) Sector 4b0edf00279341 ┆K _ ' Ahe SLM & HWB. Evaluation at lab. exercises during this week. Revision at progress test, question 3 Training room Classroom DE, I, DI Training System -4:1:1:OH 5-7 -SLM -HWB 840620 6 E '<M% ! "2<┆
0x4be00…4bf00 (75, 0, 14) Sector 4b0fff00279341 ┆K ' A 1 2793A/rt 840620 TDX CONTRO┆
0x4bf00…4c000 (75, 0, 15) Sector 4b00ff00279341 ┆K ' ALLER 4:2:1-2 2 x 45 CAMPS 1 State the MODULE Location Describe the performance Recognize the block diagram State the Front panel LEDs┆
0x4c000…4c100 (76, 0, 0) Sector 4c01ff00279341 ┆L ' A manual 2 840620 All Completely new update of the manual in accordance with CPS Log.No. 1434, ┆
0x4c100…4c200 (76, 0, 1) Sector 4c024300279341 ┆L C ' A 831021. RK4Cg4:^=~ BV4C75:g=~ Bf4 ZMo Ck4 KMo Mj ~ B 4:g=~ J 4Cq5M")IMy,M1' R 4 'M, CV4:g=~ Bg4M73~ B)4Cq5! ="(=*(=N#FMC 2.=M ':>=V V u:A=!>= AH1 R^4 ]M, C 4:>=2A=Ms!:g=~ Jr4Mj2:g=~ B}4C75! ┆
0x4c200…4c300 (76, 0, 2) Sector 4c03ff00279341 ┆L ' A 1 2793A/rt 840620 TDX SYSTEM┆
0x4c300…4c400 (76, 0, 3) Sector 4c04ff00279341 ┆L ' A STRUCTURE 4:1:1 45 CAMPS 1 Describe the TDX SYSTEM STRUCTURE: - TDX SYSTEM PERFORMANCE - TDX SYSTEM DEVICES (SHORT FORM) State the DEVICE NOs. ┆
0x4c400…4c500 (76, 0, 4) Sector 4c05c500279341 ┆L E ' A Evaluation of practice in Lesson 4:1:4-6. Revision at progress test, question 1,3,5 & 6 Classroom L Black board, 7 OHs STB I: Section 5 nu Allerede p> systemdiskette ┆
0x4c500…4c600 (76, 0, 5) Sector 4c06ff00279341 ┆L ' A 1 2793A/rt 840620 TDX DATA C┆
0x4c600…4c700 (76, 0, 6) Sector 4c07ff00279341 ┆L ' AOMMUNICATION 4:1:2 45 CAMPS 1 Describe the TDX DATA COMMUNICATION - UPPER BUS/LOWER BUS TRANSFER - DATA FRAME FORMAT - DEVICE POLLING Revision┆
0x4c700…4c800 (76, 0, 7) Sector 4b087500279341 ┆K u ' A at progress test, question 7 Classroom L Black board, 4 OHs HBK: Section 8.2.1 ┆
0x4c800…4c900 (76, 0, 8) WangDocumentHead {hdr=WangSectHead {next=(76,0, 9), len=0xff, h3=41279341}, f00=»2793A «, f01=»CPS/TMA/007 (R) (Week 4) «, f02=»rt «, f03=»NEN «, f04=»CPS Instructor's Man «, f05=21-09-82 14:28, f06=» 2 «, f07=»40 «, f08=» 6068 «, f09=23-10-84 13:44, f10=» «, f11=»03 «, f12=» 11 «, f13=18-10-84 11:49, f14=26-10-84 11:53, f15=»0248A «, f16=» 86 «, f17=» 54 «, f18=»18 «, f19=» 1548 «, f20=»139377 «, f21=» «, f22=» p «, f99=570010000110052710110180aaca1505000000000000004203a901df}
0x4c900…4ca00 (76, 0, 9) Sector 4c0a5600279341 ┆L V ' A= L L L L L L K K K K K J J J J I I I I I H H H G G G F F F E E D D C C B B A A A @ @ ? ? ? > > > = = < < < ; ; ; : : : : 9 9 8 8 8 8 8 8 7 7 7 7 6 6 5 5 5 5 5 4 4 4 3 3 3 3 2 2 ┆
0x4ca00…4cb00 (76, 0, 10) Sector 4c0b4f00279341 ┆L O ' A 1 :]=2#<:^=V V u:b=V V AH! Rv-! <6 C{-! <6 M1' Z -C7-:!<~ B -!/=6'C*-:!<~ B%-!/=6WC*-!/=6)M2&*/=MM, > I!e=6 !Z="(=e*$<kas#r 9x2"<! <6 M8)I:^=~ B#.!#<6 ! <6 M&&:!<~ J#.:!<2.=M2┆
0x4cb00…4cc00 (76, 0, 11) Sector 4c0c4f00279341 ┆L O ' A 1 ~ B[.Mr)Cp.:]=~ Bp.MP- Rm.> IM)-MI,:^=~ B~.> IMB'IM2& 9x2"<!Z="(=^#Vk"$<:]=2#<:^=~ J6.! <6 M8) R6.> I! <6 M8)I!h=6 ! =6 M")IM"):g=~ J /:h=2>=M?.Mj': < Zn.C / E*:=k 0wM% !;=4C┆
0x4cc00…4cd00 (76, 0, 12) Sector 4c0dff00279341 ┆L ' A 1 CAMPS Instructor's Manual for MT/RST Course, Week 4 CPS/TMA/007 CDRL Logistics Support No. 03A Line Item 8.2.4-B ┆
0x4cd00…4ce00 (76, 0, 13) Sector 4c0eeb00279341 ┆L k ' A Niels-Erik Nielsen Kurt Nybroe-Nielsen SHAPE (2), NEN, LT, ER[, ALG, Conf. Mgmt., LU ILS Train.Mgr. 840620 2 840620 Conf.Mgmt. 840620 6 E '<M% ! "2<┆
0x4ce00…4cf00 (76, 0, 14) Sector 4c0fff00279341 ┆L ' A 1 2793A/rt CPS/TMA/007 NEN/840620 ii CAMPS Instructor's Manual for MT/RST Course, Week No. 4 Issue 1 CAMPS 1 ┆
0x4cf00…4d000 (76, 0, 15) Sector 4c00ff00279341 ┆L ' A 821008 All Preliminary Issue of Document 1 830617 All Completely new update of ┆
