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HAWK TRAINING…02……02… HAWK
1 LT/821011
1
INTRODUCTION
HAWK
10/35 Welcome Instructor
N.N.
Classroom
Access to AMC
Lessons DI
Hours
Breaks coffee/lunch
Check-in routine
̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲
̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲
20/15 CRAS General 20 min
slide
show
(Lecture Room) slides
̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲
̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲
5/10 Objectives Student requirements
course objectives L
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̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲
10/0 Contents Lesson contents
Briefing on:
subjects L
tests
evaluation
̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲
̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲
Introduction 1 45 LT/821011
HAWK
Recognize the CR-Organization.
State the facilities of the course.
Describe the objectives of the course
Describe the contents of the course
No check performed
CAMPS classroom and lecture room
L
OH, slides
Training Plan
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HAWK TRAINING 2:1-3 LT/830228
CPU L/GW/DI HAWK
Page 1…0e…
GENERAL A CPU runs programs by continuously fetching
the next instruction from main memory and
executing it.
REQUIREMENTS 5 general requirements to be fulfilled:
1 A number of registers provided - holding
- pointer to program start - PROG
- pointer to next instruction - PRPC
- current instruction during decoding/execution
- working registers
- registers for programmer household
2 An operator - Arithmetic Logic Unit -
ALU
- to increment program counter
- to perform operations on data/addresses
3 A mainbus i/f for access to mainbus
- to read data from memory
- to write data to memory
- to transfer data to/from I/O modules
4 Internal busses connecting
- mainbus i/f
- registers
- operators
5 Controlling of the above mentioned items
executing the machine instructions.
Microprogrammed CPU:
- combinations of control signals are held
in words in a PROM
- sequencer: to sequence the addresses to
the PROM after decoding the instruction
GROUPWORKS Introduction and separation into groups. Time
consumption: 2 lessons
TASK DEFINITION What does the module do for the system?
How is this accomplished?
a) How is the input flow?
b) How is the output flow?
c) What outside (module) controls are needed?
d) What inside (module) controls are needed?
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CPU L/GW/DI HAWK
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RECOLLECTION Each group presents their results.
M̲a̲i̲n̲ ̲B̲u̲s̲ ̲I̲/̲F̲ M̲a̲i̲n̲ ̲B̲u̲s̲ ̲a̲n̲d̲ ̲T̲i̲m̲i̲n̲g̲ ̲C̲o̲n̲t̲r̲o̲l̲
C̲o̲n̲t̲r̲o̲l̲ ̲c̲o̲n̲n̲e̲c̲t̲i̲o̲n̲s̲: Bus-request, Bus granted
M̲a̲i̲n̲b̲u̲s̲:̲ O̲u̲t̲:̲ R/W, AD16-19, Transfer request.
I̲n̲:̲ 8Mhz, response (trans)
C̲P̲U̲:̲ IDR/NINS, we, clocks and timing signals
I̲n̲p̲u̲t̲ ̲D̲a̲t̲a̲ ̲R̲e̲g̲i̲s̲t̲e̲r̲
M̲a̲i̲n̲b̲u̲s̲:̲ 16-bit register to IBUS.
N̲e̲x̲t̲ ̲I̲n̲s̲t̲r̲u̲c̲t̲i̲o̲n̲ ̲r̲e̲g̲i̲s̲t̲e̲r̲
M̲a̲i̲n̲b̲u̲s̲:̲ 16-bit register to IBUS, but byte
swapped.
P̲a̲r̲i̲t̲y̲ ̲C̲h̲e̲c̲k̲
M̲a̲i̲n̲b̲u̲s̲:̲ 2 bits of parity. One for lower
byte and one for upper. 16 bits
of data. If error MBTC is told
to stop execution or transfer.
O̲u̲t̲p̲u̲t̲ ̲D̲a̲t̲a̲ ̲R̲e̲g̲i̲s̲t̲e̲r̲
M̲a̲i̲n̲b̲u̲s̲:̲ 16-bit register of data from OBUS.
P̲a̲r̲i̲t̲y̲ ̲G̲e̲n̲e̲r̲a̲t̲o̲r̲
M̲a̲i̲n̲b̲u̲s̲:̲ UP, LP on account of 16-bit of
data from OBUS.
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CPU L/GW/DI HAWK
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A̲d̲d̲r̲e̲s̲s̲ ̲R̲e̲g̲i̲s̲t̲e̲r̲
M̲a̲i̲n̲b̲u̲s̲:̲ 16-bit register of address from
ABUS.
F̲e̲t̲c̲h̲ ̲i̲n̲s̲t̲r̲u̲c̲t̲i̲o̲n̲ ̲i̲n̲ ̲p̲r̲o̲g̲r̲a̲m̲
CPU sets up an address in AR pointing to PROM(SCM)
and an address in the memory area.
MBTC: AD16-19(memory page/I/O: up/low byte
or word)
R/W = R. TRQ = 1.
AR = Address is present at mainbus
MBTC: receives RS = transfer response when
PROM accepts address.
NINS/IDR = receives data from PROM via Datalines.
O̲P̲ ̲R̲e̲g̲i̲s̲t̲e̲r̲ holds the instruction during decoding and
execution.
M̲i̲c̲r̲o̲ ̲P̲r̲o̲g̲r̲a̲m̲
S̲e̲q̲u̲e̲n̲c̲e̲r̲ consists of Feed Back Multiplexer used to
perform tests on OP-code and the
Micro Program Control Unit to setup addresses
for the Micro Program.
Micro Program Control Unit can store and sequence
5 address words of 12 bits.
M̲i̲c̲r̲o̲ ̲P̲r̲o̲g̲r̲a̲m̲ consists of 2Kword microinstructions of 64
bits and
Micro Instruction Register holding the 64bit
microinstruction during execution, and
4 registers to hold address lines for the
various registers
1 register: MPCU Instruction Register to alter
instructions, and is one of 4 inputs to MCU.
3 others OPREG, interrupts, results of data
operation.
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CPU L/GW/DI HAWK
Page
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A̲r̲i̲t̲h̲m̲e̲t̲i̲c̲a̲l̲ 4 Bitslices of 4 bits = 16 bit wide processor
L̲o̲g̲i̲c̲a̲l̲ ̲S̲e̲c̲t̲i̲o̲n̲ 1 Status and Shift Control
1 Look Ahead Carry Generator
I̲B̲U̲S̲:̲ input - instructions. O̲B̲U̲S̲:̲ output
performs the actual processing
contains the registers: RO-R7, MOD, TIMER
A̲d̲d̲r̲e̲s̲s̲ ̲C̲a̲l̲c̲u̲l̲a̲t̲i̲o̲n̲ Address calculations and mask functions.
a̲n̲d̲ ̲M̲a̲s̲k̲ ̲S̲e̲c̲t̲i̲o̲n̲
Arithmetic Logic Unit
16 registers in a file (16 bit wide): BASE,
PROG, PRPC.
T̲R̲:̲ Transfer and swop register gives access
to IBUS
O̲B̲U̲S̲:̲ receives data from ALS
A̲B̲U̲S̲:̲ connects to AR and internal to register
file
P̲r̲o̲c̲e̲s̲s̲ ̲S̲t̲a̲t̲u̲s̲
W̲o̲r̲d̲=̲ 16 bit status word. R/W via IBUS
1. group: bit 4-7 = condition of ALS
2. group: bit 8-10 = 3 switches = CPU number
3. group: bit 0-3, 11-15= 1 local interrupt
5 other interrupts
2 for memory paging
in 64k Bytes
C̲o̲m̲m̲u̲n̲i̲c̲a̲t̲i̲o̲n̲
a̲n̲d̲ ̲t̲i̲m̲i̲n̲g̲ ̲c̲n̲t̲l̲.̲ Control communication with SCM
Rx: interrupts = time, CPU, I/O's in priorities
Rx: Bus granted upon request
Tx: Bus requested, Lock Bus Granted (always)
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SCM L/GW/DI HAWK
Page
1…0e…
GENERAL System Control Module
C̲o̲n̲t̲r̲o̲l̲s̲ ̲t̲h̲e̲ ̲s̲y̲s̲t̲e̲m̲ ̲b̲y̲ ̲s̲u̲p̲p̲l̲y̲i̲n̲g̲
- timing signals: clocks
- bus access: control over bus
- handling of interrupts: I/O, timer, power
- monitors the supplied powers
- resets the system by Master Clear
- stores the initial programme to bootload
the system after power-up
A̲d̲d̲i̲t̲i̲o̲n̲a̲l̲ ̲f̲e̲a̲t̲u̲r̲e̲s̲ ̲a̲r̲e̲
- memory capacity to store part of AMC programme
- interface for V24 communication (testbox)
GROUPWORK Introduction and separation into groups.
Approach: as described earlier
Time consumption: 2 lessons
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SCM L/GW/DI HAWK
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RECOLLECTION Each group presents their results.
S̲y̲s̲t̲e̲m̲ ̲C̲o̲n̲t̲r̲o̲l̲ Contains 12k word memory-proms (Ultra
violet
M̲o̲d̲u̲l̲e̲ eraseable) - holding part of the AMC-programme.
Controls the CPU Main Bus Authority.
Receives and detects I/O-interrupts and with
Timer interrupts and power failure detection
informs/stops the CPU.
M̲a̲i̲n̲ ̲B̲u̲s̲ ̲I̲/̲F̲ Address Receiver (̲A̲R̲)̲,
Data Driver/Receiver (̲D̲R̲T̲)̲,
I/O Address Decoder (̲I̲/̲O̲ ̲A̲D̲)̲,
Memory Address Decoder (̲M̲A̲D̲)̲
Response Logic (RS).
A̲R̲:̲ 2 buffers for the address lines
D̲R̲T̲:̲ Bidirectional tranceivers controlled
by R/W enabled by TRQ + Comp 1/3/4
to address part of SCM
I̲/̲O̲A̲D̲:̲ to allow decoding of addresses
from I/O's AD 8-10+DA6 used to
address in SIOI.
(C̲o̲n̲t̲r̲o̲l̲) M̲A̲D̲:̲ AD10-19 with R/W used to select memory
area (ADO-AD9 feeded from AR)
R̲S̲:̲ generates RS-response- to TRQ when
address is accepted and SCM ready to
transfer.
M̲e̲m̲o̲r̲y̲ 3 areas of 4k UVEPROM 16-bit wide stores the
AMC-program.
By addressing, data (instructions) are sent
out on Mainbus.
Parity bits are stored as well.
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I̲n̲t̲e̲r̲r̲u̲p̲t̲ 8 bits interrupt code received on one line
of
R̲e̲c̲e̲i̲v̲e̲r̲ the mainbus (INR) in serial
the (INA) acknowledge interrupt is sent out.
4 interrupt can be stored - one in each priority
(0-3) - 2bits.
6 bits used for addressing (0-63).
CPU fetches the interrupts via Mainbus.
M̲a̲i̲n̲ ̲B̲u̲s̲ Used to grant CPU control over the mainbus.
A̲u̲t̲h̲o̲r̲i̲t̲y̲
C̲o̲n̲t̲r̲o̲l̲ CPU will always have control in this case,
but if expansion is desired with i.e. a DMA
module switching is needed.
P̲o̲w̲e̲r̲ ̲C̲o̲n̲ ̲d̲i̲t̲i̲o̲n̲ Power Detection and Master Clear circuits.
D̲e̲t̲e̲c̲t̲i̲o̲n̲
Upon Power up a Master Clear and a Computer
Clear are generated to reset the processor.
Activation of Master Clear on front panel
gives the same result.
Power is monitored: 5V, +/-12V.
If too low Power Failure is set and Power
Failure Interrupt sent to halt CPU.
Master Clear needed to clear it.
Red LED on front lit.
T̲i̲m̲i̲n̲g̲ ̲ Generates 4 clocks [1-[4 of 8,4,2,1 MHz to
G̲e̲n̲e̲r̲a̲t̲o̲r̲ the mainbus for synchronization and
2 timer interrupts for CPU: 10 msec and adjustable
10-160 usec.
Power Failure has highest priority, then timer,
then I/O.
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P̲r̲o̲g̲r̲a̲m̲m̲a̲b̲l̲e̲ Controls the communication with front plate
C̲o̲m̲m̲u̲n̲i̲c̲a̲t̲i̲o̲n̲ V24-connection for testbox(DTE/DCE:50-19200
I̲n̲t̲e̲r̲f̲a̲c̲e̲ baud) in 1200 baud.
It converts parallel (bus) to serial (V24)
To/from controlled by W/R.
The subaddress sets the mode/command.
The I/O-address is as for any I/O.
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HAWK TRAINING 2:7-9 LT/830228
PROM & RAM L/GW/DI HAWK
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GENERAL Programmable Read Only Memory - 4Kw
Random Accessable Memory - 32Kw
PROM and RAM are both modules containing memory
addressable by the CPU (256 Kwords: 4 pages
of 64 Kw)
Addressed the same way by CPU.
P̲R̲O̲M̲: a read-only-memory which during a slow
procedure can be written (loaded with programme)
and store data permanently.
A read will be relatively fast.
Used to store programme (instructions)
R̲A̲M̲: a dynamic memory storage that can be
accessed random.
Both read and write are relatively fast.
Data have to be restored continuously - done
by refresh.
Data are lost at power-down.
GROUPWORK Introduction and separation into groups.
Approach: as described previously.
Time Consumption: 1 lesson per module.
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PROM & RAM L/GW/DI HAWK
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RECOLLECTION Each group presents their results.
P̲R̲O̲M̲
Programmable Read Only Memory of 4k word of
16 bits + 2 parity bits.
Stores the most often used instructions of
the AMC-programme.
M̲a̲i̲n̲ ̲B̲u̲s̲ ̲I̲/̲F̲ Voltage Monitor Detect (̲V̲M̲O̲)̲,
Clock Interface (̲C̲I̲)̲
Memory Address Select (̲M̲A̲S̲)̲,
Clear Circuit (̲C̲C̲)̲,
Main Bus Control (̲M̲B̲C̲)̲,
Date Enable Logic (̲D̲E̲L̲)̲.
V̲M̲D̲:̲ +5V detection
C̲I̲: receiption of 8 Mhz clock
M̲A̲S̲:̲ AD 12-17 to select memory module (compare
switch)
C̲C̲:̲ at Master Clear generates a clear for
the module
M̲B̲C̲:̲ upon TRQ generates RS if R/W = R
and times the main bus read, and enables
DEL.
D̲E̲L̲: Data drivers (16+2 bits) to bus
S̲u̲b̲b̲u̲s̲ not used
B̲u̲s̲ ̲D̲e̲m̲a̲n̲d̲ ̲C̲i̲r̲c̲u̲i̲t̲ controls priority between buses. Always set
to main.
A̲d̲d̲r̲e̲s̲s̲ ̲S̲e̲l̲e̲c̲t̲
a̲n̲d̲ ̲D̲r̲i̲v̲e̲r̲ Address selection to select between Bus access.
Always Main Drivers for the PROMS.
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PROM & RAM L/GW/DI HAWK
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P̲R̲O̲M̲ ̲A̲r̲r̲a̲y̲ 8 Proms,
Prom selector, which is a demultiplexer of
bit 9-11 to select PROM,
2 Parity PROMs, one for each byte.
8 Proms contain each 512 words (16 bits)
R̲A̲M̲
Random Access Memory of 32Kword of 16bit +
2 par.
M̲a̲i̲n̲ ̲B̲u̲s̲ ̲I̲/̲F̲ Voltage Error Detection (̲V̲E̲D̲)̲,
Clock Interface (̲C̲I̲)̲, Module Clear (̲M̲C̲)̲,
Module Address Comparator (̲M̲A̲C̲)̲,
BUS Control (̲B̲C̲)̲,
Bus Receivers (̲B̲R̲)̲,
Bus Drivers (̲B̲D̲)̲.
M̲A̲C̲:̲ AD12-19 is received = detects module
address (switch) and selects upp/low
bytes.
B̲C̲:̲ receives TRQ, R/W from bus and Comp
from MAC.
generates enable signals for MC, BR,
BD.
selects between RAM area 0-16K/16-32k.
generates RS to CPU.
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PROM & RAM L/GW/DI HAWK
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B̲R̲:̲ enabled by BC, it receives DA 0-15+2
parity from MB
data sent to RAM areas
B̲D̲:̲ enabled by BC, it receives Data+parity
from RAM area and drives DA 0-15+2
on Main Bus.
C̲I̲:̲ receives by a pair of Smitt triggers
[1+[4
1 + 8 MHz clocks
M̲C̲:̲ generates CL to clear module at power
on and Master Clear.
It does not clear refresh so after
Master Clear RAM contents is valid.
V̲E̲D̲:̲ Light the green on the front when +5,
+/-12VDC is present.
A̲d̲d̲r̲e̲s̲s̲ ̲M̲u̲x̲
a̲n̲d̲ ̲R̲e̲f̲r̲e̲s̲h̲ ̲C̲o̲u̲n̲t̲ Refresh Control (̲R̲C̲)̲,̲ Address Mux (̲A̲M̲)̲.̲
A̲M̲:̲ MO-6 to select RAM-chip
receives 14 address line + a line for
up/low area spec.dyn.RAM multiplexes
to 7 lines to RAM area
R̲C̲:̲ generates the refresh signals selecting
address in the AM.
Time controlled by Timing Control.
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PROM & RAM L/GW/DI HAWK
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1̲6̲K̲R̲A̲M̲ ̲A̲r̲e̲a̲ receives 16bit data + 2 bit parity up/low
byte from Bus Receivers of Main Bus I/F
transmits 16 bit data + 2 bit parity up/low
byte to Bus Drivers of Main Bus I/F.
becomes addressed by Address Mux by MO-6
twice: 7 lines for column, 7 lines for row.
1,2,4,8,16,32,64 = 128x128 = 16,384 = 16K
becomes selected in up/low area and up/low
Byte
8 RAM-chips + RAM-parity-chip x 2 = 16-bit
+ 2 word.
B̲u̲s̲ ̲A̲n̲d̲
T̲i̲m̲i̲n̲g̲ ̲C̲o̲n̲t̲r̲o̲l̲
generates the memory timing signals:
2 signals selecting up/low byte Row, up/low
byte column to each area.
It also controls the Refresh timing and the
transfer to Main Bus.
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AV24 I/F L/GW/DI HAWK
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GENERAL Establish communication between CPU and V24
equipment - Operator's Panel.
Communicates with CR80 in parallel via Bus.
Communicates with O.P. in parallel via V24.
full duplex - asynchronous -
Buffer data - handles error detection - generates/checks
frame bits.
Sets up control lines to V24 as told by data
in control byte from CPU.
Informs CPU of V24 control line status in
status byte.
Can be strapped to any baud rate within 50
- 19200 - 1200 selected.
GROUPWORK Introduction and separation into groups.
Approach: as described previously.
Time Consumption: 1 lesson
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RECOLLECTION Each group presents their results.
Asynchronous V24 interface to D̲a̲t̲a̲ ̲T̲e̲r̲m̲i̲n̲a̲l̲
̲E̲q̲u̲i̲p̲m̲e̲n̲t̲ or Data Communication Equipment.
Communicates with O̲p̲e̲r̲a̲t̲o̲r̲s̲ ̲P̲a̲n̲e̲l̲ and P̲r̲o̲c̲e̲s̲s̲o̲r̲.
Main Bus Interface (̲M̲B̲I̲)̲,
Communication Circuit (CC),
Line Drivers/Receivers (̲L̲D̲/̲R̲)̲.
C̲o̲m̲m̲.̲w̲.̲
O̲p̲e̲r̲.̲P̲.̲ in serial -full duplex - 1200 baud - asynchronous
1 start bit - 8 data bit - 1 parity bit (even)
- 1 stop bit.
Control Lines in use: Request to Send, Carrier
Detect,
From O.P. Data Terminal Ready,
Clear to Send,
To O.P. Data Set Ready,
Carrier Detect
C̲o̲m̲m̲.̲w̲.̲ ̲C̲P̲U̲ in bytes: 1 byte status/control, 1 byte data.
CPU informed that data is ready by Interrupt
request.
M̲a̲i̲n̲ ̲B̲u̲s̲ ̲I̲/̲F̲ Voltage Error Detection (̲V̲E̲D̲)̲,
Clock Interface (̲C̲I̲)̲,
Module Address Compare (̲M̲A̲C̲)̲,
Bus Control (̲B̲C̲)̲,
Bus Driver (̲B̲D̲)̲,
Data Latches (̲D̲L̲)̲,
Interrupt circuit (̲I̲C̲)̲.
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HAWK TRAINING 2:10-11 LT/830228
AV24 I/F L/GW/DI HAWK
Page 3…0e…
V̲E̲D̲: monitors the +5, +/- 12 VDC - light
green LED.
C̲I̲:̲ 4 SCHMITT Triggers receiving
[1 - [4 (1,2,4,8 Mhz)
used for timing control in the module
M̲A̲C̲:̲ compare AD 0-5 with module address
(S1)
S1 is also used by IC as address/priority
when sending interrupt to CPU.
B̲C̲:̲ Generates a module clear signal if
power up or Master Clear:
Rx: AD17-19, R/W, TRQ Tx: RS (response)
ADA-19 and R/W selects upon acceptance
from MAC:
Read Status Byte
…0e…to CPU…0f… Read Data Byte
…0f…from CPU…0e… Load Control register
Load UART with data
D̲L̲: receives DAO-7-control/data byte from
CPU and is loaded everytime CPU accesses
module
B̲D̲:̲ transmits data from UART during Read
Data
- " - status gained from UART and
V24 lines
I̲C̲: send an interrupt request to CPU(SCM)
when tx buffer is empty or tx data
is ready
and if Request to Send
Data Terminal Ready goes Low
Carrier Detect (from O.P.)
O̲s̲c̲i̲l̲l̲a̲t̲o̲r̲ ̲a̲n̲d̲
B̲a̲u̲d̲ ̲R̲a̲t̲e̲ ̲G̲e̲n̲e̲r̲a̲t̲o̲r̲ Generates clocks of 921.6Khz and 307.2 Khz
used to create the right baud-rate-clock to
the UART (by means of strapping)
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HAWK TRAINING 2:10-11 LT/830228
AV24 I/F L/GW/DI HAWK
Page 4…0e…
U̲A̲R̲T̲ a) receives a byte of data in parallel and
Universal converts it to serial,
Async.
Receiver tx it through the line drivers to O.P. in
Transmitter correct form with start + stop + parity bits
generated by UART.
b) or receives data in serial from O.P.,
converts it to parallel,
checks on Parity error, overflow, rx/tx buffers
and DTE controlsignals.
Forms a 5-bit status word on this, which is
sent to BD in MBI together with DATA.
initiates interrupt to CPU.
C̲o̲n̲t̲r̲o̲l̲ ̲R̲e̲g̲i̲s̲t̲e̲r̲ used to hold a 3-bit control word from CPU
to LD/R.
L̲D̲/̲R̲ Line Drivers and Receivers (L̲),
Interrupt enable (I̲E̲C̲).
L̲: interfaces TTL(CR80) to V24-Lines,
and initiates
I̲E̲C̲:̲ initiating CPU-interrupt request when
Request to send, Carrier Detect, Data
Terminal Ready fails.
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HAWK TRAINING 2:12-13 LT/830228
OPERATOR'S PANEL L/GW/DI HAWK
Page 1…0e…
GENERAL Allows the operator to communicate with the
system via the AV24 I/F.
Used to received operator selected parameters
- to display verifications to the operator
- to display errors/conflicts
- to allow acknowledgements/resetting of
errors/conflicts
Microprocessor controlled scanning of keybord
and displays to collect and load data - received/transmitted
in serial to/from CPU via AV24 I/F.
GROUPWORK Introduction and separation into groups
Approach: as described previously.
Time: 1 lesson.
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HAWK TRAINING 2:12-13 LT/830228
OPERATOR'S PANEL L/GW/DI HAWK
Page 2…0e…
RECOLLECTION Each group presents their results.
O̲p̲e̲r̲a̲t̲o̲r̲s̲ ̲P̲a̲n̲e̲l̲
A display/keyboard device, micro-computer
controlled interface to AMC via A V24 i/f.
Received data are decoded and displayed on
LEDs or Hex-display.
Transmitted data are derived from keyboard.
I̲n̲p̲u̲t̲ ̲L̲i̲n̲e̲s̲(̲4̲)̲ Receive data - Ready for Sending
Data Set Ready - Carrier Detect
O̲u̲t̲p̲u̲t̲ ̲L̲i̲n̲e̲s̲(̲3̲)̲ Transmit data - Request to Send
Data Terminal Ready
D̲a̲t̲a̲ ̲F̲o̲r̲m̲a̲t̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲
S D D D D D D D D P S 1200
baud
̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲
start data parity stop
O̲p̲e̲r̲a̲t̲o̲r̲s̲ ̲P̲a̲n̲e̲l̲ Micro Processor Board (̲M̲P̲B̲,̲
Switch Board (̲S̲B̲)̲,̲
Display Board (̲D̲B̲)̲
M̲P̲B̲ Microprocessor (̲M̲P̲U̲)̲,̲
Serial I/O (̲S̲T̲O̲)̲,
Timer (̲T̲M̲R̲)̲,
Keyboard/Display I/F (̲K̲D̲I̲)̲,
Clock (̲C̲L̲K̲)̲,
Reset (̲R̲E̲S̲)̲,
DC-DC converter (̲D̲D̲C̲)̲,
Power Detect (̲P̲D̲T̲)̲.
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HAWK TRAINING 2:12-13 LT/830228
OPERATOR'S PANEL L/GW/DI HAWK
Page
3…0e…
R̲E̲S̲:̲ at power up resets the MPU and the
KDI to a pre-determined state by generating
CLR.
C̲L̲K̲:̲ 4 Mhz osc. and frequency divider.
2 phase input to MPU of 2 Mhz. CPO
(one phase) also used for TMR and KDI.
M̲P̲U̲:̲ 1K byte PROM, 64 byte RAM, 8-bit bidirectional
data bus,
port 1 (output) chipselect and control,
port 2 (input) receive interrupts.
The program stored in the PROM are
executed immediately after power-up
(CLR).
RAM used for storage during execution.
Databus is used for reception/ transmission
of data to/from KDI-SIO-TMR.
Port 1 : 5 lower bits used to select/control
the KDI-SIO-TMR.
Port 2: receives 3 interrupts from
SIO/KDI/TMR, and INTO (Lamp test)
I̲M̲R̲:̲ 2 of its 3 counters are used to establish
19.2 Khz as CP1 used by SIO as rx/tx
clock
and a 2 Hz used as interrupt to MPU
used during lamp test/blinking.
S̲I̲O̲:̲ interfaces to AV24IF module in serial-async-full
duplex-1200 baud.
Software formatted by MPU to 1200 baud
and data setup.
Data rx/tx on databus in parallel when
selected.
The signal selects instruction/data.
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HAWK TRAINING 2:12-13 LT/830228
OPERATOR'S PANEL L/GW/DI HAWK
Page 4…0e…
K̲D̲I̲:̲ rx/tx data on databus,
tx instructions on databus.
4-bit scan Lines used in conjunction
with return lines to rx information
from switches,
and with 8-bit databus to tx data to
display.
D̲D̲C̲:̲ delivers +/- 12V DC from + 5V DC.
P̲D̲T̲:̲ monitors +5, +/- 12 VDC, when right
lights LED.
S̲B̲: Switch Matrix (̲S̲M̲X̲)̲,
Scan Line Decoding (̲S̲C̲N̲)̲
S̲C̲N̲:̲ decodes the 4 scan Lines into
6 address line to SMX.
S̲M̲X̲:̲ send information via 8 return
Lines.
Data extracted by KDI in accordance
with Known address by scanlines.
D̲B̲ Scan Line Decoding (̲S̲C̲A̲)̲,̲
LED Matrix (̲L̲M̲X̲)̲,
Blanking (̲B̲L̲K̲)̲,
Numerical Display (̲N̲D̲P̲)̲.
S̲C̲A̲:̲ decodes the 4 scan lines into
7 address lines to LED matrix,
and to 6 address lines to NDP.
DVA (data available) times the
addressing.
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HAWK TRAINING 2:12-13 LT/830228
OPERATOR'S PANEL L/GW/DI HAWK
Page 5…0e…
L̲M̲X̲:̲ receives address from SCA and
data from 8-bit data bus (2 x
4-bit unidirectional).
54 LEDs. 1 column of 8 LEDs enabled
at a time.
B̲L̲K̲:̲ generates 6 blanking signals for
NDP.
DABO (display blank or not) goes
into a shift-register (one DABO
to each of the 6 displays)
while SL3 is high the info's are
shifted (time zone 0-7 of scan
cycle)
and are present as BR2-7 one for
each display (time zone 10-15).
N̲D̲P̲:̲ 6 Hex-displays addressed by SCA
(6lines) data received from KDI
(8 lines) and blanked by BLK (6
lines).
The hex-displayes contains display,
driver, and latch.
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HAWK TRAINING 2:14-16 LT/830228
ATDL LTU L/GW/DI HAWK
Page 1…0e…
GENERAL Synchronous Line Termination Unit of the ATDL
Link. Takes care of 4 channels:
connects to 2 modems each with 2 channels.
T̲x̲-̲R̲x̲ Controls the modem signals and data transfer,
but tx/rx clocks are received from modem.
Receives data in parallel from CPU a byte
a time.
Transmits data in serial to Modem.
Receives data in serial from Modem.
CPU fetches data in parallel from LTU (byte/byte)
M̲o̲d̲e̲m̲ ̲I̲F̲ T̲r̲a̲n̲s̲m̲i̲s̲s̲i̲o̲n̲:̲ data received from CPU (received
in bytes) are assembled
to a message supplied with
Sync Field, Check Bits (1),
and Block Check Character
(8). LSB of the sum of all
data.
R̲e̲c̲e̲p̲t̲i̲o̲n̲:̲ data received from Modem
are checked and stripped
of the frame.
C̲P̲U̲ ̲I̲F̲ T̲r̲a̲n̲s̲m̲i̲s̲s̲i̲o̲n̲:̲ Double buffering: 8 bytes
per channel used in the
LTU.
1 Tx Control Byte-used for
synchronization
7 Tx File Buffers for holding
data
C̲o̲n̲t̲r̲o̲l̲ ̲B̲y̲t̲e̲:̲ 1 bit in use: T̲x̲ ̲B̲u̲f̲f̲e̲r̲
̲E̲m̲p̲t̲y̲ set by LTU, cleared
by CPU - Handshaking.
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HAWK TRAINING 2:14-16 LT/830228
ATDL LTU L/GW/DI HAWK
Page 2…0e…
T̲x̲ ̲F̲i̲l̲e̲ ̲B̲u̲f̲f̲e̲r̲:̲ 7 bytes - 8 bits each -
when filled, the data is
moved to the TxShift File,
and the Tx Buffer Empty
is set in the Tx Control
Byte -
polled by CPU - informing
that new data can be loaded.
R̲e̲c̲e̲p̲t̲i̲o̲n̲:̲ CPU needs access to 8 bytes
in the memory (RAM).
1 byte of Control and 7
bytes of data.
C̲o̲n̲t̲r̲o̲l̲ ̲B̲y̲t̲e̲:̲ Rx Control byte: 5 bits
used:
Rx Buffer Full, set by LTU,
CPU clears.
BCC Error, set by LTU if
error in BCC.
Check Bit Error, set by
LTU if error.
Rx Overrun, set by LTU if
CPU fails to empty Rx Buffer
File before next frame.
Carrier Detect Off, set
by LTU if CD has been off
during reception.
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HAWK TRAINING 2:14-16 LT/830228
ATDL LTU L/GW/DI HAWK
Page 3…0e…
R̲x̲ ̲F̲i̲l̲e̲ ̲B̲u̲f̲f̲e̲r̲:̲ The Rx Shift File receives
the data in serial,
when full, data is moved
to Rx File Buffer and Rx
Buffer Full bit in the Rx
Control Byte is set.
CPU polls the Rx Control
Byte, detects the Buffer
Full bit, fetches data -
byte by byte - and clears
the Rx Buffer Full bit.
When data is moved to the
File Buffer, new message
can be entered in the Rx
Shift File.
When messages are not transmitted an idle
pattern is transmitted: alternating one/zero
bits.
If next frame is available it will follow
immediately after.
M̲o̲d̲e̲/̲S̲t̲a̲t̲u̲s̲ ̲B̲y̲t̲e̲:̲ M̲o̲d̲e̲ ̲B̲y̲t̲e̲:̲ if LTU/Modem Loop is chosen
the R̲e̲s̲e̲t̲ ̲S̲i̲n̲g̲l̲e̲ ̲C̲h̲a̲n̲n̲e̲l̲
is set together with
S̲e̲l̲e̲c̲t̲ ̲M̲o̲d̲e̲m̲ ̲L̲o̲o̲p̲/̲L̲o̲o̲p̲ ̲T̲e̲s̲t̲
̲M̲o̲d̲e̲
Test mode: D̲i̲s̲a̲b̲l̲e̲d̲ ̲M̲o̲d̲e̲/̲D̲i̲s̲a̲b̲l̲e̲
̲a̲f̲t̲e̲r̲ ̲1̲ ̲r̲u̲n̲
C̲o̲n̲n̲e̲c̲t̲ ̲D̲a̲t̲a̲ ̲S̲e̲t̲ ̲T̲o̲ ̲L̲i̲n̲e̲:̲
̲order to modem to connect
to Line
D̲a̲t̲a̲ ̲S̲i̲g̲n̲a̲l̲l̲i̲n̲g̲ ̲R̲a̲t̲e̲ ̲S̲e̲l̲e̲c̲t̲o̲r̲
used to select optional
600 baud rate.
S̲t̲a̲t̲u̲s̲ ̲B̲y̲t̲e̲:̲ response to CPU on Modem
control signals:
D̲a̲t̲a̲ ̲S̲e̲t̲ ̲R̲e̲a̲d̲y̲, and D̲a̲t̲a̲
̲C̲h̲a̲n̲n̲e̲l̲ ̲R̲e̲c̲e̲i̲v̲e̲d̲ ̲L̲i̲n̲e̲ ̲S̲i̲g̲n̲a̲l̲l̲i̲n̲g̲
̲D̲e̲t̲e̲c̲t̲o̲r̲ ̲(Carrier Detect)
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HAWK TRAINING 2:14-16 LT/830228
ATDL LTU L/GW/DI HAWK
Page 4…0e…
GROUPWORK Introduction and separation into groups.
Approach: as described previously.
Time: 2 lessons
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HAWK TRAINING 2:14-16 LT/830228
ATDL LTU L/GW/DI HAWK
Page 5…0e…
RECOLLECTION Each group presents their results.
S̲i̲g̲n̲a̲l̲f̲l̲o̲w̲:̲
M̲o̲d̲e̲m̲ ̲I̲F̲ Line Receiver (̲L̲R̲)̲,
Synchronization (̲S̲)̲,
Line Transmitter (̲L̲T̲)̲.
One of four served by one MPU.
L̲R̲:̲ 2:1 multiplexer receiving either the
external or the internal signals -
internal during Loop.
Ext: modem signals: Received data, TSET
(Txclk), RSET(Rx clk), Data Set Ready,
Carrier Detect. Line receivers interfacing
to 188 MIL STD due to optinal CRYPTO
connect.
Int: Tx-data as Tx-data from LT RxLCH and
TxLCK from LCG.
S̲:̲ receives data from LR (serial) and
sends data on to MPU REG via IBUS (serial)
together with status of CD, DSR from
LR, 2 bits of reception status, and
2 bits of transmission status.
Transfer is controlled by MPU.
L̲T̲:̲ transmits via Line drivers supplying
MIL 188 STD Data
synchronized by TSET received via LR
from LR,
and asynchroniouz CDTL, SML, DSRS to
Modem.
The 4 signals are received via IBUS.
Controlled by MPU via IVB.
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HAWK TRAINING 2:14-16 LT/830228
ATDL LTU L/GW/DI HAWK
Page 6…0e…
C̲o̲n̲t̲r̲o̲l̲ Micro Processor Unit (̲M̲P̲U̲)̲,
MPU Registers (̲M̲P̲U̲ ̲R̲E̲G̲)̲,̲
Loop Controlled Generator (̲L̲C̲G̲)̲,
Channel Number Latch (̲C̲N̲L̲)̲,
Halt Logic (̲H̲L̲)̲
M̲P̲U̲ is an 8x300 interpreter with a
1024x1b bit PROM containing the
program.
M̲P̲U̲ ̲R̲E̲G̲ 256 x 8 bit RAM divided into 4
parts - one to each channel -
and various registers used by
MPU for storage.
L̲C̲G̲:̲ generates, on behalf of (the [4
clock) the MPU generated MCLK,
a TxCLK and a RxCLK for use in
LTU Loop mode.
C̲N̲L̲:̲ stores the actual channel number
to be serviced by the MPU and
controls the clock selection in
LCG.
H̲L̲:̲ halts the processor during mainbus
access.
M̲a̲i̲n̲ ̲B̲u̲s̲ ̲I̲F̲ Module Address Compare (̲M̲A̲C̲)̲,
Main Bus Control Decoding (̲M̲C̲D̲)̲,
Main Bus Driver/Receiver (̲M̲D̲R̲)̲.̲
M̲A̲C̲ generates ITRQ when address compares
to switch.
M̲C̲D̲ decodes the MB control and generates
the RS.
M̲D̲R̲ receives/transmits data with mainbus.
IVB.
Receives memory address. ABUS.
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HAWK TRAINING 2:14-16 LT/830228
ATDL LTU L/GW/DI HAWK
Page 7…0e…
Program Once started it uses 700 usec.
Is started in time slots of 800 usec.
A CPU-access "steals" approx. 1 usec and halts
the MPU.
Max CPU-access = 100 within one program-run.
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HAWK TRAINING 2:17-18 LT/830228
ATDL MODEM L/GW/DI HAWK
Page 1…0e…
GENERAL Modulate - Demodulate line signals.
Interfaces between LTU - logic signals - and
line signal - modulated.
Transfer rate: 1200 baud - controlled by
modem-synchronous - full
duplex.
Modem is controlled by LTU.
Modulation, demodulation, bit-synchronization,
and carrier detection are controlled by a
microprocessor.
Line: 1300/2100 Hz FSK FSM
LTU (crypto): +/-6V, MIL 188C STD
2 identical channels
GROUPWORK Introduction and separation into groups.
Approach: as described previously.
Time: 1 lesson.
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HAWK TRAINING 2:17-18 LT/830228
ATDL MODEM L/GW/DI HAWK
Page 2…0e…
RECOLLECTION Each group presents their results.
A̲T̲D̲L̲ ̲M̲o̲d̲e̲m̲ Interfaces between LTU and via Line Panel
to ATDL Lines.
Serves 2 channels of 4 in a LTU
Ext Line; FSM using FSK.
LTU line interfaced according to MIL 188C
STD to allow CRYPTO-device.
1200 baud-sync (controlled by Modem)-serial-full
duplex.
Each channel consists of demodulator/ modulator.
Controlled by LTU.
F̲r̲o̲m̲ ̲L̲T̲U̲:̲ Connect Data Set to Line, Select
Modem Loop, Data Signalling Rate
Selector, Data
T̲o̲ ̲L̲T̲U̲:̲ Data Set Ready, Carrier Detect,
Data,
Tx/tx Clocks Transmit Signal Element Timing
Receive Signal Element Timing
D̲e̲m̲o̲d̲u̲l̲a̲t̲o̲r̲ Line Input Circuit (L̲I̲C̲),
Baud Pass Filter (̲B̲P̲F̲)̲,
Phase Lock Loop Detector (̲P̲L̲L̲)̲,̲
Sample Circuits (̲S̲C̲)̲,
Micro Processor Registers (̲M̲P̲R̲)̲,̲
Micro Processor Circuits (̲M̲P̲C̲)̲,̲
Receive Clock Circuit (̲R̲C̲C̲)̲,
LTU Drivers (̲L̲T̲U̲D̲)̲
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HAWK TRAINING 2:17-18 LT/830228
ATDL MODEM L/GW/DI HAWK
Page 3…0e…
M̲P̲R̲ ̲+̲ ̲M̲P̲C̲:̲ Common to both channels and the
heart of the Modem.
X-tal controlled Micro Processor
with PROMS of 1k words containing
program for seven processes,
RAM areas one for each channel,
of 128 bytes each.
Registers for storage of addresses
in the PROMS and RAMS.
The clock MCLK is 3.268 Mhz.
L̲I̲C̲:̲ receives the audio signal from
ATDL Line of 1300/2100 Hz
Mark/Space if LTU has not selected
Loop (Select Modem Loop) from
LTUR.
B̲P̲F̲:̲ filters low and high freq. noise
and distortion
P̲L̲L̲:̲ locks when signal is high enough
and informs MPC (converted to
Carrrier Detect),
converts audio input to TTL Logic.
Mark/Space high/low.
S̲L̲:̲ within a bit time the processor
takes a sample 8 times of the
data latched in the SC.
M̲P̲R̲:̲ stores the 8 samples needed to
accept a bit of Mark/space in
ODR (Output Data Register)
together with Carrier Detect gained
from PLL and Data Set Ready gained
from LTUR (Connect Data Set To
Line).
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HAWK TRAINING 2:17-18 LT/830228
ATDL MODEM L/GW/DI HAWK
Page 4…0e…
R̲C̲C̲:̲ based on the MCLK the BRM generates
a receive clock of 153.6 Khz.
This clock is synchronized by
insertion or removal of clocks
by MPC to have a clock in the
middle of a bit time and divide
by 128 to have baud rate 1200.
L̲T̲U̲D̲:̲ receives data and control signals
from ODR of MPR and Rx-clock from
RCC.
Tx to LTU clock (RSET), Data,
Carrier Detect (CD) and Data Set
Ready (DSR).
Data are +/-6V to fit MIL 188
STD.
M̲o̲d̲u̲l̲a̲t̲o̲r̲ LTU receive (̲L̲T̲U̲R̲)̲,
Binary Rate Multipliers (̲B̲R̲M̲)̲,
Sine Voltage Generator (̲S̲V̲G̲)̲,
Amplitude Regulators (̲A̲R̲)̲,
Low Pass Filter (̲L̲P̲F̲)̲,
Line Output Circuit (̲L̲O̲C̲)̲.
L̲T̲U̲R̲:̲ receives Data from LTU and the control signals
DSRS (to select tx-clock in Modem)
CDTL (Connect Data To Line)
SML (Select Modem Loop).
CDTL, SML are stored in MPR.
Data are converted from MIL to TTL and clocked
by TSET.
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HAWK TRAINING 2:17-18 LT/830228
ATDL MODEM L/GW/DI HAWK
Page 5…0e…
B̲R̲M̲:̲ the synchronized data is multiplied:
Mark/Space 332.8/537.6 Khz.
The Rx and Tx clocks (RSET, TSET)
is generated.
S̲V̲G̲:̲ the data is divided and used to scan
the 32 addresses of a PROM.
Each address produces a digital value
which applied to a D/A Converter generates
a 32 step sinewave of 1300/2100 Hz.
A̲R̲:̲ provide unity amplification and attenuation
of output in steps of 1dB.
L̲O̲C̲:̲ Drives the ATDL Line with impedance
of 600 OHM
Contains a CMOS switch for control
of CDTL.
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HAWK TRAINING 2.19-21 LT/830228
MBDL LTU L/GW/DI HAWK
Page
1…0e…
GENERAL Asynchronious Line Termination Unit of the
MBDL Link.
Takes care of 4 channels:
connects to 2 modems each with 2 channels.
T̲x̲-̲R̲x̲ Controls the modem signals and transfer.
Receives data in parallel from CPU.
Transmits data in serial to modem.
Receives data in serial from modem.
CPU fetches data in parallel from LTU.
M̲o̲d̲e̲m̲ ̲I̲F̲ T̲r̲a̲n̲s̲m̲i̲s̲s̲i̲o̲n̲:̲ data received from CPU are
supplied with MBDL format.
Generates Ready Start and
Frame Guard (LTU/Modem Loop:
even parity,Remote Starts)
R̲e̲c̲e̲p̲t̲i̲o̲n̲:̲ data received from Modem
are checked and stripped
for Ready Start, parity
(even), Frame Guard.
Remote Starts are detected
and checked.
C̲P̲U̲ ̲I̲F̲ T̲r̲a̲n̲s̲m̲i̲s̲s̲i̲o̲n̲:̲ 8 bytes per channel is needed
in the LTU for the CPU communication:
1 TX Control Byte
7 bytes of Transmit File
Buffer
Control byte needed for
synchronization
Tx File Buffer holds data.
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HAWK TRAINING 2.19-21 LT/830228
MBDL LTU L/GW/DI HAWK
Page 2…0e…
M̲o̲d̲e̲s̲:̲ Control/Status.
Control used for Loop-tests
Status mode is the normal
mode
C̲o̲n̲t̲r̲o̲l̲ ̲B̲y̲t̲e̲:̲ 3 bits in use: T̲x̲ ̲B̲u̲f̲f̲e̲r̲
̲E̲m̲p̲t̲y̲ set by LTU, cleared
by CPU-handshaking.
S̲h̲i̲f̲t̲ ̲F̲i̲l̲e̲ ̲N̲o̲ 0 or 1, when
Tx File
Buffer is full data is moved
to 0/1.
T̲x̲ ̲R̲e̲m̲o̲t̲e̲ ̲S̲t̲a̲r̲t̲ used only
in CMD mode.
T̲x̲ ̲F̲i̲l̲e̲ ̲B̲u̲f̲f̲e̲r̲:̲ when full moved to Tx Shift
File 0 or 1,
upon reception of Remote
Start, data is serial shifted
out
Tx File Buffer may be filled
with new data to be moved
to other Tx Shift File for
transmission at next Remote
Start
- if none, the first will
be retransmitted.
R̲e̲c̲e̲p̲t̲i̲o̲n̲:̲ 8 bytes per channel needed
in the LTU for the CPU to
access:
1 Rx Control Byte
7 bytes of Receive File
Buffer
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HAWK TRAINING 2.19-21 LT/830228
MBDL LTU L/GW/DI HAWK
Page 3…0e…
C̲o̲n̲t̲r̲o̲l̲ ̲B̲y̲t̲e̲:̲ Used for error/status information
and for the CPU to synchronize
to the LTU.
Transfer rate is Modem bitrate
R̲x̲ ̲B̲u̲f̲f̲e̲r̲ ̲F̲u̲l̲l̲ for handshaking.
4 error indications:
F̲r̲a̲m̲i̲n̲g̲ ̲e̲r̲r̲o̲r̲,̲
P̲a̲r̲i̲t̲y̲ ̲e̲r̲r̲o̲r̲,
C̲a̲r̲r̲i̲e̲r̲ ̲D̲e̲t̲e̲c̲t̲ ̲O̲f̲f̲,̲ ̲and
R̲x̲O̲v̲e̲r̲r̲u̲n̲ (CPU did not read
buffer before next frame
was received - data is lost
- bit applies to data in
buffer).
S̲h̲i̲f̲t̲ ̲F̲i̲l̲e̲ ̲0̲ ̲T̲x̲'̲e̲d̲,̲ ̲
S̲h̲i̲f̲t̲ ̲F̲i̲l̲e̲ ̲1̲ ̲T̲x̲'̲e̲d̲.̲
1 bit not used.
R̲e̲c̲e̲i̲v̲e̲ ̲F̲i̲l̲e̲ ̲B̲u̲f̲f̲e̲r̲:̲
The LTU awaits a Ready Start
pattern,
when all bits are detected
to be good, data is shifted
into R̲x̲ ̲S̲h̲i̲f̲t̲ ̲F̲i̲l̲e̲
when full moved to R̲x̲ ̲F̲i̲l̲e̲
̲B̲u̲f̲f̲e̲r̲ and the
Rx Buffer full bit in the
control byte is set.
When CPU polls the Rx Control
Byte it will know that data
is ready.
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HAWK TRAINING 2.19-21 LT/830228
MBDL LTU L/GW/DI HAWK
Page 4…0e…
M̲o̲d̲e̲/̲S̲t̲a̲t̲u̲s̲ ̲B̲y̲t̲e̲s̲
S̲t̲a̲t̲u̲s̲ ̲b̲y̲t̲e̲s̲ holds Modem
control Lines information:
D̲a̲t̲a̲s̲e̲t̲ ̲R̲e̲a̲d̲y̲
C̲a̲r̲r̲i̲e̲r̲ ̲D̲e̲t̲e̲c̲t̲
M̲o̲d̲e̲ ̲b̲y̲t̲e̲ used by CPU to
set
M̲o̲d̲e̲m̲ ̲c̲o̲n̲t̲r̲o̲l̲ ̲s̲i̲g̲n̲a̲l̲s̲ -
(2) - to set
LTU in C̲M̲D̲ ̲m̲o̲d̲e̲ or to set
LTU in L̲o̲o̲p̲ ̲T̲e̲s̲t̲ ̲M̲o̲d̲e̲ or
to set
LTU as after Power-up by
R̲e̲s̲e̲t̲ ̲S̲i̲n̲g̲l̲e̲ ̲C̲h̲a̲n̲n̲e̲l̲ or
Test by
D̲i̲s̲a̲b̲l̲e̲d̲ ̲M̲o̲d̲e̲ and D̲i̲s̲a̲b̲l̲e̲
̲A̲f̲t̲e̲r̲ ̲O̲n̲e̲ ̲R̲u̲n̲ used by LTU
to set D̲i̲s̲a̲b̲l̲e̲ ̲C̲h̲a̲n̲n̲e̲l̲ ̲after
power-up.
Between Message transmission the LTU transmits
idle-pattern of all zero'es (1875 hz)
GROUPWORK Introduction and separation into groups.
Approach: as described previously
Time: 2 lessons
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HAWK TRAINING 2.19-21 LT/830228
MBDL LTU L/GW/DI HAWK
Page 5…0e…
RECOLLECTION Each group presents their results.
S̲i̲g̲n̲a̲l̲ ̲f̲l̲o̲w̲ Main Bus Interface, Modem Interface, Processor.
M̲a̲i̲n̲ ̲B̲u̲s̲ ̲I̲n̲t̲e̲r̲f̲a̲c̲e̲:̲ Main Bus Driver/Receiver (̲M̲D̲R̲)̲,
Main Bus Control Decoding (̲M̲C̲D̲)̲,
Module Address Comparator (̲M̲A̲C̲)̲
P̲r̲o̲c̲e̲s̲s̲o̲r̲ ̲o̲r̲ ̲C̲o̲n̲t̲r̲o̲l̲:̲ Micro Processor Unit (̲M̲P̲U̲)̲,
MPU Registers (̲M̲P̲U̲ ̲R̲E̲G̲)̲,
Baud Rate Generator (̲B̲R̲G̲)̲,̲
Channel Number Latch (̲C̲N̲L̲)̲,
Halt Logic (̲H̲L̲)̲.̲
M̲o̲d̲e̲m̲ ̲I̲n̲t̲e̲r̲f̲a̲c̲e̲:̲ Line Receiver (̲L̲R̲)̲,̲
Synchronization (̲S̲)̲,̲
Line Transmitter (̲L̲T̲)̲
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HAWK TRAINING 2.19-21 LT/830228
MBDL LTU L/GW/DI HAWK
Page 6…0e…
M̲o̲d̲e̲m̲ ̲I̲n̲t̲e̲r̲f̲a̲c̲e̲ 4 sections - one to each channel - all
connecting via the 48-pole connector.
L̲R̲:̲ receives either the 4 external Lines or
the 2 internal lines used when LTU-Loop is
selected by IES-signal from MPU.
S̲:̲ receives the signals from LR.
Using a clock 16 times faster than bit rate
and a counter ensuring bit-sync.
Status of reception (2-bits),
transmission (2 bits) control lines (2 bits)
and data (1-bit) is transferred to MPU REG
via IBUS.
Data = bit by bit.
L̲T̲:̲ receives data (1-bit),
midfreq. (1-bit)
modem control signals (2-bits) via IBUS.
TxB and TMF are synchronized to BR (baudrate
750).
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HAWK TRAINING 2.19-21 LT/830228
MBDL LTU L/GW/DI HAWK
Page 7…0e…
C̲o̲n̲t̲r̲o̲l̲ B̲R̲G̲:̲ X-tal controlled oscillator of 3.072
Mhz. divided into BR (750 Hz) and 16xBR(12Khz).
C̲N̲L̲:̲ Stores the channel number in service,
told by MPU,
ch.no. sent to MPU REG which generates control
signals to the MIF 0/1/2/3.
M̲P̲U̲:̲ 1024 x 16 Program Prom and a Interpreter
sends out instructions on the IVB (bus).
M̲P̲U̲ ̲R̲E̲G̲:̲ RAM of 256 x 8 bit in 4 parts
one to each channel where the messages are
assembled and disassembled
and address registers to the MPU.
A register holding control signals is contained.
H̲L̲:̲ upon TRQ halts the processor for Mainbus
access.
M̲a̲i̲n̲ ̲B̲u̲s̲ ̲I̲n̲t̲e̲r̲f̲a̲c̲e̲ M̲A̲C̲:̲ Module address in a switch,
when address compare ITRQ to MCD.
M̲C̲D̲:̲ acts upon CPU access request,
initiates halts, generates response,
receives R/W.
M̲D̲R̲ receives/transmits data.
Receives memory (RAM) address.
P̲r̲o̲g̲r̲a̲m̲ Once started it runs for 1.2 msec.
Runs within time slots of 1.3
msec.
A CPU-access uses approx. 1 usec.
Max CPU accesses within a program
run = 100.
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HAWK TRAINING 2.22-23 LT/830228
MBDL MODEM I/F L/GW/DI HAWK
Page 1…0e…
GENERAL Modulator and Demodulator of line signal
Interfaces MBDL LTU logic signals
Interfaces MBDL line in FSM 1125/1500/1875
Hz
Transfer rate: 750 baud - asynchronous
full duplex
Modem controlled by LTU
2 identical channels
GROUPWORK Introduction and separation into gropus
Approach: as described previously
Time: 1 lesson
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HAWK TRAINING 2.22-23 LT/830228
MBDL MODEM I/F L/GW/DI HAWK
Page 2…0e…
RECOLLECTION Each group presents their results.
GENERAL Interfaces between MBDL LTU and via Line Panel
AN/TSQ-38 or Danish Center.
Serve 2 channels of the 4-channel LTU and
2 lines to BOC (TSQ-38/DC).
750 baud-async-full duplex.
Each channel consist of a demodulator/modulator.
M̲a̲i̲n̲ ̲B̲u̲s̲:̲ +5VDC, +/-12VDC, GND.
P̲o̲w̲e̲r̲ ̲D̲e̲t̲e̲c̲t̲i̲o̲n̲:̲ Gren LED is Lit when +/-
12V, +5 are OK.
M̲o̲d̲u̲l̲a̲t̲o̲r̲ L̲o̲g̲i̲c̲,̲ ̲Rate Multiplier (̲R̲M̲)̲,
X-tal osc (̲X̲O̲)̲;
Sine Table Prom (̲S̲T̲P̲)̲,̲
D/A Converter (̲D̲A̲C̲)̲,
A̲m̲p̲,̲ C̲D̲S̲T̲L̲ ̲S̲w̲i̲t̲c̲h̲,
L̲o̲g̲i̲c̲:̲ ̲receives data in serial from LTU and
synchronizes it with 1.6 Mhz.
R̲M̲:̲ using the XO of 6.5 Mhz
it will generate frequences of 576/960/768
Khz
from the inputs of the LTU Mark/Space/Mid.
S̲T̲P̲:̲ is a PROM with 32 entries which is
scanned during a bit-transmission time
(1.33 ms)
(Ma/Sp/Mi) 1.5/2.5/2.0 times,
giving 48/80/64 digital values to the
DAC.
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HAWK TRAINING 2.22-23 LT/830228
MBDL MODEM I/F L/GW/DI HAWK
Page 3…0e…
D̲A̲C̲:̲ converts the digital values into analog
values creating step-like sinewaves
of
1.5 wave of Markfreq. 1125Hz,
2.5 wave of space-freq. 1875 Hz,
and 2.0 wave of Midfreq. 1500 Hz.
A̲M̲P̲:̲ ensures unity gain and 600 OHM impedance
if connect Data Set to Line is enabled
by LTU.
D̲e̲m̲o̲d̲u̲l̲a̲t̲o̲r̲ L̲o̲g̲i̲c̲,̲ Phase Locked Loop And Detector (PLL),
Digital Filter (̲D̲F̲)̲,̲
Window Comparator (̲W̲C̲)̲.̲
P̲L̲L̲:̲ if LTU has not chosen S̲e̲l̲e̲c̲t̲ ̲L̲o̲o̲p̲,
in which case data will be from Modulator,
data will through an i̲n̲p̲u̲t̲ ̲a̲m̲p̲ and
B̲a̲n̲d̲ ̲p̲a̲s̲s̲ ̲f̲i̲l̲t̲e̲r̲ go to PLL
which is a free-running OSC adj to
1500 Hz,
giving error voltage if any other frequence
is applied
resulting in a high at Mark and Low
at Space.
Carrier Detect comes on when PLL is
locked
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HAWK TRAINING 2.22-23 LT/830228
MBDL MODEM I/F L/GW/DI HAWK
Page 4…0e…
W̲C̲:̲ no error voltages is generated by Mid
freq.
To detect: Midfreq. is filtered and
compared in a window to Mark/Space.
D̲F̲:̲ due to changes from Mark to Space and
visa versa causes erroneous Midfreq.
detection
the signal sends through a delay circuit
to be sure that they last more than
1.25 ms (bit time: 1.33ms)
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HAWK TRAINING 2.24 LT/830228
POWER SUPPLY L/GW/DI HAWK
Page
1…0e…
Provides +5V/32A, +12V/1.8A, - 12V/1.2.A.
Input 220V AC +10/-15% from Power Distribution Panel.
+5V Primary switching type.
Operates directly on the rectified mains voltage
(full wave).
A pulse-width-modulated power stage
switches this DC-voltage at 20 Khz,
stepped down by a transformer - rectified
- smooted.
C̲O̲N̲T̲R̲O̲L̲ compares output to an internal reference
voltage to control inputs-width for correct
output.
The voltage drop over the current resistor
is compared to an internal reference
- if too great the impuls-width is reduced
- the voltage drops.
Voltage adjust 4.5 - 5.8.
Over voltage: 6.7 - 7.3.
+/-12v needed for IC's.
+12v Secondary switching type.
Supplied from fullwave rectified transformer
output - 32v.
Conventional impuls-width-modulated regulators
of 50 Khz.
Overvoltage: 13.6 - 15.4v (+12V)
-12v - " - : 14.3 - 16.0v (-12V)
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HAWK TRAINING 2.24 LT/830228
POWER SUPPLY L/GW/DI HAWK
Page 2…0e…
Front 0.63A fuse -main fuse
3.15 A fuse - +5v fuse
Switch for the module input
Rear small hole for +5v adjust.
Power Panel Power supply is supplied from power distribution
panel via POWER PANEL with 220V.
ON/OFF switch
Fuse: 5A
JACK: connects to power distributuion panel
M̲a̲i̲n̲s̲ ̲F̲i̲l̲t̲e̲r̲ 4̲ ̲v̲e̲r̲s̲i̲o̲n̲s̲ (at the moment)
220 v/50 Hz
120 v/60 Hz
240 v/50 Hz
120 v/220v 60 (50) Hz counter only 60 Hz
C̲o̲n̲t̲e̲n̲t̲s̲:̲ Circuit Breaker (auto fuse)
Power Indicator
Time Counter
Transformer
Output filter
220 v/50 Hz - no transformer
120v/220 v - extra switch 120/220
to bypass transformer
in 220 v.
Connects: At the rear through 1 of 2 plugs
to Power distribution panel depending
on which half is utilized.
F̲a̲n̲
220v AC Blower + airfilter
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HAWK TRAINING 2.24 LT/830228
POWER SUPPLY L/GW/DI HAWK
Page 3…0e…
P̲o̲w̲e̲r̲ ̲D̲i̲s̲t̲r̲i̲b̲u̲t̲i̲o̲n̲ ̲P̲a̲n̲e̲l̲
7 extension outlets:
1 for operators panel
2 for power supplies upp/low crate
1 for fan
1 for crypto rack
1 for test box
1 spare
P̲o̲w̲e̲r̲ ̲D̲i̲s̲t̲r̲i̲b̲u̲t̲i̲o̲n̲ ̲P̲a̲n̲e̲l̲ ̲i̲n̲ ̲C̲r̲y̲p̲t̲o̲ ̲R̲a̲c̲k̲
9 extension outlets:
8 for cryptos, one to each
1 spare
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HAWK TRAINING 2.25-27 LT/830228
TEST BOX L/GW/DI HAWK
Page 1…0e…
A selfcontained unit with CPU, Power Supply,
Keyboard, and Display.
Connects to 220 VAC
Operates the off-line testprogrammes
via the SCM front connector, V24, in 1200
baud transfer.
T̲e̲s̲t̲s̲ 8 tests stored in the PROM of the Test Box
to test the modules:
SCM - CPU - RAM - PROM - AV24 - ATDL LTU/MODEM
- MBDL LTU/MODEM - OPERATORS PANEL.
Each of the tests can be loaded to the AMC,
where it is executed and the
result is returned to the Test box display.
V̲2̲4̲:̲ Loop Back Plug needed
O̲.̲P̲:̲ Operators' action needed
C̲o̲n̲n̲e̲c̲t̲/̲U̲s̲e̲ Power Cable and V24 cable connected.
Power On.
Local/On Line in On Line.
Press Reset: Enter Data and Run flashes
Press Test/Inc: Run comes on.
Press MC on AMC: Run turns off.
Enter testnumber on Keyboard: displayed at
Test/Address
Press Run:
Error/Data displays 0001 = Loading
- " - 0002 = end load
- " - 0000 = executing
- " - XXXX = result code
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HAWK TRAINING 2.25-27 LT/830228
TEST BOX L/GW/DI HAWK
Page 2…0e…
Result code if OK = checksum or FFOO (depending
on test)
U̲ ̲ ̲ ̲V̲ X̲ Y̲
…0e… ̲ ̲ ̲…0f… may be a failing part of
the test
…0e… ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲…0f… local action cause code
…0e… ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲…0f… normal FF. In LTU: special
meaning
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HAWK TRAINING 2.28-30 LT/830228
MAINTENANCE TECHNICS L/DI HAWK
Page
1…0e…
GENERAL Preventive and Corrective Maintenance.
Procedures for aid: (step-by-step).
MAINTENANCE
MANUAL p. 6 M̲o̲n̲t̲h̲l̲y̲ ̲M̲a̲i̲n̲t̲e̲n̲a̲n̲c̲e̲:̲
p. 5 a. Daily Check
p. 6 b. Fan Unit Check
p. 7 c. Power Supply Check
p. 8 F̲a̲u̲l̲t̲ ̲I̲s̲o̲l̲a̲t̲i̲o̲n̲ ̲a̲n̲d̲ ̲C̲o̲r̲r̲e̲c̲t̲i̲o̲n̲:̲
p. 9 a. Power On Indicators
p. 12 b. Fan Unit
p. 13 c. General Checkout
p. 17 d. Verification Test
Test Box Man. P. 12 General Checkout and Verification Test requires
the use of AMC Test Box and Test procedures.
Test Tools Extension module board
Multimeter
Loop back plug for ATDL
FAULT ISOLATION A faulty condition may appear during operation
or checkout.
Due to the vital need of the AMC, it is important
to isolate and correct a fault quickly.
Make as many observations as possible.
Try to establish how many modules and submodules
can be involved.
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HAWK TRAINING 2.28-30 LT/830228
MAINTENANCE TECHNICS L/DI HAWK
Page 2…0e…
METHODS Indications on Operator Panel and AMC-rack
can reveil module(s) in error.
Looping the MBDL at BOC/DL end can separate
the area.
Looping the ATDL at ADTL Line Panel can isolate
the area.
Swapping modules - remember switch setting
- and link connection (also Crypto) can isolate
the area.
Running the module tests isolates the area.
Attempting to initiate system and links may
point to the error.
PROCEDURES Fault Isolation and Correction procedure as
well as the other procedures can be of great
help to isolate the fault.
Use the procedures - but do not forget to
think - they are only aids.
HAWK TRAINING 3.1-3 LT/830228
CHECKOUT EXERCISES H HAWK
…0e… 1
Introduction Separate into groups
At AMC Do MONTHLY
MAINTENANCE
Do GENERAL CHECKOUT
Students use own manuals:
USER MANUAL
MAINTENANCE MANUAL
TEST BOX MANUAL
All test tools needed.
In class Each group goes through all mentioned
procedures in theory.
All questions and doubts will
be explained by instructor.
HAWK TRAINING 3.4-21 LT/830228
FAULT ISOLATION PRACTICE H HAWK
…0e… 1
Power supply 1 3.15 A fuse at front of P.S to
be removed.
I̲n̲d̲.̲: +5V LED on P.S = out
LED on crate-module = out
Power 1 On-board
fuse on
any module
unsoldered.
I̲n̲d̲.̲: Module LED = out
(LTU's = 4 Link errors)
HAWK TRAINING 3.4-21 LT/830228
FAULT ISOLATION PRACTICE H HAWK
…0e… 2
ATDL LTU 1 Tape on both sides of LTU mainbus
connector pin 15-30.
I̲n̲d̲.̲: "SYSTEM INIT" on = 4 Link
errors
on-corresponding to LTU.
(Right LTU selected-test 5 executed-
result = 2F3F)
2 Set module address switch to
invalid
address
I̲n̲d̲.̲: as ex.1.
HAWK TRAINING 3.4-21 LT/830228
FAULT ISOLATION PRACTICE H HAWK
…0e… 3
ATDL MODEM 1 Swap 1 modem with blind panel
I̲n̲d̲.̲: 2 Links out at initialization
Can be found with test 5.
2 Remove chip no F1 (F7). One channel
out.
I̲n̲d̲.̲: 1 ATDL Link error.
Can be found with test 5.
3 3 x 16 connector: pin 13a shorted
to 15b
I̲n̲d̲.̲: 1 Link out.
Can be found with test 5.
ATDL LINE 1 If Loop Back Plug in use: mount
one
Loop Back Plug with 1 wire cut
If Live Link in use, disconnect
somewhere invisible to the student.
I̲n̲d̲.̲: 1 ATDL Link error after
initialization. Test 5 OK.
HAWK TRAINING 3.4-21 LT/830228
FAULT ISOLATION PRACTICE H HAWK
…0e… 4
MBDL LTU 1 Tape on both sides of LTU mainbus
connector pin 15-30.
I̲n̲d̲.̲: "SYSTEM INIT" on = 4 Link
errors
on-corresponding to LTU.
(Right LTU selected-test 6 executed-
result = 2F3F)
2 Set module address switch to
invalid address.
I̲n̲d̲.̲: as ex. 1.
HAWK TRAINING 3.4-21 LT/830228
FAULT ISOLATION PRACTICE H HAWK
…0e… 5
MBDL MODEM 1 Swap 1 modem with blind panel.
I̲n̲d̲.̲: 2 Links out at initialization
Can be found with test 6.
2 Remove chip no. E15(F21). One
channel out
I̲n̲d̲.̲: 1 MBDL Link error
Can be found with test 6
3 3 x 16 connector: pin 15b shorted
to 16a
I̲n̲d̲.̲: 1 Link out
Can be found with test 6
MBDL LINE 1 Break Loop Invisible to student
by disconnecting.
I̲n̲d̲.̲: 1 MBDL Link error after
initialization. Test 6 OK.
HAWK TRAINING 3.4-21 LT/830228
FAULT ISOLATION PRACTICE H HAWK
…0e… 6
PROM 1 Remove chip no (any prom)
I̲n̲d̲.̲: O.P. = FFFFF (flashing)
RAM 1 Module address switch set to
invalid address.
I̲n̲d̲.̲:
SCM 1 Short MC-switch
I̲n̲d̲.̲: Baud Rate display Blanked
2 Remove chip no (prom)
I̲n̲d̲.̲:
CPU 1 Remove chip no (prom)
I̲n̲d̲.̲:
HAWK TRAINING 3.4-21 LT/830228
FAULT ISOLATION PRACTICE H HAWK
…0e… 7
Operators 1 Swap flat cables position UC12/UD12
Panel in O.P.
at door.
I̲n̲d̲.̲: wrong display-no keyboard
action possible.
HAWK TRAINING 3.25-27 LT/830203
PRACTICAL TEST H, DE HAWK
…0e… 1
General Each student is asked to locate
malfunctioning module.
The fault will be placed by the
instructor.
The instructor will be at the
AMC during all 3 lessons for
guidance of the student.
In class During the time students are
not attending the exercise they
will review handouts, notes and
manuals on their own.
HAWK TRAINING 3.28-30
LT/830303
FINAL TEST AND EVALUATION T,
DI HAWK
…0e…
1
Test Final Students are asked to go through
a
Test written test of 18 questions.
Time allowed: 45 min.
The questions are to be answered
individually without help from
other students.
Answer sheet is part of student
handout.
Evaluation Instructor make a copy of each
answer sheet. (If no copies can
be made - number of answers right
and wrong will be noted after
evaluation).
Students exchange answer sheet
with student next to him and
mark the answers with right/wrong
as the instructor goes through
the answers.
Course HO Students
are asked
to answer
the
Evaluation Name questions on the Course Evaluation
List and to feel free to give any
critic of any subjects or circumstances
related to the course.
Critic may also be discussed
immediately with instructor.
Students are asked to put their
name and address on the Name-list
so CRAS can mail a Course Certificate
to them.
F̲I̲N̲A̲L̲ ̲T̲E̲S̲T̲
1. Which voltages are available at the backplane?
+5VDC, +12VDC, -12VDC.
2. How many power supplies are in the AMC?
3: upper and lower crate and Operator Panel.
3. How many bits of data can be transferred at one time
by the mainbus?
16(18): 16 bits of data + 2 bits of parity.
4. Where are the system clocks generated?
In the SCM-module.
5. How will the CPU know that a LTU has data ready to
be fetched?
The CPU as a routine fetches the Rx/Tx Control
Bytes and checks the contents. When the Rx Control
Byte has a bit set for Rx Buffer Full data is
ready for CPU. Known as polling.
6. What are the frequencies of the clocks available at
the backplane?
1,2,4 and 8 Mhz.
7. What is the transfer speed of the ATDL Link?
1200 Baud.
8. What is the transfer speed of the MBDL Link?
750 Baud.
9. In what module(s) is the database stored?
32 K-word RAM-module.
10. In what module(s) is the AMC-programme stored?
4 K-word PROM-module and 12 K-word
SCM-module.
11. What is the purpose of the V24-module?
Communicate with Operators Panel and
Mainbus (CR80) or interface between
CPU (mainbus) and Operators Panel.
12. In what form is data transferred between LTU and Modem
in the MBDL Link. Serial or parallel?
Serial.
13. What module generates the control signals for the MBDL
Modem?
MBDL LTU.
14. What module generates the speed controlling signal
of the transfer between ATDL LTU and ATDL Modem when
not in internal loop mode?
ATDL Modem. RSET + TSET.
15. What module generates the speed controlling signal
of the transfer between MBDL LTU and MBDL Modem when
not in internal loop mode?
MBDL LTU.
16. During normal operation the ATDL LINK ERROR lamp for
Link F is flashing. Explain the condition of the Link.
The Link is disturbed by noise. Only some of the
messages are lost - some are accepted.
17. All green LEDs of the modules in the lower crate are
out, and the green LED on the lower crate power supply
for +5V is out. All other indications are normal. What
is the first thing you will check?
The 3.15 amp fuse located at the front of the
lower crate power supply.
18. What indication(s) will show that you have the AMC-programme
ready after power-up?
"SYSTEM INIT" on the Operators Panel is on.
