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J…06…I…0a…I…0d…I…00…I
I…07…H…0a…H…0e…H
G…08…G…0e…G…01…F…09…F…00…F…06…E…0a…E
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…02… …02… …02… …02… …86…1 …02… …02… …02… …02…
…0e…
CAMPS Instructor's Manual for
MT/RST Course, Week 4
CPS/TMA/007
CDRL Logistics Support No. 03A
Line Item 8.2.4-B
Niels-Erik Nielsen
Kurt Nybroe-Nielsen
SHAPE (2), NEN, LT,
ER[, ALG, Conf. Mgmt., LU
ILS Train.Mgr. 840620
2
840620
Conf.Mgmt. 840620
2793A/rt …02… CPS/TMA/007
…02… NEN/840620…02……02…ii
CAMPS Instructor's Manual for
MT/RST Course, Week No. 4…02… Issue 1…02… CAMPS
821008 All Preliminary Issue of
Document
1 830617 All Completely new update
of
manual
2 840620 All Completely new update
of
the manual in accordance
with CPS Log.No. 1434,
831021.
…86…1
…02… …02…
…02…
…0e… 2793A/rt
840620
TDX SYSTE STRUCTURE 4:1:1 45
CAMPS…0f…
Describe the TDX SYSTEM STRUCTURE:
- TDX SYSTEM PERFORMANCE
- TDX SYSTEM DEVICES (SHORT FORM)
State the DEVICE NOs.
Evaluation of practice
in Lesson 4:1:4-6.
Revision at progress test,
question 1,3,5 & 6
Classroom
L
Black board, 7 OHs
STB I: Section 5
…0e… 2793A/rt
840620
TDX DATA OMMUNICATION 4:1:2 45 CAMPS…0f…
Describe the TDX DATA COMMUNICATION
- UPPER BUS/LOWER BUS TRANSFER
- DATA FRAME FORMAT
- DEVICE POLLING
Revisio at progress test, question 7
Classroom
L
Black board, 4 OHs
HBK: Section 8.2.…86…1 …02… …02…
…0e… 2793A/rt
840620
TDX TRANSISSION 4:1:3 45 CAMPS…0f…
Recognize the 3 protocol levels
Describe the SPL-D CODE FORMAT
Revision of progress test, question 2 & 4
Classroom
L
Blackboard, 2 OHs
HBK: Section 8.2.2 & 8.3
STB I: Section 6…86…1 …02… …02…
…0e… 2793A/rt
840620
DEMONSTRAION OF THE 4:1:4-6 3x45 CAMPS
…0e…TDX SYSTEM,SLM & HWB…0f…
Locate all TDX SYSTEM MODULES and
POWER SUPPLIES.
Find the TDX SYSTEM related sections
in he SLM & HWB.
Evaluation at lab. exercises during
this week.
Revision at progress test, question 3
Training room
Classroom
DE, I, DI
Training System
-4:1:1:OH 5-7
-SLM
-HWB
…86…1 …02… …02…
…0e… 2793A/rt
840620
TDX CONTRLLER 4:2:1-2 2 x 45 CAMPS…0f…
State the MODULE Location
Describe the performance
Recognize the block diagram
State the Front panel LED
State the front panel connections
State the back panel connections
Perform the MODULE SET UP
Describe the BIT
Evaluation at the lab. exercises
in lesson 4:2:4-6 (TDX SYSTEM STATUS TEST)
Revision at pogress test
question 8 & 9.
Classroom
L
7 OHs
STB II: Section 20
…86…1 …02… …02…
…0e… 2793A/rt
840620
TDX HOST /F (STI/TIA) 4:2:3 45 CAMPS…0f…
State the Location of the MODULES
Describe the performance of the MODULES
Recognize the block diagrams
State the fron panel LEDs
State the function of the front panel switches
State the front panel connections
State the back plane connections
Perform the MODULE SET UP
Describe the BIT
Evaluation at the lab. exercises
in lesson 4:2:4-6 (STI TEST)
Revsion at progress test,
question 11 & 12.
Classroom
L
11 OHs
STB II: Section 18 & 19
…86…1 …02… …02…
…0e… 2793A/rt
840620
TDX SYSTEM TATUS TEST, 4:2:4-6 3x45 CAMPS
…0e…BOOT UP PROCEED. & STI TEST…0f…
- Fullfill an ERROR FREE "TDX SYSTEM STATUS TEST"
(See OBJECTIVES, SLG 4:2:4-6: page 1)
- Perform the M&D TEST "BOOT UP PROCEDURES
(See OBJECTIVES, SLG 4:2:4-6: page 2)
- Fullfill an ERROR FREE "STI TEST"
(See OBJECTIVES, SCG 4:2:4-6: page 4)
- During practical exercise.
- During evaluation of th exercise.
- The students must have performed all exercises.
Training room
GW, DI, EX
- Training system with VDUs connected to both of
the MIAs
- TDX CONTROLLER CABLE
- M&D TEST DISK PACK and M&D TEST FLOPPY
- DISKETTES -
SLG
4:2:4-6
(4
pages)
- SLM: Section 4.3.3.4, 4.7.2.1.8 & 4.7.2.2.
- 4:1:1:OH5-7
…86…1 …02… …02…
…0e… 2793A/rt
840620
BM-X 4:3:1 45 CAMPS…0f…
State the MODULE LOCATION
Describe the performance
Recognize the block diagram
State the front panel LEDs
State te function of the front panel switches
State the front panel connections
State the back plane connections
Perform the MODULE SET UP
Evaluation at the lab. exercises in
lesson 4:3:4-6 & 4:4:4-6
Revision at progress test, question 10
Classroom
L
6 OHs
STB II: Section 21…86…1 …02… …02…
…0e… 2793A/rt
840620
LUX-S 4:3:2 45 CAMPS…0f…
State the MODULE LOCATION
Describe the performance
Recognize the block diagram
State the front panel LEDs
State th function of the front panel switches
State the front panel connections
State the back plane connections
Perform the MODULE SET UP
Describe the BIT.
Evaluation at the lab. exercises in
lesson 4:3:4-6.
Revision at progress test, question10
Classroom
L
5 OHs
STB II: Section 22…86…1 …02… …02…
…0e… 2793A/rt
840620
L/L ADPTORS & OPTO T/R 4:3:3 45 CAMPS…0f…
Describe the L/L ADAPTORS & OPTO T/R
- Performance
- Main functions
- Applications
State the front panel LEDs
Evaluation at the lab. exercises in
lesson 4:4:4-6 & 4:5.4-6
Revision at progress test, question 13 & 14
Classroom
L
5 OHs
-LESSON 6:3:1-2
-SLM: Section 4.5.5
…0e… 2793A/rt
840620
M&D TD SYSTEM TEST 4:3:4-6 3x45 CAMPS…0f…
- Fullfill an ERROR FREE "TDX BUS TEST"
(See OBJECTIVES, SLG 4:3:4-6: page 1).
- Fullfill an ERROR FREE "LTUX-S SATUS TEST"
(See OBJECTIVES, SLG 4:3:4-6: page 2)
- During practical exercise.
- During evaluation of the exercise.
- The students must have performed all exercises.
Training room
GW, DI, EX
SLG 4:3:4-6 (2 pages)
- Training system with VDUs connected to both of
the MIAs
- M&D TEST DISK PACK
- M&D TEST FLOPPY DISKETTES
- SLM: Section 4.7.2.1.8, 4.7.2.2 & 4.7.2.2.
- 4:1:1:OH5-7
…86…1 …02… …02…
…0e… 2793A/rt
840620
POWERSUPPLIES, BP8 & TSP 4:4:1 45 CAMPS…0f…
Describe the TDX power supplies and the power distribution
in the TDX crate
Describe the BP8 (Back Panel type 8) unctions
Describe the TSP (Temperature Sensor Panel)
No format check
Current questions
Classroom
L
Black board, 2 OHs
-SLM: Section 4.5.4 & 4.5.5
-STB II: Section 26 & 29…86…1 …02… …02…
…0e… 2793A/rt
840620
TDX CRATE, WALL OUTLETS 4:4:2 45 CAMPS…0f…
- Describe the TDX Crate functions
- Describe the TDX CABLES
- Describe all cable connections and the module positionig
in the TTX crates
- Describe the WALL OUTLET functions
No formal check
Current questions
Classroom
L
Black board, 8 OH's
SLM: Section 4.5.4
HWB: Section 3
…0e… 2793A/rt
840620
CCA FUNCTINS OF THE BSM-X 4:4:3 45 CAMPS…0f…
- Describe the CCB communication principles
- Recognize the CCA functions of the BSM-X
Evaluation at exercise in Lesson 7:1:4-6
- The students must perform the exercise
No. 2, described in SLG 7:1:4-6
Classroom
L
12 OHs
Black board
SLM: Section 4.5.4
…0e… 2793A/rt
840620
M&D TDX SSTEM TEST 4:4:4-6 3x45 CAMPS…0f…
- Fullfill an ERROR FREE "TDX LTUX TEST"
(See OBJECTIVES, SLG 4:4:4-6: page 1).
- Fullfill an ERROR FREE "TDX LOOP TST"
(See OBJECTIVES, SLG 4:4:4-6: page 2)
- During practical exercise.
- During evaluation of the exercise.
- The students must have performed all exercises.
Training room
GW, DI, EX
- Trainng system with VDUs connected to both of
the MIAs
- M&D TEST DISK PACK &
- LOOP BACK CONNECTOR FOR V24 L/L ADAPTOR & OPTO
- T/R
- SLG 4:4:4-6 (2 pages)
- SLM: Section 4.7.2.1.8, 4.7.2.2
- 4:1:1:OH5-7
…86…1 …02… …02…
…0e… 2793A/rt
840620
PROGRES TEST 4:5:1-3 3x45 CAMPS…0f…
Evaluate his own comprehension of subjects taught in
this week.
The result of this test will be recorded in the "STDENT's
PROGRESS REPORT".
Correction of answers
Classroom
Progress test, duration 60 min.
Progress test, 4 pages (OH1-4, a copy for each student).
6 OHs
STBI, II & III
SLM…86…1 …02… …02…
…0e… 2793A/rt
840620
M&D TD SYSTEM TEST 4:5:4-6 3x45 CAMPS…0f…
- Fullfill an ERROR FREE "TDX VDU I/O TEST"
(See OBJECTIVES, SLG 4:5:4-6: page 1).
- During practical exercise.
- During evaluation of the exercise.
- The students must have performed all exercises.
Training room
GW, DI, EX
SLG 4:5:4-6 (2 pages)
- Training system with VDUs connected to both of
the MIAs
- M&D TEST DISK PACK
- M&D TEST FLOPPY DISKETTES
- SLM: Section 4.7.2.1.8, 4.7.2.2
- 4:1:1:OH5-7
…86…1 …02… …02…
-
2793A/aml 4:5:1-3
830928 1 of 2
PROGRESS TEST WEEK 4
CAMPS
NAME: ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ SCORE: ̲
̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲
1. How many LTUX-S DEVICES can e located in a
TDX CRATE?
2. How is the WATCH DOG connected to the TDX SYSTEM?
3. When does a TDX DEVICE transmit?
4. How can you get information about the TDX system
status? Does this action disturb the normal
function?
5. Wha does the number 122 in the command
DO TDX ̲VDU ̲IO122 refer to?
6. Can you exchange TDX CONTROLLERS without changing
anything else?
7. How is the TDX SYSTEM connected to the PROCESSOR?
8. What is the 5th line in the UMO indicating?
9. How can you check that an OPTO MODEM is functioning
correctly?
2793A/aml 4:5:1-3
830928
2 of 2
PROGRESS TEST WEEK 4
CAMPS
10. Which TDX DEVICE transmits on the LOWER BUS?
11. What is the BITRATE of the signal on the TDX
BSSES?
12. What is the function of the WALL OUTLET?
13. What is done to the TDX BUS to prevent reflection?
14. What happens if a DEVICE does not respond to
its
MUX NO.?
15. Does the WALL OUTLET get power from the TDX
BUS?
16. hat is the physical structure of a TDX BUS?
17. What happens if a DEVICE makes a transmission
error?
18. What is the purpose of the FLAG in TDX FRAME?
19. How many OPTO MODEMS can be connected to an
ADAPTOR POWER SUPPLY?
20. Is tere a TDX CONTROLLER in every TDX CRATE?
2793A/aml
ANSWERS TO PROGRESS TEST WEEK 4 830928
1 of 1
LESSON: 4:5:1-3
CAMPS
1. 2.
2. WATCH DOG is connected by the CCB BUS to BSMX-S.
3. When MUX NO. on LOWER BUS hit DEVICE O.
4. Connect a VDU set to 30 Baud to TDX CONTROLLER
and type S and CR. No.
5. 1 2 2
LTUX-S No. in TDX CRATE CHANNEL No.
of LTUX-S.
6. Yes.
7. Through STI/TIA module.
8. IO odule in PU CRATE, which is the STI module.
9. By doing loop test. A loop is mounted on the
OPTO MODEM.
10. TDX CONTROLLER.
11. 1.8432 MHz.
12. It connects the device to TDX BUS.
13. The twisted pair are terminated by 100 ohm.
14. fter 16 scan of MUX TABLE, 3 scan sending out
test
frame and then if no respons the DEVICE is
skiped
on the MUX TABLE.
15. No, from DEVICE.
16. Two sets of twisted pair, each pair shieldet.
17. The DEVICE is asked to retransmit.
18. t indicates the start of a FRAME.
19. 4.
20. No. There is only 2 TDX CONTROLLERs, one per
TDX BUS.
…0e… 2793A/rt
840620
TROUBLESHOTING 4:5:4-6 3 x 45
CAMPS…0f…
- Isolate and remedy TDX system faults at module
level
- During evaluation of the troubleshooting
raining room
GW, DI, EX
Training System
…0e… 2793A/rt
MT/RST 4:1:1 840620
TDX SYSTEM STRUCTURE L
1…0f…
General TDX: T̲elecommunication D̲ata E̲xchange
A unique element of the CAMPS is the TDX
SYSTEM. I essence, the TDX SYSTEM handles
nearly entire complex of terminals and communication
lines with a minimum attention by the central
processor in increased processor throughput.
The TDX SYSTEM as a hole is a STAND ALONE
SYSTEM taking care of the dta communication
between the MAIN MEMORY of the CR80 and the
USER/OPERATOR POSITIONS (PERIPHERALS).
STRUCTURE and OH1-2 STB I, Section 5.
PERFORMANCE
DEVICES OH1-2 TDX DEVICES:
- TDX CONTROLLER (1 per. TDX BUS)
- STI/TIA (1 per. PU)
- LTUXS (max. 2 per TU)
BUS SWITCH OH1 The BSM-X MODULE is a BUS SWITCHING MODULE
MODULE and a MONITORING MODULE.
TDX UNITS OH 3 Max. 15 TDX UNITS (TU) per. TDX SYSTEM. (TDX
UNIT = TDX CRATE)
The BSM-X MODULE is the "HEAD GATE" of the
TU (BSM-X MODUE NO.).
TDX CONTROLLER One TDX CONTROLLER is asssigned to TDX
BUS #
LOCATION 1; the other TDX CONTROLLER is assigned to
TDX Bus # 2. The two TDX CONTROLLERS are
located in TV # 1 and TU # 4 respectively.
ADAPTORS OH3 4 serial V24 I/O CHANNELS er. LTUX-S. LOW
LEVEL ADAPTORS and OPTIC FIBER MODEM for
the I/O CHANNELS ARE located in
OH4 the FRONT MAGAZINE or BP8 BACK PANELS are
located in the REAR MAGAZINE.
BSM-X Connections to the two TDX BUSSES and the
CCB
PANEL via the BSM-X PANEL, hich is located in the
REAR MAGAZINE.…86…1 …02… …02… …02…
…02… …02…
…0e… 2793A/rt
MT/RST 4:1:1 840620
TDX SYSTEM STRUCTURE L
2…0f…
TSP The TEMPERATURE SENSOR (ADAPTOR) PANEL is
located in the REAR MAGAZINE.
POWER OH 3 The S in the FRONT MAGAZINE is used for the
SUPPLIES …02… POWER to the TDX CONTROLLER, BSM-X MODULE, and LTUX-S
MODULE(s).
OH 3-4 The PS in the REAR MAGAZINE is used for the
POWER to the LOW LEVEL ADAPTORS and OPTIC
FIBER MODEM located in the FRONT MAGAINE.
DEVICE NO. 3 Each TDX DEVICE has a unique DEVICE ADDRESS
(DEVICE ADDR.) (Device No.) in the TDX SYSTEM as follows:
̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲
̲ ̲
Black ^ TDX DEVICE ^ ADDR.AREA
^
Board ^ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲^̲ ̲ ̲ ̲ ̲ ̲(̲H̲E̲X̲.̲ ̲N̲O̲.̲s̲)̲ ̲
̲^̲
^ TDX CONTROLLER ^ [[
^
^ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲^̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲
̲^
^ STI/(TIA) ^ [̲1̲ - [C
^
^ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲^̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲
̲^
^ LTUX-S ^ [D - FE
^
^ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲^̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲
̲^
^ DUMMY ^ FF
^
^ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲^̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲
̲^
OH 5-7 The DEVICE ADDRESSES (DEVICE NO.s) used in
the CAMPS are shown (DECIMAL & HEXADECIMAL)
fr the LTUX-S modules in TU NO. 1-9.…86…1
…02… …02… …02… …02…
…02…
…0e… 2793A/rt
MT/RST 4:1:2 840620
TDX DATA COMMUNICATION L
1…0f…
TDX BUSSES OH1 Each TDX BUS consists
of an UPPER BUS (TWISTED
PAIR CABLE) and a LOWER
BUS (WISTED PAIR CABLE).
The STI/TIA and LTUX-S MODULES t̲r̲a̲n̲s̲m̲i̲t̲ on
the UPPER BUS and r̲e̲c̲e̲i̲v̲e̲ from the LOWER
BUS.
The TDX CONTROLLER r̲e̲c̲e̲i̲v̲e̲s̲ from UPPER BUS
and t̲r̲a̲n̲s̲m̲i̲t̲s̲ on the LOWER BUS.
MUX.TABLE OH1 The MUX. TABLE on the TDX CONTROLLER is a
DVICE POLLING TABLE, the contents of which
are the DEVICE NO.'s of the TDX SYSTEM.
By the POLLING SEQUENCE these DEVICE NO.s
(named MUX.NO.s) in the row they are set
up will represent, which LTUX-S or STI/TIA
is allowed to transmit DATA.
MASTER O1 The TDX CONTROLLER contains the MASTER
CLOCK CLOCK GENERATOR of the TDX SYSTEM. The frequency
is 1.8432 MHZ.
SYNCHRONIZATION F̲R̲O̲M̲ ̲C̲O̲N̲T̲R̲O̲L̲L̲E̲R̲:̲
Contineous data stream on lower bus:
1.8432 Mbits/sec divided into 6400 timeslots
of 288 bits.
Black O̲n̲e̲ ̲T̲i̲m̲e̲s̲l̲o̲t̲:̲
Board
…0e… 2793A/rt
MT/RST 4:1:2 840620
TDX DATA COMMUNICATION L
2…0f…
HDLC FRAME The HDLC (H̲igh Level D̲ate L̲ink C̲ontrol) frame
length may differ from 200 bits (min) o 236
bits (max) due to "bitstuffing" (or each
five "1"'s an extra "0" is inserted). This
is used as an error detection feature.
One HDLC frame contains a total of 25 bytes
of 8 bits:
2 Flag bytes (01111110)
5 communication control bytes
1 data bytes
2 CRC bytes (C̲yclic R̲edundancy C̲heck)
skal der ikke v`re en side 1?
…0e… 2793A/rt
MT/RST 4:1:2 840620
TDX SYSEM THEORY L
2…0f…
LOWER BUS OH2 & 4 S̲T̲A̲R̲T̲ ̲F̲l̲a̲g̲ (1 byte)
FRAME FORMAT M̲U̲X̲.̲N̲O̲.̲ ̲1̲ ̲b̲y̲t̲e̲)̲: The MUX.NO. is a DEVICE
NO., which is generated in the controller
- it is taken from the MUX.TABLE. It indicates
which device is a̲l̲l̲o̲w̲e̲d̲ ̲t̲o̲ ̲t̲r̲a̲n̲s̲m̲i̲t̲ ̲d̲a̲t̲a̲
̲o̲n̲ ̲t̲h̲e̲ ̲u̲p̲p̲e̲r̲ ̲b̲u̲s̲ in the next timeslot. All
devices "look" at the MUX.NO., and the DEVCE
which recognizes its own NO. (= device addr.)
starts the transmission on the upper bus,
when having received bit 241 of the present
timeslot:
C̲R̲-̲I̲D̲ ̲(C̲hannel & R̲outing I̲dentifier)
2 bytes concerning DATA TYPE, HOST/MODE,
and DEVICE NO as folows.
D̲A̲T̲A̲ ̲T̲Y̲P̲E̲: Identifying v̲i̲r̲t̲u̲a̲l̲ ̲c̲h̲a̲n̲n̲e̲l̲
̲N̲O̲.̲ through which the data must be routed.
It does not necessarily correlate with
f.ex. the (four) physical channels in
a LTUX. It merely points to a specific
application.
Each LTUX-S MODULE is ble to separate
10 VIRTUAL CHANNELS as follows:
̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲
̲ ̲ ̲ ̲ ̲ ̲
^ ^
^
Black ^VIRTUAL ^ FUNTION
^
Board ^C̲H̲A̲N̲N̲E̲L̲ ̲N̲O̲.̲ ̲ ̲ ̲^̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲
̲ ̲ ̲ ̲ ̲ ̲^
^ [ ^ DATAGRAM between LTUX-s and
STI^
^ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲^̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲
̲ ̲ ̲ ̲ ̲ ̲^
^ 1 ^ DATAGRAM to TDX CONTROLLER
^
^ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲^̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲
̲ ̲ ̲ ̲ ̲^
^ 2-5 ^ 4 physical SERIAL I/O CHANNELS
^
^ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲^̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲
̲ ̲ ̲ ̲ ̲ ̲^
^ 6-9 ^ Not used in CAMPS
^
^ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲^̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲
̲ ̲ ̲ ̲ ̲ ̲^
H̲O̲S̲T̲/̲M̲O̲D̲E̲ ̲&̲ ̲D̲E̲V̲I̲C̲E̲ ̲N̲O̲.̲:̲ Describing the
SOURCE and DESTINATION DEVICES - for
the actual FRAME of DATA.
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MT/RST 4:1:2 840620
TDX SSTEM THEORY L
4…0f…
C̲O̲M̲M̲U̲N̲I̲C̲A̲T̲I̲O̲N̲ ̲B̲Y̲T̲E̲:̲ Used for information
in a packet transmissin (Packet=one or more
frames between two open (logical) channels)
f.ex. First/last frame in a packet.
C̲O̲N̲T̲R̲O̲L̲ ̲B̲Y̲T̲E̲: Frame sequence no. + no. of
data bytes in frame
F̲R̲A̲M̲E̲ ̲S̲E̲Q̲.̲N̲O̲.̲: In a packet transmission the
frames are sequentially numbered (eq.no.).
If the receiving device detects a jump in
seq.no.s, the frame is discarded and retransmission
is requested.
N̲O̲.̲ ̲O̲F̲ ̲D̲A̲T̲A̲ ̲B̲Y̲T̲E̲S̲: The actual number of data
bytes (max.16) in this frame.
Black PART OF ^ COMMUNICATION BYTE ^ FRAME
^ NUMBER OF ^
Board FRAME: ̲ ̲ ̲^̲ ̲M̲S̲B̲ ̲ ̲ ̲ ̲ ̲^̲ ̲ ̲ ̲ ̲ ̲ ̲L̲S̲B̲ ̲^̲ ̲S̲E̲Q̲.̲N̲O̲.̲
̲^̲ ̲D̲A̲T̲A̲B̲Y̲T̲E̲S̲ ̲^
^ ^ ^ ^
^
̲ ̲ ̲^̲ ̲S̲^̲S̲^̲S̲^̲S̲ ̲^̲ ̲S̲^̲S̲^̲S̲^̲S̲ ̲ ̲^̲ ̲Z̲^̲Z̲^̲Z̲ ̲
̲ ̲^̲ ̲W̲^̲W̲^̲W̲^̲W̲^̲W̲ ̲^
^ ^ ^ ^
^
^ACK/NACK ^ ^FRAME NO
^[[=NO BYTES^
^ + ^ ^IN PACKET^[1-1[…0f…HEX…0e…^
^FLOW CONTROL ^ ^
BYTES
^(RETURN TO ^=1-16…0f…DEC…0e…^
^SENDER
^"PIGGY-BACK")
^1 x 01 ^=FIRST FRAME
IN PACKET
^1 x 10 ^=LAST FRAME
^1 x 1 ^=FIRST and
LAST (only
^ ^ one)
^x 1 xx ^=BETWEEN
FIRST and
LAST FRAME
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MT/RST 840620
TDX SYSEM THEORY L
4…0f…
UPPER BUS OH3 & 4 A̲B̲O̲R̲T̲ ̲B̲Y̲T̲E̲: Dummy byte, No. MUX NO. in upper
bus rames because all the frames are t̲o̲ ̲t̲h̲e̲
̲T̲D̲X̲ ̲C̲T̲R̲L̲,̲ and the MUX.NO. is generated in
the TDX CTRL.
The rest of the frame is equal to the lower
bus frame format.
COMMUNICA- O̲N̲E̲ ̲C̲Y̲C̲L̲E̲: The TDX CTRL outputs a frame on
the LOWER
TION bus. M̲U̲X̲.̲N̲O̲.̲ inicates the device, which is
allowed to transmit on the upper bus. All
devices "look" at the M̲U̲X̲.̲N̲O̲.̲ and the C̲R̲-̲I̲D̲.
The device which recognizes its addr. in
the HOST/MODE or DEV. NO. fetches the frame.
Only the TDX CTRL receives the frame on the
uper bus.
If the HOST/MODE is [ the controller fetches
the frame (This might be a request for change
of bandwidth from a device) and transmits
a dummy frame on the lower bus (f.ex. diagnostic
frame). Change of BANDWIDTH is not used in
CAMPS.
Wenever the frame is n̲o̲t̲ destined for the
TDX CTRL, a MUX.NO. is inserted and the frame
is - without any further change - transmitted
on the lower bus in the next time slot.
DEVICE The MUX.NO. is fetched from the MUX.table
in
POLLING the TDX CTRL A device allocated a higher
bandwidth on the bus is represented more
frequently in the table than lower bandwidth
devices.
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MT/RST 4:1:3 840620
TDX TRANSMISSION L
1…0f…
PROTOCOL Black 3̲ ̲P̲r̲o̲t̲o̲c̲o̲l̲ ̲L̲e̲v̲e̲l̲s̲:̲
board
1: Physical level - Frame level All TDX
2: Link level - Packet level DEVICES
3: Network level - LDU level (only via HOST)
APPLICATION level
(LTUX-S)
(LDU = LOGICAL DATA UNIT (HBK,section 8.2.2))
LEVEL 1 Transmission of f̲r̲a̲e̲s̲ between TDX DEVICES:
- The FRONT END part of a TDX DEVICE performs
(for each frame): Bit stuffing, CRC byte
generation, ABORT and FLAG byte insertion,
parallel/serial conversion, and SPL-D
coding.
- Bus drivers transmit on UPPER BUS.
- Bu receivers on the TDX CONTROLLER then
transfer the frame to the MPCC which,
decodes SPL-D, converts serial/parallel,
removes ABORT and FLAG, deletes bit (stuffing),
checks CRC, reads DEV. NO., and inserts
MUX. NO., bitstuffing, CRC byte, flags,
par/ser. conv., SPL-D coding with internal
clock.
- Bus drivers transmit on lower bus.
- The TDX DEVICES receive and perform SPL-D
decoding, ser./par. conversion, bitstuff
deletions, flags removal, CRC check, reads
MUX. NO. and DEV. NO. The DEVICEwhich
recognizes the MUX. NO. is allowed to
transmit on upper bus. The DEVICE which
recogn. DEV. NO. transfers the frame to
the link level.
LEVEL 2 Transferred data packets are chopped into
HDLC frames. The firmware in the TDX DEVICE
perfrms the frame EN/DE-capsulation and the
error detection and correction on packet
level.
4:1:2 A packet is one or more frames transferred
page 3 between two devices. Any device which has
received a packet must return ACK/NACK.
Frames are receive errorfree from LEVEL 1
and accumulated into packets at LEVEL 2.
The first and the last frame in a packet
is indicated in the COMMUNICATION byte. The
bytecount and the continous frame count is
detected in the CONTROL BYTE (SEQ. NO. +
NO. OF DATA BYES). Any errors detected results
in rejection of the packet and request for
a retransmission by returning NACK.
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MT/RST 4:1:3 840620
TDX TRANSMISSION L
2…0f…
LEVEL 3 At LEVEL 3, the ingoing packets are routed
through VIRTUAL CHANNELS to the applicaton
routines in LTUX-S and the TDX HANDLER in
the HOST INTERFACE (STI).
CHANNELS 4:1:2 A VIRTUAL CHANNEL for a LTUX-S (10 channels)
OH 4 is identified in the DATA TYPE byte (4 bits)
of the frame.
A VIRTUAL for a HOST I/F is a combination
of theDATA TYPE and DEV. NO. (12 bits = 4096
channels).
VIRTUAL channel 0 and 1 are used entirely
for datagram messages such as diagnostics
and commands to OPEN and CLOSE channels.
An O̲P̲E̲N̲ channel is a channel with information
at LEVEL 3 about the EMOTE CHANNEL (= CR
ID).
Transfer of data can take place between any
two channels when opened.
The TDX handler opens and closes (creates
and dismantles loglines) the channels through
which datastreams may flow. Such is performed
at LEVEL 3.
The HOST INTERFACE transfers data in logical data units
(LDUs) which are a number of datapackets. At LEVEL
3 the LDUs are chopped into packets. Retransmission
may be requested for frames or packets, not for LDUs.
BANDWIDTH As one frame on the TD BUS transfers max.
(BW) 128 data bits (16 bytes x 8 bits) and a transfer
from a DEVICE only occurs when the DEVICE
NO. equals the MUX NO., then the bandwidth
of a DEVICE is directly related to the frequence
of the MUX NO.…86…1 …02… …02… …02…
…02… …02… …02…
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MT/RST 4:1:3 840620
TDX TRANSMISSION L
3…0f…
All the DEVICES in a specific system configuration
are allocated a certain BW which is prerogrammed
in the MUX table of the TDX CONTROLLER firmware
(PROM). The MUX. NO. of a high BW device
is written more frequently than a MUX. NO.
of a low BW device.
QUESTION What is the max. BW (theoretically) of the
TDX BUS?
ANSWER (16 data bytesx 8 bits x 6400 time slots/sec
= 819200 baud
BW SPEED LEVEL MUX TABLE
. . .
. . .
(EXPLAIN)
Only MUX. NO.s for DEVICES appended to the
bus (status READY) will be inserted in the
lower us frames.
BANDWIDTH OH 1 The bandwidth allocated to each device
ALLOCATION in the TDX system is determined by the MUX-table.
This table is configured as shwon on OH 1
with 14 speed levels. (HBK, Section 8.2.2.1)
Each time a frame is transmited on the lower
bus, a device-address is read from the MUX-table
in the location given by the "pointer to
next ADD" and used as MUX-No. The "pointer
to next ADD" is updated to the next "ADD",
which is either the next in the chain or
- in case it wa the last "ADD" in the speed
level chain - one of two possibilities: the
first "ADD" in the highest speed level or
the first "ADD" in the next lower speed level
dependent on the state of the FF, which is
complemented by each test. The MUX-table
shon on OH 1 will give following bandwidth-allocation
(please notice that not used speed levels
are not encountered).…86…1 …02…
…02… …02… …02… …02…
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MT/RST 4:1:3 840620
TDX TRANSMISSION L
4…0f…
BLACK AB - ABC -AB - ABCD - AB - ABC - AB - ABCDEFG
BOARD AB - ABC - AB - ABCD - AB - ABC - AB - ABCDEFGH
AB - ABC - AB - ABCD - AB - ABC - AB - ABCDEFG
AB - ABC - AB - ABCD - AB - ABC - AB -
ABCDEFGH (DUMMY)
This gives a reltive bandwidth on following:
BLACK A̲d̲d̲r̲e̲s̲s̲ R̲e̲l̲a̲t̲i̲v̲e̲ ̲B̲a̲n̲d̲w̲i̲d̲t̲h̲
BOARD
A, B 32
C 16
D 8
E, F, G 4
H 2
I, DUMMY 1
This entire cyclus is repeated ontinuously
and is called a scancyclus.
DECODER, On the TDX CONTR., on the LTUX-S, and on
the
ENCODER STI/T̲I̲A̲ a DECODER and an ENCODER is build
and in.
SPL-D CODE
OH2 When the above mentioned TDX DEVICE t̲r̲a̲n̲s̲m̲i̲t̲
on the TDX BUS, then the ENCODR will CODE
the OUTGOING bits with the CLOCK SIGNAL (1.8432
MHz) in a so-called SPL-D CODE (self clocking
differential split phase code).
When receiving from the TDX BUS the DECODER
will SEPARATE the SPL-DS CODE in bits and
clock.
The TDX CONR. contains the TDX SYSTEM CLOCK
GENERATOR (1.8432 MHz).
The clock used by the LTUX-S and TIA, when
transmitting, is derived from the respective
DECODER LOGIC.
In this way MESSAGE HANDLING in the TDX SYSTEM
is SYNCHRONIZED.…86…1 …02… …02…
…02… …02… …02…
…0e… 2793A/rt
MT/RST 4:1:4-6 840620
…0f…DEMONSTRATION OF THE
TDX SYTEM, SLM, and HWB…0e… DE, I, DI
1…0f…
TDX UNITS Show all the TDX UNITS related to the TDX
UNIT "NO.s.
TDX BUSSES Show the location of the two TDX CONTROLLERS.
Follow the cable from the "TDX BUS" connector
on the front panel of the TDX CONTROLLER
to the respective WALL OUTLET and then follow
the TDX BUS from TDX UNIT to TDX UNIT and
PU.
Exlain the relation between the BSM-X "MODULE
NO.s" and TDX UNIT "NO.s".
TDX DEVICES Show the location of the LTUX-S modules and
the STI/TIA modules.
Explain the relation between the LTUX-S "DEVICE
NO.s" and the TDX UNIT "NO.s".
Take out a LTX-S module from a TDX CRATE
and show a DIP SWITCH.
NOTE! - Always POWER OFF when removing or
inserting MODULES in TDX CRATES.
ADAPTORS Show the location of L/L ADAPTOR, OPTO T/R,
& PANELS BP8, TSP and BSM-X panel and explain the
relation to ther TDX modules, BUSSES and
PERIPHERALS.
PS Show the location of the PS and explain the
application of PS in front magazine and PS
in rear magazines.
PORT ID Go to the SUPERVISOR POSITION and SIGN ON
to ENGINEERING FUNCTION. Perform the comman
"PCON" and print out "ALL" the configuration
list of the TDX SYSTEM DEVICES and PERIPHERALS.
4:1:1 Explain the relation between the LINE PORT
ID
OH5-7 and the corresponding LTUX-S, ADAPTOR, BP8,
I/O CHANNEL (LINE), and PERIPHERAL.
SLM SLM Intrduce SLM: Section 4.5.4
INTRODUCT. Section 4.5.4
Section 4.7.2.1.8
Section 4.7.2.2
HWB HWB Introduce HWB: Section 3
INTRODUCT.
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MT/RST 4:2:1-2 840620
TDX CONTROLER L
1…0f…
M̲O̲D̲U̲L̲E̲ ̲ OH1 The TDX CONTROLLER
for the TDX BUS #1
is
P̲O̲S̲I̲T̲O̲N̲ placed in TDX UNIT No. 1, FRONT SLOT No.
1
The TDX CONTROLLER for the TDX BUS #2 is
placed in TDX UNIT No. 4, FRONT SLOT No.
1.
P̲E̲R̲F̲O̲R̲M̲A̲N̲C̲E̲ CONTROLS and SYNCHRONIZES the DATA- COMMUNICATION
between the STI MODULE in the PROCESSOR UNIT
(U) and the LTUX-S MODULES in the TDX UNITS
(TU).
The CONTROL of the DATA COMMUNICATION is
performed according to a predefinded MUX.
TABLE in the TDX CONTROLLER.
How often a certain DEVICE (LTUX-S or STI
MODULE) is allowed to send MESSAGES on he
TDX BUS is called BANDWIDTH. The BANDWIDTH
depends on how often the DEVICE No. is represented
in the MUX. TABLE.
The SYNCHRONIZING of the DATA COMMUNICATION
by the TDX CONTROLLER is due to a continious
BIT STREAM of 1.8432 Mbit/sec. which th TDX
CONTROLLER clocks and synchronizes on the
LOWER TDX BUS. This BIT STREAM is divided
into 6400 TIME SLOTS of 288 bits each. In
each TIME SLOT a DATA MESSAGE or a DUMMY
MESSAGE can be transmitted.
…0e… 2793A/rt
MT/RST 4:2:1-2 840620
TDX CONTROLER L
2…0f…
MESSAGE FORMAT, CODE FORMAT, and DATA COMMUNICATION.
(See Lesson :1:2 & 4:1:3).
Because of a REDUNDANT SYSTEM two TDX CONTROLLERS
are incorporated. The AUTOMATICALLY ENABLING
of one of these TDX CONTROLLERS and the DISABLING
of the other one is performed by the WATCH
DOG according to the STATUS of the TDX COTROLLERS,
and the STATUS of the PROCESSOR UNITS.
B̲L̲O̲C̲K̲ ̲D̲I̲A̲G̲R̲A̲M̲ OH2 The TDX BLOCK DIAGRAM described as follows:
RS-422 The DATA and CONTROL LINES from/to the
RECEIVER/DRIVER TDX BUS are differential lines in accordance
with the RS-422 recommedations.
ENCODER & DECODER The DATA and the 1.8432 MHz CLOCK are transmitted
simultaniously on the LOWER BUS a in so-called
SPL-D CODE.
The ENCODER LOGIC codes the OUTGOING SERIAL
DATA with the CLOCK.
The DECODER LOGIC will decode the DATA STRAM
being RECEIVED, that means separating the
SPL-D CODE in the DATA and the CLOCK.
OH2 The advantages of the SPL-D CODE are:
- SOURCE and DESTINATION are SYNCRONIZED
- Correct decoding in spite of delay in
cable
The TDX CONTROLLER TRANSMTS on the LOWER
BUS and RECEIVES on the UPPER BUS. Each
BUS consists of a TWISTED PAIR CABLE. UPPER
BUS + LOWER BUS = TDX BUS.…86…1
…02… …02… …02… …02… …02…
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MT/RST 4:2:1-2 840620
TDX CONTROLER L
3…0f…
MPCC M̲ULTI P̲ROTOCOL C̲OMMUNICATION C̲ONTROLLER
On RECEIVED HDLC FAMES the MPCC performs:
- Deletion of ABORT byte and FLAG bytes
- Deletion of ZEROES from the BITSTUFFING
- CYCLIC REDUNDANCY CHECK (CRC)
- SERIAL to PARALLEL conversion of each
byte
When TRANSMITTING HDLC FRAMES the MPCC performs:
- ARALLEL to SERIAL conversion of each byte
- BITSTUFFING (Insertion of ZEROES)
- CRC byte generation
- FLAGE bytes insertion
STATE This functional block CONTROLS the ROUTING
CONTROLLER of the HDLC FRAMES in the DATA BUFFER. The
LOGIC STATECONTROLLER LOGIC also CONTROLS the MPCC
functions.
DATA BUFFER F̲IRST I̲N F̲IRST O̲UT registers.
4 FIFO registers are available for ROUTING
the HDLC FRAMES. The CHANNEL ROUTING IDENTIFIER
(CR-ID) in the HDLC FRAMES contents the INFORMATION
of DSTINATION of the respective FRAMES.
If the FRAME is destined for the TDX CONTROLLER
itself ("HOST NO. = [["), the DATA INFORMATION
will be used informally by the CPU. If the
"HOST NO." in the received FRAME is n̲o̲t̲ equal
to "[[", a MUX. NO. will b inserted in the
FRAME and the FRAME will be transmitted to
the DEVICE which is IDENTIFIED in the CR-ID.…86…1
…02… …02… …02…
…02… …02…
…0e… 2793A/rt
MT/RST 4:2:1-2 840620
TDX CONTROLER L
4…0f…
CPU/MEMORY The CPU is a standard Z80 microprocessor.
Together wit the MEMORY and part of the
DATA BUFFER, the CPU constitutes the MICRO
COMPUTER PART of the TDX CONTROLLER. It
handles the MUX. TABLE and diagnostics the
communication.
USART U̲NIVERSAL S̲YNCHRONOUS A̲SYNCHRONOUS R̲ECEIVER
T̲RANSMITTER
The USRT handles the SERIAL COMMUNICATION
to/from a TEST TERMINAL (VDU) via the 24V
DRIVERS/RECEIVERS.
The BAUD RATE is 300 BAUD.
V24 RECEIVERS Standard V24 RECEIVERS/DRIVERS are
/DRIVERS OH2 associated the USART ports to obtain a standardized
conection to the TEST TERMINAL (VDU).
WATCH DOG The WATCH DOG LOGIC is MONITORING the TDX
LOGIC CONTROLLER STATUS and the STATUS of the POWER
supplied to the WALL OUTLETS.
The LOGIC is equipped with 5 drivers and
3 receivers for SIGNAL EXCHANE through the
"WATCH DOG" connector via the BSM-X and the
CONFIGURATION CONTROL BUS to the WATCH DOG
PROCESSOR UNIT.
CLOCK This circuit consists of a 1.8432 Mhz
GENERATOR oscillator. The CLOCK PULSES are used in
the ENCODER logic where the SERIL DATA is
coded with the CLOCK (SPL-D code) and transmitted
on the LOWER BUS.
…0e… 2793A/rt
MT/RST 4:2:1-2 840620
TDX CONTROLER L
5…0f…
F̲R̲O̲N̲T̲ ̲P̲A̲N̲E̲L̲ OH2 Five LEDS are available in the FRONT PANEL.
L̲E̲D̲S̲
"POWER" LED If all the 3 SUPPLIES (+ 5V, + 12V, - 12V)
(green) are present the LED will be illuminated.
"TEST" LED During the execution of the BUILD-IN TEST
(red) (BIT) the "TEST" LED will be illuminated
for a few seconds.
When te BUILD-IN TEST is fulfilled successfully
(no error) the "TEST" LED will be extinguished.
If the BUILD-IN TEST detects an ERROR the
"TEST" LED will show SLOW FLASH.
"REC.ST." LED When the TDX CONTROLLER STATUS is "UPPER
(yellow) BUS#1̲ SELCTED" the LED will be illuminated.
On the other hand when the TDX CONTROLLER
STATUS is "UPPER BUS #2̲ SELECTED" the LED
will be extinguished. However, in the CAMPS
a TDX CONTROLLER is used for each of the
two TDX BUSSES. The UPPER BUS #1 is conneced
to both RECEIVER CHANNELS on one of the TDX
CONTROLLERS and the UPPER BUS #2 is connected
to both RECEIVER CHANNELS on the other TDX
CONTROLLER. Therefore, the LED is insignificant
in the CAMPS.…86…1 …02… …02… …02… …02…
…0e… 2793A/rt
4:2:1-2 840620
MT/RST
TDX CONTROLLER L
6…0f…
"TR.ST." LED ERROR detected in the TRANSMITTED SPL-D code
(red) wll cause the "TR.ST." LED to be illuminated.
"FUSE" LED ERROR in one or both of the SUPPLIES
(red) (V…0f…cc…0e…1, V…0f…cc…0e…2) or in the FUSES for the associated
WALL OUTLET will cause the "FUSE" LED to
be illuminated.
F̲R̲O̲N̲T̲ ̲P̲A̲N̲E̲L̲ OH2 ONE!
S̲W̲I̲T̲C̲H̲E̲S̲
F̲R̲O̲N̲T̲ ̲P̲A̲N̲E̲L̲ OH2 A BNC connector and two 25 pin connectors
C̲O̲N̲N̲E̲C̲T̲I̲O̲N̲S̲ are available in the FRONT PANEL.
The BNC connector named "EXT. CLK" is used
for EXTERNAL 1.8432 MHz CLOCK SIGNAL.
OH2 The 25 pin connector named "TDX BUS is used
OH3 for the connection of the TDX CONTROLLER
to the respective TDX BUS via WALL OUTLET.
OH2 The 25 pin connector named "WATCH DOG" is
OH4 used for the connection of the TDX
OH5 CONTROLLER to the WATCH DOG via the 25 pin
connectoron the BSM-X and further on through
the CONFIGURATION CONTROL BUS.
OH2 As another application it is possible to
OH4 connect a TEST TERMINAL (VDU) to the "WATCH
DOG" connector for TDX SYSTEM STATUS TEST.
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MT/RST 4:2:1-2
840620
TDX CONTROLLER L
7…0f…
B̲A̲C̲K̲ ̲P̲L̲A̲N̲E̲ ̲ OH2 The PIN LAY OUT of the BACK PLANE CONNECTION
C̲O̲N̲N̲E̲C̲T̲I̲O̲S̲ OH6 to the TDX CONTROLLER.
This connection is used for the POWER SUPPLY
(+5V, +12V, -12V).
S̲E̲T̲ ̲U̲P̲ OH2 The DEVICE ADDRESS of the TDX CONTROLLER
OH7 identifies a unique DEVICE No. in the TDX
SYSTEM.
The ADDRESS SETTING is a FIXED SET UP (DIP
SWITCH
"S1"
not
used).
TDX CONTROLLER DEVICE ADDRESS = [[ (always).
The STRAPS SETTINGS provide the APPLICATION
of the TDX CONTROLLER to a UNIQUE PERFORMANCE.
CAMPS APPLICATION is shown.
B̲U̲I̲L̲D̲-̲I̲N̲ ̲T̲E̲S̲T̲ CHECK SUM TEST in EPROM.
READ/WRITE TEST in RAM.
…0e… 2793A/rt
MT/RST 4:2:1-2
840620
TDX CONTROLLER L
8…0f…
S̲W̲I̲T̲C̲H̲ ̲S̲E̲T̲T̲I̲N̲G̲
NONE!
The DEVICE ADDRESS is FIXED
SET UP = [[
S̲T̲R̲A̲P̲S̲ ̲S̲E̲T̲T̲I̲N̲G̲S̲
̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲
̲ ̲ ̲
^ ^ ^ ^ ^ ^ ^ ^ ^ ^
^
^ ̲P̲I̲N̲ ̲B̲L̲O̲C̲K̲ ̲N̲O̲.̲ ̲ ̲^̲ ̲2̲ ̲^̲ ̲3̲ ̲^̲ ̲4̲ ̲^̲ ̲5̲ ̲^̲ ̲6̲ ̲^̲ ̲7̲ ̲^̲ ̲8̲ ̲^̲ ̲9̲ ̲^̲
̲1̲0̲^
^ ^ ^ ^ ^ ^ ^ ^ ^ ^
^
̲S̲T̲R̲A̲P̲ ̲L̲O̲C̲A̲T̲I̲O̲N̲ ̲^̲ ̲A̲ ̲^̲ ̲B̲ ̲^̲ ̲B̲ ̲^̲ ̲C̲ ̲^̲ ̲B̲ ̲^̲ ̲B̲ ̲^̲ ̲C̲ ̲^̲ ̲B̲ ̲^̲ ̲B̲
̲^
̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲
̲ ̲ ̲
^ ^ ^ ^ ^ ^ ^ ^ ^ ^
^
^ ̲P̲I̲N̲ ̲B̲L̲O̲C̲K̲ ̲N̲O̲.̲ ̲ ̲^̲ ̲1̲1̲^̲ ̲1̲2̲^̲ ̲1̲3̲^̲ ̲1̲4̲^̲ ̲1̲5̲^̲ ̲1̲6̲^̲ ̲1̲7̲^̲ ̲1̲8̲^̲
̲1̲9̲^
^ ^ ^ ^ ^ ^ ^ ^ ^ ^
^
^ ̲S̲T̲R̲A̲P̲ ̲L̲O̲C̲A̲T̲I̲O̲N̲ ̲^̲ ̲A̲ ̲^̲ ̲A̲ ̲^̲ ̲B̲ ̲^̲ ̲B̲ ̲^̲ ̲A̲ ̲^̲ ̲A̲ ̲^̲ ̲B̲ ̲^̲ ̲B̲ ̲^̲
̲B̲ ̲^
…0e… 2793A/rt
4:2:3
840620
MT/RST
HOST I/F (STI/TIA)
1…0f…
S̲T̲I̲ ̲M̲O̲D̲U̲L̲E̲ ̲ OH1 In every PROCESSOR UNIT (PU) in FRONT SLOT
P̲O̲S̲I̲T̲I̲O̲N̲ o. 18.
P̲E̲R̲F̲O̲R̲M̲A̲N̲C̲E̲ The STI MODULE is an INTELLIGENT INTERFACE
MODULE associated the TDX SYSTEM for the
COMMUNICATION between the CR80 COMPUTER and
one TDX BUS via the TELECOMMUNICATION INTERFACE
ADAPTOR MODULE (TIA).
The MAIN PERFORMANCES ofthe STI MODULE are
as follows:
- Responds to CR80 access to the STI MODULE
- CONTROL of the CR80 access to the STI
MODULE
- DIRECT MEMORY ACCESS (DMA) transfer from
CR80 MAIN MEMORY to TIA MEMORY and vice
versa
- Establishes VIRTUAL CHANELS for COMMUNICATION
between STI MODULE and LTUX-S MODULES
- Serves the TDX PACKET PROTOCOL
- HIGH BANDWIDTH
- Connection to the CR80 CHANNEL BUS via
BACK PLANE MOTHERBOARD and connection
to the TIA MODULE via a FLAT CABLE
…0e… 2793A/rt
MT/RST 4:2:3
840620
HOST I/F (STI/IA) L
2…0f…
S̲T̲I̲ ̲M̲O̲D̲U̲L̲E̲ ̲ OH2 STI BLOCK DIAGRAM described as follows:
B̲L̲O̲C̲K̲ ̲D̲I̲A̲G̲R̲A̲M̲
M̲B̲I̲F̲: (M̲AIN B̲US I̲NTERF̲ACE)
The MBIF provides the connection between
the CR80 MAIN BUS and the internal HI-BUS.
This functionally block contains a HIGH SPEED
BIT SLICE MICROPROCESSOR and a DMA CONTROLLER.
It performs the functions as follows:
Provides the access from the CR80 to the
CENTRAL RAM.
- DIRECT MEMORY ACCESS (DMA) from the CR80
MAIN MEMORY to the TIA MEMORY and vice
versa.
- Derives the HI-BUS CLOCK from the CR80
MAIN BUS CLOCK.
- Exchanges INTERRUPTS between INGOINGPROCESSOR,
OUTGOING PROCESSOR, and CR80.
- Supervises the three POWER SOURCES (+5V,
+12V, -12V).
- Displays STATUS of the STI MODULE.
S̲T̲I̲ ̲I̲N̲G̲O̲I̲N̲G̲ OH2 INGOING DATA is data from TIA MODULE to CR80
P̲R̲O̲C̲E̲S̲S̲O̲R̲ ̲
The PROCESSOR is a standard ZIOG 80 MICRO
PROCESSOR containing the TDX PACKET PROTOCOL
TASK for the INGOING HDLC FRAMES.
The INGOING PROCESSOR also SETS UP the PARAMETERS
(SOURCE and DESTINATION) used by the MBIF
for the DMA DATA TRANSFER from the SHARED
MEMORY on the TIA MOULE to the CR80 MAIN
MEMORY.…86…1 …02… …02… …02… …02…
…0e… 2793A/rt
MT/RST 4:2:3 840620
HOST I/F (STI/IA) L
3…0f…
OUTGOING OUTGOING DATA is data from CR80 to TIA
PROCESSOR MODULE.
The Processor is a standard ZILOG 80 MICRO PROCESSOR
containing the TDX PACKET PROTOCOL TASK for the OUTGOING
HDLC FRAMES.
The OUTGOING PROCESSOR also SETS UP the PARAMETER
(SOURCE and DESTINATION) used by the MBIF
for the DMA DATA TRANSFER fromthe CR80 MAIN
MEMORY to the SHARED MEMORY on the TIA MODULE.
CENTRAL RAM The CENTRAL RAM is a 32K BYTE RAM which is
accessed via the HOST INTERFACE BUS (HI-BUS).
It contains INFORMATION about the DMA ADDRESSES.
HI-BUS ARBITOR This functiona block directs the access
to the HI-BUS where the INTERNAL DATA
TRANSFER as well as the DATA TRANSFER
between the CR80 CHANNEL BUS and the STI
MODULE are routed.
S̲T̲I̲ ̲F̲R̲O̲N̲T̲ ̲ OH2 Eight LEDs are available in the FRONT PANEL.
P̲A̲N̲E̲L̲ ̲L̲E̲D̲S̲
"POWER" ED When all the three supplies (+5V, +12V,
(green) -12V) are present, the LED will be illuminated.
…0e… 2793A/rt
MT/RST 4:2:3
840620
HOST I/F (STI/IA) L
4…0f…
"TEST" LED During the execution of the BUILD-IN TEST
(red) (BIT), the"TEST" LED will be illuminated
for a few seconds.
When the BUILD-IN TEST is fulfilled successfully
(no error), the "TEST" LED will be extinguished.
If the BUILD-IN TEST detects an ERROR, the
"TEST" LED will show CONSTANT LIGHT.
"BUSY" LED During a DIRECT MEMORY ACCESS (DMA)transfer
(yellow) on the MAIN BUS, the "BUSY" LED will be illuminated.
"H.I. DMA" During a DIRECT MEMORY ACCESS (DMA) transfer
(yellow) on the internal HI-BUS, the "H.I. DMA" LED
will be illuminated.
S̲T̲I̲P.ERROR" OH2 If a drop in the SUPPLIES (+5V, +12V, -12V)
LED (red) has occurred since the latest MASTER CLEAR,
the "P.ERROR" LED will be illuminated to
indicate an intermediate POWER ERROR.
"C.ERROR" LED If TIME-OUT or PARITY ERROR has beendetected
(red) during a DMA transfer on the MAIN BUS, the
"C.ERROR" LED will be illuminated.
"M.ERROR" LED If TIME-OUT or PARITY ERROR has been detected
(red) during a DMA transfer on the internal HI-BUS,
the "M.ERROR" LED will be illuminatd.
…0e… 2793A/rt
MT/RST 4:2:3
840620
HOST I/F (STI/IA) L
5…0f…
"RX.STATE" LED When the STI MODULE via the TIA MODULE does
(yellow) o̲t̲ receive the 1.8432 MHz SYNCHRONIZATION
CLOCK from the SPL-D CODE, the "RX.STATE"
LED will be illuminated.
S̲T̲I̲ ̲F̲R̲O̲N̲T̲ ̲ OH2 NONE!
P̲A̲N̲E̲L̲ ̲S̲W̲I̲T̲C̲H̲E̲S̲
F̲R̲O̲N̲T̲ ̲P̲A̲N̲E̲L̲ ̲ OH2 NONE!
C̲O̲N̲N̲E̲C̲T̲I̲O̲N̲S̲
B̲A̲C̲K̲ ̲P̲L̲A̲N̲E̲ ̲ OH2 The UPPER CONNECTOR (P1) is used for the
C̲O̲N̲E̲C̲T̲I̲O̲N̲S̲ POWER SUPPLY only (equal to the POWER CONNECTION
on the MIDDLE CONNECTOR).
OH2 The MIDDLE CONNECTOR (P2) performs the
OH3 connection to the CR80 CHANNEL BUS.
OH2 The LOWER CONNECTOR (P3) performs the
OH4 connection to the TIA MODUL via a FLAT CABLE.
…0e… 2793A/rt
MT/RST 4:2:3
840620
HOST I/F (STI/IA) L
6…0f…
S̲T̲I̲ ̲S̲E̲T̲ ̲U̲P̲ OH2 Two DIP SWITCHES are available on the STI
OH5 MODULE:
- DIP SWITCH "S1" DEVICE ADDRESS
(DEVICE NO. in the
TDX SYSTEM)
- DIP SWITCH "S2" I/O ADDRESS
(MODULE ADDRESS
seen from the CR80)
The DEVICE ADDRESS of the STI MODULE identifies
a unique DEVICE NO. in the TDX SYSTEM. It
is ST UP by means of the DIP SWITCH named
"S1".
NOTE! The "S1" SET UP is ignored by the
CAMPS APPLICATION SOFTWARE.
The INPUT/OUTPUT ADDRESS seen from the CR80
COMPUTER is SET UP by means of the DIP SWITCH
named "S2".
By using the DAU UNIT MAPPING COMMAND "UM"
it is possible to check, if the "SL" SWITCH
SETTING is correct.
The STRAPS SETTINGS provide the APPLICATION
of the STI MODULE to a UNIQUE PERFORMANCE.
CAMPS APPLICATION is shown.
B̲U̲I̲L̲D̲-̲I̲N̲ ̲ INITIALIZATION to te TIA MODULE.
T̲E̲S̲T̲
…0e… 2793A/rt
MT/RST 4:2:3
840620
HOST I/F (STI/IA) L
7…0f…
T̲I̲A̲ OH6 In every PROCESSOR UNIT (PU) in REAR SLOT
M̲O̲D̲U̲L̲E̲ ̲P̲O̲S̲I̲T̲I̲O̲N̲ No.16.
PERFORMANCE The TIA MODULE is an INTELLIGENT FRONT END
MODULE with the application as a SLAVE MODULE
to the STI MODULE. The data exchanges between
the STI MODULE and the TDX BUS passes via
an onboard SHARED MEMORY (RAM), shared by
the TIA MDULE and the STI MODULE.
The MAIN PERFORMANCES of the TIA MODULE are
as follows:
- DECODING and ENCODING of the SPL-D CODE
by which the DATA STREAM is transferred
on the TDX BUS.
- SERIAL/PARALLEL and PARALLEL/SERIAL conversion
of the DATASTREAM.
- Serves the HDLC FRAME CHECK.
- Routes the DATA to and from the onboard
SHARED MEMORY (RAM).
The HDLC FRAMES are RECEIVED from the LOWER
BUS and TRANSMITTED to the UPPER BUS. The
connection to the TDX BUS is obtained through
a 25pins connector in the FRONT PANEL of
the TIA MODULE via WALL OUTLET.
Connection to the STI MODULE is performed
by a FLAT CABLE via a BACK PANEL CONNECTOR.…86…1
…02… …02… …02…
…02… …02…
…0e… 2793A/rt
MT/RST 4:2:3 840620
HOST I/F (TI/TIA) L
8…0f…
T̲I̲A̲ OH7 The BLOCK DIAGRAM of the TIA MODULE
B̲L̲O̲C̲K̲ ̲D̲I̲A̲G̲R̲A̲M̲ describe as follows:
RS-422 The DATA and CONTROL LINES to/from the TDX
DRIVERS/RECEIVERS BUS are differential lines, which are in
accordance with the RS-422 recommendations.
DECODER A MESSAGE to a CR80 HOST COMPUTER via the
& ENCODER TDX CONTROLER will be RECEIVED by the destined
TIA MODULE from the LOWER TDX BUS. This
SERIAL DATA STREAM, consisting of the HDLC
FRAMES, is coded with the 1.8432 MHz CLOCK
by the TDX CONTROLLER in the SPL-D CODE.
The DECODER LOGIC will SEPARATE the SPL-
CODE in DATA and CLOCK.
When the TIA MODULE is TRANSMITTING HDLC
FRAMES, the ENCODER LOGIC on the MODULE will
CODE the OUTGOING DATA with the 1.8432 MHz
CLOCK and TRANSMIT the SPL-D CODED DATA STREAM
to the UPPER TDX BUS. The CLOCK used by
theENCODER LOGIC is derived from the DECODER
LOGIC. In this way the MESSAGE HANDLING
is SYNCRONIZED by the TDX CONTROLLER.
…0e… 2793A/rt
MT/RST 4:2:3
840620
HOST I/F (STI/IA) L
9…0f…
T̲I̲A̲ OH7 M̲ULTI P̲ROTOCOL C̲OMMUNICATION C̲ONTROLLER.
MPCC
On RECEIVED HLC FRAMES the MPCC performs:
- Deletion of FLAG BYTES.
- Deletion of ZEROES from the BITSTUFFING
- CYCLIC REDUNDANCY CHECK (CRC).
- SERIAL to PARALLEL conversion of each
byte.
When TRANSMITTING HDLC FRAMES the MPCC performs:
- PRALLEL to SERIAL conversion of each byte.
- BITSTUFFING (insertion of ZEROES).
- CRC BYTE generation.
- Insertion of FLAG BYTES and ABORT BYTE.
STATE This functional block CONTROLS the ROUTING
CONTROLLER of the HDLC FRAMES in the DAA BUFFER. The
LOGIC STATE CONTROLLER LOGIC also CONTROLS the
MPCC functions.
…0e… 2793A/rt
MT/RST 4:2:3
840620
HOST I/F (STI/IA) L
10…0f…
T̲I̲A̲ OH7 F̲IRST I̲N F̲IRST O̲UT registers
DATA BUFFER
3 FIFO registers areavailable for ROUTING
the HDLC FRAMES.
When a HDLC FRAME is about to be RECEIVED
the FLAGS are deleted by the MPCC. The REST
of the HDLC FRAME is then converted BYTE
by BYTE from SERIAL to PARALLEL and routed
to FIFO 1. During this transfer th MUX.
No. and the CHANNEL ROUTING IDENTIFIER (CR-ID)
are checked. Furthermore the CYCLIC REDUNDANCY
CHECK (CRC) is carried out. From FIFO 1
the contents are transferred to FIFO 2 from
which the FRONT END PROCESSOR will move the
"DATA BYTES" of th HDLC FRAME to an "INGOING
BUFFER" in the SHARED MEMORY.
When the TRANSMITTER function of the STI
MODULE has been activated, an outgoing HDLC
FRAME will be transferred BYTE by BYTE from
FIFO 3 and converted from PARALLEL to SERIAL
by the MPCC toether with the execution of
the remaining MPCC functions.
The contents of FIFO 3 are at an earlier
stage moved from an "OUTGOING BUFFER" in
the SHARED MEMORY to FIFO 3.
FRONT END PROCESSOR This is a standard ZILOG 80 MICRO PROCESSOR
which exeutes the APPLICATION PROGRAM of
the TIA MODULE. The APPLICATION PROGRAM is
stored in an associated EPROM containing
the TDX INTERFACE TASK and the TASK for the
ACTIVATION and CONTROLLING of the DMA transfer
between the DATA BUFFER and the SHARED MEORY.
…0e… 2793A/rt
MT/RST 4:2:3
840620
HOST I/F (STI/IA) L
11…0f…
T̲I̲A̲ OH7 This MEMORY is SHARED by the
SHARED MEMORY FRONT END PROCESSR of the TIA MODULE and
the
(RAM) INGOING and the OUTGOING PROCESSOR of the
STI MODULE.
An ARBITOR which is attached to the SHARED
MEMORY makes this MEMORY DUAL PORTED. It
directs whether the TIA or the HI-BUS has
access to the SHARED MEMORY.
DMA CONTROLLER This circuit performs the data transfer
from the DATA BUFFER (FIFO 2) to the SHARED
MEMORY as well as the data transfer from
the SHARED MEMORY to the DATA BUFFER (FIFO
3)
F̲R̲O̲N̲T̲ ̲P̲A̲N̲E̲L̲ ̲ OH7 Two LEDS are available in the FRONT PANL.
L̲E̲D̲S̲
"POWER" LED When both of the SUPPLIES (+ 5V, - 12V) are
(green) present the LED will be illuminated.
"TEST" LED If the TIA MODULE is not initialized by the
(red) STI MODULE the "TEST" LED will be illuminated.
T̲I̲A̲ OH7 NONE!
F̲R̲N̲T̲ ̲P̲A̲N̲E̲L̲
S̲W̲I̲T̲C̲H̲E̲S̲
F̲R̲O̲N̲T̲ ̲P̲A̲N̲E̲L̲ OH7 The connection to one TDX BUS is obtained
C̲O̲N̲N̲E̲C̲T̲I̲O̲N̲ OH8 through a STANDARD 25 PIN CANNON CONNECTOR
named "J1".
…0e… 2793A/rt
MT/RST 4:2:3
840620
HOST I/F (STI/IA) L
12…0f…
B̲A̲C̲K̲ ̲P̲A̲N̲E̲L̲ OH7 The connection to the STI MODULE is
C̲O̲N̲N̲E̲C̲T̲I̲O̲N̲S̲ OH9 perormed by a FLAT CABLE via the LOWER BACK
PANEL CONNECTOR.
OH7 The POWER DISTRIBUTION is performed by a
OH10 BACK PLANE MOTHERBOARD through the UPPER
CONNECTOR.
T̲I̲A̲ OH7 The BASE ADDRESS of the SHARED MEMORY seen
S̲E̲T̲ ̲U̲P̲ from the STI MODULE i SET UP by the DIP SWITCH
named "S1".
The STRAPS SETTINGS provide the APPLICATION
of the STI MODULE to a UNIQUE PERFORMANCE.
The CAMPS APPLICATION is shown.
B̲U̲I̲L̲D̲-̲I̲N̲ ̲T̲E̲S̲T̲ CHECK SUM TEST in EPROM.
READ/WRITE TEST in RAM.
TEST FRAMES re TRANSMITTED and RECEIVED by
the TIA MODULE when starting up.
Her inds`ttes tegning
Her inds`ttes tegning
F̲R̲O̲N̲T̲ ̲P̲A̲N̲E̲L̲ ̲C̲O̲N̲N̲E̲C̲T̲I̲O̲N̲
PIN LAY OUT for the TDX BUS CONNECTOR:
̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲
̲ ̲ ̲ ̲ ̲
^ ̲ ̲P̲I̲N̲ ̲ ̲ ̲S̲I̲G̲N̲A̲L̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲P̲I̲N̲ ̲ ̲ ̲ ̲S̲I̲G̲N̲A̲L̲ ̲ ̲ ̲ ̲ ̲
̲ ̲ ̲ ̲^
^
^
^ 1 Logic one 14 same as 1
^
^
^
^ 2 Logic one 15 same as 2
^
^
^
^ 3 GND 16 GND
^
^
^
^ 4 GND 17 GND
^
^
^
^ 5 GND 18 DISAB- 1
^
^
^
^ 6 DISAB+ 1 19 GND
^
^
^
^ 7 GND 20 TXDAT- 1
^
^
^
^ 8 TXDAT+ 1 21 GND
^
^
^
^ 9 GND 22 RXDAT- 2
^
^
^
^ 10 RXDAT+ 2 23 TXDAT- 2
^
^
^
^ 11 TXDAT+ 2 24 RXDAT- 1
^
^
^
^ 12 RXDAT+ 1 25 DISAB- 2
^
^
^
^ 13 DISAB+ 2
^
^ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲
̲ ̲ ̲ ̲ ̲^
B̲A̲C̲K̲ ̲P̲L̲A̲N̲E̲ ̲C̲O̲N̲N̲E̲C̲T̲I̲O̲N̲
PIN LAY OUT for the LOWER CONNECTOR:
̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲
^ ̲6̲4̲ ̲P̲O̲L̲.̲ ̲F̲L̲A̲T̲A̲B̲L̲E̲,̲ ̲H̲I̲-̲B̲U̲S̲ ̲ ̲^
^ ̲ ̲ ̲ ̲c̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲^̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲a̲ ̲ ̲ ̲ ̲^
^ ^
^ GND 1 GND ^
^ GND 2 GND ^
^ 3 ^
^ 4 ^
^ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ 5 ̲ ̲ ̲ ̲ ̲ ^
^ R̲X̲-̲S̲T̲TUS 6 E̲R̲R̲O̲R̲ ̲ ̲ ^
^ EX-INT 7 R̲E̲S̲TART ^
^ 8 M̲RQ ^
^ ̲ ̲ ̲ ̲ 9 R̲/̲W̲ ̲ ^
^ T̲E̲S̲T 10 D̲A̲T̲I̲ ^
^ PWI 11 D̲A̲CP ^
^ 12 FB ^
^ GND 13 [1 ^
GND 14 [2 ^
^ H0 15 H1 ^
^ H2 16 H3 ^
^ GND 17 GND ^
^ D0 18 D1 ^
^ D2 19 D3 ^
^ D4 20 D5 ^
^ D6 21 D7 ^
^ GND 22 GND ^
^ A0 23 A1 ^
^ A2 24 A3 ^
^ A4 25 A5 ^
^ A6 26 A7 ^
^ GND 27 GND ^
^ A8 28 A9 ^
^ A10 29 A11 ^
^ A12 30 A13 ^
^ A14 31 A15 ^
^ GND 32 GND ^
^ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲^
B̲A̲C̲K̲ ̲P̲L̲A̲N̲E̲ ̲C̲O̲N̲N̲E̲C̲T̲I̲O̲N̲
PIN LAY OUT for the UPPER CONNECTOR:
̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲
^ ̲ ̲ ̲ ̲ ̲ ̲6̲4̲ ̲P̲O̲L̲.̲ ̲O̲N̲N̲E̲C̲T̲O̲R̲ ̲ ̲ ̲ ̲^
^ ̲ ̲ ̲ ̲c̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲^̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲a̲ ̲ ̲ ̲ ̲^
^ ^
^ 1 ^
^ 2 ^
^ 3 ^
^ 4 ^
^ 5 ^
^ 6 ^
^ 7 ^
^ 8 ^
^ 9 ^
^ 10 ^
^ 11 ^
^ 12 ^
^ 13 ^
^ 14 ^
^ 15 ^
^ 16 ^
^ 17 ^
^ 18 ^
^ 19 ^
^ 20 ^
^ 21 ^
^ -24V (2) 22 24V (1) ^
^ GND 23 GND ^
^ +24V (2) 24 +24V (1) ^
^ -12V 25 -12V ^
^ GND 26 GND ^
^ +12V 27 +12V ^
^ GND 28 GND ^
^ GND 29 GND ^
^ +5V 30 +V ^
^ +5V 31 +5V ^
^ +5V 32 +5V ^
^ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲^
S̲W̲I̲T̲C̲H̲ ̲S̲E̲T̲T̲I̲N̲G̲
BASE ADDRESS of the SHARED MEMORY seen from the STI
MODULE:
DIP SWITCH "S1"
̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲
CONTACT NO. ^ ̲1̲ ̲^̲ ̲2̲ ̲^̲ ̲3̲ ̲^̲ ̲4̲ ̲
OPEN
OPEN = "1" (PRESS DOWN)
̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲
^ CONTACT NO. ^ ^ ^ ^ ^
^ ̲T̲I̲A̲ ̲L̲O̲C̲A̲T̲I̲O̲N̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲^̲ ̲1̲ ̲^̲ ̲2̲ ̲^̲ ̲3̲ ̲^̲ ̲4̲ ̲^
^ ^ ^ ^ ^ ^
^ Rear Slot 16, PU#1 ^ 0 ^ 0 ^ 0 ^ 0 ^
^ Rear Slot 14, PU#1 (SPARE) ^ 0 ^ 0 ^ 0 ^ 0 ^
^ Rear Slot 16, PU#2 ^ 0 ^ 0 ^ 0 ^ 0 ^
^ Rear Slot 14, PU#2 (SPARE) ^ 0 ^ 0 ^ 0 ^ 0 ^
^ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲^̲ ̲ ̲ ̲^̲ ̲ ̲ ̲^̲ ̲ ̲ ̲^̲ ̲ ̲ ̲^
LSB MSB
S̲T̲R̲A̲P̲S̲ ̲S̲E̲T̲T̲I̲N̲G̲S̲
̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲
̲
^ ^ ^ ^ ^ ^ ^ ^ ^
^
^ ̲P̲I̲N̲ ̲B̲L̲O̲C̲K̲ ̲N̲O̲.̲ ̲ ̲ ̲ ̲^̲ ̲ ̲^̲ ̲2̲ ̲^̲ ̲3̲ ̲^̲ ̲4̲ ̲^̲ ̲5̲ ̲^̲ ̲6̲ ̲^̲ ̲7̲ ̲^̲ ̲8̲ ̲^
^ ^ ^ ^ ^ ^ ^ ^ ^
^
^ ̲S̲T̲R̲A̲P̲ ̲L̲O̲C̲A̲T̲I̲O̲N̲ ̲ ̲ ̲^̲ ̲A̲ ̲^̲ ̲A̲ ̲^̲ ̲B̲ ̲^̲ ̲B̲ ̲^̲ ̲B̲ ̲^̲ ̲A̲ ̲^̲ ̲B̲ ̲^̲ ̲A̲
̲^
Her inds`ttes tegning
Her inds`ttes tegning
B̲A̲C̲K̲ ̲P̲L̲A̲N̲E̲ ̲C̲O̲N̲N̲E̲C̲T̲I̲O̲N̲
PIN LAYOUT for the MIDDLE CONNECTOR:
STI MAIN BUS
=
CR80 CHANNEL
BUS
B̲A̲C̲K̲ ̲P̲L̲A̲N̲E̲ ̲C̲O̲N̲N̲E̲C̲T̲I̲O̲N̲
PIN LAYOUT For the LOWER CONNECTOR:
HI-BUS
64 pol. flatcable
S̲W̲I̲T̲C̲H̲ ̲S̲E̲T̲T̲I̲N̲G̲
DEVICE ADDRESS: (DEVICE NO. in the TDX SYSTEM)
DIP SWITCH "S1"
̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲
CONTACT NO. ^ ̲1̲ ̲^̲ ̲2̲ ̲^̲ ̲3̲ ̲^̲ ̲4̲ ̲^
OPEN
OPEN = "1" (PRESS DOWN)
̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲
^ CONTACT NO. ^ ^ ^ ^ ^
^ ̲S̲T̲I̲ ̲L̲O̲C̲A̲T̲I̲O̲N̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲^̲ ̲1̲ ̲^̲ ̲2̲ ̲^̲ ̲3̲ ̲^̲ ̲4̲ ̲^
^ ^ ^ ^ ^ ^
^ Front Slot 18, PU#1 ^ 1 ^ 0 ^ 0 ^ 0 ^
^ Front Slot 18, PU#2 ^ 1 ^ 0 ^ 0 ^ 0 ^
^ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲^̲ ̲ ̲ ̲^̲ ̲ ̲ ̲^̲ ̲ ̲ ̲^̲ ̲ ̲ ̲^
LSB MSB
I/O ADDRESS: (Sen from the CR80)
DIP SWITCH "S2"
̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲
CONTACT NO. ^ ̲1̲ ̲^̲ ̲2̲ ̲^̲ ̲3̲ ̲^̲ ̲4̲ ̲^̲ ̲5̲ ̲^̲ ̲6̲ ̲^̲ ̲7̲ ̲^̲ ̲8̲ ̲^
OPEN
OPEN = "1" (PRESS DOWN)
̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲
̲ ̲ ̲ ̲ ̲ ̲ ̲
^ CONTACT NO.^ ^ ^ ^ ^ ^ ^
^ ^
^S̲T̲I̲ ̲L̲O̲C̲A̲T̲I̲O̲N̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲^̲ ̲1̲ ̲^̲ ̲2̲ ̲^̲ ̲3̲ ̲^̲ ̲4̲ ̲^̲ ̲5̲ ̲^̲ ̲6̲ ̲^̲
̲7̲ ̲^̲ ̲8̲ ̲^
^ ^ ^ ^ ^ ^ ^ ^
^ ^
^ Front Slot 8, PU#1 ^ 1 ^ 1 ^ 0 ^ 0 ^ 0 ^ 1 ^
0 ^ 0 ^
^ Front Slot 18, PU#2 ^ 1 ^ 1 ^ 0 ^ 0 ^ 0 ^ 1 ^
0 ^ 0 ^
^ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲^̲ ̲ ̲ ̲^̲ ̲ ̲ ̲^̲ ̲ ̲ ̲^̲ ̲ ̲ ̲^̲ ̲ ̲ ̲^̲ ̲ ̲ ̲^̲
̲ ̲ ̲^̲ ̲ ̲ ̲^
^ LSB MSB ^ LSB
MSB ^
^ LOWER 4 BIT ^ UPPER 4
BIT ^
S̲T̲R̲A̲P̲S̲ ̲S̲E̲T̲T̲I̲N̲G̲S̲
̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲
̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲
^ ^ ^ ^ ^ ^ ^ ^ ^ ^
^ ^ ^
^ ̲P̲I̲N̲ ̲B̲L̲O̲C̲K̲ ̲N̲O̲.̲ ̲ ̲^̲ ̲1̲ ̲^̲ ̲2̲ ̲^̲ ̲3̲ ̲^̲ ̲4̲ ̲^̲ ̲5̲ ̲^̲ ̲6̲ ̲^̲ ̲7̲ ̲^̲ ̲8̲ ̲^̲
̲9̲ ̲^̲ ̲1̲^̲ ̲1̲1̲^
^ ^ ^ ^ ^ ^ ^ ^ ^ ^
^ ^ ^
^ ̲S̲T̲R̲A̲P̲ ̲L̲O̲C̲A̲T̲I̲O̲N̲ ̲^̲ ̲B̲ ̲^̲ ̲B̲ ̲^̲ ̲B̲ ̲^̲ ̲B̲ ̲^̲ ̲X̲ ̲^̲ ̲X̲ ̲^̲ ̲A̲ ̲^̲ ̲Y̲ ̲^̲
̲X̲ ̲^̲ ̲X̲ ̲^̲ ̲B̲ ̲^
X = "DO NOT CARE"
Y = FIXED MOUNTED
skal gemmes
…0e… 2793A/rt
MT/RST 4:4:1-2 840620
CTX-CRATES L
1…0f…
CRAT FUNCTIONS The CTX crate houses 25 stations in the
FRONT POSITIONS front side the following modules:
T̲D̲X̲ ̲m̲o̲d̲u̲l̲e̲s̲:̲
TDX Controller
BSM-X
LTUX-S
OH 1 A̲D̲A̲P̲T̲O̲R̲ ̲m̲o̲d̲u̲l̲e̲s̲:̲
HWB: Fig.
3.1-3 L/L Adaptors type 1 (4 channels)
L/L Adaptors typ 2 (1 channel)
OPTO Transceivers (1 channel)
1̲ ̲P̲o̲w̲e̲r̲ ̲s̲u̲p̲p̲l̲y̲ for the TDX modules.
MOTHERBORD OH 2 The modules are plugged into a CTX
CTX: Fig. motherboard which provides:
4.2-1
- interconnection between the LTUX.S and
adaptor modules viathe I/O area.
- power distributuion from the front side
PS to the TDX modules and the adaptor
modules (+5V +/-12V)
- communication lines between the BSM-X
and LTUX-S's
- power distribution from the rear side
PS to the adaptor modules (9V A)
BACK POSITIONS In the rear of the CTX crate, the following
are to be mounted:
OH 3 - Main power panel for mains supply
HWB: Fig. (mains filter, fuse)
3.1-3
- Adaptor power supply (2x9V AC)
- V24/V28 back panels and back panel type
8 (P8)
- TSA panel (Temp. Sense Adaptor)
- BSM-X panel
…0e… 2793A/rt
MT/RST 4:4:1-2 840620
CTX-CRATES L
2…0f…
INTERNAL OH 4 Internal cable connections
HWB:
Page 87
ADAPTOR CRATE OH 5 Housing only LO LEVEL Adaptors and back
HWB: Fig. panels (BP8)
3.1-13
(sheet 1)
Only one power supply unit, the 18V AC adaptor
PS in the rear side.
OH 6 Internal cable connections
HWB: Fig.
3.1-13
(sheet 2)
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MT/RST 4:4:1-2 840620
CTX-CRATES L
3…0f…
TDX CABLES OH 7 The cable type used as the TDX bus is a two
core screened RF cable (type T () 3078) with
a char. impedance of 100 Ohm.
One cable (two cores) is used as lower bus,
and one cable is used as upper bus.
TERMINATION To prevent reflections on the bus, all cables
must be terminated in b̲o̲t̲h̲ ̲e̲n̲d̲s̲ with a 100
Ohm resistor.
SCREN To prevent ground loops, the screen must
only
GROUNDING be connected to ground in o̲n̲e̲ rack; normally
the CPU rack.
TDX OUTLET OH 7 Connects O̲N̲E̲ TDX bus - both upper and lower
FUNCTIONS (bus) - to the modules which communicate
via the TDX bus.In the CAMPS system, 2̲ ̲o̲u̲t̲l̲e̲t̲s̲
are connected to each BSM-X module but O̲N̲E̲
outlet is connected to each CTRL, and O̲N̲E̲
outlet is connected to each HOST I/F (TIA)
The termination of the bus cables and the
grounding of the screens are made directly
o the terminal block of the outlet box.
…0e… 2793A/rt
MT/RST 4:4:1-2 840620
CTX-CRATES L
4…0f…
OUTLET The bus cable connection on the terminal
block
CONNECTIONS is like:
̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲T̲X̲ ̲1̲ ̲&̲ ̲2̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲R̲X̲ ̲1̲ ̲&̲
̲2̲ ̲ ̲
C̲T̲R̲L̲ ̲O̲U̲T̲L̲E̲T̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲L̲O̲W̲E̲R̲ ̲B̲U̲S̲ ̲ ̲ ̲ ̲ ̲ ̲U̲P̲P̲E̲R̲
̲B̲U̲S̲ ̲ ̲
O̲T̲H̲E̲R̲ ̲O̲U̲T̲L̲E̲T̲S̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲U̲P̲P̲E̲R̲ ̲B̲U̲S̲ ̲ ̲ ̲ ̲ ̲ ̲L̲O̲W̲E̲R̲
̲B̲U̲S̲ ̲ ̲
(Blackboard)
The outlet box contains circuits for signal
adaption to/from the CTRL/DEVICESand provides
galvanic isolation between the bus cable
and the communicating module, i.e. between
the different racks which contain TDX equipment.
BLOCK OH 8 T̲h̲e̲ ̲T̲X̲ ̲p̲a̲r̲t̲: The SPL-D coded data from the
PRINCIPLE transmitting module is transferred o the
TDX bus via tri-state, balanced (differential)
galvanically isolated (trafo) power drivers.
The DISAB (tri-state) signal controls the
driver to be in the high impedance condition.
T̲h̲e̲ ̲R̲X̲ ̲p̲a̲r̲t̲: The SPL-D coded receive data
is transferred frm the bus via galvanic isolators
(capacitors) to a high impedance input differential
receiver.
S̲u̲p̲p̲l̲y̲ ̲V̲o̲l̲t̲a̲g̲e̲: Two +5V lines which are fused
on the TDX device module supply the outlet
box circutry with power.
gem herti…86…1 …02… …02… …02… …02… …02…
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MT/RST 4:4:3 840620
POWER SUPPLIES/BP8 L
1…0f…
ADAPTOR PS OH 1 CTX crates which contain adaptor modules
(L/L adaptor TYP 1 & 2 and fiber opic modems
TYP OM-2) are equipped with a power supply
which provides the 18V AC to the modules.
The 18V AC is led to the modules via the
CTX motherboard.
TDX PS The TDX modules in the CTX crate (LTUX, BSM,
CTRL) are supplied with DC power (+5V, +/12V)
from a power supply PS Type CR8022. The DC
voltages are distributed to the modules via
the CTX motherboard.
C̲h̲a̲r̲a̲c̲t̲e̲r̲i̲s̲t̲i̲c̲s̲:
+5V (max 32 A) Potmeter adj. to 4.5-5.8V
+12V (max 2.8 A)
-12V (max 1.2 A) …0e…not adjustable…0f…
- All outpus are short circuit protected
(constant current limiter)
- Overvoltage on the output results in immediate
shutdown
- +5V fused (primary) 3.15 A
+/-12V fused (primary) 0.63 A
- Presence of outputs is indicated on LEDs
on the front panel.
PB 8 FUNCTIONS OH 2 The back panel type
8 interconnects any
V24/V28 communicating
devices. One panel
serves 4 channels.
By means of ON-board
straps, the lines can
be interchanged or
disconnected.
2793A 4:5:1-3
840209 2 of
2
PROGRESS TEST WEEK 4 CAMPS
7 Describe the main difference between the HDLC FRAME
format when TRANSMITTING on the LOWER TDX BUS and
the UPER TDX BUS, respectively.
8 How does the WATCH DOG supervise the TDX CONTROLLER?
9 How is the TDX BUS connected to the TDX CONTROLLER?
10 How is the TDX BUS connected to the LTUX-S MODULES?
11 The STI indicates P.ERR! What is wrng?
12 Describe an easy method to check the correct switchsetting
(S2) in the STI without removing the module from
the crate.
13 Describe the main performances of the LOW LEVEL
ADAPTOR modules.
14 Describe the main difference betweenTYP 1 and TYP
2 LOW LEVEL ADAPTOR.
2793A/rt
840620…02…
GENERAL ABBREVIATIONS
…02……02…CAMPS
DI Discussion
DE Demonstration
L Lecture
GW Group Work
T Test
I Informal Talk
S Self Study
EX Exercise
LG Laboratory Guide
OH Overhead/Handout…86…1
…02… …02… …02…
2793A
840620
WEEK SPECIFIC ABBREVIATIONS
WEEK NO. 4
CAMPS
HBK CR80 MINICOMPUTER HANDBOOK 82/83
SLM CPS/TCM/005 (SITE LEVEL MAINTENANCE MANUAL)
HWB CS/SDS/017 (HARDWARE ASSY BREAKDOWN)
STB I CPS/TMA/005 (STUDENT TEXT BOOK, VOL. I)
STB II CPS/TMA/006 (STUDENT TEXT BOOK, VOL.II)
STB III CPS/TMA/024 (STUDENT TEXT BOOK, VOL. III)
SLG CPS/TMA/025 (STUDENT LABORATORY GUIDE)
2793A/rt…02…4:1:4-6
…02…NEN/840620…02……02…1
STUDENT LABORATORY GUIDE
…02… CAMPS
No exercise in Lesson 4:1:4-6
but Instructor Guided practice subjects as follows:
- TDX SYSTEM INTRODUCTION & DEMONSTRATION
- INTRODUCTION OF THE TDX RELATED SECTIONS OF THE
SLM & HWB.…86…1 …02… …02… …02… …02…
2793A/rt…02…4:2:4-6
…02…NEN/840620…02……02…1
STUDENT LABORATORY GUIDE
…02… CAMPS
T̲D̲X̲ ̲S̲Y̲S̲T̲E̲M̲ ̲S̲T̲A̲T̲U̲S̲ ̲T̲E̲S̲T̲
OBJECTIVES: ENABLE the STUDENT to
- CONFIGURATE a VDU for TDX-CONTROLLER CONNECTION
- STATE the RELATIONSHIP of DEVICE ADDRESS and
LOCATION in the TDX UNITS
- STTE the DIFFERENCE between M&D TDX SYSTEM
TESTS and TDX SYSTEM STATUS TEST
- DESCRIBE the BSM-X BUS SWITCHING
- DESCRIBE the RELATIONSHIP OF BSM-X, TDX-BUS,
and TDX CONTROLLER
REFERENCE: CAMPS SITE LEVEL MAINTENANCE MANUAL, CPS/TCM/005
EXERCISE S̲L̲M̲:̲
GUIDE: SECTION 4.3.3.4, FIGURE 4.3.3.4-2
NOTE! This TEST PROGRAM is part of the APPLICATION
SOFTWARE stored in the TDX CONTROLLER MEMORY.
RESPNSE ON S̲L̲M̲:
THE VDU: SECTION 4.3.3.4, FIGURE 4.3.3.4-2
NOTE! "DEVICE NO." is DECIMAL NO. (See 4:1:1:OH5-7…86…1
…02… …02… …02… …02…
2793A/rt…02…4:2:4-6
…02…NEN/840620…02……02…2
STUDENT LABORATORY GUIDE
…02… CAMPS
B̲O̲O̲T̲ ̲U̲P̲ ̲P̲R̲O̲C̲E̲D̲U̲R̲E̲S̲ ̲f̲o̲r̲ ̲t̲h̲e̲…01…M̲&̲D̲ ̲T̲D̲X̲ ̲S̲Y̲S̲T̲E̲M̲ ̲T̲E̲S̲T̲ ̲P̲R̲O̲G̲R̲A̲M̲S̲
OBJECTIVES: Enable the STUDENTS to BOOT UP the M&D TDX SYSTEM
TEST PROGRAMS from
- FLOPPY DRIVE (FD)
- STORAGE MODULE DRIVE (SMD)
REFEENCE: CAMPS S̲ITE L̲EVEL M̲AINTENANCE MANUAL, CPS/TCM/005
EXERCISE
GUIDE: The following COMMANDS will be entered from the
MAINTENANCE POSITION
l. SELECT an OFF-LINE PU
COMMAND: PU#1 ^ENTER^
or PU#2 ^ENTER^
2. RSET the selected PU
COMMAND: RSET ^ENTER^
3. ENABLE the selected PU
COMMAND: ENPU ^ENTER^
4. ENABLE the "TAKE OWNERSHIP" possibility of
the respective I/O Bus in the CU.
COMMAND: ENTO ^ENTER^
5. ENABLE the resective DISK CONTROLLER.
COMMAND: IR 1A .. ^CR^
MODULE ADDRESS (MA)…86…1
…02… …02… …02… …02…
2793A/rt…02…4:2:4-6
…02…NEN/840620…02……02…3
STUDENT LABORATORY GUIDE
…02… CAMPS
6. BOOT UP from FLOPPY DRIVE (FD)
NOTE! The TEST PROGRAMS concerning the LTUX-S
MODULES associated one TDX UNIT are stored
in the resective DISKETTE labeled with
the TDX UNIT N̲O̲.
Each of these DISKETTES are also containing
the STI TEST PROGRAM and the TDX BUS TEST
PROGRAM.
6.1 INSERT the selected DISKETTE in FLOPPY DISK
DRIVE [ or 1.
6.2 Perform the BOOT COMMANDS acording to S̲L̲M̲,̲
SECTION 4.7.2.1.8, STEP [.
7. BOOT UP from STORAGE MODULE DRIVE (SMD).
NOTE! The TEST PROGRAMS concerning the LTUX-S
MODULES associated one TDX UNIT are stored
in the FILE numbered with the BFD NO. according
to the table elow.
Each of these FILES are also containing
the STI TEST PROGRAM and the TDX BUS TEST
PROGRAM.
TDX SYSTEM TEST PROGRAMS STORED ON THE
DISK PACK:
̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲
^ ̲ ̲T̲D̲X̲ ̲U̲N̲I̲T̲ ̲N̲O̲.̲ ̲^̲ ̲ ̲ ̲ ̲B̲F̲D̲ ̲N̲O̲.̲ ̲ ̲ ̲ ̲^
^ ^ ^
^ 1-5 ^ 2E6 ^
^ 6-A ^ 2E7 ^
^ B-F ^ 2E8 ^
^ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲^̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲^
7.1 INSTALL the DISK PACK in the SMD,
7.2 Perform he BOOT COMMANDS according to S̲L̲M̲,̲
SECTION 4.7.2.1.8, STEP [.
2793A/rt…02…4:2:4-6
…02…NEN/840620…02……02…4
STUDENT LABORATORY GUIDE
…02… CAMPS
S̲T̲I̲ ̲T̲E̲S̲T̲
OBJECTIVES: ENABLE the STUDENT to
- STATE the TDX DEVICES which are ACCESSED by
the TEST
- DESCRIBE the FUNCTION of the TEST
- BOOT UP the TEST PROGRAM
- FULLFIL an ERROR FREE TEST
- STATE the RESPONSE appearing on the VDU
- STATE the ERROR CODES and MESSAGES
REFERENCE: CAMPS SITE LEVEL MAINTENANCE MANUAL, CPS/TCM/005
EXERCISE S̲L̲M̲:
GUIDE: SECTION 4.7.2.1.8, STEP 2-5
RESPONSE ON S̲L̲M̲:̲
THE VDU: SECTION 4.7.2.2, POINT g.2
ERROR CODES S̲L̲M̲:
AND MESSAGES: SECTION 4.7.2.2, POINTS g.8 and g.9…86…1
…02… …02… …02… …02…
2793A/rt…02…4:3:4-6
…02…NEN/840620…02……02…1
STUDENT LABORATORY GUIDE
…02… CAMPS
T̲D̲X̲ ̲B̲U̲S̲ ̲T̲E̲S̲T̲
OBJECTIVES: ENABLE the STUDENT to
- STATE the TDX DEVICES which are ACCESSED by
the TEST
- DESCRIBE the FUNCTION of the TEST
- BOOT UP the TEST PROGRAM
- FULLFIL an ERROR FREE EST
- STATE the RESPONSE appearing on the VDU
- STATE the ERROR CODES and MESSAGES
REFERENCE: CAMPS SITE LEVEL MAINTENANCE MANUAL, CPS/TCM/005
EXERCISE S̲L̲M̲:̲
GUIDE: SECTION 4.7.2.1.8, STEP 6-10
RESPONSE ON S̲L̲M̲:̲
TE VDU: SECTION 4.7.2.2, POINT g.3
ERROR CODES S̲L̲M̲:̲
AND MESSAGES: SECTION 4.7.2.2, POINTS g.8 and g.9…86…1
…02… …02… …02… …02…
2793A/rt…02…4:3:4-6
…02…NEN/840229…02……02…2
STUDENT LABORATORY GUIDE
…02… CAMPS
L̲T̲U̲X̲ ̲S̲T̲A̲T̲U̲S̲ ̲T̲E̲S̲T̲
OBJECTIVES: ENABLE the STUDENT to
- STATE the TDX DEVICES which are ACCESSED by
the TEST
- DESCRIBE the FUNCTION of the TEST
- BOOT UP the TEST PROGRAM
- FULLFIL an ERROR FEE TEST
- STATE the RESPONSE appearing on the VDU
- STATE the ERROR CODES and MESSAGES
REFERENCE : CAMPS SITE LEVEL MAINTENANCE MANUAL, CPS/TCM/005
EXERCISE S̲L̲M̲:̲
GUIDE: SECTION 4.7.2.1.8, STEP 11-14
NOTE! The LTUX ̲STATUS NO." is the respective
LTUX-S PORT ID. (See 4:1:1:OH5-7)
RESPONSE ON S̲L̲M̲:̲
THE VDU: SECTION 4.7.2.2, POINT g.4
ERROR CODES S̲L̲M̲:̲
AND MESSAGES: SECTION 4.7.2.2, POINTS g.8 and g.9…86…1
…02… …02… …02… …02…
2793A/rt…02…4:4:4-6
…02…NEN/840620…02……02…1
STUDENT LABORATORY GUIDE
…02… CAMPS
T̲D̲X̲ ̲L̲T̲U̲X̲ ̲T̲E̲S̲T̲
OBJECTIVES: ENABLE the STUDENT to
- STATE the TDX DEVICES which are ACCESSED by
the TEST
- DESCRIBE the FUNCTION of the TEST
- BOOT UP the TEST PROGRAM
- FULLFIL an ERROR FREETEST
- STATE the RESPONSE appearing on the VDU
- STATE the ERROR CODES and MESSAGES
REFERENCE : CAMPS SITE LEVEL MAINTENANCE MANUAL, CPS/TCM/005
EXERCISE S̲L̲M̲:̲
GUIDE: SECTION 4.7.2.1.8, STEP 15-18
NOTE! OPEN "NO." is the resective LINE PORT ID.
(See 4:1:1:OH5-7)
RESPONSE ON S̲L̲M̲:̲
THE VDU: SECTION 4.7.2.2, POINT g.5
ERROR CODES S̲L̲M̲:̲
AND MESSAGES: SECTION 4.7.2.2, POINTS g.8 and g.9…86…1
…02… …02… …02… …02…
2793A/rt…02…4:4:4-6
…02…NEN/840620…02……02…2
STUDENT LABORATORY GUIDE
…02… CAMPS
T̲D̲X̲ ̲L̲O̲O̲P̲ ̲T̲E̲S̲T̲
OBJECTIVES: ENABLE the STUDENT to
- STATE the TDX DEVICES, ADAPTORS, and PERIPHERALS,
which are ACCESSED by the TEST
- DESCRIBE the FUNCTION of the TEST
- BOOT UP the TEST PROGRA
- FULLFIL an ERROR FREE TEST
- STATE the RESPONSE appearing on the VDU
- STATE the ERROR CODES and MESSAGES
REFERENCE : CAMPS SITE LEVEL MAINTENANCE MANUAL, CPS/TCM/005
EXERCISE S̲L̲M̲:̲
GUIDE: SECTION 4.7.2.1.8, STEP 19-22
NOTE! LOOP "NO." is the respective LINE PORT ID.
(See 4:1:1:OH5-7)
RESPONSE ON S̲L̲M̲:̲
THE VDU: SECTION 4.7.2.2, POINT g.6
ERROR CODES S̲L̲M̲:̲
AND MESSAGES: SECTION 4.7.2.2, POINTS g.8 and g.9…86…1
…02… …02… …02… …02…
2793A/rt…02…4:5:4-6
…02…NEN/840620…02……02…1
STUDENT LABORATORY GUIDE
…02… CAMPS
T̲D̲X̲ ̲V̲D̲U̲ ̲I̲/̲O̲ ̲T̲E̲S̲T̲
OBJECTIVES: ENABLE the STUDENT to
- STATE the TDX DEVICES which are ACCESSED by
the TEST
- DESCRIBE the FUNCTION of the TEST
- BOOT UP the TEST PROGRAM
- FULLFIL an ERROR FEE TEST
- STATE the RESPONSE appearing on the VDU
- STATE the ERROR CODES and MESSAGES
REFERENCE : CAMPS SITE LEVEL MAINTENANCE MANUAL, CPS/TCM/005
EXERCISE S̲L̲M̲:̲
GUIDE: SECTION 4.7.2.1.8, STEP 23-26
NOTE! IO "NO." is the repective LINE PORT ID.
(See 4:1:1:OH5-7)
RESPONSE ON S̲L̲M̲:̲
THE VDU: SECTION 4.7.2.2, POINT g.7
ERROR CODES S̲L̲M̲:̲
AND MESSAGES: SECTION 4.7.2.2, POINTS g.8 and g.9…86…1
…02… …02… …02… …02…
2793A/rt…02…4:5:4-6
…02…NEN/840620…02……02…2
STUDENT LABORATORY GUIDE
…02… CAMPS
C̲R̲A̲T̲E̲ ̲C̲A̲B̲L̲I̲N̲G̲
OBJECTIVES: ENABLE the STUDENT to identify all cables and cable
connections in the TDX SYSTEM.
REFERENCES: CAMPS HARDWARE ASSEMBLY BREAKDOWN/HARDWARE TREE
(CPS/SDS/017).
OH 4 & 5 of te LESSON 4:4:2.
EXERCISE
GUIDE: Switch OFF the MAINS POWER to the TDX CRATES.
Check all TDX CABLE CONNECTIONS according to this
LAB.GUIDE, page 3-7.
Check the INTERNAL CABLE CONNECTIONS according
the OH4 & 5 of the LESSON 4:4:2.
INSERT/CNNECT the MODULES/CABLES if any are REMOVED/DISCONNECTED.
Switch ON the MAINS POWER.
