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Notes: PROPOSED CAMPS HARDWARE C
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…02…
…02…CPS/AUX/002
…02…BHB/19800909…02…#
PROPOSED CAMPS HARDWARE CONFIGURATION
…02……02…CAMPS
T̲A̲B̲L̲E̲ ̲O̲F̲ ̲C̲O̲N̲T̲E̲N̲T̲S̲
1 SCOPE ................................... 4
1.1 SUMMARY ............................. 4
1.2 ..................................... 4
1.3 REFERENCED DOCUMENTS ................ 4
…02…2 PROPOSED CAMPS HARDWARE CONFIGURATION ... 5
…02……02…2.1 HARDWARE SYSTEM PARTITIONING ........ 5
2.1.1 Processor ........................ 5
2.1.2 I/O System ....................... 5
2.1.3 Telecommunications Data Exchange . 6
2.1.4 Distribution ..................... 6
…02……02…2.2 EQUIPMENT DESCRIPTION ............... 8
…02……02……02…2.2.1 Camps Processor Units ........... 8
2.2.1.1 Bus Structure ............... 8
2.2.1.2 CPU's ...................... 34
2.2.1.3 Memory Modules .............. 35
2.2.1.5 Security Aspects ............ 40
2.2.1.6 Data Sheets ................. 42
2.2.2 SCC-System ...................... 43
2.2.2.1 Processor Units ............. 44
2.2.2.2 I/O System .................. 44
2.2.2.3 TDX Bus and LTUX's .......... 45
2.2.3 I/O-system ...................... 45
2.2.3.1 Introduction ................ 48
2.2.3.2 I/O-channel ................. 48
2.2.3.3 Specification for the
CR80D Flatcable bus ......... 49
2.2.3.4 Disk System ................. 72
2.2.3.5 LTU System .................. 74
2.2.3.6 Data Sheets ................. 75
2.2.4 Telecommunications Data Exchange 76
2.2.4.1 76
2.2.4.2 TDX Equipment Structure ..... 77
2.2.4.3 Functional overview of the
TDX concept ................ 82
2.2.5 Distribution ................... 105
2.2.6 Site Equipment Complement ...... 106
1̲ ̲ ̲S̲C̲O̲P̲E̲
1.1 S̲U̲M̲M̲A̲R̲Y̲
A new modified H/W-configuration was presented to SHAPE
in document No. CPS/007/PRO/0002 (ref. 1). CPS/007/PRO/0002
is a revised edition of the original H/W-configuration
document, CPS/007/PRO/0001. These two documents have
the same structure and supply the same detailed information
concerning the proposed H/W-configurations.
Analyses have been conducted and will continuously
be conducted in search for improvements of specifications
and performance.
On the progress meeting 19/20 June 1980 (ref. 2) the
actual status was discussed.
The scope of this document is:
a) to supply additional documentation of the proposed
H/W-configuration.
b) to define a baseline document for the Hardware
configuration.
1.2
1.3 R̲E̲F̲E̲R̲E̲N̲C̲E̲D̲ ̲D̲O̲C̲U̲M̲E̲N̲T̲S̲
1) Revised Technical Proposal HARDWARE CONFIGURATION
Document No.: CPS/007/PRO/0002 February 1980.
2) PROGRESS, Minutes of Meeting No. 2, 19/20 June
80, Item No. 14.
2.1 H̲A̲R̲D̲W̲A̲R̲E̲ ̲S̲Y̲S̲T̲E̲M̲ ̲P̲A̲R̲T̲I̲T̲I̲O̲N̲I̲N̲G̲ ̲
The hardware configuration for CAMPS is an integral
part of a total system concept which also includes
software and operational procedures. The system functions
are allocated between hardware, software or firmware
and partitioned so as to provide the optimum implementation
of the CAMPS systems.
The allocation of functions between system elements
has resulted in the hardware configuration described
in this section. This configuration has been further
partitioned into well-defined sub-sysems or equipment
groups.
There are (four) major elements to the CAMPS; these
are depicted in figure 2.1-1 and defined as follows:
2.1.1 P̲r̲o̲c̲e̲s̲s̲o̲r̲
Processor composed of a dual set of Processor units
capable of individual operation, with multiple CPUs,
memory modules, buses and control.
Their operation within the system is coordinated and
monitored by the System and Status Controller (SSC).
The SSC coordinates and monitors the operation of
the other elements of the system as well. "Watchdog"
functions distributed throughout the system are monitored
by the SSC.
2.1.2 I̲/̲O̲ ̲S̲y̲s̲t̲e̲m̲
The I/O system is composed of a dual channel I/O crate
system containing:
a) Triple Disk Subsystem: This system contains three
identical assemblies including controller, disk
drive and 80 MB disk. Each assembly is ported
towards both the I/O channels and is thus controllable
by either PU.
b) LTU Subsystem: This system is composed of LTUs.
These are used for driving the heavy communication
protocols. Each LTU is ported towards both I/O
channels and is thus controllable by either PU.
2.1.3 T̲e̲l̲e̲c̲o̲m̲m̲u̲n̲i̲c̲a̲t̲i̲o̲n̲s̲ ̲D̲a̲t̲a̲ ̲E̲x̲c̲h̲a̲n̲g̲e̲ ̲(̲T̲D̲X̲)̲
Telecommunications Data Exchange (TDX) is comprised
of 2 Host I/F assemblies (each connected to the PU-buses
with direct memory access), the dualized TDX input/output
transfer buses, multiplexer controllers and the complement
of line termination units (LTUX's)
2.1.4 D̲i̲s̲t̲r̲i̲b̲u̲t̲i̲o̲n̲
The connection of external circuits and terminals to
the CAMPS is done by the distribution equipment. When
different interfaces with different I/F-concepts are
required, the distribution equipment configuration
will show a number of variants to apply with the test,
monitor, and connection requirements of each interface
concept:
a) VDUs and printers connected by optical fibre cables.
b) Low speed channels connected by electrical secure
wiring.
c) Local external circuits without crypto.
d) Remote terminals (VDUs and printers) with crypto-conversion
and modem transmission.
e. Remote external circuits with crypto-conversion
and modem transmission.
The distribution equipment is constructed in a modular
way so that changes and maintenance are easily handled.
Having identified the Hardware System elements and
defined the nomeclature, each element will be described
into details in the following sections.
Fig. 2.1-1
2.2 E̲Q̲U̲I̲P̲M̲E̲N̲T̲ ̲D̲E̲S̲C̲R̲I̲P̲T̲I̲O̲N̲
2.2.1 C̲A̲M̲P̲S̲ ̲P̲R̲O̲C̲E̲S̲S̲O̲R̲ ̲U̲N̲I̲T̲S̲
2.2.1.1 B̲u̲s̲ ̲S̲t̲r̲u̲c̲t̲u̲r̲e̲ ̲a̲n̲d̲ ̲C̲o̲n̲t̲r̲o̲l̲ ̲M̲o̲d̲u̲l̲e̲s̲
2.2.1.1.1 C̲R̲8̲0̲D̲ ̲B̲u̲s̲e̲s̲
The CR80D minicomputer is a modular and flexible system
with a processing range from a single card single bus
system to a multiple processor units multiple buses
system.
The basis elements in the CR80D are the modules which
are functional and mechanical selfcontained building
blocks interconnected by one or two transfer buses
as shown in figure 2.2.1.1.1.-1.
The number of modules which can be interconnected without
active bus extension is restricted by the length of
the transfer bus due to delay and distortion.
Figure 2.2.1.1.1-1
2.2.1.1.2 M̲o̲d̲u̲l̲e̲ ̲I̲n̲t̲e̲r̲c̲o̲n̲n̲e̲c̲t̲i̲o̲n̲ ̲B̲u̲s̲e̲s̲
The module interconnection buses are from a functional
point of view different, but concerning the mechanical,
electrical and timing characteristics they are compatible.
The buses and their position in the system are illustrated
in figure 2.2.1.1.2-1.
In the processor unit (PU) two transfer buses are available
for module intercommunication; the Processor bus and
the Channel Bus.
The Processor Bus is used by the CPU's for data and
instruction communication with the memory modules and
for set-up, status and control communication with the
MAP and DMA modules.
The Channel Bus is not available for the CPU's but
is used by the MAP and DMA modules for information
exchange with the connected equipment (I/O crates and/or
PU's).
In the I/O crate two transfer buses are available for
information exchangement between the I/O modules and
the PU's. These two buses are functional equal and
are used as back up for each other in redundance systems.
In the following a detailed description of the mechanical,
electrical and timing characteristics of the buses
are given. As mentioned before the interface specifications
for the four buses are the same (The CR80D Main Bus
specifications).
Figure 2.2.1.1.2-1
2.2.1.1.3 C̲R̲8̲0̲D̲ ̲M̲a̲i̲n̲ ̲B̲u̲s̲ ̲S̲p̲e̲c̲i̲f̲i̲c̲a̲t̲i̲o̲n̲
The CR80D modules are mechanical selfcontained units
housed in a standard 19" mechanical frame (crate).
The modules are inserted in the crate from the front
and connects to the Main Bus/Buses by 86 pin edge connectors
located at the rear of the module (ref. figure 2.2.1.1.3-1).
Within a crate the CR80D Main Bus (DMB) is a PCB equipped
with connectors (Mother Board see figure 2.2.1.1.3-2)
for the module interface.
The DMB is terminated in both ends by termination board
to form a set of transmission lines well suitable as
the communication paths between the modules.
The mother board gives a parallel bus structure with
86 parallel lines meaning that the main bus does not
put any restrictions on the modules location within
the crate. Pin lay-out for the Main Bus connector is
shown in figure 2.2.1.1.3-3.
Figure 2.2.1.1.3-1
Figure 2.2.1.1.3-2
Figure 2.2.1.1.3-3
2.2.1.1.4 F̲u̲n̲c̲t̲i̲o̲n̲a̲l̲ ̲D̲e̲s̲c̲r̲i̲p̲t̲i̲o̲n̲ ̲o̲f̲ ̲C̲R̲8̲0̲D̲ ̲M̲a̲i̲n̲ ̲B̲u̲s̲
The Main Bus performs the media for exchange of information
between the modules connected to the bus as well as
for the I/O interrupt and timing signals.
Data and instruction transfer is performed under control
of a CPU or DMA module by means of the handshaking
signals TRQ(L), AE(L) and (RS(L). The CPU or DMA module
transmits the location address (I/O or memory) to the
bus address lines AD0-AD17, LS0, LS1, BS0, BS1 and
R/W (L/H) and transmit or receive the addressed information
(16 bits word/8 bits byte).
The transfer is asynchroneous so that modules with
different response times can be connected to the bus.
The I/O interrupt code is transmitted in serial form
from the modules in synchroneous with the master timing
signals.
In the following the signals on the Main Bus are defined:
M̲a̲s̲t̲e̲r̲ ̲T̲i̲m̲i̲n̲g̲ [1(A35) and [2 (A38)
Two signals [1 and [2 are available on the bus for
I/O interrupt transmission and for internal timing
in the modules connected to the Main Bus. The timing
diagram figure 2.2.1.1.4-1 defines the signals.
I̲/̲O̲ ̲I̲n̲t̲e̲r̲r̲u̲p̲t̲ ̲S̲i̲g̲n̲a̲l̲s̲ INA(H) (A32) and INR(L) (A33)
The CR80D I/O interrupt system is based upon serial
transmission, of the interrupt code, from the interrupting
I/O module.
The serial code will be converted to parallel form
either by the SCM module or by the I/O channel I/F
and thereby be available for the CPU upon request.
Two of the Main Bus lines are used for I/O interrupt
transmission:
INR (Interrupt Request) & INA (Interrupt Acknowledge).
The interrupt code consisting of 8 bit is transmitted
on the INR line synchroneous with the 1 MHZ signal
[1.
INR is an open collector line so that all the I/O modules
can transmit on the same line, which means that if
one module is transmitting an "0" and another a "1",
the line will contain the "0".
INA is an open collector line too, because it is driven
from the Main Bus termination boards, one in each end
of the Bus. The contents of INA is INR inverted. Each
of the interrupting I/O module compares for each of
the eight bits the contents of INA with the bits it
is transmitting to INR. If the comparison does not
match which means that a module with a higher interrupt
code is transmitting at the same time, the module disables
the transferring of its code to INR until the next
1 MHZ period.
On that way the contents of INR will be unique and
correspond to the highest interrupt transmitted during
that period. The module which detects this situation
has got its interrupt acknowledge and will stop the
interrupt sending.
Figure 2.2.1.1.4-2 illustrates the function and the
connection of the I/O interrupt circuit.
The 8 bits interrupt code consists of two parts; a
2 bits priority corresponding to four levels and a
6 bits module address corresponding to 64 modules which
can operate with I/O interrupt.
Two of the 64 module addresses are restricted:
The address 00 will not be recognized because it corresponds
to the idle state of the interrupt lines. The address
63 is not allowed, since it is used by the interrupt
receiving module when its internal interrupt queue
is full and it therefore has to queue the interrupts
directly on the Main Bus interrupt lines.
When an I/O module will transmit an interrupt, it starts
with priority bits and continue with the address bits
ref. timing diagram figure 2.2.1.1.4.-3.
Figure 2.2.1.1.4-1
Figure 2.2.1.1.4-2
Figure 2.2.1.1.4-3
M̲a̲s̲t̲e̲r̲ ̲C̲l̲e̲a̲r̲ MC(H) (B29)
The Master Clear signal is used for resetting the modules
to a well defined state when power is switched on and
when the System Control Module (SCM) is commanded to
generate a clear by a CPU. The signal sequence during
power up and programmed clear is shown in figure 2.2.1.1.4-4.
When the I/O modules recognize a Master Clear they
have to reset all their internal functions to the start
up condition.
The memory modules must not use the Master Clear signal
but only the power up sequence for resetting.
A̲d̲d̲r̲e̲s̲s̲ ̲L̲i̲n̲e̲s̲
AD0-AD17 (A16-B19, A21-B25)
BS0 (A36), BS1 (B36), LS0 (A26), LS1 (B26)
R/W (L/H) (A34)
The parallel CR80D address bus contains 23 lines allowing
addressing of up to 1 mega word (2 mega bytes) and
64 I/O modules.
The R/W (L/H) signal specify the source for the data
bus.
R/W (L/H) Logic "0" Read: Contents of addressed loca-
tion is transferred to
the
data bus.
R/W (L/H) Logic "1" Write: Contents of data bus sourced
by the CPU or DMA are
trans-
ferred to the addressed
loca-
tion.
LS0, LS1 these two address bits specify whether the
location addressed by the remaining part of the address
bus is an I/O, memory word or byte as defined in figure
2.2.1.1.4-5.
Fig. 2.2.1.1.4-4
F̲i̲g̲.̲ ̲2̲.̲2̲.̲1̲.̲1̲.̲4̲-̲5̲
L̲o̲c̲a̲t̲i̲o̲n̲ ̲S̲e̲l̲e̲c̲t̲i̲o̲n̲
L̲S̲1̲ ̲ ̲ ̲ L̲S̲0̲ ̲ ̲ ̲ ̲ ̲ A̲d̲d̲r̲e̲s̲s̲e̲d̲ ̲L̲o̲c̲a̲t̲i̲o̲n̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲
0 0 I/O Module
0 1 Lower byte DA0-DA7 Memory
1 0 Upper byte DA8-DA15 Module
1 1 Word DA0-DA15
D̲a̲t̲a̲ ̲L̲i̲n̲e̲s̲
DA0-DA15 (A2-B9), LP (B28), UP (A28)
The information communicated on the parallel CR80D
data bus is 16 bit + 2 parity bit. There is one parity
bit for each of the two 8 bit bytes; UP is parity for
upper byte DA8-DA15 and LP for lower byte DA0-DA7.
During read operation from I/O modules the parity
bits are not checked.
During read of byte from memory both parity bits have
to be correct independent of which byte is addressed.
Odd parity is used for both bytes. DA0 is LSB and
DA15 is MSB in the data word.
The data bus is bidirectional and the source for this
bus is specified in the Main Bus address field by the
R/W (L/H) signal.
R/W (L/H): Logic "0" Read: Operation is performed
meaning that the content
of the addressed location
in the module (I/O or
me-
mory) is transmitted
to the
data bus.
R/W (L/H): Logic "1" Write: Operation is performed
meaning that the address
sourcing module
(CPU or DMA)
transmit on
the data bus.
For the timing specification for the data bus lines
ref. CR80D Main Bus communication.
BS0, BS1 memory address bits used for selecting one
out of the four possible 256K word memory banks in
the Main Bus as shown in figure 2.2.1.1.4-6
F̲i̲g̲.̲ ̲2̲.̲2̲.̲1̲.̲1̲.̲4̲-̲6̲
M̲e̲m̲o̲r̲y̲ ̲B̲a̲n̲k̲ ̲S̲e̲l̲e̲c̲t̲i̲o̲n̲
BS1 BS0 Selected Bank Address Space
0 0 0 0 to 256K-1
0 1 1 256K to 512K-1
1 0 2 512K to 768K-1
1 1 3 768K to 1024K-1
AD0-AD17 lines are the word pointer within the selected
memory bank when the addressed location is in a memory
module. If the addressed location is in a I/O module
only the 12 LSB are valid for the module while the
remaining part of the address bus is used by the MAP
module. The 12 bits address field valid for I/O modules
is divided in two parts:
AD0-AD5: 6 bits module address corresponding to
the address part of the I/O interrupt code.
AD6-AD11: 6 bits command field for the addressed
module.
Figure 2.2.1.1.4-7 gives a summary of the CR80D Main
Bus address bus. For the timing specification for
the address lines ref. Main Bus Communication.
F̲i̲g̲.̲ ̲2̲.̲2̲.̲1̲.̲1̲.̲4̲-̲7̲
T̲r̲a̲n̲s̲f̲e̲r̲ ̲C̲o̲n̲t̲r̲o̲l̲ ̲S̲i̲g̲n̲a̲l̲s̲
TRQ(L) (A31), AE(L) (A37)
RS(L) (A30) & BD(L) (A29)
Four signals on the CR80D Main Bus are used for controlling
of the information transfer on the bus. Three of the
signals TRQ(L), AE(L), BD(L) are used as address validity
control during read operation and as address and data
validity control during write operation.
The signal TRQ(L) is generated by the CPU or DMA module
specifying that the address bus except BS0 and BS1
is valid.
BD(L) is transmitted from the MAP module to the CPU's
and DMA to switch off address lines AD9-AD17.
AE(L) is issued from the MAP validity control for the
complete modified address field.
The last signal RS(L) is the response signal from the
addressed module indicating when going active in Read
operation or data received in Write operation
Two different sequences will be possible for the signals.
One sequence when there is a MAP module connected
to the Main Bus and another without as illustrated
in figure 2.2.1.1.4-8. The timing restrictions on
the signals in relationship to the address and data
signals are defined in Main Bus Communication.
F̲i̲g̲.̲ ̲2̲.̲2̲.̲1̲.̲1̲.̲4̲-̲8̲
2.2.1.1.5 M̲a̲i̲n̲ ̲B̲u̲s̲ ̲C̲o̲m̲m̲u̲n̲i̲c̲a̲t̲i̲o̲n̲
This part describes the timing specification for the
two different module types connected to the CR80D Main
Bus, the address sourcing modules (CPU/DMA) and the
address destination modules (I/O/Memory).
Address Sourcing Modules:
The CPUs and DMA modules get control of the Main Bus
by requesting the bus arbitrator module (SCM). The
signals used for the control of the Main Bus access
are Bus Request BRQ(L) , Bus Grant BG(L) and Lock
Bus Grant LBG(L) . Each address sourcing module has
its own BRQ, LBG and BG connected directly between
the module and the arbitrator outside the Main Bus.
When a module requires the authority over the Main
Bus it issues BRQ(L). When the Main Bus is free the
module receives (BG(L), meaning that bus transfer may
be carried out without conflict with other modules.
If the module operates with semaphore the signal LBG(L)
is issued and thereby lock the Main Bus authority to
the module during transfer of more than one data word.
A detailed description of these signals are given in
the CR80D System Control Connections.
The signal sequences for communication on the CR80D
bus and the timing specifications for the signals are
given in figure 2.2.1.1.5-1 for addressing sourcing
modules (CPU/DMA).
In figure 2.2.1.1.5-2 the specifications for the MAP
module are given.
The specifications applicable for I/O and memory modules
(Address Destination Modules) are given in figure 2.2.1.1.5-3.
In figure 2.2.1.1.5-4 the complete signal sequence
during data transfer on the CR80D Main Bus is shown.
Figure 2.2.1.1.5.-1
Figure 2.2.1.1.5-2
Figure 2.2.1.1.5-3
Figure 2.2.1.1.5-4
2.2.1.2 C̲P̲U̲s̲ ̲(̲B̲a̲s̲i̲c̲ ̲P̲r̲o̲c̲e̲s̲s̲o̲r̲ ̲M̲o̲d̲u̲l̲e̲s̲)̲
The CPU module is a general purpose processing unit
with a 16 bit word length and able to address 256K
words of memory. The CPU has two instruction sets.
The standard instruction repertoire has 274 basic arithmetic,
logic, transfer and special instructions including
bit, byte and multiple word manipulations.
Internal registers include 8 general purpose accumulator
or index registers, a data base register (BASE), a
program base register (PROG), a program counter (PRPC),
a timer register (TIMER), a process status word (PSW)
and a modify register (MOD).
Instructions are provided to save and load all registers
minimizing overhead when switching processes.
Instructions can be addressed directly relative to
PROG and PRPC, indexed relative to PRPC and indirect
through process data or program parameters relative
to PROG. The length of all instructions is one 16 bit
word.
The standard instruction set is contained in 700 words
of a 2K x 64 bits PROM.
The alternative instruction set may contain:
- Decimal arithmetic instructions
- Instructions supporting high level languages
- (Microcoded) Monitor routines
- User defined instructions.
The hardware of the CPU supports base register machines
as well as stack oriented machines: two 16 bit ALUs
allow address calculations involving three elements
to be performed in one cycle, or address and data manipulations
to be performed in parallel. In addition, special hardware
is employed to optimize decoding of opcodes and addresses
and extracting displacement fields of the instructions.
Cycle time is 250 nsec.
Interrupts are resolved by the hardware. Three types
of interrupts exist:
CPU, TIMER, and I/O interrupt. Independent masks are
available in the process status word for each interrupt.
I/O interrupts (up to 256) are grouped in 4 priority
levels. Only interrupts with priority higher than or
equal to the priority of the process executing in the
CPU are serviced. I/O interrupts can be handled by
user defined microprogram or result in swithching of
software process. TIMER interrupts normally occur every
150 us and are serviced by u-program. When received
the TIMER register is decremented and tested (takes
2 cycles). If negative a local interrupt is generated.
CPU interrupts are serviced by the u-program, handling
the message related to the interrupt. Depending on
the message a switch of software process may take place
or the current process may continue.
2.2.1.3 M̲e̲m̲o̲r̲y̲ ̲M̲o̲d̲u̲l̲e̲s̲
2.2.1.3.1 C̲R̲8̲0̲D̲ ̲M̲e̲m̲o̲r̲y̲ ̲M̲a̲n̲a̲g̲e̲m̲e̲n̲t̲
B̲a̲c̲k̲g̲r̲o̲u̲n̲d̲ ̲t̲o̲ ̲A̲d̲d̲r̲e̲s̲s̲ ̲T̲r̲a̲n̲s̲l̲a̲t̲i̲o̲n̲
The concept behind the various memory management features
available with the CR80D computer is that of "Logical-to-Physical
Address Translation". The amount of memory required
by a user's program is defined to be his "logical address
space". This space may be as large as 64 1K pages.
The areas of physical storage assigned to the user
are defined to be his "physical address space". The
address translation function that converts addresses
in the logical space to address in the physical space
is called the "address map segment" for that user.
Each user has his own, unique logical-to-physical address
map. In addition, there are separate map segments for
I/O data channel. The CR80D Advanced Multiprocessing
Operating System (DAMOS) determines what these maps
are to be, and then relays this information to the
address translation hardware. Figure 2.2.1.3.1-1 shows
the logical to physical address translation.
Each user owning his private 64K virtual address map
segment, the setup of which is totally under control
of the system software and where each of 1 K pages
can be read or write protected, ensures total integrity
and security from interference form other users, e.g.
programs being debugged while the system is running
in actual on-line operation. Beyond being able to be
read and write protected, each 1K page separately can
be marked "absent" giving raise to a system interrupt
when accessed. This feature is utilized by the file
management system to implement a very efficient disc
overlay routine, ensuring efficient utilization of
memory by only rolling those pages of program or data
in from discs which are actually absent, e.g. physical
memory page has recently been utilized by other users.
Each CPU in a Processor Unit (PU) can work with different
64K memory map segments concurrently, which ensures
safe, hardware protected multiprocessing.
The I/O Data Channel likewise is ensured not unwantedly
to interfere with users by working through its private
64K memory map segment.
Figure 2.2.1.3.1-1
2.2.1.3.2 C̲R̲8̲0̲D̲ ̲M̲e̲m̲o̲r̲y̲ ̲M̲a̲p̲ ̲A̲d̲d̲r̲e̲s̲s̲ ̲T̲r̲a̲n̲s̲l̲a̲t̲i̲o̲n̲
The memory map performs address relocation and memory
protection for up to 16384K words (K = 1,024) of physical
memory by translating the 16 bit memory address and
a 6 bit key into a 24 bit physical address. Mapping
operations can be performed independently in up to
sixtyfour 64K logical (virtual) memory areas.
The logical memory addresses are mapped into physical
memory pages consisting of 1K word each. Page assignments
for each logical memory are under control of the page
allocation routine.
The segment register to be used for a table look up
is selected as a function of the address sourcing modules
number, known from the bus authority control, two registers
are available per module and which of the two registers
to be used is determined for the CPU by the address
bit number 16 ('1' Program & '0' Data) and for
the DMA modules on the channel bus the R/W signal performs
the one out of two segment register selections.
The segment register configuration described above
means that 64K words of program and 64K words of data
is available for a CPU without changing the segment
register set up, and that a DMA module can operate
with a read only area of 64K words and a write only
area of 64K words with one specific register set.
Output from the segment registers (six bits) together
with six bits (AD10-15) from the logical address forms
the address input to the address look up table (4K
x 16 bit RAM). Output from the table consists of 18
bits, two bits for odd parity, one for each byte, two
bits for memory access protection and the remaining
14 bits form the high order bits of the physical address
field. Together with the ten least significant bits
of the logical address, the output from the look up
table forms a 24 bits word address given a total address
space of 16 mega words.
As seen in figure 2.2.1.3.2-1 the implemented memory
address translation allows an efficient utilization
of the memory because programs and data do not need
to be contiguous areas, but are divided into pages
of 1K word. Another feature is that exchange of working
memory in the physical space is performed by changing
only two registers, the program - and the data segment
register.
Figure 2.2.1.3.2-1
A̲c̲c̲e̲s̲s̲ ̲P̲r̲o̲t̲e̲c̲t̲i̲o̲n̲
In connection with the fourteen bits page address the
two protection bits are used to avoid unauthorized
access to the protected parts of the memory. The two
bits define the following conditions: Full access,
Read only, No access, Page absent.
AD17 from the logical address specifies the state of
the current active process in the CPU, user or system
state, if in the system state the whole physical area
is available for the process.
If an not allowed access is performed the transfer
is terminated without sending the physical address
to the memory by signalling a transfer error to the
CPU.
This signalling is performed outside the two transfer
buses in the PU, but on the special system control
signals connected directly between the MAP and the
address sourcing modules in the system.
The transfer error will force the CPU into its error
micro program routine, and this routine will fetch
the error cause by a normal I/O transfer from the MAP
module.
2.2.1.5 S̲e̲c̲u̲r̲i̲t̲y̲ ̲A̲s̲p̲e̲c̲t̲s̲
The inherent logical separation of programs and data
in the CR80 architecture is well suited for restricting
unauthorized access to data and processes and for preventing
non-intended modification of programs.
Security features are implemented in the Central Processor
by means of privileged instructions and memory protection.
The objectives of the protective mechanisms in the
CR80 processor are:
- to protect data belonging to a process against
non-intended modification by other processes and
against non-authorized reading;
- to protect programs against non-intended modifications,
and,
- to prevent processes from monopolizing the processor.
The protection mechanisms are implemented by introducing
a processor state variable which can take two values
- USER STATE
- SYSTEM STATE
and by dividing the instruction set into privileged
or non-privileged instructions. The privileged instructions
can only be executed in the SYSTEM STATE; the instructions
are:
SVP, LDM, LDS, LDT, SVS, SVT,
LDP, LDN, LDR, XRM,
CIA, SIO, WIO, RIO, CPU, INT.
Attempted execution of these instruction in the USER
STATE generates a local interrupt upon which the CPU
will automatically enter the SYSTEM STATE.
2.2.1.6 D̲a̲t̲a̲ ̲S̲h̲e̲e̲t̲ ̲(̲P̲U̲-̲m̲o̲d̲u̲l̲e̲s̲)̲
The following data sheets are as follows:
CR8003D/YYYPX/00 CPU CACHE, p. 1-4
CP8016D/YYYXX/00 RAM, p. 1-2
CR8020D/OXXPC/00 MAP & I/O CHANNEL DMA, p. 1-4
CR8071D/010--/00 MAP TO I/O CHANNEL ADAPTER, p. 1-1
CR8055D/010XX/00 MBT MAIN BUS TERMINATION, p. 1-1
CR80D CRATE AND CABLING, p. 1-6.
2.2.2 S̲S̲C̲ ̲S̲y̲s̲t̲e̲m̲ ̲(̲S̲y̲s̲t̲e̲m̲ ̲S̲t̲a̲t̲u̲s̲ ̲a̲n̲d̲ ̲C̲o̲n̲t̲r̲o̲l̲l̲e̲r̲)̲
The CAMPS hardware configuration is continuously monitored
by the System Status and Controller. Switchover of
the Central Processors from active to stand-by can
be under automatic or manual control. Reconfiguration
commands from the ON-LINE processor or system control
console are executed by a microprocessor in the SSC.
The System Status and Controller, SSC, continuously
monitors the operational status and functioning of
the CAMPS configuration. When a failure is detected,
SSC sets an alarm and sends a control message to the
stand-by CP and to the system console; in most cases
this will initiate a central processor switchover.
Peripheral failure will result in partial reconfiguration.
The current configuration status is displayed at the
system panel at all times.
The SSC operates in two modes: manual or automatic.
In the automatic mode the peripherals are claimed and
controlled by the ON-LINE processor; in the manual
mode, peripheral assignments and reconfiguration are
initiated or overridden at the Status Control Panel
or by a system control transaction through the system
control console.
This section lists and describes the functions performed
by the SSC.
The SSC monitors and controls the status and availability
of all major subsystems through hard-wired interfaces
and data channels. The Central Processors each report
status and receive commands through a 9600-baud (V24/V28)
data channel.
The dual TDX monitoring and selection is under control
by the CP with status display and override at the SSC.
The TDX-connected LTUX's are controlled in multi-unit
groups at the crate level by fixed wiring from the
SSC which also displays the status of each crate; indivudual
LTU's, normally in the automatic mode can be disabled
by switching the unit to the manual mode. The interaction
of each subsystem with the SSC is briefly described
in the following paragraphs.
The major subsystems which interact the SSC are:
- Processor Units
- Disk System
- LTU-System
- TDX-System
2.2.2.1 P̲r̲o̲c̲e̲s̲s̲o̲r̲ ̲U̲n̲i̲t̲s̲
The SSC receives periodic status reports from both
the active and stand-by PU at a predetermined frequency
via 9600-baud data channels. The status pattern received
from the PU's is compared against an internal PROM-resident
table; the status pattern alternates such that two
subsequent patterns don't remain in the same steady
condition.
If a failure is recognized in the ON-LINE PU an alarm
is set and a control message is sent to the OFF-LINE
PU, and displayed at the system control console. If
a failure is recognized in the OFF-LINE PU, the same
procedure is followed when the PU is in the standby
mode, should the OFF-LINE PU be taken out of service
or unavailable, it is removed from the status check
sequence.
In the automatic mode, detection of ON-LINE PU failure
results in a switch-over request from the SSC to the
standby PU. The stand-bu PU acknowledges the request
when it is in a position to accept control of the peripherals.
In the manual mode, no switchover occurs on failure,
the reaction to the alarm condition is expected from
operating personnel.
2.2.2.2 I̲/̲O̲-̲S̲y̲s̲t̲e̲m̲
The dual-posted I/O-subsystems provide an interface
to the dualized I/O-channels.
Each subsystem is assigned to one of the PU-systems.
The subsystem has "ownership" on the subsystem.
Ownership is changes only by the operating system issuing
a TAKE OWNERSHIP I/O command.
Execution of ownership changes is controlled by the
SSC on the I/O-subsystems, i.e. the tripple disk system
and the LTU system.
2.2.2.3 T̲D̲X̲ ̲B̲U̲S̲ ̲A̲N̲D̲ ̲L̲T̲U̲X̲'̲S̲
The status monitoring and control for the TDX-connected
LTUX units can be effected at two levels: at the crate
level for a group of LTUX or on System level, switching
the LTUXs to TDX Bus no. 1 or no. 2. At the crate level,
the status of each crate is monitored and displayed
through wiring from the SSC. Control is either manual
or automatic from the ON-LINE PU via the SSC microprocessor.
At the LTUX level, the automatic mode control operation
may be disabled by switching to manual mode; a mode
switch is provided in each LTUX. In the automatic mode,
this switch can be controlled by a command on the active
TDX bus.
2.2.3 I̲/̲O̲ ̲S̲Y̲S̲T̲E̲M̲
a̲.̲ ̲I̲n̲t̲r̲o̲d̲u̲c̲t̲i̲o̲n̲
The I/O system has a design goal of being very efficient
in a transaction, on-line oriented environment. This
environment has constraints different from those of
a batch environment. The figure of merit in an on-line
system is the number of transactions/
second/dollar that can be handled by the system. We
also wanted an I/O system that had low overhead, fast
transfer rates, no overruns, and no interrupts to the
system until a logical entity of work was completed
(i.e., no character by character interrupts from the
terminals). The resulting design satisfied these goals
by implementing and I/O system that was extremely simple.
I/O controllers reconnect to the channel when their
buffers are stressed past a configurable threshold,
transfer data in a burst mode until their buffer stress
is zero (buffer empty on input operations, full on
output operations) and disconnect from the channel.
When the transfer terminates the I/O controller interrupts
the processor. Controllers may interrupt for other
reasons than an exhausted byte count, e.g., a terminal
controller receiving and end-of-page character from
a page mode terminal, or I/O channel error condition,
or a disc pack being mounted.
b̲.̲ ̲T̲h̲e̲ ̲I̲n̲p̲u̲t̲/̲O̲u̲t̲p̲u̲t̲ ̲C̲h̲a̲n̲n̲e̲l̲
The heart of the CR80D I/O System is the I/O channel.
All bulk I/O is done on a direct memory access (DMA)
basis. With the block size determined by the individual
application. All I/O controllers are buffered to some
degree so that all transfers over the I/O channel are
at memory speed (2M words/second) and never wait for
mechanical motion since the transfers always come from
a buffer in the I/O controller, rather than from the
actual I/O controller, rather than from the actual
I/O device.
For setup, control and status between PU and I/O controllers,
programmed I/O (direct from CPU's) can be used concurrently
with the data channel DMA transfers.
The channel does not execute channel programs as on
many systems, but it does do data transfer in parallel
with program execution. The memory system priority
on PU channel bus always permits I/O accesses (in an
on-line, transaction oriented environment, it is rare
that a system is not I/O bound). The maximum I/O transfer
is 64K bytes.
c̲.̲ ̲D̲u̲a̲l̲-̲P̲o̲r̲t̲ ̲C̲o̲n̲t̲r̲o̲l̲l̲e̲r̲s̲
The dual-ported I/O device controllers provide the
interface between the CR80D standard I/O channel and
a variety of peripheral devices using distinct interfaces.
While the I/O controllers are vastly different there
is a commonality among them that folds then into the
CR80D fault resistant architecture.
Each controller contains two independent I/O channel
ports implemented by IC packages which are physically
separate from each other so that no interface chip
can simultaneously cause failure of both ports. Each
port of each controller has a 6-bit configurable controller
number, and interrupt priority setting. These settings
can be different on each port. The only requirement
is that each port attached to an I/O channel must be
assigned a controller number and priority distinct
from controller numbers and priorities of other ports
attached to the same I/O channel.
A power-on condition causes a controller reset and
also gives an interrupt to one of the two processors
to which it is attached. The output of the Power On
Detection circuit is also used to enable all the I/O
channel bus transceivers so that a controller being
powered down will not cause interference on the I/O
channels during the power transient. This is possible
because the PON circuit operates with very low supply
voltage and special transceivers are used which correctly
stay in a high impedance state as long as the supply
voltage is too low for correct functioning of the board
logic circuitry.
Logically only one of the two ports of an I/O controller
is active and the other port is utilized only in the
event of a part failure to the primary port. There
is an "ownership" bit indicating to each port if it
is the primary port or the alternate. Ownership is
changes only by the operating system issuing a TAKE
OWNERSHIP I/O command. Executing this special command
causes the I/O controller to swap its primary and alternate
port designation and to do a controller reset. Any
attempt to use a controller which is not owned by a
given processor will result in a ownership violation.
If a processor determines that a given controller is
malfunctioning on its I/O channel, it can issue a DISABLE
PORT command that logically disconnects the port from
that I/O controller. This does not affect the ownership
status. That way, if the problem is within the port,
the alternate path can be used, but if the the problem
is in the common portion of the controller, ownership
is not forced upon the other processor.
A controller signals an interrupt on the I/O channel
if the channel has indicated an exhausted transfer
count, if the controller terminates the transfer prematurely,
or for attention purposes.
When simultaneous interrupts occur on an I/O channel,
standard CR80D priority scheme determines which interrupt
is handled first.
Note, only 256 I/O controllers can be assigned to a
given channel and each one has a unique rank and position
designation. The highest priority controller is granted
access to the interrupt system. Thus a radial polling
technique allows the processor to resolve 256 different
controller priorities in just one poll cycle. Each
port of a controller has a separate set of configuration
jumpers so that a controller can have different priorities
on its primary and alternate path.
2.2.3.1 I̲n̲t̲e̲r̲c̲o̲n̲n̲e̲c̲t̲i̲o̲n̲s̲ ̲i̲n̲ ̲I̲/̲O̲-̲S̲y̲s̲t̲e̲m̲
The I/O channel bus, connecting I/O crates to the Processor
Unit, is implemented with ribbon cable. The I/O channel
ribbon cable is connected to the Datachannel and Memory
Map module in the Processor Unit via the MAP to I/O
channel Adaptor card (MIA), positioned in the Adaptor
crate at the rear of the processor crate. At the I/O
crates the ribbon cable is connected to either the
A or B Bus (standard 86 pin CR80 Main Busses) via the
crate to I/O channel adaptor (CIA, A or CIA, B) positioned
at the rear of the I/O crate.
Peripheral I/O devices are connected by cable via a
Line Interface Adaptor card (LIA), positioned in the
peripheral adaptor crate placed at the rear of the
I/O crate.
2.2.3.2 I̲/̲O̲ ̲C̲h̲a̲n̲n̲e̲l̲
The CR80D I/O Channel performs the interface between
the Processor Unit and the I/O Crate (I/O modules).
The communication is controlled from the processor
unit meaning that no bus arbitration function is included
in the I/O crate.
The data transfer is performed as block transfer except
that the data transfer is bidirectional (to/from the
bus controlling processor unit).
2.2.3.3 S̲p̲e̲c̲i̲f̲i̲c̲a̲t̲i̲o̲n̲ ̲f̲o̲r̲ ̲t̲h̲e̲ ̲C̲R̲8̲0̲D̲ ̲F̲l̲a̲t̲ ̲C̲a̲b̲l̲e̲ ̲B̲u̲s̲
2.2.3.3.1 M̲e̲c̲h̲a̲n̲i̲c̲a̲l̲ ̲B̲u̲s̲ ̲L̲a̲y̲o̲u̲t̲
The Cr 80D FLAT CABLE BUS utilizing differential transmitter/receiver
is a bidirectional parallel bus capable of interfacing
processor units and I/O crates by two twisted pair
flat cables.
The maximum transfer rate for the bus is as high as
4 Mega Word in the standard configuration, with a bus
length of up to 10 m.
The bus is connected to the CR80D system on the rear
of the crate by means of standard flat cable connector,
see figure 2.2.3.3.1.-1.
The pin configurations for the connectors are given
in table 2.2.3.3.1.-2 and -3.
Figure 2.2.3.3.1-1
Figure 2.2.3.3.1.-2
Figure 2.2.3.3.1.-3
2.2.3.3.2 F̲u̲n̲c̲t̲i̲o̲n̲a̲l̲ ̲D̲e̲s̲c̲r̲i̲p̲t̲i̲o̲n̲ ̲o̲f̲ ̲S̲i̲g̲n̲a̲l̲s̲
The following is a functional description of the signals
in the CR80D Flat Cable Bus.
I̲n̲f̲o̲r̲m̲a̲t̲i̲o̲n̲ ̲l̲i̲n̲e̲s̲:̲ ̲I̲N̲F̲O̲ ̲-̲ ̲I̲N̲F̲2̲3̲ ̲
These twentyfour lines carry the information transferred
on the bus.
In the set up phase the content is the address set
up and control information specifying the transfer
for the addressed unit. In the data phase sixteen
bits are used for data INFO - INF15 (INFO LSB) while
the remaining bits are available for special purposes
to be determined by communicating units. In the termination
phase the lines contain the word count and status from
the transmitting unit used for verification of correct
transfer. The content is determined by the communicating
units.
The INF signals are transmitted to the bus on the falling
edge of the signal Word Timing (WT) and be stable at
least two times the low period of WT (ref. figure 2.2.3.3.2-1.
P̲a̲r̲i̲t̲y̲ ̲L̲i̲n̲e̲s̲:̲ ̲ ̲P̲O̲-̲P̲2̲
The parity lines contain the odd parity for the bytes
presented on the information lines. PO corresponds
to INFO-7, P1 to INF8-15 and P2 to INF16-23. The timing
of the signals is as for the information lines.
W̲o̲r̲d̲ ̲T̲i̲m̲i̲n̲g̲:̲ ̲W̲T̲
The rising edge of WT indicates for the receiving units
that the content of the information lines is valid.
Timing diagram figure 2.2.3.3.2-1 shows the relationship
between the information lines and WT.
B̲u̲s̲ ̲O̲c̲c̲u̲p̲i̲e̲d̲:̲ ̲B̲O̲
BO is generated by the bus controlling unit as indication
for that the bus authority must not change and as qualifier
for the information lines and the master unit generated
transfer control lines. Timing diagram fig. 2.2.3.3.2-2
shows the function of the signal.
Figure 2.2.3.3.2-1
Timing Diagram for Information lines.
Figure 2.2.3.3.2-2
BO Timing Diagram.
S̲e̲l̲e̲c̲t̲i̲o̲n̲ ̲A̲c̲c̲e̲p̲t̲e̲d̲:̲ ̲ ̲S̲A̲
SA is response signal from the addressed unit during
link set up. The signal is held low through the complete
transfer. The signal is also used as qualifier for
transfer control signals generated by the addressed
unit. Timing diagram figure 2.2.3.3.2-3 shows the
function of the signal.
If the master unit has not received SA within 4 us
after start of the link set up, the transfer is terminated
due to time out.
C̲o̲n̲t̲r̲o̲l̲ ̲O̲u̲t̲:̲ ̲ ̲C̲O̲
CO specifies that the content of the information lines
is the set up command when a link set up is performed.
When in block mode it specifies the termination word
too. The signal is generated by the master unit during
the link set up and in link termination it is generated
by the unit which has transmitted data to the bus.
I/O Control: I/O 0-3
These three signals are used for specifying transfer
direction (Read/Write) and address locations (I/O,
Word, Byte) when the bus is operated in single data
transfer mode (I/O Channel). The lines are controlled
from the master units and are only valid in clearing
link set up. The timing for the signals is as for
the INF lines figure 2.2.3.3.2-1.
C̲o̲n̲t̲r̲o̲l̲ ̲A̲c̲c̲e̲p̲t̲e̲d̲:̲ ̲ ̲C̲A̲
CA is generated by the addressed unit in the link set
up phase and indicate that the command is accepted
and the unit is prepared to execute it.
CA presents simultaneously with TA indicates that the
receiving module has detected an error either illegal
command or parity error. If an overrun occurs in the
data receiving unit this situation is signalled by
issuing CA. Timing diagram figure 2.2.3.3.2-5 illustrates
the operation of CA.
T̲r̲a̲n̲s̲f̲e̲r̲ ̲A̲c̲c̲e̲p̲t̲e̲d̲:̲ ̲ ̲T̲A̲
TA is generated by the unit which receives the information
words as accept of the complete transfer. If a transmission
error occurs the signal is presented together with
CA if the information source is the master unit. If
the master unit receives information it will generate
CO together with TA to indicate transfer error. Timing
diagram figure 2.2.3.3.2-6 specifies TA.
Figure 2.2.3.3.2-3
SA Timing Diagram
Figure 2.2.3.3.2-4
CO Timing Diagram
Figure 2.2.3.3.2-5
CA Timing Diagram
Figure 2.2.3.3.2-6
TA Timing Diagram
A̲r̲b̲i̲t̲r̲a̲t̲i̲o̲n̲ ̲C̲l̲o̲c̲k̲p̲u̲l̲s̲e̲:̲ ̲ ̲A̲R̲C̲P̲
This signal is generated by the unit which is bus master
and is used for synchronization of the connected units'
bus request transmission.
B̲u̲s̲ ̲R̲e̲q̲u̲e̲s̲t̲:̲ ̲ ̲B̲R̲Q̲
On the BRQ line the units which require the bus authority
transmit a pulse in a predetermined time slot and thereby
get the bus authority when the current information
transfer is terminated. When the other requesting
modules recognize a pulse in a time slot which does
not correspond to their address they will wait for
the next request period (link set up) and try again.
When a unit has got the bus authority it will send
its own address to the BRQ line during the link set
up and thereby define the priority of the time slots
on the BRQ line. If unit A has the bus authority unit
A+1 has the highest priority. If there is not any
request for the bus within a request cycle, a new cycle
with module No. is transmitted to the line.
Timing diagram figure 2.2.3.3.2-7 defines the signal
sequence.
B̲u̲s̲ ̲R̲e̲q̲u̲e̲s̲t̲ ̲S̲y̲n̲c̲h̲r̲o̲n̲i̲z̲a̲t̲i̲o̲n̲:̲ ̲S̲Y̲N̲C̲H̲
The SYNCH signal is generated by the bus controlling
module to indicate that its address is present on the
BRQ line. The length of the signal is determined by
the number of master units connected to the bus (switch
selectable on the interface board).
Timing diagram figure 2.2.3.3.2-7
B̲u̲s̲ ̲R̲e̲q̲u̲e̲s̲t̲ ̲R̲e̲s̲y̲n̲c̲h̲r̲o̲n̲i̲z̲a̲t̲i̲o̲n̲:̲ ̲ ̲R̲E̲S̲Y̲N̲C̲H̲
This signal is used for resynchronization of the bus
authority circuits in the master modules. The signal
is dasichained meaning that no conflict occurs when
resynchronization is performed because the first unit
in the chain will get the authority. The circuit is
shown below.
To avoid that the chain is broken, for example power
failure, the modules using this signal shall include
a switch so that RESYNCH IN is shortened to RESYNCH
OUT. Besides the power condition the switch is also
controllable from software. The switch function is
shown in fig. 2.2.3.3.2-8
Bus resynchronization is performed when the following
situation occurs: System initialization, certain module
failure, spurious noise on the lines.
S̲y̲s̲t̲e̲m̲ ̲I̲n̲i̲t̲i̲a̲l̲i̲z̲a̲t̲i̲o̲n̲
When the system is initialized there is no current
master module on the bus and, therefore, a possible
conflict situation could occur if two master modules
were powered up and requesting the bus at the same
time. To avoid that the master modules will after
a power up check the bus timing signals (ARCP & WT)
for a proper function for a period longer than the
worst case response time during a transfer (10 uS).
If no valid timing is recognized, the module will
pull down the RESYNCH OUT line and if the RESYNCH IN
line is high, wait 10 uS and take over the bus authority
for the bus by issuing the SYNCH pulse and transmit
its module number to the bus (BRQ) which means that
the bus is synchronized.
M̲o̲d̲u̲l̲e̲ ̲F̲a̲i̲l̲u̲r̲e̲ ̲
If the arbitration synchronization is lost due to failure
in a master module, the bus will be resynchronized.
The resynchronization is performed by the module/modules
which recognize the erronous signals on the bus by
pulling down the RESYNCH OUT line and check the RESYNCH
IN line as described under System Initialization.
S̲p̲u̲r̲i̲o̲u̲s̲ ̲N̲o̲i̲s̲e̲ ̲
If spurious noise occurs on the lines it could be possible
to destroy the arbitration function so that resynchronization
is necessary. The resynch is performed as described
under System Initialization.
Timing diagram figures 2.2.3.3.2-7 and -8 illustrate
the CR80D Flat Cable Bus authority control signals.
Fig. 2.2.3.3.2-7
Fig. 2.2.3.3.2-8
2.2.3.3.3 T̲i̲m̲i̲n̲g̲ ̲d̲i̲a̲g̲r̲a̲m̲s̲ ̲f̲o̲r̲ ̲d̲a̲t̲a̲t̲r̲a̲n̲s̲f̲e̲r̲ ̲o̲n̲ ̲C̲R̲8̲0̲D̲
f̲l̲a̲t̲c̲a̲b̲l̲e̲ ̲B̲u̲s̲
Figure 2.2.3.3.3-1
Figure 2.2.3.3.3-2
Figure 2.2.3.3.3-3
Figure 2.2.3.3.3-4
Figure 2.2.3.3.3-5
Figure 2.2.3.3.3-6
2.2.3.4 D̲i̲s̲k̲ ̲S̲y̲s̲t̲e̲m̲
This system contains three identical assemblies including
controller, disk drive and 80 MB Disk.
These three systems are used for ON-LINE and OFF-LINE
mass storage in the CAMPS system.
2.2.3.4.1 D̲i̲s̲c̲ ̲C̲o̲n̲t̲r̲o̲l̲l̲e̲r̲ ̲C̲o̲n̲s̲i̲d̲e̲r̲a̲t̲i̲o̲n̲s̲
CR80D provides automatic mirroring of data bases.
A disc volume is a set of data contained on one spindle
or one removable disc pack. A user may declare any
of the disc volumes as mirrored pairs at system generation
time. The system then maintains these pairs so they
always contain identical data. Thus protection is
achieved for a single drive failure. Each of the disc
controllers is dual ported and connected between two
processors.
The disc controller is buffered for a maximum length
record which provides several features important in
an on-line system. First, the disc controller is absolutely
immune to overruns. Second, data to be written on
two drives need to be transferred over the I/O channel
only once. The data may then be posted twice from
the controller's internal buffer. Thus the channel's
data transfer capacity is little impaired by mirrored
volumes.
Since overlapped seeks are allowed by the controller,
when data is to be read from a mirrored pair it can
be read from the drive which has its arm closest to
the data cylinder. It is interesting to note that
since the majority of transactions in an on-line system
is reads, mirrored volumes actually can increase performance.
Ref. figure 2.2.3.4.1-1.
Fig. 2.2.3.4.1-1
2.2.3.5 L̲T̲U̲ ̲S̲y̲s̲t̲e̲m̲
The LTU system is constructed by individual LTU-modules.
The modules are connected to the I/O-system, when
inserted in the I/O-crates.
For further details on the LTU, see Data sheet (sect.
2.2.3.6).
2.2.3.6 D̲a̲t̲a̲ ̲S̲h̲e̲e̲t̲ ̲(̲I̲/̲O̲-̲s̲y̲s̲t̲e̲m̲)̲ ̲
List of Datasheets:
The list of datasheets is as follows:
CR8081D/010XX/00 CIAA, CIAB
I/O CHANNEL - I/O CRATE INTERFACE, p. 1-2
CR8055D/010XX/00 MBT MAIN BUS TERMINATION , p. 1-1
CR8044D/0YYXX/00 DISK CTRL, p. 1-3
CR8084D/010--/00 DCA, DISK CONTROLLER ADAPTER, p. 1-2
CR8066D/YYYXX/00 LTU, LINE TERMINATION UNIT, p. 1-3
2.2.4 T̲e̲l̲e̲c̲o̲m̲m̲u̲n̲i̲c̲a̲t̲i̲o̲n̲s̲ ̲D̲a̲t̲a̲ ̲E̲x̲c̲h̲a̲n̲g̲e̲
2.2.4.1 T̲e̲l̲e̲c̲o̲m̲m̲u̲n̲i̲c̲a̲t̲i̲o̲n̲s̲ ̲D̲a̲t̲a̲ ̲E̲x̲c̲h̲a̲n̲g̲e̲
The TDX equipment is a front-end system used for interconnection
of user terminals and communication lines with the
Processor Units.
This front-end system handles the peculiarity of the
communication channels and various terminal devices.
In CAMPS the TDX is used for interconnecting the PU's
with:
- VDU's for user and supervisory positions.
- Medium speed page printers for user and supervisory
positions.
- Low speed TTY-lines.
The TDX-bus links together all the functional elements
of the TDX-system. The TDX bus is essentially a high
rate digital link. The bus interconnects the TDX HOST
I/F-modules of the PU's with the line termination units
(LTUX's) of the line termination equipment.
The LTUX's are basically interfacing the communication
lines with CCITT V24/28 interface circuits. Each LTUX-module
has capacity for handling 1,2 or 4 connected channels,
depending on the transmission speed and the characteristics
of the channels.
The LTUX's can be extended with adapters for different
transmission lines. In the CAMPS systems are used
adapters for optical link-transmission and secure wiring.
In section 2.2.4.2 below are described the modules
and assemblies of the TDX-system used to meet the requirements
for the CAMPS system.
The following section 2.2.4.3 gives a general overview
of the unique specifications of the TDX concept and
details on the modules of the concept.
2.2.4.2 T̲D̲X̲ ̲E̲q̲u̲i̲p̲m̲e̲n̲t̲ ̲S̲t̲r̲u̲c̲t̲u̲r̲e̲ ̲
This section gives a description of that part of the
TDX system which interconnects the TDX-buses with the
IDF of the site equipment. The IDF is the distribution
facility, where the CAMPS equipment is connected with
the various transmission lines of the installation.
The blocked diagram, fig. 2.2.4.2-1 shows the included
modules and the interconnections.
T̲h̲e̲ ̲B̲u̲s̲ ̲C̲o̲n̲n̲e̲c̲t̲o̲r̲ connects the TDX-buses and bus control
signals to the crate.
All the modules within the crate are connected to a
motherboard by a multiconnector. The motherboard is
a printed circuit board designed with the necessary
interconnection wiring.
T̲h̲e̲ ̲B̲T̲M̲ (Bus termination module) contains 2 switching
functions related to the modules, which are supported
by the BTM:
a1 Power switching.
The power switch selects one of the two regulated
power source inputs. If the one power source is
defect, the switch will perform an instantaneous
switch-over to the alternative power source.
a2 TDX Bus switching.
The bus switch facility of the BTM controls and
monitors which TDX bus is selected for connection
to the LTUX-modules supported by the BTM.
Control is either manual or automatic. Automatic control
is conducted by the bus control signals. These are
in the CAMPS system operated by the SSC-system (S̲ystem
S̲tatus and C̲ontrol).
On the front plate of the BTM module switches are provided
for disabling the automatic control and manually operating
the TDX bus selection.
The table in fig. 2.2.4.2-2 shows the mode of the bus
selection operation.
Fig. 2.2.4.2-1
TDX Bus Control.
Fig. 2.2.4.2-2
Lines of the Installtion.
The LTUX's are driven by the bus selected by the BTM.
Each LTUX can interface up to 4 V24/28 channels.
The transmission lines may require special adaption
as it is the case where optical lines are used.
The opto mux/demux converts the channels of the LTUX
into the driver/receiver signals which drive the opto
tranceivers.
The opto-tranceivers are located in the IDF-crate.
The power to the tranceivers is fed through the cable
from the Opto-m/d.
As it is seen in fig. 2.2.4.2-1 each LTUX-crate contains
max. 2 groups of channels as described above. The
rack is the same whether the connected lines are opto
lines or of other requirements. The differences are
the adapter used and the IDF equipment.
This concept assures a great flexibility for using
different types of transmission lines and for making
changes in the interconnection capacity.
In each crate a Power Supply module can be placed.
As shown in fig. 2.2.4.2-1 and 2.2.4.2-3 the opto-tranceivers
are placed in separate crates. These are crates designed
to be IDB-crates. The opto fiber cables of the installation
are drawn from the rear side of the crate through the
opening and are connected with opto-connectors on the
front of the opto tranceivers-modules.
When placed, e.g. as shown on figures 2.2.4.2-3, the
equipment connecting each line of the installation
is easily identified and thus the availability of the
system is improved.
The IDF-rack is suggested to be the location of the
equipment, where all external lines are terminated.
Fig. 2.2.4.2-3
2.2.4.3 F̲u̲n̲c̲t̲i̲o̲n̲a̲l̲ ̲o̲v̲e̲r̲v̲i̲e̲w̲ ̲o̲f̲ ̲t̲h̲e̲ ̲T̲D̲X̲ ̲c̲o̲n̲c̲e̲p̲t̲
2.2.4.3.1 I̲n̲t̲r̲o̲d̲u̲c̲t̲i̲o̲n̲ ̲t̲o̲ ̲t̲h̲e̲ ̲T̲D̲X̲ ̲S̲y̲s̲t̲e̲m̲
The TDX Bus (Telecommunication Data Exchange) is essentially
a high rate digital link utilizing standard HDLC like
format with high immunity to interference, incorporating
full EDC protocol (Error Detection and Correction developed
by CHRISTIAN ROVSING A/S for communication between
equipments in telecommunications, terminals process
monitoring and control and command/control systems
within buildings, ships or aircraft.
By means of two screened twisted pair of cables, it
transmits data at a clock rate of 1.8432 Mbit with
a maximum throughput of 1.638400 Mbit. An addressing
scheme allows up to 256 devices to share the TDX BUS.
This greatly reduces the number of separate circuits
required in many systems, so that many large and expensive
multicore cables can be replaced by a single pair of
cables.
The design has been especially aimed at ensuring very
high immunity to electrical interference and low generation
of interference itself. It can, therefore, safely
be used in electrically noisy locations where conventional
data transmision could be unreliable as well as where
it is essential to restrict radiated noise to a low
level.
The TDX BUS supports both simple, low cost applications
as well as very sophisticated, dynamically reconfigurable
in real-time applications. This has been accompoished
by implementing the design with standard LSI's and
micro computers.
Full packet protocol with error detection and correction
is implemented on the TDX bus for data integrity.
The maximum cable length is 1.2 km, and a TDX BUS can
consist of as many 1.2 km cables as wished, radiating
out from the central controller thereby covering the
area within a circle of 2.4 km diameter.
Fig. 2.2.4.3.1-1
TDX BUS.
2.2.4.3.1.1
T̲D̲X̲ ̲D̲e̲v̲i̲c̲e̲ ̲T̲y̲p̲e̲s̲
Three functionally different device types are utilized
with the TDX bus: CONTROLLER, HOST INTERFACES and
LTUX.
The CONTROLLER is central to the TDX bus and all data
passes through it from the unidirectional upper bus
to the lower bus.
The HOST INTERFACES of which up to 12 can be attached
to a TDX bus is capable of connecting a very large
number of logical channels (up to 4096) to the TDX
bus and is therefore most often used for interfacing
HOST computers to the bus.
The LTUX's (Line Termination Unit, TDX) of which up
to 242 can be attached connect a limited number of
logical channels to the bus (up to 16) and are used
with interfacing of terminals, communication lines,
process monitoring and control equipment etc. to the
TDX bus.
2.2.4.3.1.1.1
T̲D̲X̲ ̲C̲o̲n̲t̲r̲o̲l̲l̲e̲r̲
The time division multiplexed serial transfer TDX bus
is clocked and synchronized by the TDX controller.
The controller outputs a continuous bit stream of
1.8432 Mbit on the lower bus. This stream is divided
into 6400 timeslots of 288 bit per second.
Each time slot on the lower bus contains a standard
HDLC frame with control information (5 bytes), DATA
to be transferred (16 bytes), and CCITT-16 (2 bytes)
cyclic redundancy check (CRC). The HDLC frame starts
at begin of time slot and takes up maximally 236 bits
of the 288 bits in the time slot, the remaining bits
being all "ONES" and from bit No. 240 all "ZEROs".
The controller inserts as second byte in the HDLC frame
on the lower bus a device No. taken from a MUX table
(MUX-No.) that is scanned according to the speed level
assigned to each device on the TDX.
Fig. 2.2.4.3.1.1-1
All devices with their unique device No. on the TDX
BUS look at the MUX No. byte, and if it coincides with
its device No., this device has the use of the upper
bus, to transmit data, at the end of the frame on the
lower bus, provided that the lower bus CRC check shows
no errors, thereby ensuring that only one device will
transmit on the upper bus at any time.
The band width assigned to each device at initialization
time by the MUX table, is dynamically changeable in
real time, by request from any device to the controller.
A transmitted HDLC frame on the upper bus is received
by the controller and if the destination is not the
controller, the HDLC frame is opened up, MUX No. added
as second byte, and the frame is transmitted with a
one frame delay on the lower bus with a recomputed
CRC.
If the destination of an upper bus frame is the controller
(e.g. request for band width change) or if no frame
is transmitted by the polled device, the controller
can utilize the, at that time, free time slot on the
lower bus in a cycle sealing manner to output device
control information (e.g. acknowledge of band width
change request to the device etc.) or data frames on
the lower bus. If no data is awaiting transmission
a dummy frame (MUX-No.=FF) will be transmitted. This
will happen with a minimum bandwidth on 100 b/sec.,
as MUX-NO FF is inlaid in the MUX-table on the lowest
bandwidth.
Transmission is continuous on the lower bus, thereby
making it possible to use the highly stable clock of
1.8432 Mhz as master clock at the devices (1.8432 Mhz
corresponds to 9600 x 12, especially suitable for modems).
2.2.4.3.1.1.2
T̲D̲X̲ ̲H̲o̲s̲t̲ ̲I̲n̲t̲e̲r̲f̲a̲c̲e̲
The TDX HOST interface is a high band width device
type (up to 500K baud) is capable of interfacing all
or a group of LTUXs attached to the TDX bus to a Host
computer. It also handles call up and establishing
of logical channels for communication between LTUXs,
Host and LTUXs, as well as Host to Host communication.
The group of LTUXs, either communicating or having
connection control on some of their logical channels,
by a HOST I/F is said to belong to its domain. The
domains of HOST I/Fs can be overlapping.
FIGURE 2.2.4.3.1.1.2-1
2.2.4.3.1.1.3
L̲T̲U̲X̲
The LTUX device is the standard interface between Input/Output
applications (communication lines, terminals, process
monitoring/control etc.) and the TDX bus. The LTUX
device type is built around a microprocessor using
standard microprocessor interface LSIs for interfacing
to the TDX bus and the user applications. The sum of
bandwidth assigned to the channels through one LTUX
is dynamically changeable by request to the TDX controller
from any device.
2.2.4.3.2 T̲D̲X̲ ̲P̲r̲o̲t̲o̲c̲o̲l̲,̲ ̲O̲v̲e̲r̲v̲i̲e̲w̲
The software, firmware and hardware of the TDX-system
may be devided into the following levels:
L̲e̲v̲e̲l̲ ̲1̲:̲ This level is handled by the Front-Ends in
TDX-devices and by the TDX-controller. The Front-End
of a TDX-device is the interface between the TDX-packet
protocol routines and the TDX-bus.
The controller polls the TDX-devices in accordance
with its MUX-table. When a F.E. recognizes its number
in the MUX-field of a frame on the lower bus, and a
frame containing data is transferred from packet level
to front end, it starts a frame transmission on the
upper bus. If no frame is ready F.E. does nothing.
Concerning reception, F.E. looks at the lower bus for
its own device number in the CR-ID field.
When a number is matching the actual frame is transferred
to packet level.
Besides this LTUX II may use a broadcast-mode, which
includes check of device No. as origin identifier via
a HIT-table.
The third and last task of the frame protocol is to
detect bit errors. This is done through a C.R.C check,
and when an error occurs, frame is disregarded in the
receiving F.E. It is left to the TDX-packet level to
recover from the error.
L̲e̲v̲e̲l̲ ̲2̲:̲ The TDX-packet protocol serves communication
between two TDX-devices of any type. This can be HOST-I/F
to HOST I/F ,HOST-I/F to LTUX or LTUX to LTUX. Packets
may consist of a variable number of frames less than
for instance 8. The packets protocol makes use of byte
3 and 4 in the frame format, which contain communication
control, sequence number and byte count. A connection
between two TDX-devices is always made for transmission
in both directions. The TDX-packet protocol goes only
one step back, which means that only one packet is
transmitted between the reception of two acknowledges.
In multiframe packets frames are numbered sequentially
modulo 8. In this way missing frames are detected and
by a not-acknowledge response, and retransmission of
the erroneous packet is performed. If an error occurs
in the transmission of a single frame packet the missing
response will cause a retransmission.
L̲e̲v̲e̲l̲ ̲3̲:̲ This level serves the I/F between application
routines and the TDX-system. This includes setup and
deletion of TDX-channels, change in the assigned TDX-channel-bandwidth,
transfer of data buffers and actions upon unrecoverable
transmission errors.
L̲e̲v̲e̲l̲ ̲4̲:̲ Application level includes all user-defined
routines resident in LTUXs or in HOST-computers.
FIGURE 2.2.4.3.2-1
2.2.4.3.3 T̲D̲X̲ ̲B̲u̲s̲ ̲C̲l̲o̲c̲k̲ ̲E̲n̲c̲o̲d̲e̲r̲ ̲a̲n̲d̲ ̲D̲e̲c̲o̲d̲e̲r̲
Data and clock are communicated on the TDX BUS using
the self-clocking differential split phase code SPL-D.
SPL-D changes polarity at start of each bit cell, and
in the middle of bit cells to indicate a zero. This
allows data and clock to be transmitted via the same
set of wires. Phase ambiguity is solved by the decoder
when a "one" is input.
Therefore, on the lower bus where SPL-D is continuously
transmitted, phase ambiguity is automatically solved.
On the upper bus, where transmission is discontinous,
the ABORT byte (all ones) preceeding each frame solves
the phase ambiguity.
Transmitting clock together with data on the buses
have several advantages. The major one being that the
bus delay has no significance for the correct decoding
as clock and data are delayed equally. Also, no need
exists to synchronize a transmitter and receiver.
Also that the TDX controller clock is continouisly
transmitted on the lower bus makes this available to
all TDX devices. One application for example being
to use this clock for modems attached to the TDX Bus,
thereby eliminating the problem of modem clocks being
slightly out of phase, and the difference in transfer
speed is thereby slowly accumulating in data buffers
until overflow.
The following schematics show circuits and waveforms
of the SPL-D encoder and decoder.
FIGURE 2.2.4.3.3.-1
FIGURE 2.2.4.3.3-2
2.2.4.3.4 T̲D̲X̲ ̲B̲u̲s̲ ̲D̲a̲t̲a̲ ̲F̲o̲r̲m̲a̲t̲
The two formats for lower and upper TDX BUS are shown
in figures 2.2.4.3.4-1 and 2.2.4.3.4-2. They only differ
on two points, namely that lower bus includes MUX No.
M in its data field, and upper bus has an ABORT byte
(all ONE's) as preamble.
Both upper and lower bus frames are standard HDLC FRAMES
with bitstuffing in order to have a unique synchronization
byte (FLAG: 01111110). Bitstuffing is done between
the beginning FLAG and ending FLAG, each time five
ONE's are met in the data stream, a zero is inserted.
The zero is then removed at receiving end, thereby
restoring the original data.
The bit stuffing (depending on number of subsequent
ONE's in data stream) makes the length of frames variable
- on lower bus between 200 and 236 bits, and on upper
bus between 200 and 235 bits.
FIGURE 2.2.4.3.4-1
figure 2.2.4.3.4-2
2.2.4.3.4.1
L̲o̲w̲e̲r̲ ̲B̲u̲s̲ ̲F̲o̲r̲m̲a̲t̲
Following the flag each byte has the following function:
B̲y̲t̲e̲ ̲N̲o̲.̲ ̲1̲,̲ ̲M̲U̲X̲ ̲N̲o̲.̲ ̲M̲:̲
This byte is inserted by the TDX BUS Controller to
signal that the device with the number M is to transmit
on the upper bus at the end (actually at bit count
241) of the frame on the lower bus.
B̲y̲t̲e̲ ̲N̲o̲.̲ ̲2̲,̲ ̲D̲A̲T̲A̲ ̲T̲Y̲P̲E̲ ̲F̲I̲E̲L̲D̲ ̲&̲ ̲C̲O̲N̲T̲R̲O̲L̲/̲H̲O̲S̲T̲ ̲F̲I̲E̲L̲D̲S̲
The DATA TYPE (dddd) indicates the data stream number
(channel number) which the following DATA in the frame
belongs to.
Datatype 0 and 1 are reserved for channel set up and
system control purposes.
The HOST/CONTROL field (hhhh) is defined as
0000 destination of the frame is the controller
0001
. destination of the frame is the HOST I/F indi-
. cated (giving up to 12 HOST I/F exclusive of
the
000C controller).
000D broadcast mode, frame can only be received
by devices with Origin ID hit tables.
000E destination of frame is device (Type LTUX)
indicated in byte 3 "TDX DEVICE NO.", source
is a DEVICE.
000F destination of frame is device (type LTUX)
indicated in byte 3 "TDX DEVICE NO.", source
is a HOST I/F.
B̲y̲t̲e̲ ̲N̲o̲.̲ ̲3̲,̲ ̲T̲D̲X̲ ̲D̲E̲V̲I̲C̲E̲ ̲N̲O̲.̲:̲
For HOST/CONTROL field = 0000-000D this 8 bit No. (0-255)
indicates the device no. of the device where the frame
was originated (source). For HOST/CONTROL field = 000E-000F
this 8 bit no. indicates the device no. of the device
where the frame is destinated (destination). Device
No. FF indicates a dummy frame, where no device normally
is assigned.
B̲y̲t̲e̲ ̲N̲o̲.̲ ̲4̲,̲ ̲C̲O̲M̲M̲U̲N̲I̲C̲A̲T̲I̲O̲N̲ ̲B̲Y̲T̲E̲:
This byte is used for the TDX Packet protocol control.
B̲y̲t̲e̲ ̲N̲o̲.̲ ̲5̲,̲ ̲N̲O̲.̲ ̲O̲F̲ ̲D̲A̲T̲A̲ ̲B̲Y̲T̲E̲S̲ ̲I̲N̲ ̲F̲R̲A̲M̲E̲:
BITS 5-7: inserted by the originating device of the
frame to sequentially number frames, modulo 8 in a
communication with a specific receiving device, in
order that the receiving device can request retransmission
when a jump in SEQ. No. occurs. This is used for Error
Detection and Correction, example: A CRC error occurred
in frame with SEQ. No. n; this frame was, therefore,
thrown away by the receiving device. At correct receival
of frame with SEQ. No. n+1, the receiving device detects
an increase in SEQ. No. of 2, from previous correctly
received SEQ. No. n-1. The Packet level of the receiving
device accordingly requests retransmission.
B̲I̲T̲S̲ ̲0̲-̲4̲:
As the number of bytes in the DATA field transmitted
is fixed at 16 (128 bits), the five least significant
bits of this byte indicate the number of actual DATA
bytes in a possible partly filled data field (hexadecimal:
[[ - 1[.
B̲y̲t̲e̲ ̲N̲o̲.̲ ̲6̲ ̲t̲o̲ ̲B̲y̲t̲e̲ ̲N̲o̲.̲ ̲2̲1̲,̲ ̲D̲A̲T̲A̲:̲
This is the information field containing data to be
communicated from originating device (source) to receiving
device (destination).
B̲y̲t̲e̲ ̲N̲o̲.̲ ̲2̲2̲ ̲&̲ ̲N̲o̲.̲ ̲2̲3̲;̲ ̲C̲R̲C̲:̲
The Cyclic Redundancy Check (CCITT-16) is inserted
by the originating device and utilized by the receiving
device to verify the correctness of the total received
frame.
T̲r̲a̲i̲l̲i̲n̲g̲ ̲"̲O̲N̲E̲'̲S̲"̲ ̲a̲f̲t̲e̲r̲ ̲F̲r̲a̲m̲e̲
Following the frame, the controller inserts "1"s until
bitcount of time slot reaches 241 and thereafter "0"
until end of time slot. The change from 1 to 0 is
used for starting transmission on the upper bus by
the selected TDX device (MUX No.) at an exact point
in the time slot.
2.2.4.3.4.2
U̲p̲p̲e̲r̲ ̲B̲u̲s̲ ̲F̲o̲r̲m̲a̲t̲
The format on the upper bus is identical to the format
on the lower bus, except for the following:
a) An abort byte (all ONE'S) is transmitted as a preamble
to the HDLC frame in order to absorb common mode
swing of the bus at switch-on of the TDX device
transmitter, and to synchronize the clock and data
encoder at the controller receiving end.
b) No MUX No. is included in the upper bus format.
This shift the format one byte in proportion to
the lower bus:
Upper byte No. identical to lower bus byte
No.:
Byte No. 1 Byte No. 2
2 3
3 4
4 5
5-20 6-21
21,22 22,23
c) No trailing ONE'S after flag, transmission stops
and TDX device transmitter stops transmitting immediately
after last flag.
2.2.4.3.4.3
T̲D̲X̲ ̲B̲u̲s̲ ̲T̲i̲m̲i̲n̲g̲
Figure 2.2.4.3.4.3-1 shows the timing diagram for the
TDX BUS.
The criteria that decides maximum length of bus, with
regard to timing, is that two devices should not have
their transmitted frames on the upper bus at the same
time. The TDX device transmission starts at bitcount
241 when the transition from 1 to 0 is detected on
the lower bus with a delay T, dependent on cable length
between the TDX device and the Controller. The TDX
device then transmits a maximum of 235 bits of which
the trailing edge reaches the Controller with a cable
delay of T. Because of the distance between TDX devices,
transmitting 288 bitclocks in a timeslot, we therefore
have:
2̲8̲8̲-̲2̲3̲5̲ 5̲3̲
Max allowable delay: T = = bitclocks
max 2 2
The standard bitclock frequency is 1.8432 Mhz, and
the delay per meter cable being less than 5 nanosecs,
we therefore have maximum distance between Device and
Controller, D…0f…max…0e…:
5̲3̲ 1̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲
x 6
T̲m̲a̲x̲ ̲(̲s̲e̲c̲)̲ 2̲ ̲ ̲ ̲ ̲1̲.̲8̲4̲3̲2̲ ̲x̲ ̲1̲0̲ ̲ 2̲8̲7̲5̲ ̲m̲e̲t̲e̲r̲
D = =
max -9 -9
5x10 5x10
figure 2.2.4.3.4.3-1
2.2.4.3.5 T̲D̲X̲ ̲B̲u̲s̲ ̲R̲e̲d̲u̲n̲d̲a̲n̲c̲y̲ ̲C̲o̲n̲s̲i̲d̲e̲r̲a̲t̲i̲o̲n̲s̲
Capability for redundancy and automatic switchover
in case of equipment failure has been a major consideration
in the design of the TDX BUS.
2.2.4.3.5.1
T̲D̲X̲ ̲C̲o̲n̲t̲r̲o̲l̲l̲e̲r̲ ̲R̲e̲d̲u̲n̲d̲a̲n̲c̲y̲
Figure 2.2.4.3.5.1-1 shows the block diagram of the
configuration having both controllers and buses dualized.
1. Loss of clock on output to TDX bus from the active
TDX controller makes Watchdog immediately switch
TDX Controllers in order not to loose clock to
TDX devices.
2. CRC errors on input of TDX Controller and controller
on-line diagnostic status are handed to the Watchdog.
Watchdog then decides if switchover should occur,
based on seriousness and number of errors.
Figure 2.2.4.3.5.1-1
2.2.5 D̲i̲s̲t̲r̲i̲b̲u̲t̲i̲o̲n̲
Various types of terminal equipment and external circuits
shall be connected to the CAMPS Equipment.
The individual channels shall be transmitted using
transmission equipment in accordance with the location
and requirements determined by the actual channel application.
A number of modular elements will be used for construction
of the distribution equipment in order to assure:
a1 a clean, structured disposition within the equipment
racks.
a2 that the availability of each channel is maximum.
a3 that changes in connection capacity can be easily
handled.
The following distribution concepts are considered:
b1 channels for connecting VDU's and medium speed
printers to the CAMPS equipment by optical fibre
cables.
b2 Channels for connecting low speed terminals (TTYs)
to the CAMPS equipment by secure electrical wiring.
b3 Channels for connecting local external circuits
by secure electrical wiring (without inserting
encrypting devices).
b4 Channels for connecting remote VDU's and Medium
Speed printers move channels are multiplexed, encrypted
and transmitted by modems to the remote location.
b5 Channels for connecting remote external circuits.
The channel is encrypted and transmitted by modems
to the remote location.
The following subsections will describe the solution
for each distribution concept.
2.2.6 S̲i̲t̲e̲ ̲E̲q̲u̲i̲p̲m̲e̲n̲t̲ ̲C̲o̲m̲p̲l̲e̲m̲e̲n̲t̲
The basic equipment complement is identical for all
CAMPS sites.
The basic equipment complement, other than the operating
and maintenance positions or user terminals can be
divided into:
a) The Processor Equipment Racks
b) The Line Equipment Racks
Figure 2.2.6-1 and 2.2.6-2 show Rack-Layouts for the
two rack assemblies.
The processor Equipment (PE) Racks are built up identical
at all sites. The rack-up contains the dual Processor
Units, the dual I/O-system and the tripte disc storage
units.
The I/O-system contains the Line termination for the
medium and high speed interfaces to external circuits.
The volume of the units that make up the PE racks is
shown in figure 2.2.6.-1.
The line Equipment Racks are tailored to each site
and contain equipment in 2 functional levels:
a. The line termination units, LTUX-s, which have
all the same standard I/F on the line-side.
b. The signal conditioning, monitoring and patching
equipment.
Within this equipment each line is adapted to the actual
transmission media:
- opto fiber cables
- secure cables
- single channel or time division multiplexed channels
The CAMPS equipment racks are fed from supply mains
which are connected to the mains filter box.
The CAMPS equipment is powered from three single phases.
The power from the phases is distributed such that
redundant units are connected to different phases.
Failure of a single phase will not cause interruption
in system operation.
Figure 2.2.6-1
Figure 2.2.6.-2
