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⟦d60448780⟧ Wang Wps File
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Names: »~ORPHAN68.08«
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└─⟦003a8b650⟧ Bits:30006009 8" Wang WCS floppy, CR 0044A
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WangText
…00……00……00……00……00…D…0a……00……00…D…0b…B…0b…B…02…B…07…A…0b…A…0c…A…0d…A…0e…A…01…A A…05…@…0a…@…0d…@
4…08…4…0c…4 3…09…3…0a…3…0c…3…0d…3…0e…3…01…3…02…3
3 2…0b…2…0d…2…0e…2
1…09…1…0a…1…0b…1…0f…1…00…1 1…07…0…0d…0
0 0…05…0…06…0…07…/…08…/…0e…/…01…/…02….…09….…00…. -…86…1 …02… …02… …02…
…02…CPS/SDS/001
…02…SRA/810430…02……02…
CAMPS SYSTEM DESIGN SPECIFICATION
…02…ISSUE 1…02…CAMPS
T̲A̲B̲L̲E̲ ̲O̲F̲ ̲C̲O̲N̲T̲E̲N̲T̲S̲
5 SUBSYSTEM SPECIFICATION ......................
3
5.1 CR80D SYSTEM DESIGN .....................
3
5.1.1 Scope ................................
3
5.1.2 CR80D Crate Assy. ....................
3
5.1.3 CR80D Buses ..........................
8
5.1.3.1 CR80D Main Buses (DMB) ...........
8
5.1.3..1 Functional Description of the
CR80D Main Bus (DMB) .........
11
5.1.3.1.2 Electrical Description of the
CR80D Main Bus ...............
22
5.1.3.2 The CR80D Data Channel (DDC)......
26
5.1.3.2.1 Funcional Description of the
DDC ..........................
26
5.1.4 Processor Sub-System (PRS) ...........
33
5.1.4.1 Design & Construction ............
35
5.1.4.1.1 Functional Description of the
CR80D Contol Bus (DCB) ......
35
5.1.4.1.2 Electrical Description of the
DCB ..........................
42
5.1.4.1.3 Central Processing Unit and
CACHE Memory (CPU/CACHE) .....
43
5.1.4.1.3.1 The CPU .................
43
5.1.4.1.3.2 The CACHE Memory CTRL ....
47
5.1.4.1.3.3 Mechanical & Electrical
Specifications ...........
53
5.1.4.1.4 The MAP and Map Interface Adapter
(MIA) ........................
54 5.1.4.1.4.1
The
MAP
Module
...........
56
5.1.4.1.4.2 The MIA Module ...........
75
5.1.4.1.4.3 Mechanical & Electrical
Specifications ...........
89
5.1.4.1.5 Intentionally Left Blank .....
93
.1.4.1.6 The RAM Module ...............
94
5.1.4.1.6.1 Mechanical & Electrical
Specifications ...........
97
5.1.4.1.7 The STI/TIA Modules ..........
98
5.1.4.1.7.1 The TIA ..................
100
5.1.4.1.7.2 The STI ..................
104
5.1.4.1.7.3 Mechanial & Electrical
Specifications ...........
109
5.1.4.1.8 The CCA Module ...............
110
5.1.4.1.9 The Power Supply .............
110
5.1.4.2 Documentation ....................
110
5.1.4.3 Environment ..................... 110
5.1.5 I/O Sub-System .......................
111
5.1.5.1 Design & Construction ............
113
5.1.5.1.1 The CIA Module ...............
114
5.1.5.1.1.1 Mechanical & Electrical
Specifictions ........... 121
5.1.5.1.2 The Disk CTRL & DCA ..........
122
5.1.5.1.2.1 The Disk CTRL ............
122
5.1.5.1.2.2 The DCA ..................
135
5.1.5.1.2.3 Mechanical & Electrical
Specification ........... 138
5.1.5.1.3 The LTU & Adapter ............
141
5.1.5.1.3.1 The LTU ..................
141
5.1.5.1.3.2 The V24/V28(L) Adapter ...
149
5.1.5.1.3.3 Mechanical & Electrical
Specification ........... 149
5.1.5.1.4 The Floppy Disk Controller &
Adapter ......................
152
5.1.5.1.4.1 Mechanical & Electrical
Specification ............
152
5.1.5.1.5 The CCA ......................
152
5.1.5.1.6 The Power Supply ............. 153
5.1.5.2 Documentation ....................
153
5.1.5.3 Environment ......................
153…86…1 …02… …02… …02… …02…
5̲ ̲ ̲S̲Y̲S̲T̲E̲M̲ ̲B̲R̲E̲A̲K̲-̲D̲O̲W̲N̲
This chapter presents a more detailed specification
of the major H/W and S/W packages which have been identified
in chapter 4.
5.1 C̲R̲8̲0̲D̲ ̲S̲Y̲S̲T̲E̲M̲ ̲D̲E̲S̲I̲G̲N̲
5.1.1 S̲c̲o̲p̲e̲
The scope of this document is:
- to supply documentation and functional specification
of the present CR80D H/W configuration
- to define a baseline document for the CR80D H/W configuration
This section will provide a general dscription of the
two main CR80D assemblies
- the Processor Unit Assembly (PU) (sec. 5.1.4)
- the Channel Unit Assembly (CU) (sec. 5.1.5)
Furthermore, other subsystems interfaced from the PU
and the CU, if any, are referenced.
To provide a mre comprehensive understanding of the
CR80D system each of the assemblies are broken down
into basic functional elements (i.e. crate, buses and
modules) each given a detailed functions/mechanical
description.
5.1.2 C̲R̲8̲0̲D̲ ̲C̲r̲a̲t̲e̲ ̲A̲s̲s̲e̲m̲b̲l̲y̲
The CR8D modules/elements are mechanical self contained
units housed in a standard 19" mechanical frame, the
CR80D crate assembly shown on fig. 5.1.2-1.
The crate assembly consists of a front crate and a
rear crate (interface adapter crate) placed back to
back. On the back panels of the two crates are bus
motherboards (Printed ciruit boards) for module interconnections
and also edge connectors for front-rear crate interconnections.
As an example the front crate back panel is shown on
fig. 5.1.2-2.
The rear crate has no main buses, but it has a control
and power bus in theupper row, motherboard or individual
connectors in the middle row and individual connectors
in the lower row. Cables external to the crate assembly
(subsystem interface cables) are connected to interface
adapter modules in the rear crate. Adapter odules
are connected to modules in the front crate by flat
cables as shown in fig. 5.1.2-3.
Figure 5.1.2-1…86…1 …02… …02… …02… …02…
Figure 5.1.2-2…86…1 …02… …02… …02… …02…
Figure 5.1.2-3…86…1 …02… …02… …02… …02…
5.1.3 C̲R̲8̲0̲D̲ ̲B̲u̲s̲e̲s̲
5.1.3.1 C̲R̲8̲0̲D̲ ̲M̲a̲i̲n̲ ̲B̲u̲s̲e̲s̲ ̲(̲D̲M̲B̲)̲
The CR80D Main Buses are:
- The Processor Bus (PB) and Channel Bus (CB) in
the Processsor Unit (PU).
- The I/O Bus A and IO Bus B in the Channel Unit
(CU).
Each of the 4 DMB appears physically as a printed circuit
(PCB), called a motherboard, equipped with module connectors.
The motherboard (fig. 5.1.3.1-1) provides a parallel
bus structure with 50 lines used for arallel addressing
and data transfer along with associated handshake signal
lines (ref. fig. 5.1.3.1-2).
Fig. 5.1.3.1-3 shows how CR80D modules Plugs onto the
DMB.
Figure 5.1.3.1-1…01…C̲R̲8̲0̲D̲ ̲M̲o̲t̲h̲e̲r̲ ̲B̲o̲a̲r̲d̲
The DMB in a PU and a CU is terminated in both ends
by termination boards to form a set of transmission
lines suitable as the communication path between the
modules.
Within a P each DMB is terminated in each end by a
Main Bus Termination module (MBT). This module contains,
apart from the passive terminating circuitry, also
the inverter circuitry supporting the PU I/O interrupt
system (sec. 5.1.3.1.1b).
Within a CU eachDMB is terminated in one end by a MBT,
and in the other end by a CIA (sec. 5.1.5.1.1), which
apart from the CIA circuitry described contains the
passive terminating circuitry and the inverter circuitry
supporting the CU I/O interrupt system.
Figure 5.1.3.1-2…86…1 …02… …02… …02… …02…
Figure 5.1.3.1-3…01…D̲ ̲M̲o̲d̲u̲l̲e̲s̲ ̲o̲n̲ ̲t̲h̲e̲ ̲D̲M̲B̲s̲
5.1.3.1.1 F̲u̲n̲c̲t̲i̲o̲n̲a̲l̲ ̲D̲e̲s̲c̲r̲i̲p̲t̲i̲o̲n̲ ̲o̲f̲ ̲t̲h̲e̲ ̲C̲R̲8̲0̲D̲ ̲M̲a̲i̲n̲ ̲B̲u̲s̲ ̲(̲D̲M̲B̲)̲
In a Processor Unit (PU) two transfer buses are availale
for module intercommunication; the Processor Bus (PB)
and the Channel Bus (CB). The two buses are from a
functional point of view different:
- The PB is used by CPU modules for data and instruction
communication with memory modules and for setup,
status and control communication with the MAP module.
- The CB is not available to the CPUs but is used
by the STI(Host I/F) and MAP modules for information
exhange with the connected subsystems (I/O subsystem,
TDX subsystem). The cache memor section of a CPU
though, has m̲o̲n̲i̲t̲o̲r̲i̲n̲g̲ ̲a̲c̲c̲e̲s̲s̲ to the CB (sec. 5.1.4.1.3).
Concerning the mechanical, electrical and timing characteristics
the two buses are identical. The buses and their connection
in the system are illustrated in fig. 5.1.3.11-1.
…01…Figure 5.1.3.1.1-1
C̲o̲n̲n̲e̲c̲t̲i̲o̲n̲,̲ ̲M̲a̲i̲n̲b̲u̲s̲e̲s̲ ̲i̲n̲ ̲a̲ ̲P̲U̲
In the Channel unit two transfer buses are available
for information exchange between the I/O modules and
the Ps. These two buses are functionally equal and
are used as back up for each other in redundant systems.
The buses and their connection in the system are shown
in figure 5.1.3.1.1-2 below.
Figure 5.1.3.1.1-2…01…C̲o̲n̲n̲e̲c̲t̲i̲o̲n̲,̲ ̲M̲a̲i̲n̲B̲u̲s̲e̲s̲ ̲i̲n̲ ̲a̲ ̲C̲U̲…86…1 …02… …02… …02… …02…
In the following a detailed description of the mechanical
and electrical characteristics of the buses are given.
The interface specifications for the four buses are
the same (The R80D Main Bus specifications) except
for supply voltages; dualized supply for a CU module
and single supply for a PU module.
a) M̲a̲s̲t̲e̲r̲ ̲T̲i̲m̲i̲n̲g̲
Two signals [1(A35) and [2(A38) (both generated
on the MAP) are available for I/O interrupt timing
an for internal timing in the modules connected
to the DMB. The timing signals are shown below
in fig. 5.1.3.1-3, [1 being a 1 MHz clock and [2
a 8 MHz clock. [1 is derived from [2.
Figure 5.1.3.1.1-3…01…T̲i̲m̲i̲n̲g̲ ̲S̲i̲g̲n̲a̲l̲s̲
b) I̲/̲O̲ ̲I̲n̲t̲e̲r̲r̲u̲p̲t̲ ̲i̲g̲n̲a̲l̲s̲
The CR80D System is based on serial transmission
of the interrupt code from the interrupting I/O
module using the lines INA (A32) and INR (A33).
The interrupt code consists of 8 bits, of which
2 are priority bits and the remaining 6 bis are
the I/O module number. The 8 bits are transmitted
within one [1 (1MHZ) cycle each bit synchronized
to the [2 (8 MHZ) clock. The interrupt code is
transmitted on the INR line (fig 5.1.3.1-4).
INR is an open collector line. Thus all the I/Omodules
can transmit on the same line, which means that
if one module is transmitting an "L" and another
an "H", the line will contain the "L".
INA is an open collector line too. It is driven
from the Main Bus termination boards (MBT or CIA),
one in each end of the Bus. The contents of INA
is INR inverted. Each of the iterrupting I/O modules
compares each of the eight bits returning from
INA with the bit it is transmitting to INR. If
the compare does not match, which means that a
module with a higher priority interrupt code is
transmitting at the same time, the mdule disables
the transferring of its code to INR until the next
1 MHZ period.
In this way the contents of INR will be unique
and correspond to the highest priority interrupt
transmitted during that period. The module which
detects this situatio has got its interrupt acknowledge
and will stop the interrupt sending.
If two modules interrupting at the same time have
the same priority, it is the module with the highest
address that overrides the other.
Figure 51.3.1.1-4 …01…The I/O Interrupt System
