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Derivation
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A…08…A…09…A…00…A
A @…08…@…09…@…00…@…07…?…0e…? >…09…>…0b…>…0c…>…05…=…0d…=…00…=…01…=…07…<…0c…<…0e…<…05…;…0a……86…1
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…86…1
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5.1.5 T̲h̲e̲
̲I̲/̲O̲
̲S̲u̲b̲s̲y̲s̲t̲e̲m̲
The
I/O
subsystem
is
composed
of
one
Channel
Unit
(CU)
with
a
dualized
(redundant)
I/O
bus
configuration.
The
system
is
equipped
with
three
types
of
I/O
ontrollers
(interfaces
between
the
I/O
buses
and
the
I/O
devices):
- Disk
controllers,
which
via
the
Disk
Controller
adapter
interfaces
the
disk
drivers
to
the
I/O
sub-system.
- Floppy
disk
controller,
which
via
an
adapter
is
connected
to
a
dua
floppy
disk
drive.
- Line
Termination
Units
(LTU's),
which
via
the
V24/V28
adapters
are
used
for
driving
the
heavy
communication
protocols
towards
the
TARE-,
CCIS-,
and
SCARS
system.
The
I/O
subsystem
interfaces
to
(fig.
5.1.5-1):
- the
Procssor
Sub-System
through
the
dualized
CIA
(sec.
5.1.5.1.1)
-
Data
Channel
(sec.
5.1.4.1.5)
-
MIA
(sec.
5.1.4.1.4.2)
link.
- the
Watchdog
Processor
through
the
serial
configuration
control
bus
and
the
CCA
(sec.
5.1.5.1.4).
- the
TARE-,
CCIS-,
andSCARS-circuits
via
the
V24/V28(L)
adapters
(sec.
5.1.5.1.3.2).
Fig. 5.1.5-1
THE I/O SYSTEM INTERFACES
5.1.5.1 D̲e̲s̲i̲g̲n̲ ̲&̲ ̲C̲o̲n̲s̲t̲r̲u̲c̲t̲i̲o̲n̲
The design implements an I/O subsystem that has low
overhead, fast transfer rates, no overruns, and no
interrupts to the system until a logical entiy of work
is completed (i.e., no character by character interrupts
from the terminals). The design produced an I/O system
that is extremely simple.
The heart of the CR80D I/O subsystem is the Data Channel.
All bulk I/O is done on a direct memor access (DMA)
basis. With the block size determined by the individual
application. All I/O controllers are buffered to some
degree so that all transfers over the I/O channel are
at memory speed (2M words/second) and never wait for
mechanical motin since the transfers always come from
a buffer in the I/O controller, rather than from the
actual I/O device.
For setup, control and status between PU and I/O controllers,
programmed I/O (direct from CPUs) can be used concurrently
with the Data hannel DMA transfers.
Transfer on the Data Channel does not put any load
on the program execution, because the transfer concept
is implemented in hardware.
The memory system priority on the PU Channel bus always
permits I/O accesses (in an on-lne, transaction oriented
environment, it is rare that a system is not I/O bound).
In the following sections a detailed explanation of
the basic modules within a CU is given:
- CR80D Channel Interface Adapter (CIA)
- CR80D Disk Controller
- CR0D Disk Controller Adapter (DCA)
- CR80D Line Termination Unit (LTU)
- CR80D V24/V28 (L) Adapter
- CR80D Power Supply (PSU)
- CR80D Floppy disk Controller
- CR80D Floppy disk Controller Adapter (SFA)
5.1.5.1.1 T̲h̲e̲ ̲C̲I̲A̲ ̲M̲o̲d̲u̲l̲e̲
The Channel Interface Adapter is the interface between
the Data Channel and the dual bus structure of the
Channel Unit (fig. 5.1.5.1.1-1). Two versions f the
CIA are available, one for interfacing the Data Bus
A (CIA-A) and one for interfacing the Data Bus B (CIA-B).
The two versions are functionally identical, but the
printed circuit board either has an edge connector
towards the A-Bus or the B-us (figs. 5.1.5.1.1-2 and
-3)
Fig. 5.1.5.1.1-1…01…D̲A̲T̲A̲ ̲C̲H̲A̲N̲N̲E̲L̲ ̲I̲N̲T̲E̲R̲F̲A̲C̲E̲S̲
Fig. 5.1.1.5.1.1-2…01…T̲h̲e̲ ̲C̲I̲A̲-̲A̲
Fig. 5.1.5.1.1-3…01…T̲h̲e̲ ̲C̲I̲A̲-̲B̲
The main function of the CIA is to transfer data between
the I/O bus and the Data Channel. The CIA is master
to the I/O bus but slave to the Data Channel. This
means that a tranfer is initiated from the Data Channel,
which then awaits for the CIA to complete the transfer.
Interrupts from the Channel Unit modules are stored
in the CIA to be fetched by the Data Channel.
The CIA also undertakes several support functions owards
the I/O Bus:
a) Clock generation
b) Power supervision
c) Power up reset
d) Bus termination
The functional blocks of the CIA are shown in fig.
5.1.5.1.1-4.
a) D̲a̲t̲a̲ ̲T̲r̲a̲n̲s̲f̲e̲r̲
The information path of the Data Channel is shared
by addesses, data and error messages. Thus a transfer
is divided into three phases. This transfer description
is mainly a repetition of parts of sec. 5.1.4.1.4.2.…86…1
…02… …02… …02… …02…
Fig. 5.1.5.1.1-4
The CIA Module
1) A̲d̲d̲r̲e̲s̲s̲ ̲P̲h̲a̲s̲e̲
Three different types of addressing modes are
defined for the Data Channel:
- single
- set up
- reduced
A single type address is three bytes whch are
received on the Data Channel information path.
The address is stored temporarily in the address
register and the four most significant bits
are compared to the CIA-number on a switch
array. If they match, the address is forwarded
to the I/ Bus and the transfer can proceed.
If the control bits on the information path
indicate that the address is a "set-up", then
it is stored in the Reduced Address Register
(RAR) instead of being transmitted on the Data
Bus. The address is now usd as a base to the
following reduced address transfers.
A reduced address is only one byte and it contains
only the CIA-number. When a CIA recognizes
its number in a reduced address, it transmits
the RAR on the I/O Bus.
The RAR is incremened after each memory transfer
to facilitate block transfers of up to 64 words.
Further reduced address transfers must be preceded
by a new set up.
All received addresses are parity checked.
2) D̲a̲t̲a̲ ̲P̲h̲a̲s̲e̲
Besides giving the address type, he control
bits of the address phase also specifies whether
it is a read or write operation and whether
it is a memory or I/O transfer. This information
is transmitted to the I/O Bus simultaneously
with the address. The data phase is a transfer
o two bytes, lower byte first and then upper
byte.
a) R̲e̲a̲d̲ ̲o̲p̲e̲r̲a̲t̲i̲o̲n̲
When the address is stable on the Data
Bus, the CR80D handshaking procedure
(sec. 5.1.3.1) is initiated and data
is fetched. The parity is checked
and he data is transmitted via the
transmit register to the Data Channel
with a regenerated parity.
b) W̲r̲i̲t̲e̲ ̲o̲p̲e̲r̲a̲t̲i̲o̲n̲
The data of a write operation arrives
from the Data Channel just after the
address and is loaded in the data register.
A arity check is performed and the
data is then forwarded to the I/O Bus
if parity was OK.
3) T̲e̲r̲m̲i̲n̲a̲t̲i̲o̲n̲ ̲P̲h̲a̲s̲e̲
The main purpose of the termination phase is
to make it possible to determine whether a
transfer succeeded or not.
Two types oferrors are considered:
a) No response detected by time out
b) Bit error detected by parity
The termination phase is characterized by an
acknowledge on the DA-line of the Data Channel.
Normally the CIA issues the DA-signal when
the ransfer is completed, but if the maximum
response time is exceeded, it is issued by
the Data Channel. The DA-signal resets the
connected CIA to expect a new address phase.
This time out condition typically arises when
the addressed module is not resent.
If the CIA detects a parity error in the data
phase during a write-operation or on the I/O
Bus during a read-operation, an error message
is sent on the information path simultaneously
with the DA-signal. Parity error in the address
phae does not result in an error message, because
either the CIA-number or control information
might be invalid.
b) I̲n̲t̲e̲r̲r̲u̲p̲t̲ ̲H̲a̲n̲d̲l̲i̲n̲g̲
Interrupts from I/O-modules in the Channel Unit
are received according to the CR80D Main Bus specifications
(sec. 5.1.3.1). This implies that the interruting
module address is received in serial form. If
two modules interrupt simultaneously, the one with
the highest priority and address is chosen.
When an interrupt address has been shifted into
the interrupt register, further interrupts are
disbled until the address is fetched by the Data
Channel.
The fetch command, interrupt request (IRQ), is
received from the Data Channel in serial form.
It contains a four bit address which is compared
to the CIA-number from the switch array. If tey
equal each other, the content of the interrupt
register is transmitted in serial form to the Data
Channel through the interrupt transmit register.
If the interrupt register is empty or if a parity
error has been detected in the fetch command, te
interrupt address is replaced by a status message.
c) I̲/̲O̲ ̲B̲u̲s̲ ̲S̲u̲p̲p̲o̲r̲t̲
The CIA is the only address sourcing unit connected
to the I/O Bus and this eliminates the need for
bus arbitration. The remaining support functions
are described in the ollowing.
1) C̲l̲o̲c̲k̲ ̲G̲e̲n̲e̲r̲a̲t̲i̲o̲n̲
The clock signals ]1 and ]2 on the I/O Bus
are 1MHz and 8 MHz, respectively. They are
derived from a 16 MHz crystal oscillator on
the CIA, which also provides the CIA-sequencer
with basic timing. [1 and ]2 arethe time base
for interrupt receiving on the I/O Bus.
2) P̲o̲w̲e̲r̲ ̲S̲u̲p̲e̲r̲v̲i̲s̲i̲o̲n̲
The CIA includes a voltage comparator circuit,
which monitors the power inputs (+5V, +12V
and -12V). If a drop occurs in one of the
three voltages that s not so severe as to cause
power up reset, a Power Failure flip-flop (PFF)
is set and a power failure interrupt is issued
on the next interrupt fetch command from the
Data Channel.
As long as the PFF is set a red LED on the
front panel of the IA is activated.
A special interrupt fetch command is used to
reset the PFF.
3) P̲o̲w̲e̲r̲ ̲u̲p̲ ̲R̲e̲s̲e̲t̲
CR80D-modules connected to a dual bus structure
generate power up reset on their own. The
CIA, however, can also be used as interface
towardsa single I/O bus structure, and therefore
a power up reset (not used in this system)
is carried to the I/O Bus.
The power up reset observes the Master Clear
specifications of the CR80D Main Bus (sec.
5.1.3.1.1).
4) I̲/̲O̲ ̲B̲u̲s̲ ̲T̲e̲r̲m̲i̲n̲a̲t̲i̲o̲n̲
Th physical appearance of the I/O Bus is a
motherboard (DMB) and the signals are electrically
terminated on one end by the CIA and on the
other by a terminating board, the MBT.
5.1.5.1.1.1 M̲e̲c̲h̲a̲n̲i̲c̲a̲l̲ ̲&̲ ̲E̲l̲e̲c̲t̲r̲i̲c̲a̲l̲ ̲S̲p̲e̲c̲i̲f̲i̲c̲a̲t̲i̲o̲n̲s̲
M̲e̲c̲h̲a̲n̲i̲c̲a̲l̲ ̲D̲i̲m̲e̲n̲s̲o̲n̲s̲ ̲o̲f̲ ̲t̲h̲e̲ ̲C̲I̲A̲
Height: 263 mm
Width: 17,1 mm ( l Module)
Depth: 280 mm
E̲l̲e̲c̲t̲r̲i̲c̲a̲l̲ ̲S̲p̲e̲c̲i̲f̲i̲c̲a̲t̲i̲o̲n̲s̲ ̲f̲o̲r̲ ̲t̲h̲e̲ ̲C̲I̲A̲
P̲o̲w̲e̲r̲ ̲C̲o̲n̲s̲u̲m̲p̲t̲i̲o̲n̲
+ 5V: 3 A
+ 12V: 80 mA
- 12V: 80 mA
C̲I̲A̲/̲D̲a̲t̲a̲ ̲C̲h̲a̲n̲n̲e̲l̲ ̲S̲i̲g̲n̲a̲l̲s̲
The Data Channel signals are pulsed with a nominal
ulse width of 62.5 ns.
Transformer driver specifications:
I…0f…OL…0e… max …0f…-…0e… 100 mA
V…0f…O…0e… max …0f…-…0e… 10 V
Receiver specification:
Sensitivity: 0.2 V
Hysteresis: 30 mV
The signals are terminated in the PU-end and in the
CU end by a 120 Ohm shun resistor.
5.1.5.1.2 T̲h̲e̲ ̲D̲i̲s̲k̲ ̲C̲o̲n̲t̲r̲o̲l̲l̲e̲r̲ ̲a̲n̲d̲ ̲t̲h̲e̲ ̲D̲i̲s̲k̲ ̲C̲o̲n̲t̲r̲o̲l̲l̲e̲r̲ ̲A̲d̲a̲p̲t̲e̲r̲
(̲D̲C̲A̲)̲
The Disk Controller and the DCA constitute the complete
interface between the CR80D I/O buses and up to 4 disk
drives. Any combination of drives from Control Data
orporation's (CDC) SMD, MMD, and CMD families is possible.
5.1.5.1.2.1 T̲h̲e̲ ̲D̲i̲s̲k̲ ̲C̲o̲n̲t̲r̲o̲l̲l̲e̲r̲ ̲M̲o̲d̲u̲l̲e̲
The Disk Controller module consists of two functionally
independent modules (ref. fig. 5.1.5.1.2.1-1):
- an I/O module (disk controller) occupyng 1 of the
possible 62 in-crate module addresses.
- a RAM module forming 16K (32K) of the possible
1M words of in-crate memory.
The controller receives commands and delivers status
via its own bus control logic, whereas instrucions
concerning disk operations, are fetched from the RAM.
The RAM is furthermore used as a data buffer.
Fig. 5.1.5.1.2.1-1
The Disk Controller
The controller contains two independent I/O bus ports
implemented by physically separate IC packages. Thus
no interface chip can simultaneously cause failure
of both ports. Eachport of the controller has a 6-bit
configurable controller number, as well as a 2-bit
interrupt priority setting. The only requirement is
that the controller must be assigned a controller number
distinct from controller numbers located within the
ame Channel Unit.
A power-on condition causes a controller reset and
also gives an interrupt to one of the two Processor
Units to which it is attached. The output of the Power
On detection circuit is also used to control all the
Data bus transcevers so that a controller being powered
down will not cause interference on the I/O buses during
the power transient. This is possible because the
power circuit operates with very low supply voltage
and special transceivers are used which correctl stay
in a high impedance state as long as the supply voltage
is too low for correct functioning of the board logic
circuitry.
Logically only one of the two ports of the controller
is active, while the other port, the alternative, is
utilized in he event of a path failure of the primary
port. There is an "ownership" bit associated with
each port which indicates whether it is the primary
port or the alternate. Ownership is changed only by
a PU issuing a TAKE OWNERSHIP I/O command. Executng
this special command will cause the controller to define
its primary and alternate port designation and to do
a controller reset. Any attempt to use a controller
which is not owned by a given Processor Unit will result
in an ownership violation If a Processor Unit determines
that a controller is malfunctioning on its Data Channel
it can issue a DISABLE PORT command which logically
disconnects the port from that I/O controller. However,
this does not affect the ownership status.
If th problem is within the port, the alternate path
can be used, but if the problem is in the common part
of the controller, ownership is not forced upon the
other Processor Unit.
a) D̲i̲s̲k̲ ̲C̲o̲n̲t̲r̲o̲l̲l̲e̲r̲ ̲S̲e̲c̲t̲i̲o̲n̲
The disk controller part is a standard I/O module,
called DIF (Disk I/F and Formatter), which responds
to I/O commands from the currently selected I/
bus. The controller interfaces to the disk adaptor
(DCA) for connection of max. 4 disk drives in daisy
chain.
The DIF (Disk I/F and formatter) provides all controller
and formatter functions for the disk drives connected.
When a daisy chain cnfiguration is used (Fig.
5.1.5.1.2.1-2), only one drive may be written to
or read from at a time. However, overlapped seeks
are possible, since all drives are at all times
monitored for "seek over" conditions.
The communication with a Processo Unit is carried
out via the I/O bus (I/O-commands), while memory
is accessed via the internal micro-bus. The memory
is used for data transfer to and from disk and
for information between a Processor Unit and the
DIF.
An o̲p̲e̲r̲a̲t̲i̲o̲n̲ is defined asa task for the DIF concerning
a specified drive. An operation may include for
instance reading or writing data or initiation
of a seek (move of recording heads). During an
operation, the DIF is considered busy.
When the DIF is not busy, a Procssor Unit CPU may
initiate an operation by an I/O-command. Information
about the desired operation must have been stored
in the memory by the CPU. As long as the DIF is
busy with the operation, it will not receive requests
for more operations. Te DIF indicates by a bit
in its status word whether it is busy or not.
If enabled, an interrupt is sent to the CPU when
the operation has been completed (Operation Complete
(OPC) interrupt).
Return information to the CPU primarily consists
of:
1) A status word concerning the DIF and the latest
operation, and
2) A unit flag word concerning the disk drives.
Interrupts may be caused by certain changes in
the status word (OPC - and ICM (Illegal Command
Interrupts)) and by the unit flags (unit interrupt).
Unit interrupts and OPC interupt may be masked
off.
The DIF provides generation and checking of a 2
byte CRC code added to the address field as well
as to the data field of each sector.
During an operation, various checks are carried
out considering the status lines of te drive, memory
parity, CRC check, validity of address field etc.
Fig. 5.1.5.1.2.1-2
Max. Disk Drive Configuration…86…1 …02… …02… …02… …02…
The DIF consists of:
- a micro-programmed disk control processor
- a data synchronizer and serial/parallel converter
- drive control logics and
- bus control logics
Te control processor interprets instructions stored
in the RAM memory, controls and monitors the drives,
performs word and byte oriented formatting and
data transfers, and does all the sequencing of
operations. The processor includes an ALU (Arithmtic
& Logic Unit) and 16 registers for handling memory
addresses and disk parameters such as:
- cylinder number
- head number
- sector number
- drive status etc.
The data synchronizer and serial/parallel converter
include shift register CRC generator/checker, byte
synchronizer and sequencer for the serial data
and clock.
The drive control transmits control signals as
well as cylinder, head, and sector numbers from
the control processor. The status of the drive(s)
is received nd transferred to the control processor.
Furthermore, the drive control transfers "seek
complete" and "drive not busy" conditions to the
bus control.
The bus control logic (disk) interprets commands
from the internal I/O bus. It puts drive andcontroller
status on the internal I/O bus, requests the control
processor for operations, sets interrupt masks
etc. Furthermore, it generates interrupts in accordance
with status and masks.
b) R̲A̲M̲ ̲M̲e̲m̲o̲r̲y̲ ̲S̲e̲c̲t̲i̲o̲n̲
The RAM memory part consists of:
- a RAM
- RAM control
- address and data multiplexers
- bus control logic
- switch array
The RAM part of th Disk Controller module forms
16 K or 32 K words (type dependent) of the memory
space connected to the currently selected bus.
Each word consists of 16 bit data and 2 bit parity
in accordance with CR80D standard.
The RAM is dual ported. One pot is connected to
the current I/O bus, and one port is connected
to the disk controller, cf. fig. 5.1.5.1.2.1-1.
The RAM Control switches via the multiplexers the
access over between the disk controller and the
internal I/O bus in turn. For thi purpose the
RAM Control receives requests from the bus control
logic (RAM) and the disk control processor. The
bus control logic (RAM) transfers data and address
between the internal I/O bus and the RAM.
Memory transfer rate:
From/to a disk 625 Kwords/second
From/to I/O Bus: 2 Mwords/second
The actual address space covered by the RAM is
set by switches on the printed circuit board (fig.
5.1.5.1.2.1-3):
switch no: 1 2 3 4 5 6
bank select, AD19-AD18
(switch 6 = MSB)
32K section within selected
bank: SW4 = AD17
SW3 = AD16
SW2 = AD15
For 16K version: SW 1 = AD14
For 32K version: SW 1 = "don't care"
Fig. 5.1.5.1.2.1-3…01…R̲A̲M̲ ̲A̲D̲D̲R̲E̲S̲S̲ ̲S̲W̲I̲T̲C̲H̲
1) I̲/̲O̲ ̲B̲u̲s̲ ̲P̲o̲r̲t̲
The RAM will respond to the bus, only if AD
19-18 and AD17-14 (for 32K version: AD17-15)
match the switch settings and LS1-0 = 00 (indicating
I/O)
Response time from TRQ(L) = 0 and AE(L) = 0
to RS(L) = 0: max. 900 ns
typ. 450 ns
(These signals are described in sec. 5.1.3.1.1).
2) D̲i̲s̲k̲ ̲C̲o̲n̲t̲r̲o̲l̲l̲e̲r̲ ̲P̲o̲r̲t̲
The RAM will always respond to the controller
port. For 16K version, the lower 14 address
bits are used, and for 32K version, the
lower 15 address bits are used as adress
relative to the start of the RAM space included.
A brief description of the commands issued
from a PU to the Disk Controller is given
on the following pages.
The Address/Command format is shown in fig.
5.1.5.1.2.1-4, and the Command Cde interpretation
is shown in table 5.1.5.1.2.1-5.
c) D̲i̲s̲k̲ ̲C̲o̲n̲t̲r̲o̲l̲l̲e̲r̲ ̲C̲o̲m̲m̲a̲n̲d̲s̲
1) R̲e̲a̲d̲ ̲S̲t̲a̲t̲u̲s̲ ̲W̲o̲r̲d̲
The DIF puts its status word on the I/O
bus data lines DA15 - DA0.
2) R̲e̲a̲d̲ ̲S̲t̲a̲t̲u̲s̲ ̲W̲o̲r̲d̲,̲ ̲C̲l̲e̲a̲r̲ ̲I̲n̲t̲e̲r̲r̲u̲p̲t̲
As "Read Status Word" except hat the interrupt
flag internal in the DIF is cleared, thus
enabling the DIF to send further interrupts.
This is a message to the DIF, that an interrupt
is received.
3) R̲e̲a̲d̲ ̲U̲n̲i̲t̲ ̲F̲l̲a̲g̲s̲
The DIF puts the unit flag (4 bit) on the
I/O bus data ines DA3-DA0.
4) R̲e̲a̲d̲ ̲U̲n̲i̲t̲ ̲F̲l̲a̲g̲s̲,̲ ̲C̲l̲e̲a̲r̲ ̲I̲n̲t̲e̲r̲r̲u̲p̲t̲
As "Read Unit Flags" except that the interrupt
flag internal in the DIF is cleared.
5) R̲e̲s̲e̲t̲
This command immediately forces the DI to execute
the start up routine.
R/W: '0' = input (DIF to PU)
'1' = output (PU to DIF)
OPC interrupt: During output (R/W = 1) - except RESET
- this bit is interpreted as the mask
bit for OP - interrupt:
'0' = enable
'1' = disable
AD10 is ignored if R/W = 0
Command code: These two bits specify together with
R/W the command.
Module address: Specifies the module to which the
I/O
i related. The module address is
selected by means of switches in the
DIF.
BUS SWITCH ̲ ̲ ̲ ̲ ̲A̲D̲ ̲ ̲1̲1̲ ̲ ̲ ̲1̲0̲ ̲ ̲ ̲9̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲
̲ ̲ ̲
COMMANDS: 1 0 0 DISABLE DISK CTRL,
RESET
1 0 1 ENABLE DISK CTRL,
RESET
Fig. 5.1.5.1.2.1-4…01…A̲D̲D̲R̲E̲S̲S̲ ̲F̲O̲R̲M̲A̲T̲
R/W Command Code Command
̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲
̲ ̲ ̲ ̲ ̲ ̲ ̲
0 0 0 read status wod.
0 0 1 read status word, clear interrupt.
0 0 0 read unit flags.
0 1 1 read unit flags, clear interrupt.
1 0 0 reset.
1 0 1 load unit interrupt mask
1 1 0 load instruction pointer,
initiate operation.
1 1 1 terminate operation.
Table 5.1.5.1.2.1-5…01…C̲O̲M̲M̲A̲N̲D̲ ̲I̲N̲T̲E̲R̲P̲R̲E̲T̲A̲T̲I̲O̲N̲
6) L̲o̲a̲d̲ ̲U̲n̲i̲t̲ ̲I̲n̲t̲e̲r̲r̲u̲p̲t̲ ̲M̲a̲s̲k̲
The I/O bus datalines DA3-DAO are loaded into
the unit interrupt mask (UM) register. This
register determines, which of the unit flags
may cause interrupt or not.
7) L̲o̲a̲d̲ ̲I̲n̲s̲t̲r̲u̲c̲t̲i̲o̲n̲ ̲P̲o̲i̲n̲t̲e̲r̲,̲ ̲I̲n̲i̲t̲i̲a̲t̲e̲ ̲O̲p̲e̲r̲a̲t̲i̲o̲n̲
The I/O bus datalines DA15 - DAO are interpreted
as the start address of an instruction field
in the emory. The operation specified here
is then carried out. The DIF will be busy
until the operation has been completed, and
if enabled an OPC interrupt is sent when the
DIF is ready.
If this command is issued while the DIF is
busy, it will be inored, except that the ICM
bit of the status word is set and an interrupt
is sent. The current operation is not affected.
8) T̲e̲r̲m̲i̲n̲a̲t̲e̲ ̲o̲p̲e̲r̲a̲t̲i̲o̲n̲
An internal termination flag is set, and the
current operation will be terminated when allowed.
Depending on the kind and progress of the
current opertion, this may be completed in
a normal way regardless of the terminate command.
When the DIF is ready (i.e. operation is over),
a bit in the status word tells, if the operation
has been terminated by the terminate command.
Also in this case an OC interrupt is sent
if enabled.
9) D̲i̲s̲a̲b̲l̲e̲ ̲D̲i̲s̲k̲ ̲C̲o̲n̲t̲r̲o̲l̲e̲r̲,̲ ̲R̲e̲s̲e̲t̲
By this command the Disk Controller is disabled
from both I/O buses and reset to a well defined
state.
10) E̲n̲a̲b̲l̲e̲ ̲D̲i̲s̲k̲ ̲C̲o̲n̲t̲r̲o̲l̲l̲e̲r̲,̲ ̲R̲e̲s̲e̲t̲
By this command the Disk Controler is enabled
towards the I/O Bus that transferred the command,
and disabled from the other I/O Bus. In case
a transfer between an I/O Bus and the Disk
Controller RAM area is ative at the time of
an enable command received from the opposite
I/O bus the bus switch is delayed to guarantee
correct contents of the RAM area.
The Disk Controller is then initialized. If
an enable command is received and the Disk
Controller is already enabled towards the transferring
I/O Bus then the Disk Controler is initialized.
5.1.5.1.2.2 T̲h̲e̲ ̲D̲C̲A̲
The DCA (Disk Controller Adapter) is the interface
between the Disk Controller and one or more (max. 4)
disk drives, as shown on fig. 5.1.5.1.2.1-2.
The DCA is connected to the disk drive(s) via at leat
2 flatcables and a maximum of 5 flatcables (4 disks
connected). One flatcable (the A cable), is a common
bus (daisy chain) for all connected drives.
Furthermore, each drive is connected to the DCA via
an individual flatcable (the B cable).
The A cable is a 30 twisted pair flatcable. Each B
cable is a 26 conductor flatcable ith ground plane
and drain wire.
A disk operation performed by the Disk Controller has
to contain information about:
- The disk drive to be used (1 of 4).
- The disk cylinder number (head position)
- The Head number and
- The disk sector nuber.
These control signals, of which not all have to be
used in every operation, are forwarded to the connected
drive(s) via the DCA control register and the common
A cable.
The disk drive number latched in the control register
selects via the ata & Clock multiplexer and the status
multiplexer the B cable connected to the selected drive.
The B cable transfers serial data & clock signals
to/from the selected drive plus status signals such
as "seek end" and "unit selected" from the selectd
drive.
The "seek end" status signal from all connected drives
is, via the Drive interrupt circuitry, sent to the
Controller as an interrupt condition (if not masked)
for a Processor Unit. Another status signal which
causes an interrupt (if notmasked) to a Processor Unit
is the "Unit Ready" signal transferred via the A cable
(only accessed from the selected drive).
The DCA furthermore contains circuitry to monitor supply
voltages and clock signals. If a power or clock failure
in the cntroller or the DCA is detected then the connected
drive(s) is (are) disabled.
Fig. 5.1.5.1.2.2-1
The DCA Module
5.1.5.1.2.3 M̲e̲c̲h̲a̲n̲i̲c̲a̲l̲ ̲&̲ ̲E̲l̲e̲c̲t̲r̲i̲c̲a̲l̲ ̲S̲p̲e̲c̲i̲f̲i̲c̲a̲t̲i̲o̲n̲s̲
M̲e̲c̲h̲a̲n̲i̲c̲a̲l̲ ̲d̲i̲m̲e̲n̲s̲i̲o̲n̲s̲ ̲o̲f̲ ̲t̲h̲e̲ ̲D̲i̲s̲k̲ ̲C̲o̲n̲t̲r̲o̲l̲l̲e̲r̲
Height: 412,6 mm ( 10 U crate)
Width: 17,1 mm ( 1 Module)
Depth: 305 m
The Disk Controller is a front crate mounted module.
P̲o̲w̲e̲r̲ ̲C̲o̲n̲s̲u̲m̲p̲t̲i̲o̲n̲ ̲o̲f̲ ̲t̲h̲e̲ ̲D̲i̲s̲k̲ ̲C̲o̲n̲t̲r̲o̲l̲l̲e̲r̲
+ 5V: 8 A
+12U: 0.5 A
M̲e̲c̲h̲a̲n̲i̲c̲a̲l̲ ̲d̲i̲m̲e̲n̲s̲i̲o̲n̲s̲ ̲o̲f̲ ̲t̲h̲e̲ ̲D̲C̲A̲
Height: 412,6 mm ( 10 U crate)
Width: 17,1 mm ( 1 Module)
Depth: 160 mm
The DCA is a rear crate mounted module.
P̲o̲w̲e̲r̲ ̲c̲o̲n̲s̲u̲m̲p̲t̲i̲o̲n̲ ̲o̲f̲ ̲t̲h̲e̲ ̲D̲C̲A̲
+ 5V: 1,5 A
-12V: 0,3 A
E̲l̲e̲c̲t̲r̲i̲c̲a̲l̲ ̲s̲p̲e̲c̲i̲f̲i̲c̲a̲t̲i̲o̲n̲ ̲o̲f̲ ̲t̲h̲e̲ ̲D̲i̲s̲k̲ ̲C̲o̲n̲t̲r̲o̲l̲l̲e̲r̲/̲D̲C̲A̲
F̲l̲a̲t̲ ̲C̲a̲b̲l̲e̲ ̲C̲o̲n̲n̲e̲c̲t̲i̲o̲n̲ ̲B̲u̲s̲
The adapter is connected through the 86-pin I/O connector
of te controller. Only 64 pins are used, thus allowing
64 pole twisted pair flat cable to be used. The pin
assignment is shown in fig. 5.1.5.1.2.3-1.
The electrical specifications apply to the disk controller.
That is, driver specifications are for sgnals originated
in the controller, and receiver specifications are
for signals originated in the adapter.
DRIVER SPECS. …0e…V…0f…OH MIN …0e…V…0f…OL MAX …0e…I…0f…OH MIN …0e…I…0f…OL
MIN
B2-9 2.4V .5V 2.6 mA 24
mA
AB11-18 2.5V 0.5V 20 mA 20
mA
B30 2.4V 0.5V 5 mA 30
mA
RECEIVER SPECS …0e…V…0f…IH MIN …0e…V…0f…IL MAX …0e…I…0f… IH MAX …0e…I…0f…IL
MAX
A10 2.0V 0.8V 20 micro A 0.36
mA
B19-22 2.0V 0.8V 20 micro A 0.40
mA
B 23-29 2.0V 0.8V 20 micro A 0.20
mA
B30 1.0V1.0V 20 micro A 0.40 mA
A B
not used 1 not used
GND 2 XC4
GND 2 XC5
GND 4 XC6
GND 5XC7
GND 6 XC0
GND 7 XC1
GND 8 XC2
GND 9 XC3
XLU 10 ZLU
XCK 11 ZCK
XRD 12 ZRD
XWC 13 ZWC
XWD 14 ZWD
XMC 15 ZMC
XLD 16 ZLD
XRU 17 ZRU
XFM 18 ZFM
GND 19 XSO
GND 20 XS1
GND 21 XS2
GND 22 XS3
GND 23 XIN
GND 24 XSC
GND 25 XOC
GND26 XUF0
GND 27 XUF1
GND 28 XUF2
GND 29 XUF3
GND 30 XVOK
+5V 31 +5V
+5V 32 +5V
-12V 33 -12V
not used 34 not used
not used 35 not used
FIGURE 5.1.5.1.2.3-1
DISK CTRL. - Adapter Connector Pn Lay-Out…86…1 …02… …02… …02… …02…
5.1.5.1.3 T̲h̲e̲ ̲L̲i̲n̲e̲ ̲T̲e̲r̲m̲i̲n̲a̲t̲i̲o̲n̲ ̲U̲n̲i̲t̲ ̲(̲L̲T̲U̲)̲ ̲a̲n̲d̲ ̲t̲h̲e̲ ̲V̲2̲4̲/̲V̲2̲8̲(̲L̲)̲
A̲d̲a̲p̲t̲e̲r̲
The LTU and the V24/V28(L) Adapter constitutes the
heavy protocol driving interface between the CR80D
I/O buss and up to 4 external V24/V28 communication
lines, which can be served with a speed of up to 9,6
KBaud full duplex on each channel, dependent on protocol.
For CAMPS Connectivity refer to sec. 5.3.
5.1.5.1.3.1 T̲h̲e̲ ̲L̲T̲U̲ ̲M̲o̲d̲u̲l̲e̲
The LTU is a stadard CR80D I/O module occupying 1 of
62 possible in-crate module addresses. It communicates
with the Processor Unit CPUs via FIFO oriented block
transfers. A block diagram of the LTU is shown on
fig. 5.1.5.1.3.1-1.
The LTU is divided into two mjor parts:
- The interface circuitry towards the
I/O bus.
- The V24/V28 communication controlling
microprocessor part.
Fig. 5.1.5.1.3.1-1
The LTU Module
Communication between the I/O bus interface and the
microprocessor section is done via a RAM area, called
the shared RAM, on the LTU.
The I/O bus interface contains two independnt I/O bus
ports implemented by physically separate IC packages.
Thus no interface chip can simultaneously cause failure
of both ports. Each port of the LTU has a 6-bit configurable
controller number, as well as an interrupt priority
setting. Th only requirement is that the LTU must
be assigned an I/O number distinct from I/O controller
numbers located within the same channel unit.
The functions of the dual I/O bus ports plus the Bus
Select circuitry are equal to the dual port descriptin
given in sec. 5.1.5.1.2.1 (The Disk Controller).
Furthermore, the I/O interface circuitry contains:
- An Interface Control (including Interrupt Logic)
- An Address Counter
- A Sequencer (micro programmed)
The microprocessor part contains:
- A system RAM
- A Bootload PROM
- A microprocessor section
When a LTU is addressed the Interface Control takes
over the control of the LTU. It handles all accesses
from a PU, and ensures that no new access is started
before the current is inished. Upon address recognition,
the Interface Control gives a start signal to the Sequencer.
The Sequencer is controlled by a microprogram. This
program handles the access to the shared RAM, Loading
of the Address Counter, parity control andthe hand
shaking between a PU and the microprocessor section
when sharing the shared RAM area. Part of the addressing
bits (bit 6-11) are by the Sequencer decoded as an
instruction to the LTU.
The Address Counter is a 16 bit up/down counter whic
holds the next address in shared RAM to be accessed
from a PU. The loading is as mentioned controlled
by the Sequencer which when it detects a "Load Address
counter" instruction, loads the Address Counter with
the contents of the I/O bus Data lins.
The Shared Ram area is a 16K x 9 bits (8 bit data +
1 parity bit) dynamic RAM. It is the data exchange
interface between I/O bus and the LTU microprocessor
part. Access to this AM is controlled by the Shared
RAM Control Logic. Normally, the microprocessor part
has direct access to the Shared RAM, but if a PU wants
to access this area, a bus request signal is sent from
the Sequencer. As soon as the microprocessor part
ha finished a possible access to the shared RAM, the
bus is shifted over to the I/O bus and controlled by
the Sequencer. After finishing the access, the RAM
bus is returned to the microprocessor part.
The microprocessor part of the LTU runs the V2/V28
communication ports transferring data to/from the Shared
Ram area. The firmware programs controlling the microprocessor
are resident in the System RAM which is a 16K x 9 bit
(8 bit data + 1 bit parity) dynamic RAM.
The firmware is loaded tothe system RAM by a multi
step bootload procedure. The PU issues a "boot load"
command to the LTU. This puts the LTU in bootload
mode, having the effect that all microprocessor section
reads are performed in the bootload PROM ("shadow"
PROM) and ll writes are done to the System RAM. The
bootload PROM is a "shadow PROM" because the PROM in
the bootload mode during read operations occupies the
8K lower bytes of the system RAM. The microprocessor
now executes the programs resident in the PRM starting
with an offline diagnostic test program. If the test
reveals no failures then the PROM resident bootload
program is executed. If the test detects a failure,
no bootloading is performed. The bootload program
takes care of loading the LU firmware from the Shared
RAM, to which it has been loaded from a PU, to the
System RAM. Handshaking between a PU and the microprocessor
part during bootload is performed via a status word
in the shared RAM. When the bootload has finished,
the LU is set in normal mode by a "programmed clear"
command from the PU, and the LTU starts executing the
firmware program.
The microprocessor section contains hardware necessary
to serve the serial communication channels:
- Serial input/output ciruitry, which converts parallel
data to serial data for transmission and vice versa
for reception.
- DMA circuitry for fast data transfer between serial
input/output circuitry and shared RAM.
- Timer circuitry for generating the different baud
clocks for each channel. Baud rates are under
Software control.
- Parallel I/O circuitry giving an extended set of
control sgnals on the V24/V28 communication lines.
Via the Transceiver block, the electrical conversion
between TTL level signals and line level signals and
vice versa is performed. These Transceivers are standard
circuitry in accordance with CCITT's V24V28 and EIA's
RS-232C recommendations.
In the following, a short description of the commands
issued from a PU to control the LTU is given.
Fig. 5.1.5.1.3.1-2 shows the Address format on the
I/O bus when addressing a LTU, and table 5.1.5.1.3.1-3gives
the different command interpretations.
a) L̲T̲U̲ ̲C̲o̲m̲m̲a̲n̲d̲s̲
1) D̲i̲s̲a̲b̲l̲e̲ ̲L̲T̲U̲,̲ ̲P̲r̲o̲g̲r̲a̲m̲m̲e̲d̲ ̲C̲l̲e̲a̲r̲
This command disables the LTU from both I/O
Buses, and makes the LTU go through an overall
clear routine. This clear does not affect the
RAM contnts. The address counter will be reset
and point to location 0 in the shared RAM.
2) E̲n̲a̲b̲l̲e̲ ̲L̲T̲U̲,̲ ̲P̲r̲o̲g̲r̲a̲m̲m̲e̲d̲ ̲C̲l̲e̲a̲r̲
This command enables the LTU towards the I/O
bus transferring the command. The LTU is disabled
from the opposite I/O Bus. A prorammed clear
similar to that of the Disable LTU Programmed
Clear is performed.
3) E̲n̲a̲b̲l̲e̲ ̲L̲T̲U̲,̲ ̲S̲e̲t̲ ̲L̲T̲U̲ ̲i̲n̲ ̲B̲o̲o̲t̲ ̲L̲o̲a̲d̲ ̲M̲o̲d̲e̲
This command enables the LTU towards the I/O
Bus transferring the command. The LTU is disabled
from the opposite I/O Bus.Then the clear routine
is performed and the LTU is set in boot load
mode.
Before the bootload operation takes place,
the bootloader performs an off line diagnostic
self test to ensure that there is no failure
in the module.
4) I̲n̲t̲e̲r̲r̲u̲p̲t̲ ̲R̲e̲q̲u̲e̲s̲t̲
The result of this command is an interrupt issued
to the LTU microprocessor.
R/W: "0" data transfer LTU to PU
"1" data transfer PU to LTU
Module type: LS1 "0" I/O Module
LS0 "0"
Command Code: These 6 bits together wth R/W specify
the actual command to the LTU.
Module address: The 6 bits together with LS1 and LS0
is the module address. The module
address is selectable by means of
switches.
Fig. 5.1.5.1.3.1-2…01…A̲D̲D̲E̲S̲S̲ ̲F̲O̲R̲M̲A̲T̲
̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲
̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲
ADDR. 6-11
R/W 11 10 9 8 7 6 Command
̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲
̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲
0 l 0 0 0 0 0 Disable LTU, Programmed
clear
0 1 0 1 0 0 0 Enable LTU, Programmed
clear
0 1 1 1 0 0 0 Enable LTU, Set LTU in
Bootoad mode
0 0 1 0 0 0 0 Interrupt request to
micro-
processor.
1 0 0 0 0 1 1 Load Address Counter
0 0 0 0 0 0 0 Read Status Word B(0),
B(1), P=2
0 0 0 0 1 0 0 Read word B(P), B(P+1)
Fetch word B(P2), B(P+3)
0 0 0 0 1 0 1 Read Lower Byte B(P)
P=P+1
1 0 0 1 0 0 0 Write word B(P), B(P+1)
P = P+2
1 0 0 0 0 0 1 Write lower byte B(P),
P = P+1
1 0 0 0 0 1 0 Write upper byte B(P)
P=P+1
0 0 0 1 0 1 1 Read Parity Status
̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲
̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲
Table 5.1.5.1.3.1-3…01…C̲O̲M̲M̲A̲N̲D̲ ̲I̲N̲T̲E̲R̲P̲R̲E̲T̲A̲T̲I̲O̲N̲
5) L̲o̲a̲d̲ ̲A̲d̲d̲r̲e̲s̲s̲ ̲C̲o̲u̲n̲t̲e̲r̲
Before an access, read or write, to the shared
RAM can be performed by a PU, it is necessary
to load the Address Counter with an address
pointing to te location in shared RAM where
the access is to take place. The address loaded
by this command is the contents of the I/O
bus Data lines. Since the size of the Shared
RAM is 16K bytes, the "pointer" must have a
value:
0 …0f…-…0e… pointer …0f…-…0e… 3FFF ex.
6) R̲e̲a̲d̲ ̲S̲t̲a̲t̲u̲s̲ ̲W̲o̲r̲d̲ ̲B̲(̲0̲)̲,̲ ̲B̲(̲1̲)̲,̲ ̲P̲=̲2̲
This command resets the pointer (P) (held in
Address counter) and reads the Status word
contained in the bytes B(0) and B(1). The
pointer is auto incremented to 2.
7) R̲e̲a̲d̲ ̲W̲o̲r̲d̲ ̲B̲(̲P̲)̲,̲ ̲B̲(̲P̲+̲1̲)̲,̲ ̲F̲e̲t̲c̲h̲ ̲(̲P̲+̲2̲)̲,̲ ̲B̲(̲P̲+̲3̲)̲
This command reads a word (two bytes) from
the shared RAM location addressed by the pointer.
To give faster response to the PU, the next
word is fetched and kept ready for the next
transfer.
8) R̲e̲a̲d̲ ̲L̲o̲w̲e̲r̲ ̲B̲y̲t̲e̲ ̲B̲(̲P̲)̲,̲ ̲P̲=̲P̲+̲1̲
his command reads 1 byte from the shared RAM
location to which the pointer points. The
result is placed in the lower part of the I/O
bus data lines. The pointer is incremented
by one.
9) W̲r̲i̲t̲e̲ ̲W̲o̲r̲d̲ ̲B̲(̲P̲)̲,̲ ̲B̲(̲P̲+̲1̲)̲,̲ ̲P̲=̲P̲+̲2̲
This command writes aword (2 bytes) to the
shared RAM location to which the pointer points.
To give faster response, the data is latched
and response sent to the PU. Then the data
is stored in the RAM. The pointer is incremented
by 2.
10) W̲r̲i̲t̲e̲ ̲L̲o̲w̲e̲r̲ ̲B̲y̲t̲e̲ ̲B̲(̲B̲)̲,̲ ̲P̲=̲P̲+̲1̲
This command writes the lower byte of the I/O
bus data lines into the shared RAM location
addressed by the pointer. Data is latched
to give aster response. The pointer is incremented
by one.
11) W̲r̲i̲t̲e̲ ̲U̲p̲p̲e̲r̲ ̲B̲y̲t̲e̲ ̲B̲(̲P̲)̲,̲ ̲P̲=̲P̲+̲1̲
This command writes the upper byte of the I/O
bus data lines into the shared RAM location
to which the pointer points. Data is latched
to give faster respose. The pointer is incremented
by one.
12) R̲e̲a̲d̲ ̲P̲a̲r̲i̲t̲y̲ ̲S̲t̲a̲t̲u̲s̲
This command reads the parity status. If there
has been a parity error in any of the two RAM
areas, the status word will be 01 Hex. If
no error the status word will be 00 Hex.
5.1.5.1.3.2 T̲h̲e̲ ̲V̲2̲4̲/̲V̲2̲8̲(̲L̲)̲ ̲A̲d̲a̲p̲t̲e̲r̲
The functions of the Low Level adapter is explained
in sec 5.3.2.4.
5.1.5.1.3.3 M̲e̲c̲h̲a̲n̲i̲c̲a̲l̲ ̲&̲ ̲E̲l̲e̲c̲t̲r̲i̲c̲a̲l̲ ̲S̲p̲e̲c̲i̲f̲i̲c̲a̲t̲i̲o̲n̲s̲
M̲e̲c̲h̲a̲n̲i̲c̲a̲l̲ ̲D̲i̲m̲e̲n̲s̲i̲o̲n̲s̲ ̲o̲f̲ ̲t̲h̲e̲ ̲L̲T̲U̲
Height: 412,6 mm ( 10 U crate)
Width: 17, mm ( 1 Module)
Depth: 305 mm
The LTU is a front crate mounted module.
P̲o̲w̲e̲r̲ ̲C̲o̲n̲s̲u̲m̲p̲t̲i̲o̲n̲ ̲o̲f̲ ̲t̲h̲e̲ ̲L̲T̲U̲
+ 5V: 4,2 A
+12V: 0,25 A
-12V: 0,15 A
M̲e̲c̲h̲a̲n̲i̲c̲a̲l̲ ̲D̲i̲m̲e̲n̲s̲i̲o̲n̲s̲ ̲o̲f̲ ̲t̲h̲e̲ ̲V̲2̲4̲/̲V̲2̲8̲(̲L̲)̲ ̲A̲d̲a̲p̲t̲e̲r̲
Height: 412,6 mm ( 10 U crate)
Width: 17,1 mm ( 1 Module)
Depth: 160 mm
The Adapter is a rear crate mounted modle.
P̲o̲w̲e̲r̲ ̲C̲o̲n̲s̲u̲m̲p̲t̲i̲o̲n̲ ̲o̲f̲ ̲t̲h̲e̲ ̲A̲d̲a̲p̲t̲e̲r̲
+ 5V: N/A
+12V: 0,1 A
-12V: 0,1 A
E̲l̲e̲c̲t̲r̲i̲c̲a̲l̲ ̲S̲p̲e̲c̲i̲f̲i̲c̲a̲t̲i̲o̲n̲ ̲o̲f̲ ̲t̲h̲e̲ ̲L̲T̲U̲/̲A̲d̲a̲p̲t̲e̲r̲ ̲F̲l̲a̲t̲c̲a̲b̲l̲e̲
C̲o̲n̲n̲e̲c̲t̲i̲o̲n̲ ̲B̲u̲s̲
Fig. 5.1.5.1.3.3-1 shows the signals transferred on
the flatcable bus. The circuits used fo each circuitry,
with the exception of CALL, are in accordance with
CCITT's V24 - and EIA's RS-232C Recommendation.
Fig. 5.1.5.1.3.3-1
LTU Flatcable I/O Connector
5.1.5.1.4 T̲h̲e̲ ̲F̲l̲o̲p̲p̲y̲ ̲D̲i̲s̲k̲ ̲C̲o̲n̲t̲r̲o̲l̲l̲e̲r̲ ̲&̲ ̲A̲d̲a̲p̲t̲e̲r̲
The Standard Floppy Disk Controller (SFDC) and the
Standard Floppy Disk Controller Adapter (SFA) constitute
the complete interfacebetween the CR80D I/O buses and
up to 4 Floppy disk drives (FDDs) of the type Shuggart
SA 800/850. Only two of the four possible drives are
provided within CAMPS.
The CAMPS FDDs are Shuggart SA 800, or equivalent,
characterized by:
- Single desity disk (IBM 3740 compatible)
- Single sided disk
- Soft Sector
- 77 tracks/disk
- 26 sectors/track
The FDDs are connected to the SFA (rear crate module)
via a flatcable. The SFA is in turn connected to the
SFDC (front crate module) via a latcable. The SFA
only acts as an extension board between the SFDC flatcable
connector and the FDD flatcable connector. The SFA
contains neither active nor passive circuitry.
CAMPS configuration of the Floppy Disk system is shown
in fig. 5.1.5..4-1.
5.1.5.1.4.1 T̲h̲e̲ ̲F̲l̲o̲p̲p̲y̲ ̲D̲i̲s̲k̲ ̲C̲o̲n̲t̲r̲o̲l̲l̲e̲r̲
The SDFC module (ref. fig. 5.1.5.1.4.1-1) provides
all necessary timing, buffering and signal conversion
between the CR80D I/O buses and 2 FDDs.
To adapt the SDFC to the dualized I/O bus structurea
bus switch logic is included providing dynamical switching
between the two I/O buses. The bus switch logic controls
two independent I/O bus ports implemented by physically
separate IC packages.
Thus no interface chip can simultaneously cause filure
of both ports. Each port of the controller has a 6-bit
configurable controller number, as well as a 2-bit
interrupt priority setting. The only requirement to
the switch setting is that the controller must be assigned
a controller number disinct from controller numbers
located within the same Channel Unit.…86…1 …02… …02…
…02… …02…
A power-on condition causes a controller reset and
also gives an interrupt to one of the two Processor
Units to which it is attached. The output of the Power
On detection circuitis also used to control all the
Data bus transceivers so that a controller being powered
down will not cause interference on the I/O buses during
the power transient. This is possible because the
power circuit operates with very low supply voltageand
special transceivers are used which correctly stay
in a high impedance state as long as the supply voltage
is too low for correct functioning of the board logic
circuitry.
Logically only one of the two ports of the controller
is active, whilethe other port, the alternative, is
utilized in the event of a path failure of the primary
port. There is an "ownership" bit associated with
each port which indicates whether it is the primary
port or the alternate. Ownership is changed only by
aPU issuing a TAKE OWNERSHIP I/O command. Executing
this special command will cause the controller to define
its primary and alternate port designation and to do
a controller reset. Any attempt to use a controller
which is not owned by a given Proessor Unit will result
in an ownership violation. If a Processor Unit determines
that the controller is malfunctioning on its Data Channel
it can issue a DISABLE PORT command which logically
disconnects the port from the controller. However,
thisdoes not affect the ownership status.
If the problem is within the port, the alternate path
can be used, but if the problem is in the common part
of the controller, ownership is not forced upon the
other Processor Unit.
Fig. 5.1.5.1.4.1-1…01…The Floppy Disk Controller…86…1 …02… …02… …02… …02…
The SFDC is a standard I/O module which only, with
the exception of Bus-switch commands, responds to I/O
commands from the currently selected I/O Bus.
Operation of the floppy dik system is performed via
a set of I/O commands. An operation may include for
instance reading or writing data from/to a Floppy Disk
or initiation of a seek (move of read/write head).
During an operation, the SFDC is considered busy.
This is inicated by setting the BUSY bit contained
in a status word called the additional status code.
When the operation is terminated (successfully or
due to an error), the BUSY bit is reset and the SFDC
as a result of this generates a non maskable interrpt.
Information about the completed operation will be
available in two different status words, the Auto status
and the Additional status (the content of these status
words will be explained in sec. 5.1.5.1.4.1 b).
a) S̲F̲D̲C̲ ̲c̲o̲m̲m̲a̲n̲d̲s̲
The addressng format when addressing the SFDC is
shown in fig. 5.1.5.1.4.1-2. Part of the address
(Bits 6-11 incl.) is decoded by the SFDC as a command
as shown in table 5.1.5.1.4.1-3.
In the following the possible commands are explained:
1) D̲i̲s̲a̲b̲l̲e̲ ̲M̲o̲u̲l̲e̲,̲ ̲r̲e̲s̲e̲t̲
By this command the floppy disk controller
is disabled from b̲o̲t̲h̲ main buses and the module
is reset to a well defined state.
2) E̲n̲a̲b̲l̲e̲ ̲S̲w̲i̲t̲c̲h̲,̲ ̲r̲e̲s̲e̲t̲
By this command the floppy disk controller
is enabled onto the bus, which is ourcing the
command and disabled from the other bus. Transfer
on the other bus if any will be destroyed.
R/W: "0" transfer from SFDC to PU
"1" transfer from PU to SFDC
LS1 = LS0 = "0" I/O operation
Command code: These 6 bits specify the command type
Moule address: These 6 bits specify the I/O module
address. This address is selectable
by means of switches on the module.
Fig. 5.1.5.1.4.1-2…01…A̲d̲d̲r̲e̲s̲s̲ ̲F̲o̲r̲m̲a̲t̲
R/W ADDR 6-11 COMMAND
̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲
11 10 9 8 7 6
̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲
̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲
1 1 0 0 X 0 1 Disable module,
eset
1 1 0 1 X 0 1 Enable module,
reset
1 0 X X X 0 0 Normal system
command
1 0 X X X 0 1 Reset RAM Pointer
1 0 X X X 1 0 Write data to
buffer
0 0 X X X 0 0 Read auto status
0 0 X X X 0 1 Read additional
status
0 0 X X X 1 0 Read data from buffer
X = "don't care condition".
Table 5.1.5.1.4.1-3…01…C̲o̲m̲m̲a̲n̲d̲ ̲I̲n̲t̲e̲r̲p̲r̲e̲t̲a̲t̲i̲o̲n̲
3) N̲o̲r̲m̲a̲l̲ ̲S̲y̲s̲t̲e̲m̲ ̲C̲o̲m̲m̲a̲n̲d̲
This command is actually a set of different
commands. The command to be performed must
be specified simultaneously in the data word
as shown in tabe 5.1.5.1.4.1-4. Each system
command is given a detailed explanation.
D̲a̲t̲a̲ ̲W̲o̲r̲d̲,̲ ̲b̲y̲t̲e̲ ̲p̲o̲s̲i̲t̲i̲o̲n̲
̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲
̲ ̲ ̲ ̲
1514 13 12 11 10 9 8 7 6 5 4 3 2 1 0
̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲
̲ ̲ ̲ ̲ ̲
0 0 0 0 0 0 D D X X X X X X X X
s̲e̲l̲e̲c̲t̲
drive
0 0 1 0 0 0 D D T T T T T T T T
s̲e̲e̲k̲
track
0 1 0 0 0 0 D D X X X X X X X X
r̲e̲s̲t̲o̲e̲
head
0 0 0 1 0 0 D D R R R R R R R R
r̲e̲a̲d̲
initial
record
0 0 0 1 0 0 D D R R R R R R R R
w̲r̲i̲t̲e̲
initial
record
0 0 1 0 1 0 D D R R R R R R R R
w̲r̲i̲t̲e̲
̲d̲e̲l̲e̲t̲e̲d̲
recrd
̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲
̲ ̲ ̲ ̲ ̲ ̲ ̲
T Track number (0:76)
R Record (sector) number (1-26)
D Drive number (0;1)
X Don't care condition
Table 5.1.5.1.4.1-4
N̲o̲r̲m̲a̲l̲ ̲S̲y̲s̲t̲e̲m̲ ̲C̲o̲m̲m̲a̲n̲d̲,̲ ̲D̲a̲t̲a̲ ̲W̲o̲r̲d̲
When a system command is given, transfer between the
formatter and the disk drives takes place, and it is
necessary to wait for the completion of the command.
The completion of the command is indicated in two ways:
1. An additional status bit changes from a BUSY to
a NOT BUSY indication.
2. An interrupt is generated
a) S̲e̲l̲e̲c̲t̲
This command performs drive selection and presents
the following status (if the status condition exists):
1. DRIVE NOT READY
2. WRITE PROTECT
3. TWO SIDED
The selected drive would not be ready if a diskette
is not properly installed r the drive is not up
to operational speed. WRITE PROTECT status indicates
that the diskette may only be read. TWO SIDED
status indicates that a diskette with data tracks
on both sides is installed (Not applicable to CAMPS).
b) S̲e̲e̲k̲
The trak number passed within the SEEK command
is located and verified automatically. If the
verify does not succeed within 4 revolutions of
the diskette, a SEEK ERROR status is presented.
A successful completion of a seek indicated by
track address comarison and CRC check would set
SEEK COMPLETE status. A CRC error would set ID
DATA CHECK status after four verify attempts.
Present track address is maintained for each drive
at all times.
c) R̲e̲s̲t̲o̲r̲e̲
The RESTORE command causes the drive to tep out
max. 256 times and tests for a TRACK 00 signal.
Upon issuing 256 steps, if TRACK 00 fails to be
detected, a RECALIBRATE ERROR status is set. When
the TRACK 00 signal is detected, a verify is performed
as for SEEK.…86…1 …02… …02… …02… …02…
d) R̲e̲a̲d̲
The READ command is initiated after a SEEK
or RESTORE command. The drive orients to the
sector number within the command. Data is
read from that sector until one ofthe following
occurs:
1. A full sector (128 bytes) has been read
and stored in the sector buffer RAM on
the SFDC.
2. An error is detected.
If the record ID fails to compare without an
ID DATA CHECK error after 4 disk revolutions,
the RED operation is terminated and an ID NOT
FOUND status will be presented.
If the data field CRC check fails, the status
DATA CHECK will be presented.
e) W̲r̲i̲t̲e̲
The WRITE command is initiated after a SEEK
or RESTORE command. The drive oriens to the
sector number within the command and the FB
hex (11111011 binary) data pattern indicating
the record address mark is written to precede
the record data field. The write operation
continues until one of the following occurs:
1. A full ector (128 bytes) has been written
from the sector buffer RAM on the SFDC.
2. An error is detected.
If the record ID fails to compare without ID
DATA CHECK error after 4 disk revolutions,
the WRITE operation is terminated and an ID
NOT FOUN status is set.
f) W̲r̲i̲t̲e̲ ̲D̲e̲l̲e̲t̲e̲d̲ ̲R̲e̲c̲o̲r̲d̲
Identical to the WRITE command except that
an F8 hex (11111000 binary) address mark is
written instead of an FB.…86…1 …02… …02… …02…
…02…
4) R̲e̲s̲e̲t̲ ̲R̲A̲M̲ ̲P̲o̲i̲n̲t̲e̲r̲
This command is used to reset the pointer used
to indicate the sector buffer RAM location where
transfer of data takes place.
The address pointer of thesector buffer RAM is
automatically reset at the start of and at successful
termination of either of the system commands:
Read, Write, and Write Deleted.
5) W̲r̲i̲t̲e̲ ̲D̲a̲t̲a̲ ̲t̲o̲ ̲B̲u̲f̲f̲e̲r̲
Transfers a 16 bit data word into the sector buffer
(64 words of AM). The address of the RAM is automatically
incremented after each "Write data to buffer" command.
Note: Before filling the sector buffer, the RAM
Buffer pointer should be reset, by issuing
a Reset RAM Pointer System Command.
"Write data o buffer" command is used (typ.
64 times) before giving a WRITE system
command.
6) R̲e̲a̲d̲ ̲A̲u̲t̲o̲ ̲S̲t̲a̲t̲u̲s̲
When this command is sued, the SFDC will put the
auto status, the format of which is shown in table
5.1.5.1.4.1-5, onto the I/O Bus data lines.
7) R̲e̲a̲d̲ ̲A̲d̲d̲i̲t̲i̲o̲n̲a̲l̲ ̲S̲t̲a̲t̲u̲s̲
Equivalent to Read auto status. Though it will
be the additional status, the format of which is
shown in table 5.1.5.1.4.1-6, that is presented
on the I/O Bus datalines.
8) R̲e̲a̲d̲ ̲D̲a̲t̲a̲ ̲f̲r̲o̲m̲ ̲B̲u̲f̲f̲e̲r̲
This command trasfers one 16 bit data word from
the sector buffer (RAM). The address of the RAM
is automatically incremented after each command.
When the command is used after a READ System command,
the sector buffer contains the addressed sector,
even if the tatus bit DATA CHECK or DELETED RECORD
was set.…86…1 …02… …02… …02… …02…
b) S̲F̲D̲C̲ ̲p̲r̲o̲v̲i̲d̲e̲d̲ ̲s̲t̲a̲t̲u̲s̲ ̲i̲n̲f̲o̲r̲m̲a̲t̲i̲o̲n̲
After the completion of an operation, the SFDC
utilizes two types of status information, the
auto status (table 5.1.5.1.4.1-5) and the addtional
status (table 5.1.5.1.4.1-6), both loaded during
operation and upon completion (successfully
or due to errors) of an operation.
̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲
̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲
Bit Position Description Definition
̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲
̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲
0 Seek Complete Seek command was executed
successfully.
1 ID DATA CHECK CRC failed to compare
in the
ID field.
2 PROGRAM ERROR Invalid command.
3 NOT USED
4 DATA CHECK CRC check failed on
the data
field.
5 ID
NOT
FOUND Search
of
the
ID
field
was
not successful after
4 re-
volutions.
6 EQUIPMENT CHECK Resident Microdiagnostics
failed.
7 ADD. STATUS One or more bits in
the
NOT ZERO additional status
are set.
8 WRITE PRTECT selected drive is
write pro-
tected.
9 NOT USED
10 NOT USED
11 DRIVE NOT READY Selected drive is
not ready.
12 SEEK ERROR Upon completion of
the SEEK or RESTORE
command, the track
address does not compare.
13 RECALIBATE Track 00 was not detected
in
ERROR response to a RESTORE
command.
14-15 NOT USED
Table 5.1.5.1.4.1-5…01…A̲u̲t̲o̲ ̲S̲t̲a̲t̲u̲s̲ ̲C̲o̲d̲e̲…86…1 …02… …02… …02…
̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲
̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲
Bit Position Description Definition
̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲
̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲
0 DISK CH 0 Disk Change, Drive
0
1 DISK CH 1 Disk Change, Drive
1
2 DISK CH 2 Disk Change, Drive
2 (N/A)
3 DISK CH 3 Disk Change, Drive
3 (N/A)
4 DEL REC DELETED RECORD, i.e.
an F8
address mark found
during
read operation.
5 OVERRUN HANDSHAKE ERROR, transfer
between floppy disk
drive
and sector buffer
failed.
6 BUSY The formatter is executing
a command.
7 TWO SIDED The selected drive
contains a two sided
diskette. (N/A)
8 - 15 UNDEFINED
Table 5.1.5.1.4.1-6…01…A̲d̲d̲i̲t̲i̲o̲n̲a̲l̲ ̲S̲t̲a̲t̲u̲s̲ ̲C̲o̲d̲e̲…86…1 …02… …02… …02… …02…
5.1.5.1.4.2 M̲e̲c̲h̲a̲n̲i̲c̲a̲l̲ ̲&̲ ̲E̲l̲e̲c̲t̲r̲i̲c̲a̲l̲ ̲S̲p̲e̲c̲i̲f̲i̲c̲a̲t̲i̲o̲n̲s̲
M̲e̲c̲h̲a̲n̲i̲c̲a̲l̲ ̲S̲p̲e̲c̲i̲f̲i̲c̲a̲t̲i̲o̲n̲ ̲f̲o̲r̲ ̲t̲h̲e̲ ̲F̲l̲o̲p̲p̲y̲ ̲D̲i̲s̲k̲ ̲C̲o̲n̲t̲r̲o̲l̲l̲e̲r̲
Height: 412,6 mm ( 10 U crate)
Width: 17,1 mm ( 1 Module)
Deph: 305 mm
The Floppy Disk Controller is a front crate mounted
module.
P̲o̲w̲e̲r̲ ̲C̲o̲n̲s̲u̲m̲p̲t̲i̲o̲n̲ ̲f̲o̲r̲ ̲t̲h̲e̲ ̲F̲l̲o̲p̲p̲y̲ ̲D̲i̲s̲k̲ ̲C̲o̲n̲t̲r̲o̲l̲l̲e̲r̲
+ 5V: 3,5 A
+12V: 25 mA
-12V: N/A
M̲e̲c̲h̲a̲n̲i̲c̲a̲l̲ ̲S̲p̲e̲c̲i̲f̲i̲c̲a̲t̲i̲o̲n̲ ̲f̲o̲r̲ ̲t̲h̲e̲ ̲A̲d̲a̲p̲t̲e̲r̲
Height: 412,6 mm ( 10 U crate)
Width: 7,1 mm ( 1 Module)
Depth: 160 mm
P̲o̲w̲e̲r̲ ̲C̲o̲n̲s̲u̲m̲p̲t̲i̲o̲n̲ ̲f̲o̲r̲ ̲t̲h̲e̲ ̲A̲d̲a̲p̲t̲e̲r̲
Not applicable.
E̲l̲e̲c̲t̲r̲i̲c̲a̲l̲ ̲S̲p̲e̲c̲i̲f̲i̲c̲a̲t̲i̲o̲n̲s̲ ̲f̲o̲r̲ ̲t̲h̲e̲ ̲F̲l̲o̲p̲p̲y̲ ̲D̲i̲s̲k̲ ̲C̲o̲n̲t̲r̲o̲l̲l̲e̲r̲/̲A̲d̲a̲p̲t̲e̲r̲
̲F̲l̲a̲t̲c̲a̲b̲l̲e̲ ̲B̲u̲s̲
All specifications apply to drivers/receivers on the
SFDC.
Drivers: thee are open collector drivers with
the pull up resistor placed in
the FDDs.
(the far end)
V…0f…0H…0e… - 5,5V
0V - V…0f…OL…0e… - 0,4V
I…0f…OL…0e… : N/A
I…0f…OL…0e… - 48 mA
Receivers: A pull up resistor is provded at each
input.
2V - V…0f…IH…0e… - 5V
V…0f…IL…0e… - 0,8V
I…0f…IH…0e… - 20 micro A
I…0f…IL…0e… - 35 mA
