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Notes: CPS/TMA/007 (R) (Week 4)
Names: »2793A «
Derivation
└─⟦3e271d8e9⟧ Bits:30006157 8" Wang WCS floppy, CR 0198A
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WangText
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K K…06…J…0a…J…0d…J…00…J
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I…07…H…0b…H…0e…H…02…H…05…G…08…G…0b…G…0f…G…02…G…06…F…0b…F…00…F…06…E…09…E…01…D…08…D…00…C…09…C…01…B…08…B…02…A…09…A…01…@…08…@…00…@…06…?…0d…? >…0b…>…01…>…07…=…0c…=…01…<…09…<…0f…<…06…;…0c…;
:…86…1 …02… …02… …02… …02…
CAMPS Instructor's Manual for
MT/RST Course, Week 4
CPS/TMA/007
CDRL Logistics Support No. 03A
Line Item 8.2.4-B
Niels-Erik Nielsen
Kurt Nybroe-Nielsen
SHAPE (2), NEN, LT,
ER[, ALG, Conf. Mgmt., LU
ILS Train.Mgr. 840620
2
840620
Conf.Mgmt. 840620
…0f……86…1 …02… …02…
…02…
2793A/rt …02… CPS/TMA/007
…02… NEN/840620…02……02…ii
CAMPS Instructor's Manual for
MT/RST Course, Week No. 4…02… Issue 1…02… CAMPS
821008 All Preliminary Issue of
Document
1 830617 All Completely new update
of
manual
2 840620 All Completely new update
of
the manual in accordance
with CPS Log.No. 1434,
831021.
…0e… 2793A/rt
840620
TDX SYSTEM STRUCTURE 4:1:1 45 CAMPS…0f…
Describe the TDX SYSTEM STRUCTURE:
- TDX SYSTEM PERFORMANCE
- TDX SYSTEM DEVICES (SHORT FORM)
State the DEVICE NOs.
Evaluation of practice
in Lesson 4:1:4-6.
Revision at progress test,
question 1,3,5 & 6
Classroom
L
Black board, 7 OHs
STB I: Section 5
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840620
TDX BUS COMMUNICATION 4:1:2 45 CAMPS…0f…
Describe the TDX BUS COMMUNICATION
- UPPER BUS/LOWER BUS TRANSFER
- DATA FRAME FORMAT
- DEVICE POLLING
Revision at progress test, question 7
Classroom
L
Black board, 4 OHs
HBK: Section 8.2.1…86…1 …02… …02…
…0e… 2793A/rt
840620
TDX PROTOCOL, BAND WIDTH
& CODE FORMAT 4:1:3 45 CAMPS…0f…
Recognize the 3 protocol levels
Describe the BAND WIDTH allocation
Describe the SPL-D CODE FORMAT
Revision of progress test, question 2 & 4
Classroom
L
Blackboard, 2 OHs
- HBK: Section 8.2.2 & 8.3
- STB I: Section 6
…0e… 2793A/rt
840620
DEMONSTRATION OF THE
…0e…TDX SYSTEM, SLM & HWB 4:1:4-6 3x45 CAMPS…0f…
Locate all TDX SYSTEM MODULES and
POWER SUPPLIES.
Find the TDX SYSTEM related sections
in the SLM & HWB.
Evaluation at lab. exercises during
this week.
Revision at progress test, question 3
Training room
Classroom
DE, I, DI
Training System
-Lesson 4:1:1:OH 5-7
-SLM
-HWB
…0e… 2793A/rt
840620
TDX CONTROLLER 4:2:1-2 2 x 45 CAMPS…0f…
State the MODULE Location
Describe the performance
Recognize the block diagram
State the Front panel LEDs
State the front panel connections
State the back panel connections
Perform the MODULE SET UP
Describe the BIT
Evaluation at the lab. exercises
in lesson 4:2:4-6 (TDX SYSTEM STATUS TEST)
Revision at progress test
question 8 & 9.
Classroom
L
7 OHs
STB II: Section 20
…0e… 2793A/rt
840620
TDX HOST I/F (STI/TIA) 4:2:3 45 CAMPS…0f…
State the Location of the MODULES
Describe the performance of the MODULES
Recognize the block diagrams
State the front panel LEDs
State the function of the front panel switches
State the front panel connections
State the back plane connections
Perform the MODULE SET UP
Describe the BIT
Evaluation at the lab. exercises
in lesson 4:2:4-6 (STI TEST)
Revision at progress test,
question 11 & 12.
Classroom
L
11 OHs
STB II: Section 18 & 19
…0e… 2793A/rt
840620
…0f…TDX SYSTEM STATUS TEST,…0e…
BOOT UP PROCEED.& STI TEST 4:2:4-6 3x45 CAMPS
- Fulfil an ERROR FREE "TDX SYSTEM STATUS TEST"
(See OBJECTIVES, SLG 4:2:4-6: page 1)
- Perform the M&D TEST "BOOT UP PROCEDURES
(See OBJECTIVES, SLG 4:2:4-6: page 2)
- Fulfil an ERROR FREE "STI TEST"
(See OBJECTIVES, SLG 4:2:4-6: page 4)
- During practical exercise.
- During evaluation of the exercise.
- The students must have performed all exercises.
Training room
GW, DI, EX
- Training system with VDUs connected to both of
the MIAs
- TDX CONTROLLER CABLE
- M&D TEST DISK PACK and M&D TEST FLOPPY DISKETT.
- SLG 4:2:4-6 (4 pages)
- SLM: Section 4.3.3.4, 4.7.2.1.8 & 4.7.2.2.
- Lesson 4:1:1:OH5-7
…0e… 2793A/rt
840620
BSM-X 4:3:1 45 CAMPS…0f…
State the MODULE LOCATION
Describe the performance
Recognize the block diagram
State the front panel LEDs
State the function of the front panel switches
State the front panel connections
State the back plane connections
Perform the MODULE SET UP
Evaluation at the lab. exercises in
lesson 4:3:4-6 & 4:4:4-6
Revision at progress test, question 10
Classroom
L
6 OHs
STB II: Section 21
…0e… 2793A/rt
840620
LTUX-S 4:3:2 45 CAMPS…0f…
State the MODULE LOCATION
Describe the performance
Recognize the block diagram
State the front panel LEDs
State the function of the front panel switches
State the front panel connections
State the back plane connections
Perform the MODULE SET UP
Describe the BIT.
Evaluation at the lab. exercises in
lesson 4:3:4-6.
Revision at progress test, question 10
Classroom
L
5 OHs
STB II: Section 22
…0e… 2793A/rt
840620
L/L ADAPTORS & OPTO T/R 4:3:3 45 CAMPS…0f…
Describe the L/L ADAPTORS & OPTO T/R
- Performance
- Main functions
- Applications
State the front panel LEDs
Evaluation at the lab. exercises in
lesson 4:4:4-6 & 4:5.4-6
Revision at progress test, question 13 & 14
Classroom
L
5 OHs
-LESSON 6:3:1-2
-SLM: Section 4.5.5
…0e… 2793A/rt
840620
M&D TDX SYSTEM TEST 4:3:4-6 3x45 CAMPS…0f…
- Fulfil an ERROR FREE "TDX BUS TEST"
(See OBJECTIVES, SLG 4:3:4-6: page 1).
- Fulfil an ERROR FREE "LTUX-S STATUS TEST"
(See OBJECTIVES, SLG 4:3:4-6: page 2)
- During practical exercise.
- During evaluation of the exercise.
- The students must have performed all exercises.
Training room
GW, DI, EX
- SLG 4:3:4-6 (2 pages)
- Training system with VDUs connected to both of
the MIAs
- M&D TEST DISK PACK
- M&D TEST FLOPPY DISKETTES
- SLM: Section 4.7.2.1.8, 4.7.2.2 & 4.7.2.2.
- LESSON 4:1:1:OH5-7
2793A/rt
840620
POWER SUPPLIES, BP8 & TSP 4:4:1 45 CAMPS
Describe the TDX power supplies and the power distribution
in the TDX crate
Describe the BP8 (Back Panel type 8) functions
Describe the TSP (Temperature Supervision Panel)
No formal check
Current questions
Classroom
L
4 OHs
-SLM: Section 4.5.4 & 4.5.5
-STB II: Section 26 & 29
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840620
TDX CRATES, WALL OUTLETS 4:4:2 45 CAMPS…0f…
- Describe the TDX Crate functions
- Describe the TDX CABLES
- Describe all cable connections and the module positioning
in the TDX crates
- Describe the WALL OUTLET functions
No formal check
Current questions
Classroom
L
Black board, 8 OHs
- SLM: Section 4.5.4
- HWB: Section 3
…0e… 2793A/rt
840620
CCA FUNCTIONS OF THE BSM-X 4:4:3 45 CAMPS…0f…
- Describe the CCB communication principles
- Recognize the CCA functions of the BSM-X
Evaluation at exercises in Lesson 7:1:4-6
- The students must perform the exercise
No. 2, described in SLG 7:1:4-6
Classroom
L
12 OHs
Black board
SLM: Section 4.5.4
…0f… 2793A/rt
840620
M&D TDX SYSTEM TEST 4:4:4-6 3x45 CAMPS…0e…
- Fulfil an ERROR FREE "TDX LTUX TEST"
(See OBJECTIVES, SLG 4:4:4-6: page 1).
- Fulfil an ERROR FREE "TDX LOOP TEST"
(See OBJECTIVES, SLG 4:4:4-6: page 2)
- …0f…During practical exercise.
- During evaluation of the exercise.
- The students must have performed all exercises.
Training room
GW, DI, EX
- Training system with VDUs connected to both of
the MIAs
- M&D TEST DISK PACK and M&D TEST FLOPPY DISKTS.
- LOOP BACK CONNECT. FOR V24 L/L ADAPT.& OPTO T/R
- SLG 4:4:4-6 (2 pages)
- SLM: Section 4.7.2.1.8, 4.7.2.2
- LESSON 4:1:1:OH5-7…0e…
…0e… 2793A/rt
840620
PROGRESS TEST 4:5:1-3 3x45 CAMPS…0f…
Evaluate his own comprehension of subjects taught in
this week.
The result of this test will be recorded in the "STUDENT's
PROGRESS REPORT".
Correction of answers
Classroom
Progress test, duration 60 min.
Progress test, 4 pages (OH1-4, a copy for each student).
6 OHs
- STB I, II & III
- SLM
…0f… 2793A/rt
840620
M&D TDX SYSTEM TEST 4:5:4-6 3x45 CAMPS…0e…
- Fulfil an ERROR FREE "TDX VDU I/O TEST"
(See OBJECTIVES, SLG 4:5:4-6: page 1).
- During practical exercise.
- During evaluation of the exercise.
- The students must have performed all exercises.
Training room
GW, DI, EX
- SLG 4:5:4-6 (2 pages)
- Training system with VDUs connected to both of
the MIAs
- M&D TEST DISK PACK
- M&D TEST FLOPPY DISKETTES
- SLM: Section 4.7.2.1.8, 4.7.2.2
- LESSON 4:1:1:OH5-7
-
2793A/aml 4:5:1-3
830928 1 of 2
PROGRESS TEST WEEK 4
CAMPS
NAME: ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ SCORE: ̲
̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲
1. How many LTUX-S DEVICES can be located in a
TDX CRATE?
2. How is the WATCH DOG connected to the TDX SYSTEM?
3. When does a TDX DEVICE transmit?
4. How can you get information about the TDX system
status? Does this action disturb the normal
function?
5. What does the number 122 in the command
DO TDX ̲VDU ̲IO122 refer to?
6. Can you exchange TDX CONTROLLERS without changing
anything else?
7. How is the TDX SYSTEM connected to the PROCESSOR?
8. What is the 5th line in the UMO indicating?
9. How can you check that an OPTO MODEM is functioning
correctly?
2793A/aml 4:5:1-3
830928
2 of 2
PROGRESS TEST WEEK 4
CAMPS
10. Which TDX DEVICE transmits on the LOWER BUS?
11. What is the BITRATE of the signal on the TDX
BUSSES?
12. What is the function of the WALL OUTLET?
13. What is done to the TDX BUS to prevent reflection?
14. What happens if a DEVICE does not respond to
its
MUX NO.?
15. Does the WALL OUTLET get power from the TDX
BUS?
16. What is the physical structure of a TDX BUS?
17. What happens if a DEVICE makes a transmission
error?
18. What is the purpose of the FLAG in TDX FRAME?
19. How many OPTO MODEMS can be connected to an
ADAPTOR POWER SUPPLY?
20. Is there a TDX CONTROLLER in every TDX CRATE?
2793A/aml
ANSWERS TO PROGRESS TEST WEEK 4 830928
1 of 1
LESSON: 4:5:1-3
CAMPS
1. 2.
2. WATCH DOG is connected by the CCB BUS to BSMX-S.
3. When MUX NO. on LOWER BUS hit DEVICE NO.
4. Connect a VDU set to 30 Baud to TDX CONTROLLER
and type S and CR. No.
5. 1 2 2
LTUX-S No. in TDX CRATE CHANNEL No.
of LTUX-S.
6. Yes.
7. Through STI/TIA module.
8. IO module in PU CRATE, which is the STI module.
9. By doing loop test. A loop is mounted on the
OPTO MODEM.
10. TDX CONTROLLER.
11. 1.8432 MHz.
12. It connects the device to TDX BUS.
13. The twisted pair are terminated by 100 ohm.
14. After 16 scan of MUX TABLE, 3 scan sending
out test
frame and then if no respons the DEVICE is
skiped
on the MUX TABLE.
15. No, from DEVICE.
16. Two sets of twisted pair, each pair shieldet.
17. The DEVICE is asked to retransmit.
18. It indicates the start of a FRAME.
19. 4.
20. No. There is only 2 TDX CONTROLLERs, one per
TDX BUS.
…0e… 2793A/rt
840620
TROUBLESHOOTING 4:5:4-6 3 x 45
CAMPS…0f…
- Isolate and remedy TDX system faults at module
level
- During evaluation of the troubleshooting
Training room
GW, DI, EX
Training System
…0e… 2793A/rt
MT/RST 4:1:1 840620
TDX SYSTEM STRUCTURE L
1…0f…
General TDX: T̲elecommunication D̲ata Ex̲change
A unique element of the CAMPS is the TDX
SYSTEM. In essence, the TDX SYSTEM handles
nearly entire complex of terminals and communication
lines with a minimum attention by the central
processor in increased processor throughput.
The TDX SYSTEM as a hole is a STAND ALONE
SYSTEM taking care of the data communication
between the MAIN MEMORY of the CR80 and the
USER/OPERATOR POSITIONS (PERIPHERALS).
STRUCTURE and OH1-2 STB I, Section 5.
PERFORMANCE
DEVICES OH1-2 TDX DEVICES:
- TDX CONTROLLER (1 per. TDX BUS)
- STI/TIA (1 per. PU)
- LTUX-S (max. 2 per TU)
BSM-X OH1 The BSM-X MODULE is a BUS SWITCHING MODULE
and a MONITORING MODULE.
TDX UNITS OH 3 Max. 15 TDX UNITS (TU) per. TDX SYSTEM.
(TDX UNIT = TDX CRATE)
The BSM-X MODULE is the "HEAD GATE" of the
TU (BSM-X MODULE NO.).
TDX CONTROLLER One TDX CONTROLLER is asssigned to TDX
BUS #
LOCATION 1; the other TDX CONTROLLER is assigned to
TDX Bus # 2. The two TDX CONTROLLERS are
located in TU # 1 and TU # 4 respectively.
ADAPTORS OH3 4 serial V24 I/O CHANNELS per. LTUX-S. LOW
LEVEL ADAPTORS and OPTIC FIBER MODEM for
the I/O CHANNELS ARE located in the FRONT
OH4 MAGAZINE or BP8 BACK PANELS are located in
the REAR MAGAZINE.
BSM-X Connections to the two TDX BUSSES and the
CCB
PANEL via the BSM-X PANEL, which is located in
the REAR MAGAZINE.
…0e… 2793A/rt
MT/RST 4:1:1 840620
TDX SYSTEM STRUCTURE L
2…0f…
TSP The TEMPERATURE SENSOR (ADAPTOR) PANEL is
located in the REAR MAGAZINE.
POWER OH 3 The PS in the FRONT MAGAZINE is used for
the
SUPPLIES …02… POWER to the TDX CONTROLLER, BSM-X MODULE, and LTUX-S
MODULE(s).
OH 3-4 The PS in the REAR MAGAZINE is used for the
POWER to the LOW LEVEL ADAPTORS and OPTIC
FIBER MODEM located in the FRONT MAGAZINE.
DEVICE NO. OH 3 Each TDX DEVICE has a unique DEVICE ADDRESS
(DEVICE ADDR.) (Device No.) in the TDX SYSTEM as follows:
̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲
̲ ̲
Black ^ TDX DEVICE ^ ADDR.AREA
^
Board ^ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲^̲ ̲ ̲ ̲ ̲ ̲(̲H̲E̲X̲.̲ ̲N̲O̲.̲s̲)̲ ̲
̲^̲
^ TDX CONTROLLER ^ [[
^
^ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲^̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲
̲^
^ STI/(TIA) ^ [̲1̲ - [C
^
^ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲^̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲
̲^
^ LTUX-S ^ [D - FE
^
^ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲^̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲
̲^
^ ^ DUMMY ADDR.: FF
^
^ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲^̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲
̲^
OH 5-7 The DEVICE ADDRESSES (DEVICE NO.s) used in
the CAMPS are shown (DECIMAL & HEXADECIMAL)
for the LTUX-S modules in TU NO. 1-9.
…0e… 2793A/rt
MT/RST 4:1:2 840620
TDX BUS COMMUNICATION L
1…0f…
TDX BUSSES OH1 Each TDX BUS consists
of an UPPER BUS (TWISTED
PAIR CABLE) and a LOWER
BUS (TWISTED PAIR CABLE).
The STI/TIA and LTUX-S MODULES t̲r̲a̲n̲s̲m̲i̲t̲ on
the UPPER BUS and r̲e̲c̲e̲i̲v̲e̲ from the LOWER
BUS.
The TDX CONTROLLER r̲e̲c̲e̲i̲v̲e̲s̲ from UPPER BUS
and t̲r̲a̲n̲s̲m̲i̲t̲s̲ on the LOWER BUS.
MUX.TABLE OH1 The MUX. TABLE on the TDX CONTROLLER is a
DEVICE POLLING TABLE, the contents of which
are the DEVICE NO.'s of the TDX SYSTEM.
By the POLLING SEQUENCE these DEVICE NO.s
(named MUX.NO.s) in the row they are set
up will represent, which LTUX-S or STI/TIA
is allowed to transmit DATA.
MASTER OH1 The TDX CONTROLLER contains the MASTER
CLOCK CLOCK GENERATOR of the TDX SYSTEM. The frequency
is 1.8432 MHZ.
SYNCHRONIZATION F̲R̲O̲M̲ ̲C̲O̲N̲T̲R̲O̲L̲L̲E̲R̲:̲
Contineous data stream on lower bus:
1.8432 Mbits/sec divided into 6400 timeslots
of 288 bits.
Black O̲n̲e̲ ̲T̲i̲m̲e̲s̲l̲o̲t̲:̲
Board
HDLC FRAME The HDLC (H̲igh Level D̲ate L̲ink C̲ontrol) frame
length may differ from 200 bits (min) to
236 bits (max) due to "bitstuffing" (or each
five "1"s an extra "0" is inserted). This
is used as an error detection feature.
One HDLC frame contains a total of 25 bytes
of 8 bits:
2 Flag bytes (01111110)
5 Communication Control bytes
16 Data bytes
2 CRC bytes (C̲yclic R̲edundancy C̲heck)
…0e… 2793A/rt
MT/RST 4:1:2 840620
TDX BUS COMMUNICATION L
2…0f…
LOWER BUS OH2 & 4 S̲T̲A̲R̲T̲ ̲F̲l̲a̲g̲ (1 byte)
FRAME FORMAT
M̲U̲X̲.̲N̲O̲.̲ ̲(̲1̲ ̲b̲y̲t̲e̲)̲: The MUX.NO. is a DEVICE
NO., which is generated in the controller
- it is taken from the MUX.TABLE. It indicates
which device is a̲l̲l̲o̲w̲e̲d̲ ̲t̲o̲ ̲t̲r̲a̲n̲s̲m̲i̲t̲ ̲d̲a̲t̲a̲
̲o̲n̲ ̲t̲h̲e̲ ̲u̲p̲p̲e̲r̲ ̲b̲u̲s̲ in the next timeslot. All
devices "look" at the MUX.NO., and the DEVICE
which recognizes its own NO. (= device addr.)
starts the transmission on the upper bus,
when having received bit 241 of the present
timeslot:
C̲R̲-̲I̲D̲ ̲(C̲hannel & R̲outing I̲dentifier)
2 bytes concerning DATA TYPE, HOST/MODE,
and DEVICE NO. as follows.
D̲A̲T̲A̲ ̲T̲Y̲P̲E̲: Identifying v̲i̲r̲t̲u̲a̲l̲ ̲c̲h̲a̲n̲n̲e̲l̲
̲N̲O̲.̲ through which the data must be routed.
It does not necessarily correlate with
f.ex. the (four) physical channels in
a LTUX. It merely points to a specific
application.
Each LTUX-S MODULE is able to separate
10 VIRTUAL CHANNELS as follows:
̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲
̲ ̲ ̲ ̲ ̲ ̲
^ ^
^
Black ^VIRTUAL ^ FUNCTION
^
Board ^C̲H̲A̲N̲N̲E̲L̲ ̲N̲O̲.̲ ̲ ̲ ̲^̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲
̲ ̲ ̲ ̲ ̲ ̲^
^ [ ^ DATAGRAM between LTUX-S and
STI^
^ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲^̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲
̲ ̲ ̲ ̲ ̲ ̲^
^ 1 ^ DATAGRAM to TDX CONTROLLER
^
^ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲^̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲
̲ ̲ ̲ ̲ ̲ ̲^
^ 2-5 ^ 4 physical SERIAL I/O CHANNELS
^
^ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲^̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲
̲ ̲ ̲ ̲ ̲ ̲^
^ 6-9 ^ Not used in CAMPS
^
^ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲^̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲
̲ ̲ ̲ ̲ ̲ ̲^
H̲O̲S̲T̲/̲M̲O̲D̲E̲ ̲&̲ ̲D̲E̲V̲I̲C̲E̲ ̲N̲O̲.̲:̲ Describing the
SOURCE and DESTINATION DEVICES - for
the actual FRAME of DATA.
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MT/RST 4:1:2 840620
TDX BUS COMMUNICATION L
3…0f…
C̲O̲M̲M̲U̲N̲I̲C̲A̲T̲I̲O̲N̲ ̲B̲Y̲T̲E̲:̲ Used for information
in a PACKET transmission (PACKET = one or
more FRAMES between two open VERTUAL CHANNELS
e.g. FIRST/LAST FRAME in a PACKET.
C̲O̲N̲T̲R̲O̲L̲ ̲B̲Y̲T̲E̲: FRAME SEQUENCE NO. and NUMBER
OF DATA BYTES.
F̲R̲A̲M̲E̲ ̲S̲E̲Q̲.̲N̲O̲.̲: In a PACKET transmission
the FRAMES are sequentially numbered (seq.no.).
If the receiving device detects a jump
in seq.no.s, the FRAME is discarded and
retransmission is requested.
N̲U̲M̲B̲E̲R̲ ̲O̲F̲ ̲D̲A̲T̲A̲ ̲B̲Y̲T̲E̲S̲: The actual number
of data bytes (max.16) in the frame.
^ COMMUNICATION BYTE ^ CONTROL
BYTE ^
PART OF Black ^ ^ FRAME
NUMBER OF ^
FRAME board: ̲ ̲^̲ ̲M̲S̲B̲ ̲ ̲ ̲ ̲ ̲ ̲^̲ ̲ ̲ ̲ ̲ ̲ ̲L̲S̲B̲ ̲^̲ ̲S̲E̲Q̲.̲N̲O̲.̲
̲^̲ ̲D̲A̲T̲A̲B̲Y̲T̲E̲S̲ ̲^̲ ̲ ̲
^ ^ ^ ^
^
̲ ̲^̲ ̲ ̲S̲^̲S̲^̲S̲^̲S̲ ̲^̲ ̲S̲^̲S̲^̲S̲^̲S̲ ̲ ̲^̲ ̲Z̲^̲Z̲^̲Z̲ ̲
̲ ̲^̲ ̲W̲^̲W̲^̲W̲^̲W̲^̲W̲ ̲^̲ ̲ ̲
^ ^ ^ ^
^
^ACK/NACK ^ ^FRAME NO.^[[=NO
BYTES^
^ + ^ ^IN THE
^[1-1[…0f…HEX…0e…
^
^FLOW ^ ^PACKET ^=1-16
BYTES^
^CONTROL ^ ^ ^
^
^(RETURN TO^ ^ ^
^
^SENDER ^ ^ ^
^
^"PIGGY- ^ ^ ^
^
^BACK") ^ ^ ^
^
^ 1 X 0 1 : FIRST FRAME
in PACKET
^ 1 X 1 0 : LAST FRAME
in PACKET
^ 1 X 1 1 : FIRST and
LAST FRAME
^ (A PACKET
with 1 FRAME)
^ X 1 X X : Between
FIRST and
LAST FRAME
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MT/RST 4:1:2 840620
TDX BUS COMMUNICATION L
4…0f…
UPPER BUS OH3 & 4 A̲B̲O̲R̲T̲ ̲B̲Y̲T̲E̲: Dummy byte. No MUX NO. in upper
FRAME FORMAT bus frames because all the frames are t̲o̲
̲t̲h̲e̲ ̲T̲D̲X̲ ̲C̲T̲R̲L̲,̲ and the MUX.NO. is generated
in the TDX CTRL.
The rest of the frame is equal to the lower
bus frame format.
COMMUNICATION O̲N̲E̲ ̲C̲Y̲C̲L̲E̲: The TDX CTRL outputs a frame on
the LOWER bus. M̲U̲X̲.̲N̲O̲.̲ indicates the device,
which is allowed to transmit on the upper
bus. All devices "look" at the M̲U̲X̲.̲N̲O̲.̲ and
the C̲R̲-̲I̲D̲. The device which recognizes its
addr. in the HOST/MODE or DEV. NO. fetches
the frame.
Only the TDX CTRL receives the frame on the
upper bus.
If the HOST/MODE is [ the controller fetches
the frame (This might be a request for change
of bandwidth from a device) and transmits
a dummy frame on the lower bus (f.ex. diagnostic
frame). Change of BANDWIDTH is not used in
CAMPS.
Whenever the frame is n̲o̲t̲ destined for the
TDX CTRL, a MUX.NO. is inserted and the frame
is - without any further change - transmitted
on the lower bus in the next time slot.
DEVICE The MUX.NO. is fetched from the MUX.table
in
POLLING the TDX CTRL. A device allocated a higher
bandwidth on the bus is represented more
frequently in the table than lower bandwidth
devices.
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MT/RST 4:1:3 840620
TDX PROTOCOL, BW & CODEFORMAT L
1…0f…
PROTOCOL Black 3̲ ̲P̲r̲o̲t̲o̲c̲o̲l̲ ̲L̲e̲v̲e̲l̲s̲:̲
board
1: Physical level - Frame level All TDX
2: Link level - Packet level DEVICES
3: Network level - LDU level (only via HOST)
- APPLICATION level
(LTUX-S)
(LDU = LOGICAL DATA UNIT (HBK,section 8.2.2))
LEVEL 1 Transmission of f̲r̲a̲m̲e̲s̲ between TDX DEVICES:
- The FRONT END part of a TDX DEVICE performs
(for each frame): Bit stuffing, CRC byte
generation, ABORT and FLAG byte insertion,
parallel/serial conversion, and SPL-D
coding.
- Bus drivers transmit on the UPPER BUS.
- Bus receivers in the TDX CONTROLLER then
transfer the frame to the MPCC which,
decodes SPL-D, converts serial/parallel,
removes ABORT and FLAG, deletes bit (stuffing),
checks CRC, reads DEV. NO., and inserts
MUX. NO., bitstuffing, CRC byte, flags,
par./ser. conv., SPL-D coding with internal
clock.
- Bus drivers transmit on the LOWER BUS.
- The TDX DEVICES receive and perform SPL-D
decoding, ser./par. conversion, bitstuff
deletions, flags removal, CRC check, reads
MUX. NO. and DEV. NO. The DEVICE which
recognizes the MUX. NO. is allowed to
transmit on the UPPER BUS. The DEVICE
which recogn. DEV. NO. transfers the frame
to the link level.
LEVEL 2 Transferred data packets are chopped into
HDLC frames. The firmware in the TDX DEVICE
performs the frame EN/DE-capsulation and
the error detection and correction on packet
level.
4:1:2 A packet is one or more frames transferred
page 3 between two devices. Any DEVICE which has
received a packet must return ACK/NACK.
Frames are received errorfree from LEVEL
1 and accumulated into packets at LEVEL 2.
The first and the last frame in a packet
is indicated in the COMMUNICATION byte. The
bytecount and the continous frame count is
detected in the CONTROL BYTE (SEQ. NO. +
NUMBER OF DATA BYTES). Any errors detected
results in rejection of the packet and request
for a retransmission by returning NACK.
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MT/RST 4:1:3 840620
TDX PROTOCOL, BW & CODE FORMAT L
2…0f…
LEVEL 3 At LEVEL 3 the Ingoing Packets are routed
through VIRTUAL CHANNELS to the application
routines in LTUX-S and the TDX HANDLER in
the HOST INTERFACE (STI).
CHANNELS 4:1:2 A VIRTUAL CHANNEL for a LTUX-S (10 channels)
OH 4 is identified in the DATA TYPE nibble (4
bits) of the frame.
A VIRTUAL CHANNEL for a HOST I/F is a combination
of the DATA TYPE and DEV. NO. (12 bits =
4096 channels).
VIRTUAL CHANNEL 0 and 1 are used entirely
for datagram messages such as diagnostics
and commands to OPEN and CLOSE channels.
An O̲P̲E̲N̲ channel is a channel with information
at LEVEL 3 about the REMOTE CHANNEL (= CR
ID).
Transfer of data can take place between any
two channels when opened.
The TDX handler opens and closes (creates
and dismantles loglines) the channels through
which datastreams may flow. Such is performed
at LEVEL 3.
The HOST INTERFACE transfers data in LOGICAL
DATA UNITS (LDUs) which are a number of datapackets.
At LEVEL 3 the LDUs are chopped into packets.
Retransmission may be requested for frames
or packets, not for LDUs.
BANDWIDTH As one frame on the TDX BUS transfers max.
(BW) 128 data bits (16 bytes x 8 bits) and a transfer
from a DEVICE only occurs when the DEVICE
NO. equals the MUX NO., then the bandwidth
of a DEVICE is directly related to the frequence
of the MUX NO.
…0e… 2793A/rt
MT/RST 4:1:3 840620
TDX PROTOCOL, BW & CODE FORMAT L
3…0f…
All the DEVICES in a specific system configuration
are allocated a certain BW which is preprogrammed
in the MUX table of the TDX CONTROLLER firmware
(PROM). The MUX. NO. of a high BW device
is written more frequently than a MUX. NO.
of a low BW device.
QUESTION What is the max. BW (theoretically) of the
TDX BUS?
ANSWER 16 data bytes x 8 bits x 6400 time slots/sec
= 819200 baud
BANDWIDTH OH 1 Only MUX. NO.s for DEVICES appended to the
ALLOCATION bus (status READY) will be inserted in the
lower bus frames.
The bandwidth allocated to each device
in the TDX system is determined by the MUX-table.
This table is configured as shwon on OH 1
with 14 speed levels. (HBK, Section 8.2.2.1)
Each time a frame is transmitted on the lower
bus, a device-address is read from the MUX-table
in the location given by the "pointer to
next ADD" and used as MUX-No. The "pointer
to next ADD" is updated to the next "ADD",
which is either the next in the chain or
- in case it was the last "ADD" in the speed
level chain - one of two possibilities:
Either the first "ADD" in the highest speed
level or the first "ADD" in the next lower
speed level.
This depends on the state of the FF, which
is complemented by each test.
The MUX-table shown on OH 1 will give following
bandwidth-allocation (please notice that
not used speed levels are not encountered).
…0e… 2793A/rt
MT/RST 4:1:3 840620
TDX PROTOCOL, BW & CODEFORMAT L
4…0f…
BLACK AB - ABC - AB - ABCD - AB - ABC - AB - ABCDEFG
BOARD AB - ABC - AB - ABCD - AB - ABC - AB - ABCDEFGH
AB - ABC - AB - ABCD - AB - ABC - AB - ABCDEFG
AB - ABC - AB - ABCD - AB - ABC - AB -
ABCDEFGHI (DUMMY)
This gives a relative bandwidth on following:
BLACK A̲d̲d̲r̲e̲s̲s̲ R̲e̲l̲a̲t̲i̲v̲e̲ ̲B̲a̲n̲d̲w̲i̲d̲t̲h̲
BOARD
A, B 32
C 16
D 8
E, F, G 4
H 2
I, DUMMY 1
This entire cyclus is repeated continuously
and is called a scancyclus.
DECODER, On the TDX CONTR., on the LTUX-S, and on
the
ENCODER STI/T̲I̲A̲ a DECODER and an ENCODER is build
and in.
SPL-D CODE
OH2 When the above mentioned TDX DEVICE t̲r̲a̲n̲s̲m̲i̲t̲
on the TDX BUS, then the ENCODER will CODE
the OUTGOING bits with the CLOCK SIGNAL (1.8432
MHz) in a so-called SPL-D CODE (self clocking
differential split phase code).
When receiving from the TDX BUS the DECODER
will SEPARATE the SPL-DS CODE in Bits and
Clock Pulses.
The TDX CONTR. contains the TDX SYSTEM CLOCK
GENERATOR (1.8432 MHz).
The Clock Pulses used by the LTUX-S and TIA,
when transmitting, are derived from the respective
DECODER LOGIC.
In this way MESSAGE HANDLING in the TDX SYSTEM
is SYNCHRONIZED.
…0e… 2793A/rt
MT/RST 4:1:4-6 840620
…0f…DEMONSTRATION of the
TDX SYSTEM, SLM, and HWB…0e… DE, I, DI
1…0f…
TDX UNITS Show all the TDX UNITS related to the TDX
UNIT "NO.s".
TDX BUSSES Show the location of the two TDX CONTROLLERS.
Follow the cable from the "TDX BUS" Connector
on the Front Panel of the TDX CONTROLLER
to the respective WALL OUTLET and then follow
the TDX BUS from TDX UNIT to TDX UNIT and
PU.
Explain the relation between the BSM-X "MODULE
NO.s" and TDX UNIT "NO.s".
TDX DEVICES Show the location of the LTUX-S modules and
the STI/TIA modules.
Explain the relation between the LTUX-S "DEVICE
NO.s" and the TDX UNIT "NO.s".
Take out a LTUX-S module from a TDX CRATE
and show a DIP SWITCH.
NOTE! - Always POWER OFF when removing or
inserting MODULES in TDX CRATES.
ADAPTORS Show the location of L/L ADAPTOR, OPTO T/R,
& PANELS BP8, TSP and BSM-X PANEL and explain the
relation to other TDX modules, BUSSES and
PERIPHERALS.
PS Show the location of the PS and explain the
application of PS in front magazines and
PS in rear magazines.
PORT ID Go to the SUPERVISOR POSITION and SIGN ON
to ENGINEERING FUNCTION. Perform the command
"PCON" and print out "ALL" the configuration
list of the TDX SYSTEM DEVICES and PERIPHERALS.
4:1:1 Explain the relation between the LINE PORT
ID
OH5-7 and the corresponding LTUX-S, ADAPTOR, BP8,
I/O CHANNEL (LINE), and PERIPHERALS.
SLM SLM Introduce SLM: Section 4.5.4
INTRODUCT. Section 4.5.5
Section 4.7.2.1.8
Section 4.7.2.2
HWB HWB Introduce HWB: Section 3
INTRODUCT.
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MT/RST 4:2:1-2 840620
TDX CONTROLLER L
1…0f…
M̲O̲D̲U̲L̲E̲ ̲ OH1 The TDX CONTROLLER
for the TDX BUS #1
is
L̲O̲C̲A̲T̲I̲O̲N̲ placed in TDX UNIT No. 1, FRONT SLOT No.
1
The TDX CONTROLLER for the TDX BUS #2 is
placed in TDX UNIT No. 4, FRONT SLOT No.
1.
P̲E̲R̲F̲O̲R̲M̲A̲N̲C̲E̲ CONTROLS and SYNCHRONIZES the DATA- COMMUNICATION
between the STI MODULE in the PROCESSOR UNIT
(PU) and the LTUX-S MODULES in the TDX UNITS
(TU).
The CONTROL of the DATA COMMUNICATION is
performed according to a predefinded MUX.
TABLE in the TDX CONTROLLER.
How often a certain DEVICE (LTUX-S or STI
MODULE) is allowed to send MESSAGES on the
TDX BUS is called BANDWIDTH. The BANDWIDTH
depends on how often the DEVICE No. is represented
in the MUX. TABLE SCAN SEQUENCE.
The SYNCHRONIZING of the DATA COMMUNICATION
by the TDX CONTROLLER is due to a continious
BIT STREAM of 1.8432 Mbit/sec. which the
TDX CONTROLLER clocks and synchronizes on
the LOWER TDX BUS. This BIT STREAM is divided
into 6400 TIME SLOTS of 288 bits each. In
each TIME SLOT a DATA MESSAGE or a DUMMY
MESSAGE can be transmitted.
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MT/RST 4:2:1-2 840620
TDX CONTROLLER L
2…0f…
OH1 MESSAGE FORMAT, CODE FORMAT, and DATA COMMUNICATION.
(See Lesson 4:1:2 & 4:1:3).
Because of a REDUNDANT SYSTEM two TDX CONTROLLERS
are incorporated. The AUTOMATICALLY ENABLING
of one of these TDX CONTROLLERS and the DISABLING
of the other one is performed by the WATCH
DOG according to the STATUS of the TDX CONTROLLERS,
and the STATUS of the PROCESSOR UNITS.
B̲L̲O̲C̲K̲ ̲D̲I̲A̲G̲R̲A̲M̲ OH2 The TDX BLOCK DIAGRAM described as follows:
RS-422 The DATA and CONTROL LINES from/to the
RECEIVER/DRIVER TDX BUS are differential lines in accordance
with the RS-422 recommendations.
ENCODER & DECODER The DATA and the 1.8432 MHz CLOCK are transmitted
simultaniously on the LOWER BUS a in so-called
SPL-D CODE.
The ENCODER LOGIC codes the OUTGOING SERIAL
DATA with the CLOCK.
The DECODER LOGIC will decode the DATA STREAM
being RECEIVED, that means separating the
SPL-D CODE in the DATA and the CLOCK.
The advantages of the SPL-D CODE are:
- SOURCE and DESTINATION are SYNCRONIZED
- Correct decoding in spite of delay in
cable
The TDX CONTROLLER TRANSMITS on the LOWER
BUS and RECEIVES on the UPPER BUS. Each
BUS consists of a TWISTED PAIR CABLE. UPPER
BUS + LOWER BUS = TDX BUS.
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MT/RST 4:2:1-2 840620
TDX CONTROLLER L
3…0f…
MPCC OH2 M̲ULTI P̲ROTOCOL C̲OMMUNICATION C̲ONTROLLER
On RECEIVED HDLC FRAMES the MPCC performs:
- Deletion of ABORT byte and FLAG bytes
- Deletion of ZEROES from the BITSTUFFING
- CYCLIC REDUNDANCY CHECK (CRC)
- SERIAL to PARALLEL conversion of each
byte
When TRANSMITTING HDLC FRAMES the MPCC performs:
- PARALLEL to SERIAL conversion of each
byte
- BITSTUFFING (Insertion of ZEROES)
- CRC byte generation
- FLAGE bytes insertion
STATE This functional block CONTROLS the ROUTING
CONTROLLER of the HDLC FRAMES in the DATA BUFFER. The
LOGIC STATE CONTROLLER LOGIC also CONTROLS the
MPCC functions.
DATA BUFFER F̲IRST I̲N F̲IRST O̲UT registers.
4 FIFO registers are available for ROUTING
the HDLC FRAMES. The CHANNEL ROUTING IDENTIFIER
(CR-ID) in the HDLC FRAMES contents the INFORMATION
of DESTINATION of the respective FRAMES.
If the FRAME is destined for the TDX CONTROLLER
itself ("HOST NO. = [["), the DATA INFORMATION
will be used informally by the CPU. If the
"HOST NO." in the received FRAME is n̲o̲t̲ equal
to "[[", a MUX. NO. will be inserted in the
FRAME and the FRAME will be transmitted to
the DEVICE which is IDENTIFIED in the CR-ID.
…0e… 2793A/rt
MT/RST 4:2:1-2 840620
TDX CONTROLLER L
4…0f…
CPU/MEMORY OH2 The CPU is a standard Z80 microprocessor.
Together with the MEMORY and part of the
DATA BUFFER, the CPU constitutes the MICRO
COMPUTER PART of the TDX CONTROLLER. It
handles the MUX. TABLE and diagnostics the
communication.
USART U̲NIVERSAL S̲YNCHRONOUS A̲SYNCHRONOUS R̲ECEIVER
T̲RANSMITTER
The USART handles the SERIAL COMMUNICATION
to/from a TEST TERMINAL (VDU) via the 24V
DRIVERS/RECEIVERS.
The BAUD RATE is 300 BAUD.
V24 RECEIVERS Standard V24 RECEIVERS/DRIVERS are
/DRIVERS associated the USART ports to obtain a standardized
connection to the TEST TERMINAL (VDU).
WATCH DOG The WATCH DOG LOGIC is MONITORING the TDX
LOGIC CONTROLLER STATUS and the STATUS of the POWER
supplied to the WALL OUTLETS.
The LOGIC is equipped with 5 drivers and
3 receivers for SIGNAL EXCHANGE through the
"WATCH DOG" connector via the BSM-X and the
CONFIGURATION CONTROL BUS to the WATCH DOG
PROCESSOR UNIT.
CLOCK This circuit consists of a 1.8432 Mhz
GENERATOR oscillator. The CLOCK PULSES are used in
the ENCODER logic where the SERIAL DATA is
coded with the CLOCK (SPL-D code) and transmitted
on the LOWER BUS.
…0e… 2793A/rt
MT/RST 4:2:1-2 840620
TDX CONTROLLER L
5…0f…
F̲R̲O̲N̲T̲ ̲P̲A̲N̲E̲L̲ OH2 Five LEDS are available in the FRONT PANEL.
L̲E̲D̲S̲
"POWER" LED If all the 3 SUPPLIES (+ 5V, + 12V, - 12V)
(green) are present the LED will be illuminated.
"TEST" LED During the execution of the BUILD-IN TEST
(red) (BIT) the "TEST" LED will be illuminated
for a few seconds.
When the BUILD-IN TEST is fulfilled successfully
(no error) the "TEST" LED will be extinguished.
If the BUILD-IN TEST detects an ERROR the
"TEST" LED will show SLOW FLASH.
"REC.ST." LED When the TDX CONTROLLER STATUS is "UPPER
(yellow) BUS#1̲ SELECTED" the LED will be illuminated.
On the other hand when the TDX CONTROLLER
STATUS is "UPPER BUS #2̲ SELECTED" the LED
will be extinguished. However, in the CAMPS
a TDX CONTROLLER is used for each of the
two TDX BUSSES. The UPPER BUS #1 is connected
to both RECEIVER CHANNELS on one of the TDX
CONTROLLERS and the UPPER BUS #2 is connected
to both RECEIVER CHANNELS on the other TDX
CONTROLLER. Therefore, the LED is insignificant
in the CAMPS.
…0e… 2793A/rt
4:2:1-2
840620
MT/RST
TDX CONTROLLER L
6…0f…
"TR.ST." LED ERROR detected in the TRANSMITTED SPL-D code
(red) will cause the "TR.ST." LED to be illuminated.
"FUSE" LED ERROR in one or both of the SUPPLIES
(red) (V…0f…cc…0e…1, V…0f…cc…0e…2) or in the FUSES for the associated
WALL OUTLET will cause the "FUSE" LED to
be illuminated.
F̲R̲O̲N̲T̲ ̲P̲A̲N̲E̲L̲ OH2 NONE!
S̲W̲I̲T̲C̲H̲E̲S̲
F̲R̲O̲N̲T̲ ̲P̲A̲N̲E̲L̲ OH2 A BNC connector and two 25 pin connectors
C̲O̲N̲N̲E̲C̲T̲I̲O̲N̲S̲ are available in the FRONT PANEL.
The BNC connector named "EXT. CLK" is used
for EXTERNAL 1.8432 MHz CLOCK SIGNAL.
OH2 The 25 pin connector named "TDX BUS" is used
OH3 for the connection of the TDX CONTROLLER
to the respective TDX BUS via WALL OUTLET.
OH2 The 25 pin connector named "WATCH DOG" is
OH4 used for the connection of the TDX
OH5 CONTROLLER to the WATCH DOG via the 25 pin
connector on the BSM-X and further on through
the CONFIGURATION CONTROL BUS.
OH2 As another application it is possible to
OH4 connect a TEST TERMINAL (VDU) to the "WATCH
DOG" connector for TDX SYSTEM STATUS TEST.
…0e… 2793A/rt
MT/RST 4:2:1-2
840620
TDX CONTROLLER L
7…0f…
B̲A̲C̲K̲ ̲P̲L̲A̲N̲E̲ ̲ OH2 The PIN LAY OUT of the BACK PLANE CONNECTION
C̲O̲N̲N̲E̲C̲T̲I̲O̲N̲S̲ OH6 to the TDX CONTROLLER is shown on OH6.
This connection is used for the POWER SUPPLY
(+5V, +12V, -12V).
S̲E̲T̲ ̲U̲P̲ OH2 The DEVICE ADDRESS of the TDX CONTROLLER
OH7 identifies a unique DEVICE No. in the TDX
SYSTEM.
The ADDRESS SETTING is a FIXED SET UP
(DIP SWITCH "S1" not used).
TDX CONTROLLER DEVICE ADDRESS = [[ (always).
The STRAPS SETTINGS provide the APPLICATION
of the TDX CONTROLLER to a UNIQUE PERFORMANCE.
CAMPS APPLICATION is shown on OH7.
B̲U̲I̲L̲D̲-̲I̲N̲ ̲T̲E̲S̲T̲ CHECK SUM TEST in EPROM.
READ/WRITE TEST in RAM.
…0e… 2793A/rt
MT/RST 4:2:1-2
840620
TDX CONTROLLER L
8…0f…
S̲W̲I̲T̲C̲H̲ ̲S̲E̲T̲T̲I̲N̲G̲
NONE!
The DEVICE ADDRESS is FIXED
SET UP = [[
S̲T̲R̲A̲P̲S̲ ̲S̲E̲T̲T̲I̲N̲G̲S̲
̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲
̲ ̲ ̲
^ ^ ^ ^ ^ ^ ^ ^ ^ ^
^
^ ̲P̲I̲N̲ ̲B̲L̲O̲C̲K̲ ̲N̲O̲.̲ ̲ ̲^̲ ̲2̲ ̲^̲ ̲3̲ ̲^̲ ̲4̲ ̲^̲ ̲5̲ ̲^̲ ̲6̲ ̲^̲ ̲7̲ ̲^̲ ̲8̲ ̲^̲ ̲9̲ ̲^̲
̲1̲0̲^
^ ^ ^ ^ ^ ^ ^ ^ ^ ^
^
^ ̲S̲T̲R̲A̲P̲ ̲L̲O̲C̲A̲T̲I̲O̲N̲ ̲^̲ ̲A̲ ̲^̲ ̲B̲ ̲^̲ ̲B̲ ̲^̲ ̲C̲ ̲^̲ ̲B̲ ̲^̲ ̲B̲ ̲^̲ ̲C̲ ̲^̲ ̲B̲ ̲^̲
̲B̲ ̲^
̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲
̲ ̲ ̲
^ ^ ^ ^ ^ ^ ^ ^ ^ ^
^
^ ̲P̲I̲N̲ ̲B̲L̲O̲C̲K̲ ̲N̲O̲.̲ ̲ ̲^̲ ̲1̲1̲^̲ ̲1̲2̲^̲ ̲1̲3̲^̲ ̲1̲4̲^̲ ̲1̲5̲^̲ ̲1̲6̲^̲ ̲1̲7̲^̲ ̲1̲8̲^̲
̲1̲9̲^
^ ^ ^ ^ ^ ^ ^ ^ ^ ^
^
^ ̲S̲T̲R̲A̲P̲ ̲L̲O̲C̲A̲T̲I̲O̲N̲ ̲^̲ ̲A̲ ̲^̲ ̲A̲ ̲^̲ ̲B̲ ̲^̲ ̲B̲ ̲^̲ ̲A̲ ̲^̲ ̲A̲ ̲^̲ ̲B̲ ̲^̲ ̲B̲ ̲^̲
̲B̲ ̲^
2793A/rt
WATCH DOG SIGNALS 4:2:1-2
5
TDX CONTROLLER/BSM-X
(TDX CONTR. BSM-X)
̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲
̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲
RS : UPPER TDX BUS # 1 CONNECTED = "0"
UPPER TDX BUS # 2 CONNECTED = "1"
("REC.ST" LED of the TDX-CONTR.)
̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲
̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲
TS : TDX CLOCK
MISSING = "0" / OK = "1"
("TR.ST" LED of the TDX-CONTR:)
̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲
̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲
FS : FUSES to the WALL OUTLET
OK = "1", NOT OK = "0"
("FUSE" LED of the TDX-CONTR.)
̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲
̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲
BS : BUS SELECT
WALL OUTLET # 1 = "0"
WALL OUTLET # 2 = "1"
̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲
̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲
COMI 1: Not used!
̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲
̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲
COMI 2: RECEIVER on the TDX-CONTR.
ENABLE = "0" / DISABLE = "1"
̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲
̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲
(CO1) COMO 1: TDX-CONTR. BUILD-IN TEST (BIT)
EXECUTING = "0" / FINISHED = "1"
(NO ERROR)
̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲
̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲
(CO2) COMO 2: TDX-CONTR. ON-LINE DIAGNOSTIC
OK = "0" / DOWN = "1"
̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲
̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲
CC : TDX-CONTR. FUNCTIONALLY CONNECTED
to the TDX-BUS = "0"
TDX-CONTR. FUNCTIONALLY DISCONNECTED
to the TDX-BUS = "1"
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MT/RST 4:2:3
840620
HOST I/F (STI/TIA) L
1…0f…
S̲T̲I̲ ̲M̲O̲D̲U̲L̲E̲ ̲ OH1 In every PROCESSOR UNIT (PU) in FRONT SLOT
L̲O̲C̲A̲T̲I̲O̲N̲ No. 18.
P̲E̲R̲F̲O̲R̲M̲A̲N̲C̲E̲ The STI MODULE is an INTELLIGENT INTERFACE
MODULE associated the TDX SYSTEM for the
COMMUNICATION between the CR80 COMPUTER and
one TDX BUS via the TELECOMMUNICATION INTERFACE
ADAPTOR MODULE (TIA).
The MAIN PERFORMANCES of the STI MODULE are
as follows:
- Responds to CR80 access to the STI MODULE
- CONTROL of the CR80 access to the STI
MODULE
- DIRECT MEMORY ACCESS (DMA) transfer from
CR80 MAIN MEMORY to TIA MEMORY and vice
versa
- Establishes VIRTUAL CHANNELS for COMMUNICATION
between STI MODULE and LTUX-S MODULES
- Serves the TDX PACKET PROTOCOL
- HIGH BANDWIDTH
- Connection to the CR80 CHANNEL BUS via
BACK PLANE MOTHERBOARD and connection
to the TIA MODULE via a FLAT CABLE
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MT/RST 4:2:3
840620
HOST I/F (STI/TIA) L
2…0f…
S̲T̲I̲ ̲M̲O̲D̲U̲L̲E̲ ̲ OH2 STI BLOCK DIAGRAM described as follows:
B̲L̲O̲C̲K̲ ̲D̲I̲A̲G̲R̲A̲M̲
M̲B̲I̲F̲: M̲AIN B̲US I̲NTERF̲ACE.
The MBIF provides the connection between
the CR80 MAIN BUS and the internal HI-BUS.
This functionally block contains a HIGH SPEED
BIT SLICE MICROPROCESSOR and a DMA CONTROLLER.
It performs the functions as follows:
- Provides the access from the CR80 to the
CENTRAL RAM.
- DIRECT MEMORY ACCESS (DMA) from the CR80
MAIN MEMORY to the TIA MEMORY and vice
versa.
- Derives the HI-BUS CLOCK from the CR80
MAIN BUS CLOCK.
- Exchanges INTERRUPTS between INGOING PROCESSOR,
OUTGOING PROCESSOR, and CR80.
- Supervises the three POWER SOURCES (+5V,
+12V, -12V).
- Displays STATUS of the STI MODULE.
INGOING INGOING DATA is data from TIA MODULE to CR80
PROCESSOR
The PROCESSOR is a standard ZILOG 80 MICRO
PROCESSOR containing the TDX PACKET PROTOCOL
TASK for the INGOING HDLC FRAMES.
The INGOING PROCESSOR also SETS UP the PARAMETERS
(SOURCE and DESTINATION) used by the MBIF
for the DMA DATA TRANSFER from the SHARED
MEMORY on the TIA MODULE to the CR80 MAIN
MEMORY.
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MT/RST 4:2:3
840620
HOST I/F (STI/TIA) L
3…0f…
S̲T̲I̲
OUTGOING OH2 OUTGOING DATA is data from CR80 to TIA
PROCESSOR MODULE.
The PROCESSOR is a standard ZILOG 80 MICRO
PROCESSOR containing the TDX PACKET PROTOCOL
TASK for the OUTGOING HDLC FRAMES.
The OUTGOING PROCESSOR also SETS UP the PARAMETER
(SOURCE and DESTINATION) used by the MBIF
for the DMA DATA TRANSFER from the CR80 MAIN
MEMORY to the SHARED MEMORY on the TIA MODULE.
CENTRAL RAM The CENTRAL RAM is a 32K BYTE RAM which is
accessed via the HOST INTERFACE BUS (HI-BUS).
It contains INFORMATION about the DMA ADDRESSES.
HI-BUS ARBITOR This functional block directs the access
to the HI-BUS where the INTERNAL DATA
TRANSFER as well as the DATA TRANSFER
between the CR80 CHANNEL BUS and the STI
MODULE are routed.
F̲R̲O̲N̲T̲ ̲P̲A̲N̲E̲L̲ ̲ OH2 Eight LEDs are available in the FRONT PANEL.
L̲E̲D̲S̲
"POWER" LED When all the three supplies (+5V, +12V,
(green) -12V) are present, the LED will be illuminated.
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MT/RST 4:2:3
840620
HOST I/F (STI/TIA) L
4…0f…
S̲T̲I̲
"TEST" LED O̲H̲2̲ During the execution of the BUILD-IN TEST
(red) (BIT), the "TEST" LED will be illuminated
for a few seconds.
When the BUILD-IN TEST is fulfilled successfully
(no error), the "TEST" LED will be extinguished.
If the BUILD-IN TEST detects an ERROR, the
"TEST" LED will show CONSTANT LIGHT.
"BUSY" LED During a DIRECT MEMORY ACCESS (DMA)transfer
(yellow) on the MAIN BUS, the "BUSY" LED will be illuminated.
"H.I. DMA" During a DIRECT MEMORY ACCESS (DMA) transfer
(yellow) on the internal HI-BUS, the "H.I. DMA" LED
will be illuminated.
"P.ERROR" LED If a drop in the SUPPLIES (+5V, +12V,
-12V)
(red) has occurred since the latest MASTER CLEAR,
the "P.ERROR" LED will be illuminated to
indicate an intermediate POWER ERROR.
"C.ERROR" LED If TIME-OUT or PARITY ERROR has been detected
(red) during a DMA transfer on the MAIN BUS, the
"C.ERROR" LED will be illuminated.
"M.ERROR" LED If TIME-OUT or PARITY ERROR has been detected
(red) during a DMA transfer on the internal HI-BUS,
the "M.ERROR" LED will be illuminated.
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MT/RST 4:2:3
840620
HOST I/F (STI/TIA) L
5…0f…
S̲T̲I̲
"RX.STATE" LED OH2 When the STI MODULE
via the TIA MODULE
does
(yellow) n̲o̲t̲ receive the 1.8432 MHz SYNCHRONIZATION
CLOCK from the SPL-D CODE, the "RX.STATE"
LED will be illuminated.
F̲R̲O̲N̲T̲ ̲P̲A̲N̲E̲L̲ OH2 NONE!
S̲W̲I̲T̲C̲H̲E̲S̲
F̲R̲O̲N̲T̲ ̲P̲A̲N̲E̲L̲ OH2 NONE!
C̲O̲N̲N̲E̲C̲T̲I̲O̲N̲S̲
B̲A̲C̲K̲ ̲P̲L̲A̲N̲E̲ OH2 The UPPER CONNECTOR (P1) is used for the
C̲O̲N̲N̲E̲C̲T̲I̲O̲N̲S̲ POWER SUPPLY only (equal to the POWER CONNECTION
on the MIDDLE CONNECTOR).
OH2 The MIDDLE CONNECTOR (P2) performs the
OH3 connection to the CR80 CHANNEL BUS.
OH2 The LOWER CONNECTOR (P3) performs the
OH4 connection to the TIA MODULE via a FLAT CABLE.
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MT/RST 4:2:3
840620
HOST I/F (STI/TIA) L
6…0f…
S̲T̲I̲ ̲S̲E̲T̲ ̲U̲P̲ OH2 Two DIP SWITCHES are available on the STI
OH5 MODULE:
- DIP SWITCH "S1" DEVICE ADDRESS
(DEVICE NO. in the
TDX SYSTEM)
- DIP SWITCH "S2" I/O ADDRESS
(MODULE ADDRESS
seen from the CR80)
The DEVICE ADDRESS of the STI MODULE identifies
a unique DEVICE NO. in the TDX SYSTEM. It
is SET UP by means of the DIP SWITCH named
"S1".
NOTE! The "S1" SET UP is ignored by the
CAMPS APPLICATION SOFTWARE.
The INPUT/OUTPUT ADDRESS seen from the CR80
COMPUTER is SET UP by means of the DIP SWITCH
named "S2".
By using the DAMU UNIT MAPPING COMMAND "UM"
it is possible to check, if the "S2" SWITCH
SETTING is correct.
The STRAPS SETTINGS provide the APPLICATION
of the STI MODULE to a UNIQUE PERFORMANCE.
CAMPS APPLICATION is shown on OH5.
B̲U̲I̲L̲D̲-̲I̲N̲ INITIALIZATION to the TIA MODULE.
T̲E̲S̲T̲
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MT/RST 4:2:3
840620
HOST I/F (STI/TIA) L
7…0f…
T̲I̲A̲ OH6 In every PROCESSOR UNIT (PU) in REAR SLOT
M̲O̲D̲U̲L̲E̲ ̲L̲O̲C̲A̲T̲I̲O̲N̲ No. 16.
PERFORMANCE The TIA MODULE is an INTELLIGENT FRONT END
MODULE with the application as a SLAVE MODULE
to the STI MODULE. The data exchanges between
the STI MODULE and the TDX BUS passes via
an onboard SHARED MEMORY (RAM), shared by
the TIA MODULE and the STI MODULE.
The MAIN PERFORMANCES of the TIA MODULE are
as follows:
- DECODING and ENCODING of the SPL-D CODE
by which the DATA STREAM is transferred
on the TDX BUS.
- SERIAL/PARALLEL and PARALLEL/SERIAL conversion
of the DATA STREAM.
- Serves the HDLC FRAME CHECK.
- Routes the DATA to and from the onboard
SHARED MEMORY (RAM).
The HDLC FRAMES are RECEIVED from the LOWER
BUS and TRANSMITTED to the UPPER BUS. The
connection to the TDX BUS is obtained through
a 25 pins connector in the FRONT PANEL of
the TIA MODULE via WALL OUTLET.
Connection to the STI MODULE is performed
by a FLAT CABLE via a BACK PANEL CONNECTOR.
…0e… 2793A/rt
MT/RST 4:2:3 840620
HOST I/F (STI/TIA) L
8…0f…
T̲I̲A̲ OH7 The BLOCK DIAGRAM of the TIA MODULE
B̲L̲O̲C̲K̲ ̲D̲I̲A̲G̲R̲A̲M̲ described as follows:
RS-422 The DATA and CONTROL LINES to/from the TDX
DRIVERS/RECEIVERS BUS are differential lines, which are in
accordance with the RS-422 recommendations.
DECODER A MESSAGE to a CR80 HOST COMPUTER via the
& ENCODER TDX CONTROLLER will be RECEIVED by the destined
TIA MODULE from the LOWER TDX BUS. This
SERIAL DATA STREAM, consisting of the HDLC
FRAMES, is coded with the 1.8432 MHz CLOCK
by the TDX CONTROLLER in the SPL-D CODE.
The DECODER LOGIC will SEPARATE the SPL-D
CODE in DATA and CLOCK.
When the TIA MODULE is TRANSMITTING HDLC
FRAMES, the ENCODER LOGIC on the MODULE will
CODE the OUTGOING DATA with the 1.8432 MHz
CLOCK and TRANSMIT the SPL-D CODED DATA STREAM
to the UPPER TDX BUS. The CLOCK used by
the ENCODER LOGIC is derived from the DECODER
LOGIC. In this way the MESSAGE HANDLING
is SYNCRONIZED by the TDX CONTROLLER.
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MT/RST 4:2:3
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HOST I/F (STI/TIA) L
9…0f…
T̲I̲A̲ OH7 M̲ULTI P̲ROTOCOL C̲OMMUNICATION C̲ONTROLLER.
MPCC
On RECEIVED HDLC FRAMES the MPCC performs:
- Deletion of FLAG BYTES.
- Deletion of ZEROES from the BITSTUFFING
- CYCLIC REDUNDANCY CHECK (CRC).
- SERIAL to PARALLEL conversion of each
byte.
When TRANSMITTING HDLC FRAMES the MPCC performs:
- PARALLEL to SERIAL conversion of each
byte.
- BITSTUFFING (insertion of ZEROES).
- CRC BYTE generation.
- Insertion of FLAG BYTES and ABORT BYTE.
STATE This functional block CONTROLS the ROUTING
CONTROLLER of the HDLC FRAMES in the DATA BUFFER. The
LOGIC STATE CONTROLLER LOGIC also CONTROLS the
MPCC functions.
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MT/RST 4:2:3
840620
HOST I/F (STI/TIA) L
10…0f…
T̲I̲A̲ OH7 F̲IRST I̲N F̲IRST O̲UT registers.
DATA BUFFER
3 FIFO registers are available for ROUTING
the HDLC FRAMES.
When a HDLC FRAME is about to be RECEIVED
the FLAGS are deleted by the MPCC. The REST
of the HDLC FRAME is then converted BYTE
by BYTE from SERIAL to PARALLEL and routed
to FIFO 1. During this transfer the MUX.
No. and the CHANNEL ROUTING IDENTIFIER (CR-ID)
are checked. Furthermore the CYCLIC REDUNDANCY
CHECK (CRC) is carried out. From FIFO 1
the contents are transferred to FIFO 2 from
which the FRONT END PROCESSOR will move the
"DATA BYTES" of the HDLC FRAME to an "INGOING
BUFFER" in the SHARED MEMORY.
When the TRANSMITTER function of the STI
MODULE has been activated, an outgoing HDLC
FRAME will be transferred BYTE by BYTE from
FIFO 3 and converted from PARALLEL to SERIAL
by the MPCC together with the execution of
the remaining MPCC functions.
The contents of FIFO 3 are at an earlier
stage moved from an "OUTGOING BUFFER" in
the SHARED MEMORY to FIFO 3.
FRONT END This is a standard ZILOG 80 MICRO PROCESSOR
PROCESSOR which executes the APPLICATION PROGRAM of
the TIA MODULE. The APPLICATION PROGRAM is
stored in an associated EPROM containing
the TDX INTERFACE TASK and the TASK for the
ACTIVATION and CONTROLLING of the DMA transfer
between the DATA BUFFER and the SHARED MEMORY.
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MT/RST 4:2:3
840620
HOST I/F (STI/TIA) L
11…0f…
T̲I̲A̲ OH7 This MEMORY is SHARED by the
SHARED MEMORY FRONT END PROCESSOR of the TIA MODULE
and the
(RAM) INGOING and the OUTGOING PROCESSOR of the
STI MODULE.
An ARBITOR which is attached to the SHARED
MEMORY makes this MEMORY DUAL PORTED. It
directs whether the TIA or the HI-BUS has
access to the SHARED MEMORY.
DMA CONTROLLER This circuit performs the data transfer
from the DATA BUFFER (FIFO 2) to the SHARED
MEMORY as well as the data transfer from
the SHARED MEMORY to the DATA BUFFER (FIFO
3)
F̲R̲O̲N̲T̲ ̲P̲A̲N̲E̲L̲ ̲ OH7 Two LEDS are available in the FRONT PANEL.
L̲E̲D̲S̲
"POWER" LED When both of the SUPPLIES (+ 5V, - 12V) are
(green) present the LED will be illuminated.
"TEST" LED If the TIA MODULE is not initialized by the
(red) STI MODULE the "TEST" LED will be illuminated.
F̲R̲O̲N̲T̲ ̲P̲A̲N̲E̲L̲ OH7 NONE!
S̲W̲I̲T̲C̲H̲E̲S̲
F̲R̲O̲N̲T̲ ̲P̲A̲N̲E̲L̲ OH7 The connection to one TDX BUS is obtained
C̲O̲N̲N̲E̲C̲T̲I̲O̲N̲ OH8 through a STANDARD 25 PIN CANNON CONNECTOR
named "J1".
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MT/RST 4:2:3
840620
HOST I/F (STI/TIA) L
12…0f…
T̲I̲A̲
B̲A̲C̲K̲ ̲P̲A̲N̲E̲L̲ OH7 The connection to the STI MODULE is
C̲O̲N̲N̲E̲C̲T̲I̲O̲N̲S̲ OH9 performed by a FLAT CABLE via the LOWER BACK
PANEL CONNECTOR.
OH7 The POWER DISTRIBUTION is performed by a
OH10 BACK PLANE MOTHERBOARD through the UPPER
CONNECTOR.
S̲E̲T̲ ̲U̲P̲ OH7 The BASE ADDRESS of the SHARED MEMORY seen
OH11 from the STI MODULE is SET UP by the DIP
SWITCH named "S1".
The STRAPS SETTINGS provide the APPLICATION
of the STI MODULE to a UNIQUE PERFORMANCE.
The CAMPS APPLICATION is shown on OH11.
B̲U̲I̲L̲D̲-̲I̲N̲ ̲T̲E̲S̲T̲ CHECK SUM TEST in EPROM.
READ/WRITE TEST in RAM.
TEST FRAMES are TRANSMITTED and RECEIVED
by the TIA MODULE when starting up.
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MT/RST 4:2:4-6
840620
TDX SYSTEM STATUS TEST,
BOOT UP PROCEDURES & STI TEST EX,GW,DI
1…0f…
I̲N̲T̲T̲R̲O̲D̲U̲C̲T̲I̲O̲N̲ SLG, Describe the lab. exercises for the students
page 1-4 (SLG 4:2:4-6).
Split up into two groups.
Group NO. 1: VDU # 1 (TDX SYST.STAT.TEST).
Group NO. 2: VDU # 2 (BOOT UP via the WD
& STI TEST).
When the exercises are fulfilled, then shift
the exercises.
Remember the SWITCH SETTING on the front
panel of the CUCP, and the MAN.MODE SELECT
as well as the BUS SELECT on the front panel
of the BSM-X.
LAB. WORK Perform the Lab. exercise as described in
the SLG 4:2:4-6.
EVALUATION Discuss the results and observations during
the lab. exercises in the training room and
after the exercises in the classroom.
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MT/RST 4:3:1
840620
BSM-X L
1…0f…
M̲O̲D̲U̲L̲E̲ ̲L̲O̲C̲A̲T̲I̲O̲N̲ OH1 In every TDX UNIT (TU)
in FRONT SLOT No. 2
P̲E̲R̲F̲O̲R̲M̲A̲N̲C̲E̲ Switches the LTUX-S BUS to either the TDX
BUS #1 or the TDX BUS #2.
Enables the WATCH DOG to MONITORING and CONTROLLING
through the CONFIGURATION CONTROL BUS as
follows:
- VOLTAGES of the TDX CRATE
- STATUS of TDX CONTROLLER
- STATUS of AUTO/MANUAL SWITCH
- TEMPERATURE LEVEL in the RACK via ADDITIONAL
DIGITAL INPUT.
- RESYNCHRONIZATION ALARM signal via ADDITIONAL
DIGITAL INPUT.
Connections as follows:
- To the LTUX BUS
- To the TDX BUS #1 and #2
- To the CONFIGURATION CONTROL BUS (CCB)
- To the TDX CONTROLLER
- To the POWER SUPPLY
- To the TEMPERATURE SUPERVISION PANEL (TSP)
B̲L̲O̲C̲K̲ ̲D̲I̲A̲G̲R̲A̲M̲ OH2 BSM-X BLOCK DIAGRAM is described as follows:
RS-422 The DATA and CONTROL LINES to/from the
TDX
DRIVER/RECEIVER BUS are differential lines, in accordance
with the RS 422 recommendations.
ASRT A̲S̲YNCHRONOUS R̲ECEIVER/T̲RANSMITTER
This circuit is an ADDRESSABLE asynchronous
receiver/transmitter. The signals are according
to the specifications for the CONFIGURATION
CONTROL BUS. These SERIAL SIGNALS are used
by the communication between the WATCH DOG
PROCESSOR UNIT (WDP) and the BSM-X MODULE.
The ADDRESS to be recognized is sent from
the WDP and compared with the ADDRESS which
is SET UP by means of the DIP SWITCH named
"S1" on the BSM-X MODULE.
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MT/RST 4:3:1 840620
BSM-X L
2…0f…
BUS SWITCH OH2 This functional block switches either the
LOGIC TDX BUS #1 or the TDX BUS #2 to the LTUX-S
BUS according to the position of the FRONT
PANEL SWITCHES or the information from the
WATCH DOG PROCESSOR UNIT.
CONTROL LOGIC This functional block handles the TDX CONTROLLER
STATUS SIGNALS, the SIGNALS from the A/D
CONVERTER,the BUS SWITCH STATUS, and the
SIGNALS from the ADDITIONAL DIGITAL INPUTS.
The COMBINED STATUS is TRANSMITTED via the
ASRT to the WATCH DOG PROCESSOR UNIT. As
a result of this STATUS INFORMATION the WATCH
DOG returns with COMMANDS about ENABLING/DISABLING
of the TDX CONTROLLER and AUTOMATICALLY BUS
SWITCHING of the TDX BUSSES.
MUX. MULTIPLEXER
The ANALOG MULTIPLEXER connects one by one
the four internal signals + 5V, +12V, - 12V,
and V…0f…REFERENCE…0e… through a VOLTAGE DIVIDER
to the A/D CONVERTER. The frequency of this
scanning is approximately 100 Hz.
A/D CONVERTER The ANALOG to DIGITAL CONVERTER changes the
ANALOG INPUT VALUE to a 10 bit binary value
used by the CONTROL LOGIC.
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MT/RST 4:3:1
840620
BSM-X L
3…0f…
F̲R̲O̲N̲T̲ ̲P̲A̲N̲E̲L̲ OH2 Six LEDS are available in the FRONT PANEL.
L̲E̲D̲S̲
"POWER" LED When all of the 3 SUPPLIES (+ 5V, + 12V,
and
(green) -12V) are present the LED will be illuminated.
"EXT. POWER" When both of the SUPPLIES (V…0f…cc…0e…1, V…0f…cc…0e…2)
LED (green) to the WALL OUTLETS are present, the "EXT.
POWER" LED will be illuminated.
"BUS 1" LED If the TDX BUS-SWITCH-LOGIC has selected
TDX
(yellow) BUS #1, the "BUS 1" LED will be illuminated.
"BUS 2" LED If the TDX BUS-SWITCH-LOGIC has selected
TDX
(yellow) BUS #2, the "BUS 2" LED will be illuminated.
"AUTO" LED If the SWITCHING of the TDX BUSSES is
(yellow) controlled by the WATCH DOG, the "AUTO" LED
will be illuminated.
This MODE is named AUTO-MODE, and it is performed
by the FRONT PANEL MODE-SWITCH in position
"AUTO".
"MAN" LED If the SWITCHING of the TDX-BUSSES is
(yellow) controlled by the FRONT PANEL BUS-SELECT-SWITCH
the "MAN" LED will be illuminated. This
MODE is named MANUAL MODE and it is performed
by the FRONT PANEL MODE SWITCH in position
"MAN".
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MT/RST 4:3:1 840620
BSM-X L
4…0f…
F̲R̲O̲N̲T̲ ̲P̲A̲N̲E̲L̲ OH2 Two SWITCHES are available in the FRONT
S̲W̲I̲T̲C̲H̲E̲S̲ PANEL.
"AUTO"/"MAN."/ In position "AUTO" (AUTO MODE) the SWITCHING
"OFF" MODE-SWITCH of the TDX BUSSES is controlled by the WATCH
DOG (remote control).
In position "MAN" (MAN MODE) the SWITCHING
of the TDX BUSSES is controlled by the FRONT
PANEL BUS-SELECT SWITCH in position "BUS
1" and "BUS 2" (manual control).
In position "OFF" (OFF MODE) NO SWITCHING
takes place and a 3-state logic ensures that
the BSM-X MODULE is functionally disconnected
from the TDX BUSSES.
"BUS 1"/"BUS 2" In position "BUS 1" the BSM-X MODULE is
SELECT-SWITCH functionally connected to the TDX-BUS #1.
In position "BUS 2" the BSM-X MODULE is functionally
connected to the TDX-BUS #2.
NOTE!
This MANUAL CONTROL of the TDX BUS-SWITCHING
can only be obtained when the FRONT PANEL
MODE-SWITCH is switched to position "MAN".
FRONT PANEL OH2 The PIN CONFIGURATION of the 25 pin FRONT
CONNECTION OH3 PANEL CONNECTOR named "TDX CONTR.".
This CONNECTOR performs the connection between
the TDX CONTROLLER and the WATCH DOG PROCESSOR
UNIT (WDP) via the BSM-X MODULE. (LESSON
4:2:1-2: OH5).
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MT/RST 4:3:1
840620
BSM-X L
5…0f…
B̲A̲C̲K̲ ̲P̲L̲A̲N̲E̲ OH2 BACK PLANE CONNECTIONS are described as
C̲O̲N̲N̲E̲C̲T̲I̲O̲N̲S̲ OH4 follows:
OH5 Connection to the TDX BUS #1 and #2 occurs
through FLAT CABLES via the BSM-X PANEL in
the REAR MAGAZINE and further on to WALL
OUTLETS.
Connection to the WATCH DOG PROCESSOR UNIT
(WDP) passes through a FLAT CABLE to the
above mentioned BSM-X PANEL and further on
through the CONFIGURATION CONTROL BUS (CCB).
Connection to the TEMPERATURE SENSOR occurs
through the BACK PLANE MOTHERBOARD to a 10
pin WRAP CONNECTOR and further on via FLAT
CABLE to TEMPERATURE SUPERVISION PANEL (TSP)
in the REAR MAGAZINE.
Connection TDX BUS to the LTUX-S passes through
the BACK PLANE MOTHERBOARD (LTUX-S BUS) to
the respective LTUX-S CONNECTOR.
S̲E̲T̲ ̲U̲P̲ OH2 The "MODULE NO." is the IDENTIFICATION of
OH6 the CCA FUNCTIONS in the BSM-X MODULE. This
IDENTIFICATION is used by the WATCH DOG and
it is SET UP by means of the DIP SWITCH named
"S1". (See also 4:1:1:OH5-7).
The CCA (CONFIGURATION CONTROL ADAPTOR) FUNCTIONS
are the MONITORING and CONTROL FUNCTIONS
of the BSM-X module.
The STRAPS SETTINGS PROVIDE the APPLICATION
of the BSM-X MODULE to a UNIQUE PERFORMANCE.
CAMPS APPLICATION is shown on OH6.
Her inds`ttes tegning
CAMPS GENERIC BLOCK DIAGRAM
Her inds`ttes tegning
ASSEMBLY VIEW m.m.
F̲R̲O̲N̲T̲ ̲P̲A̲N̲E̲L̲ ̲C̲O̲N̲N̲E̲C̲T̲I̲O̲N̲
PIN LAY OUT for the "TDX CONTR." CONNECTOR:
B̲A̲C̲K̲ ̲P̲L̲A̲N̲E̲ ̲C̲O̲N̲N̲E̲C̲T̲I̲O̲N̲
PIN LAY OUT:
Her inds`ttes tegning
CAMPS GENERIC BLOCK DIAGRAM
OG…01……01…TDX UNIT (REAR VIEW)
S̲W̲I̲T̲C̲H̲ ̲S̲E̲T̲T̲I̲N̲G̲
MODULE NO.:
DIP SWITCH "S1"
̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲
CONTACT NO. ^ ̲1̲ ̲^̲ ̲2̲ ̲^̲ ̲3̲ ̲^̲ ̲4̲ ̲^̲ ̲5̲ ̲^̲ ̲6̲ ̲^
OPEN
OPEN = "1" (PRESS DOWN)
̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲
^ CONTACT NO.^ ^ ^ ^ ^ ^ ^
^ BSM-X ^ 1 ^ 2 ^ 3 ^ 4 ^ 5 ^ 6 ^
^ ̲L̲O̲C̲A̲T̲I̲O̲N̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲^̲ ̲ ̲ ̲^̲ ̲ ̲ ̲^̲ ̲ ̲ ̲^̲ ̲ ̲ ̲^̲ ̲ ̲ ̲^̲ ̲ ̲ ̲^̲
^ ^ ^ ^ ^ ^ ^ ^
^ Front Slot 2, TU#1 ^ 1 ^ 0 ^ 0 ^ 0 ^ 1 ^ X ^
^ Front Slot 2, TU#2 ^ 0 ^ 1 ^ 0 ^ 0 ^ 1 ^ X ^
^ Front Slot 2, TU#3 ^ 1 ^ 1 ^ 0 ^ 0 ^ 1 ^ X ^
^ Front Slot 2, TU#4 ^ 0 ^ 0 ^ 1 ^ 0 ^ 1 ^ X ^
^ Front Slot 2, TU#5 ^ 1 ^ 0 ^ 1 ^ 0 ^ 1 ^ X ^
^ Front Slot 2, TU#6 ^ 0 ^ 1 ^ 1 ^ 0 ^ 1 ^ X ^
^ Front Slot 2, TU#7 ^ 1 ^ 1 ^ 1 ^ 0 ^ 1 ^ X ^
^ Front Slot 2, TU#8 ^ 0 ^ 0 ^ 0 ^ 1 ^ 1 ^ X ^
^ Front Slot 2, TU#9 ^ 1 ^ 0 ^ 0 ^ 1 ^ 1 ^ X ^
^ Front Slot 2, TU#A ^ 0 ^ 1 ^ 0 ^ 1 ^ 1 ^ X ^
^ Front Slot 2, TU#B ^ 1 ^ 1 ^ 0 ^ 1 ^ 1 ^ X ^
^ Front Slot 2, TU#C ^ 0 ^ 0 ^ 1 ^ 1 ^ 1 ^ X ^
^ Front Slot 2, TU#D ^ 1 ^ 0 ^ 1 ^ 1 ^ 1 ^ X ^
^ Front Slot 2, TU#E ^ 0 ^ 1 ^ 1 ^ 1 ^ 1 ^ X ^
^ Front Slot 2, TU#F ^ 1 ^ 1 ^ 1 ^ 1 ^ 1 ^ X ^
^ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲^̲ ̲ ̲ ̲^̲ ̲ ̲ ̲^̲ ̲ ̲ ̲^̲ ̲ ̲ ̲^̲ ̲ ̲ ̲^̲ ̲ ̲ ̲^̲
LSB MSB
X = "do not care"
S̲T̲R̲A̲P̲S̲ ̲S̲E̲T̲T̲I̲N̲G̲S̲
̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲
^ ^ ^ ^ ^ ^ ^ ^ ^ ^
^ ̲P̲I̲N̲ ̲B̲L̲O̲C̲K̲ ̲N̲O̲.̲ ̲ ̲^̲ ̲1̲ ̲^̲ ̲2̲ ̲^̲ ̲3̲ ̲^̲ ̲4̲ ̲^̲ ̲5̲ ̲^̲ ̲6̲ ̲^̲ ̲7̲ ̲^̲ ̲8̲ ̲^
^ ^ ^ ^ ^ ^ ^ ^ ^ ^
^ ̲S̲T̲R̲A̲P̲ ̲L̲O̲C̲A̲T̲I̲O̲N̲ ̲^̲ ̲B̲ ̲^̲ ̲A̲ ̲^̲ ̲B̲ ̲^̲ ̲B̲ ̲^̲ ̲B̲ ̲^̲ ̲A̲ ̲^̲ ̲B̲ ̲^̲ ̲B̲ ̲^
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MT/RST 4:3:2
840620
LTUX-S L
1…0f…
M̲O̲D̲U̲L̲E̲ ̲L̲O̲C̲A̲T̲I̲O̲N̲ OH1 In every TDX UNIT (TU)
max. two LTUX-S MODULES
are placed. One MODULE
in FRONT SLOT No. 3
and one in FRONT SLOT
No. 11.
PERFORMANCE The LTUX-S is an INTELLIGENT INTERFACE MODULE
between the TDX BUS and 4 SERIAL CHANNELS
(LINES) to the DISTRIBUTION EQUIPMENT for
the LOW LEVEL PERIPHERALS.
The HDLC FRAMES are RECEIVED from the LOWER
BUS and TRANSMITTED to the UPPER BUS.
DECODING and ENCODING of the SPL-D CODE as
well as SERIAL/PARALLEL and PARALLEL/SERIAL
CONVERSION are carried out by the LTUX-S
MODULE.
CYCLIC REDUNDANCY CHECK (CRC) and BITSTUFFING
is also performed.
COMMUNICATION to the DISTRIBUTION EQUIPMENT
for the PERIPHERALS passes SERIAL INPUT/OUTPUT
PORTS and V24 LINE DRIVERS/RECEIVERS.
B̲L̲O̲C̲K̲ ̲D̲I̲A̲G̲R̲A̲M̲ OH2 LTUX-S BLOCK DIAGRAM is described as follows:
DECODER & ENCODER A MESSAGE to a LTUX-S MODULE via the TDX
CONTROLLER will be RECEIVED by the destined
LTUX-S MODULE from the LOWER TDX BUS. This
SERIAL DATA STREAM, consisting of the HDLC
FRAMES, is CODED with the 1.8432 MHz CLOCK
by the TDX CONTROLLER in the SPL-D CODE.
The DECODER LOGIC will SEPARATE the SPL-D
CODE in DATA and CLOCK.
When the LTUX-S MODULE is TRANSMITTING HDLC
FRAMES, the ENCODER LOGIC on the MODULE will
CODE the OUTGOING DATA with the 1.8432 MHz
CLOCK and TRANSMIT the SPL-D CODED DATA STREAM
to the UPPER TDX BUS.
The CLOCK used by the ENCODER LOGIC is derived
from the DECODER LOGIC. In this way the
MESSAGE HANDLING is SYNCRONIZED by the TDX
CONTROLLER.
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MT/RST 4:3:2 840620
LTUX-S L
2…0f…
M̲P̲C̲C̲ OH2 M̲ULTI P̲ROTOCOL C̲OMMUNICATION C̲ONTROLLER
On RECEIVED HDLC FRAMES the MPCC performs:
- Deletion of FLAG BYTES
- Deletion of ZEROES from the BITSTUFFING
- CYCLIC REDUNDANCY CHECK (CRC)
- SERIAL to PARALLEL conversion of each
byte
When TRANSMITTING HDLC FRAMES, the MPCC performs:
- PARALLEL to SERIAL conversion of each
byte
- BITSTUFFING (insertion of ZEROES)
- CRC BYTE generation
- Insertion of FLAG BYTES and ABORT BYTES.
STATE This functional block CONTROLS the ROUTING
CONTROLLER of the HDLC FRAMES in the DATA BUFFER.
LOGIC The STATE CONTROLLER LOGIC also CONTROLS
the MPCC functions.
DATA BUFFER F̲IRST I̲N F̲IRST O̲UT registers
3 FIFO registers are available for ROUTING
the HDLC FRAMES.
When a HDLC FRAME is about to be RECEIVED,
the FLAGS are deleted by the MPCC. The REST
of the HDLC FRAME is then converted BYTE
by BYTE from SERIAL to PARALLEL and routed
to FIFO 1. During this transfer the MUX
No. and the CHANNEL ROUTING IDENTIFIER (CR-ID)
are checked. Furthermore the CYCLIC REDUNDANCY
CHECK (CRC) is carried out. From FIFO 1
the contents are transferred to FIFO 2 from
which the CPU will move the "DATA BYTES"
of the HDLC FRAME to a CHANNEL BUFFER in
the DATA MEMORY.
When the TRANSMITTER function of the LTUX-S
MODULE has been activated, an outgoing HDLC
FRAME will be transferred BYTE by BYTE from
FIFO 3 and converted from PARALLEL to SERIAL
by the MPCC together with the execution of
the remaining MPCC functions.
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MT/RST 4:3:2 840620
LTUX-S L
3…0f…
OH2 The contents of FIFO 3 are at an earlier
stage moved from a CHANNEL BUFFER in the
DATA MEMORY to FIFO 3.
CPU C̲ENTRAL P̲ROCESSING U̲NIT
This is a standard ZILOG 80 MICRO PROCESSOR
which executes the APPLICATION PROGRAM of
the LTUX-S MODULE resident in the PROGRAM
MEMORY.
PROGRAM MEMORY The APPLICATION PROGRAM of the LTUX-S
MODULE is stored in the PROGRAM EPROM,
containing the TDX INTERFACE TASK, the
TDX PACKET PROTOCOL TASK, and the TDX
CHANNEL SET UP TASK.
DATA MEMORY The INTERMEDIATE DATA will be stored in the
DATA RAM. A certain area is used as CHANNEL
BUFFER for the "DATA BYTES" of HDLC FRAMES.
This is the "INTERCONNECTIONS" between the
"DATA BYTES" of the HDLC FRAMES and the SERIAL
CHANNELS to/from the PERIPHERALS.
USART U̲NIVERSAL S̲YNCHRONOUS A̲SYNCHRONOUS R̲ECEIVER
T̲RANSMITTER
The USART is 2 dual ported SIOs (S̲ERIAL I̲NPUT
O̲UTPUT). Each SIO PORT consists of 1 SERIAL
INPUT LINE and 1 SERIAL OUTPUT LINE (= 1
SERIAL CHANNEL). All together 4 SERIAL INPUT
LINES and 4 SERIAL OUTPUT LINES (= 4 SERIAL
CHANNELS) are available. The BAUD RATE is
SET UP AUTOMATICALLY by DOWNLOAD from SUPERIOR
PROGRAMS according to the APPLICATION.
V24 RECEIVERS/ Standard V24 RECEIVERS/DRIVERS are associated
DRIVERS with the SIO ports to obtain a standardized
connection to the DISTRIBUTION EQUIPMENT
for the PERIPHERALS.
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MT/RST 4:3:2 840620
LTUX-S L
4…0f…
F̲R̲O̲N̲T̲ ̲P̲A̲N̲E̲L̲ OH2 Seven LEDS are available in the FRONT PANEL.
L̲E̲D̲S̲
"POWER" LED When all of the 3 SUPPLIES (+ 5V, + 12V,
- 12V)
(green) are present, the LED will be illuminated.
"TEST" LED During the execution of the BUILD-IN TEST
(red) (BIT), the "TEST" LED will be illuminated
for a few seconds.
When the BUILD-IN-TEST is fulfilled successfully
(no error), the "TEST" LED will be extinguished.
If the BUILD-IN TEST detects an ERROR, the
"TEST" LED will show CONSTANT LIGHT.
"TDX ST." When the LTUX-S MODULE is connected to the
(red) TDX BUS and receives the SPL-D CODE continously
the "TDX ST." LED will be extinguished.
CH 1-4 LEDS When the corresponding SWITCH "CH 1", "CH
2",
(yellow) "CH 3", or "CH 4" in the FRONT PANEL is in
position "ON", the LED will be illuminated
to indicate that the respective SERIAL CHANNEL
to the PERIPHERALS is enabled.
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MT/RST 4:3:2 840620
LTUX-S L
5…0f…
F̲R̲O̲N̲T̲ ̲P̲A̲N̲E̲L̲ OH2 Four SWITCHES are available in the FRONT
S̲W̲I̲T̲C̲H̲E̲S̲ PANEL.
CH 1-4 SWITCHES These SWITCHES are used for ENABLING and
DISABLING of the corresponding SERIAL
CHANNELS to the PERIPHERALS.
Each SWITCH has 2 POSITIONS:
- POSITION "ON" = ENABLE
- POSITION "OFF" = DISABLE
F̲R̲O̲N̲T̲ ̲P̲A̲N̲E̲L̲ OH2 NONE!
C̲O̲N̲N̲E̲C̲T̲I̲O̲N̲S̲
B̲A̲C̲K̲ ̲P̲L̲A̲N̲E̲ OH2 The BACK PLANE CONNECTIONS are described
C̲O̲N̲N̲E̲C̲T̲I̲O̲N̲S̲ OH3 as follows:
Connection to the TDX BUS 1 and 2 occurs
from the LTUX-S BUS on the BACK PLANE MOTHERBOARD
via the BUS SWITCH MODULE (BSM-X), the BSM-X
PANEL, and WALL OUTLETS.
Connection to the DISTRIBUTION EQUIPMENT
passes either through a FLAT CABLE to a BACK
PANEL in the REAR MAGAZINE or via the BACK
PLANE MOTHERBOARD to ADAPTORS in the FRONT
MAGAZINE.
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MT/RST 4:3:2 840620
LTUX-S L
6…0f…
S̲E̲T̲ ̲U̲P̲ OH2 Two DIP SWITCHES are available on the LTUX-S
OH4 MODULE:
- DIP SWITCH "S1" = DEVICE ADDRESS
- DIP SWITCH "S2" = CHANNEL BAUD RATE
("S2" is not used in CAMPS).
The DEVICE ADDRESS of the LTUX-S MODULE IDENTIFIES
a unique DEVICE NO. in the TDX SYSTEM. It
is SET UP by means of the DIP SWITCH named
"S1". (See also 4:1:1 OH5-7).
The CHANNEL BAUD RATE is the SPEED of the
DATA TRANSMISSION between the LTUX-S MODULE
and the PERIPHERALS.
NOTE!
This BAUD RATE is SET UP AUTOMATICALLY by
DOWNLOAD from SUPERIOR PROGRAMS according
to the APPLICATION of the LTUX-S.
1 CHANNEL : MAX. 9600 BAUD
2 CHANNELS: MAX. 4800 BAUD per
CH.
3-4 CHANNELS: MAX. 2400 BAUD per
CH.
OH5 The STRAPS SETTINGS provide the APPLICATION
of the BSM-X to a UNIQUE PERFORMANCE.
CAMPS APPLICATION as shown.
V̲E̲R̲S̲I̲O̲N̲S̲ 3 versions of LTUX-S MODULES are used in
the CAMPS.
- VDU APPLICATION
- MSP and PTP/R APPLICATION
- OCR APPLICATION
B̲U̲I̲L̲D̲-̲I̲N̲ ̲T̲E̲S̲T̲ TEST FRAMES are TRANSMITTED and RECEIVED
by the LTUX-S MODULE when starting up (Power
on).
Her inds`ttes tegning
Her inds`ttes tegning
B̲A̲C̲K̲ ̲P̲L̲A̲N̲E̲ ̲C̲O̲N̲N̲E̲C̲T̲I̲O̲N̲S̲
PIN LAY OUT:
̲ ̲ ̲ ̲ ̲ ̲ ̲A̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲B̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲
̲ ̲ ̲ ̲ ̲ ̲G̲N̲D̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲^ ̲ ̲1̲ ̲^ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲G̲N̲D̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲
^ V24 CIRCUIT 101 ^ 2 ^ V24 CIRCUIT 101 ^
^ ^ 3 ^ - 113 ^
^ ^ 4 ^ ^ I/O
^ - 115 ^ 5 ^ ^ CHANNEL
#1
^ - 109 ^ 6 ^ - 106 ^
^ - 105 ^ 7 ^ - 108 ^
^ ̲ ̲ ̲ ̲ ̲-̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲1̲0̲3̲ ̲ ̲ ̲ ̲^̲ ̲ ̲8̲ ̲^̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲-̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲1̲0̲4̲ ̲^
̲ ̲ ̲ ̲ ̲N̲O̲T̲ ̲U̲S̲E̲D̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲^̲ ̲ ̲9̲ ̲^̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲N̲O̲T̲ ̲U̲S̲E̲D̲ ̲ ̲ ̲ ̲ ̲
^ V24 CIRCUIT 101 ^ 10 ^ V24 CIRCUIT 102 ^
^ ^ 11 ^ - 113 ^
^ ^ 12 ^ ^ I/O
^ - 115 ^ 13 ^ ^ CHANNEL
#2
^ - 109 ^ 14 ^ - 106 ^
^ - 105 ^ 15 ^ - 108 ^
^ ̲ ̲ ̲ ̲ ̲-̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲1̲0̲3̲ ̲ ̲ ̲ ̲^̲ ̲1̲6̲ ̲^̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲-̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲1̲0̲4̲ ̲^
NOT USED ^ 17 ^ NOT USED
̲ ̲ ̲ ̲ ̲N̲O̲T̲ ̲U̲S̲E̲D̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲^̲ ̲1̲8̲ ̲^̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲N̲O̲T̲ ̲U̲S̲E̲D̲ ̲ ̲ ̲ ̲ ̲
^ V24 CIRCUIT 101 ^ 19 ^ V24 CIRCUIT 102 ^
^ ^ 20 ^ - 113 ^
^ ^ 21 ^ ^ I/O
^ - 115 ^ 22 ^ ^ CHANNEL
#3
^ - 109 ^ 23 ^ - 106 ^
^ - 105 ^ 24 ^ - 108 ^
^ ̲ ̲ ̲ ̲ ̲-̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲1̲0̲3̲ ̲ ̲ ̲ ̲^̲ ̲2̲5̲ ̲^̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲-̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲1̲0̲4̲ ̲^
̲ ̲ ̲ ̲ ̲N̲O̲T̲ ̲U̲S̲E̲D̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲^̲ ̲2̲6̲ ̲^̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲N̲O̲T̲ ̲U̲S̲E̲D̲ ̲ ̲ ̲ ̲ ̲
^ V24 CIRCUIT 101 ^ 27 ^ V24 CIRCUIT 102 ^
^ ^ 28 ^ - 113 ^
^ ^ 29 ^ ^ I/O
^ - 115 ^ 30 ^ ^ CHANNEL
#4
^ - 109 ^ 31 ^ - 106 ^
^ - 105 ^ 32 ^ - 108 ^
^ ̲ ̲ ̲ ̲ ̲-̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲1̲0̲3̲ ̲ ̲ ̲ ̲^̲ ̲3̲3̲ ̲^̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲-̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲1̲0̲4̲ ̲^
TX-DATA ^ 34 ^ TX-EN
(SIGN.) GND ^ 35 ^ (SIGN. GND) LTUX-S BUS
RX-DATA 1 ^ 36 ^ RX-DATA 2
GND ^ 37 ^ GND
+12V ^ 38 ^ +12V
-12V ^ 39 ^ -12V
+5V ^ 40 ^ +5V
+5V ^ 41 ^ +5V
GND ^ 42 ^ GND
GND ^ ̲4̲3̲ ̲^ GND
S̲W̲I̲T̲C̲H̲ ̲S̲E̲T̲T̲I̲N̲G̲
DEVICE ADDRESS:
DIP SWITCH "S1"
̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲
CONTACT NO. ^ ̲1̲ ̲^̲ ̲2̲ ̲^̲ ̲3̲ ̲^̲ ̲4̲ ̲^̲ ̲5̲ ̲^̲ ̲6̲ ̲^̲ ̲7̲ ̲^̲ ̲8̲ ̲^
OPEN
OPEN = "1" (PRESS DOWN)
^ ^
^
̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲^̲ ̲ ̲ ̲ ̲ ̲T̲U̲ ̲N̲O̲.̲ ̲ ̲ ̲ ̲^̲ ̲L̲O̲C̲A̲T̲I̲O̲N̲
̲I̲N̲ ̲T̲U̲^
^ CONTACT NO.^ ^ ^ ^ ^ ^ ^
^ ^
^ LTUX-S ^ 1 ^ 2 ^ 3 ^ 4 ^ 5 ^ 6 ^
7 ^ 8 ^
^ ̲L̲O̲C̲A̲T̲I̲O̲N̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲^̲ ̲ ̲ ̲^̲ ̲ ̲ ̲^̲ ̲ ̲ ̲^̲ ̲ ̲ ̲^̲ ̲ ̲ ̲^̲ ̲ ̲ ̲^̲
̲ ̲ ̲^̲ ̲ ̲ ̲^ ̲ ̲ ̲
^ ^ ^ ^ ^ ^ ^ ^
^ ^
^ Front Slot 3, TU#1 ^ 1 ^ 0 ^ 0 ^ 0 ^ 1 ^ 0 ^
0 ^ 0 ^ R
^ Front Slot 3, TU#2 ^ 0 ^ 1 ^ 0 ^ 0 ^ 1 ^ 0 ^
0 ^ 0 ^ E
^ Front Slot 3, TU#3 ^ 1 ^ 1 ^ 0 ^ 0 ^ 1 ^ 0 ^
0 ^ 0 ^ L.
^ Front Slot 3, TU#4 ^ 0 ^ 0 ^ 1 ^ 0 ^ 1 ^ 0 ^
0 ^ 0 ^
^ Front Slot 3, TU#5 ^ 1 ^ 0 ^ 1 ^ 0 ^ 1 ^ 0 ^
0 ^ 0 ^ M
^ Front Slot 3, TU#6 ^ 0 ^ 1 ^ 1 ^ 0 ^ 1 ^ 0 ^
0 ^ 0 ^ O
^ Front Slot 3, TU#7 ^ 1 ^ 1 ^ 1 ^ 0 ^ 1 ^ 0 ^
0 ^ 0 ^ D
^ Front Slot 3, TU#8 ^ 0 ^ 0 ^ 0 ^ 1 ^ 1 ^ 0 ^
0 ^ 0 ^ U
^ Front Slot 3, TU#9 ^ 1 ^ 0 ^ 0 ^ 1 ^ 1 ^ 0 ^
0 ^ 0 ^ L
^ Front Slot 3, TU#A ^ 0 ^ 1 ^ 0 ^ 1 ^ 1 ^ 0 ^
0 ^ 0 ^ E
^ Front Slot 3, TU#B ^ 1 ^ 1 ^ 0 ^ 1 ^ 1 ^ 0 ^
0 ^ 0 ^
^ Front Slot 3, TU#C ^ 0 ^ 0 ^ 1 ^ 1 ^ 1 ^ 0 ^
0 ^ 0 ^ N
^ Front Slot 3, TU#D ^ 1 ^ 0 ^ 1 ^ 1 ^ 1 ^ 0 ^
0 ^ 0 ^ O.
^ Front Slot 3, TU#E ^ 0 ^ 1 ^ 1 ^ 1 ^ 1 ^ 0 ^
0 ^ 0 ^
^ Front Slot 3, TU#F ^ 1 ^ 1 ^ 1 ^ 1 ^ 1 ^ 0 ^
0 ^ 0 ^ ̲1̲ ̲
^ Front Slot 11, TU#1 ^ 1 ^ 0 ^ 0 ^ 0 ^ 0 ^ 1 ^
0 ^ 0 ^
^ Front Slot 11, TU#2 ^ 0 ^ 1 ^ 0 ^ 0 ^ 0 ^ 1 ^
0 ^ 0 ^ R
^ Front Slot 11, TU#3 ^ 1 ^ 1 ^ 0 ^ 0 ^ 0 ^ 1 ^
0 ^ 0 ^ E
^ Front Slot 11, TU#4 ^ 0 ^ 0 ^ 1 ^ 0 ^ 0 ^ 1 ^
0 ^ 0 ^ L.
^ Front Slot 11, TU#5 ^ 1 ^ 0 ^ 1 ^ 0 ^ 0 ^ 1 ^
0 ^ 0 ^
^ Front Slot 11, TU#6 ^ 0 ^ 1 ^ 1 ^ 0 ^ 0 ^ 1 ^
0 ^ 0 ^ M
^ Front Slot 11, TU#7 ^ 1 ^ 1 ^ 1 ^ 0 ^ 0 ^ 1 ^
0 ^ 0 ^ O
^ Front Slot 11, TU#8 ^ 0 ^ 0 ^ 0 ^ 1 ^ 0 ^ 1 ^
0 ^ 0 ^ D
^ Front Slot 11, TU#9 ^ 1 ^ 0 ^ 0 ^ 1 ^ 0 ^ 1 ^
0 ^ 0 ^ U
^ Front Slot 11, TU#A ^ 0 ^ 1 ^ 0 ^ 1 ^ 0 ^ 1 ^
0 ^ 0 ^ L
^ Front Slot 11, TU#B ^ 1 ^ 1 ^ 0 ^ 1 ^ 0 ^ 1 ^
0 ^ 0 ^ E
^ Front Slot 11, TU#C ^ 0 ^ 0 ^ 1 ^ 1 ^ 0 ^ 1 ^
0 ^ 0 ^
^ Front Slot 11, TU#D ^ 1 ^ 0 ^ 1 ^ 1 ^ 0 ^ 1 ^
0 ^ 0 ^ N
^ Front Slot 11, TU#E ^ 0 ^ 1 ^ 1 ^ 1 ^ 0 ^ 1 ^
0 ^ 0 ^ O.
^ Front Slot 11, TU#F ^ 1 ^ 1 ^ 1 ^ 1 ^ 0 ^ 1 ^
0 ^ 0 ^
^ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲^̲ ̲ ̲ ̲^̲ ̲ ̲ ̲^̲ ̲ ̲ ̲^̲ ̲ ̲ ̲^̲ ̲ ̲ ̲^̲ ̲ ̲ ̲^̲
̲ ̲ ̲^̲ ̲ ̲ ̲^ ̲2̲ ̲
^ LSB MSB ^ LSB
MSB ^
^ LOWER 4 BIT ^ UPPER
4 BIT ^
S̲T̲R̲A̲P̲S̲ ̲S̲E̲T̲T̲I̲N̲G̲S̲
̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲
̲ ̲ ̲
^ ^ ^ ^ ^ ^ ^ ^ ^ ^
^
^ ̲P̲I̲N̲ ̲B̲L̲O̲C̲K̲ ̲N̲O̲.̲ ̲ ̲^̲ ̲1̲ ̲^̲ ̲2̲ ̲^̲ ̲3̲ ̲^̲ ̲4̲ ̲^̲ ̲5̲ ̲^̲ ̲6̲ ̲^̲ ̲7̲ ̲^̲ ̲8̲ ̲^̲
̲9̲ ̲^
^ ^ ^ ^ ^ ^ ^ ^ ^ ^
^
^ ̲S̲T̲R̲A̲P̲ ̲L̲O̲C̲A̲T̲I̲O̲N̲ ̲^̲ ̲B̲ ̲^̲ ̲A̲ ̲^̲ ̲A̲ ̲^̲ ̲B̲ ̲^̲ ̲A̲ ̲^̲ ̲B̲ ̲^̲ ̲A̲ ̲^̲ ̲B̲ ̲^̲
̲B̲ ̲^
̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲
̲ ̲ ̲
^ ^ ^ ^ ^ ^ ^ ^ ^ ^
^
^ ̲P̲I̲N̲ ̲B̲L̲O̲C̲K̲ ̲N̲O̲.̲ ̲ ̲^̲ ̲1̲0̲^̲ ̲1̲1̲^̲ ̲1̲2̲^̲ ̲1̲3̲^̲ ̲1̲4̲^̲ ̲1̲5̲^̲ ̲1̲6̲^̲ ̲1̲7̲^̲
̲1̲8̲^
^ ^ ^ ^ ^ ^ ^ ^ ^ ^
^
^ ̲S̲T̲R̲A̲P̲ ̲L̲O̲C̲A̲T̲I̲O̲N̲ ̲^̲ ̲A̲ ̲^̲ ̲A̲ ̲^̲ ̲A̲ ̲^̲ ̲A̲ ̲^̲ ̲A̲ ̲^̲ ̲A̲ ̲^̲ ̲A̲ ̲^̲ ̲A̲ ̲^̲
̲A̲ ̲^
̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲
̲ ̲ ̲
^ ^ ^ ^ ^ ^ ^ ^ ^ ^
^
^ ̲P̲I̲N̲ ̲B̲L̲O̲C̲K̲ ̲N̲O̲.̲ ̲ ̲^̲ ̲1̲9̲^̲ ̲2̲0̲^̲ ̲2̲1̲^̲ ̲2̲2̲^̲ ̲2̲3̲^̲ ̲2̲4̲^̲ ̲2̲5̲^̲ ̲2̲6̲^̲
̲ ̲ ̲^
^ ^ ^ ^ ^ ^ ^ ^ ^ ^
^
^ ̲S̲T̲R̲A̲P̲ ̲L̲O̲C̲A̲T̲I̲O̲N̲ ̲^̲ ̲A̲ ̲^̲ ̲A̲ ̲^̲ ̲A̲ ̲^̲ ̲C̲ ̲^̲ ̲B̲ ̲^̲ ̲C̲ ̲^̲ ̲B̲ ̲^̲ ̲B̲ ̲^̲
̲ ̲ ̲^
Her inds`ttes tegning
Her inds`ttes tegning
F̲R̲O̲N̲T̲ ̲P̲A̲N̲E̲L̲ ̲C̲O̲N̲N̲E̲C̲T̲I̲O̲N̲
PIN LAY OUT for the TDX BUS CONNECTOR:
̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲
̲ ̲ ̲ ̲ ̲
^ ̲ ̲P̲I̲N̲ ̲ ̲ ̲S̲I̲G̲N̲A̲L̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲P̲I̲N̲ ̲ ̲ ̲ ̲S̲I̲G̲N̲A̲L̲ ̲ ̲ ̲ ̲ ̲
̲ ̲ ̲ ̲ ̲^
^
^
^ 1 Logic one 14 same as 1
^
^
^
^ 2 Logic one 15 same as 2
^
^
^
^ 3 GND 16 GND
^
^
^
^ 4 GND 17 GND
^
^
^
^ 5 GND 18 DISAB- 1
^
^
^
^ 6 DISAB+ 1 19 GND
^
^
^
^ 7 GND 20 TXDAT- 1
^
^
^
^ 8 TXDAT+ 1 21 GND
^
^
^
^ 9 GND 22 RXDAT- 2
^
^
^
^ 10 RXDAT+ 2 23 TXDAT- 2
^
^
^
^ 11 TXDAT+ 2 24 RXDAT- 1
^
^
^
^ 12 RXDAT+ 1 25 DISAB- 2
^
^
^
^ 13 DISAB+ 2
^
^ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲
̲ ̲ ̲ ̲ ̲^
B̲A̲C̲K̲ ̲P̲L̲A̲N̲E̲ ̲C̲O̲N̲N̲E̲C̲T̲I̲O̲N̲
PIN LAY OUT for the LOWER CONNECTOR:
̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲
^ ̲6̲4̲ ̲P̲O̲L̲.̲ ̲F̲L̲A̲T̲C̲A̲B̲L̲E̲,̲ ̲H̲I̲-̲B̲U̲S̲ ̲ ̲^
^ ̲ ̲ ̲ ̲c̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲^̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲a̲ ̲ ̲ ̲ ̲^
^ ^
^ GND 1 GND ^
^ GND 2 GND ^
^ 3 ^
^ 4 ^
^ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ 5 ̲ ̲ ̲ ̲ ̲ ^
^ R̲X̲-̲S̲T̲A̲TUS 6 E̲R̲R̲O̲R̲ ̲ ̲ ^
^ EX-INT 7 R̲E̲S̲TART ^
^ 8 M̲RQ ^
^ ̲ ̲ ̲ ̲ 9 R̲/̲W̲ ̲ ^
^ T̲E̲S̲T 10 D̲A̲T̲I̲ ^
^ PWI 11 D̲A̲CP ^
^ 12 FB ^
^ GND 13 [1 ^
^ GND 14 [2 ^
^ H0 15 H1 ^
^ H2 16 H3 ^
^ GND 17 GND ^
^ D0 18 D1 ^
^ D2 19 D3 ^
^ D4 20 D5 ^
^ D6 21 D7 ^
^ GND 22 GND ^
^ A0 23 A1 ^
^ A2 24 A3 ^
^ A4 25 A5 ^
^ A6 26 A7 ^
^ GND 27 GND ^
^ A8 28 A9 ^
^ A10 29 A11 ^
^ A12 30 A13 ^
^ A14 31 A15 ^
^ GND 32 GND ^
^ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲^
B̲A̲C̲K̲ ̲P̲L̲A̲N̲E̲ ̲C̲O̲N̲N̲E̲C̲T̲I̲O̲N̲
PIN LAY OUT for the UPPER CONNECTOR:
̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲
^ ̲ ̲ ̲ ̲ ̲ ̲6̲4̲ ̲P̲O̲L̲.̲ ̲C̲O̲N̲N̲E̲C̲T̲O̲R̲ ̲ ̲ ̲ ̲^
^ ̲ ̲ ̲ ̲c̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲^̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲a̲ ̲ ̲ ̲ ̲^
^ ^
^ 1 ^
^ 2 ^
^ 3 ^
^ 4 ^
^ 5 ^
^ 6 ^
^ 7 ^
^ 8 ^
^ 9 ^
^ 10 ^
^ 11 ^
^ 12 ^
^ 13 ^
^ 14 ^
^ 15 ^
^ 16 ^
^ 17 ^
^ 18 ^
^ 19 ^
^ 20 ^
^ 21 ^
^ -24V (2) 22 -24V (1) ^
^ GND 23 GND ^
^ +24V (2) 24 +24V (1) ^
^ -12V 25 -12V ^
^ GND 26 GND ^
^ +12V 27 +12V ^
^ GND 28 GND ^
^ GND 29 GND ^
^ +5V 30 +5V ^
^ +5V 31 +5V ^
^ +5V 32 +5V ^
^ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲^
S̲W̲I̲T̲C̲H̲ ̲S̲E̲T̲T̲I̲N̲G̲
BASE ADDRESS of the SHARED MEMORY seen from the STI
MODULE:
DIP SWITCH "S1"
̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲
CONTACT NO. ^ ̲1̲ ̲^̲ ̲2̲ ̲^̲ ̲3̲ ̲^̲ ̲4̲ ̲^
OPEN
OPEN = "1" (PRESS DOWN)
̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲
^ CONTACT NO. ^ ^ ^ ^ ^
^ ̲T̲I̲A̲ ̲L̲O̲C̲A̲T̲I̲O̲N̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲^̲ ̲1̲ ̲^̲ ̲2̲ ̲^̲ ̲3̲ ̲^̲ ̲4̲ ̲^
^ ^ ^ ^ ^ ^
^ Rear Slot 16, PU#1 ^ 0 ^ 0 ^ 0 ^ 0 ^
^ Rear Slot 14, PU#1 (SPARE) ^ 0 ^ 0 ^ 0 ^ 0 ^
^ Rear Slot 16, PU#2 ^ 0 ^ 0 ^ 0 ^ 0 ^
^ Rear Slot 14, PU#2 (SPARE) ^ 0 ^ 0 ^ 0 ^ 0 ^
^ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲^̲ ̲ ̲ ̲^̲ ̲ ̲ ̲^̲ ̲ ̲ ̲^̲ ̲ ̲ ̲^
LSB MSB
S̲T̲R̲A̲P̲S̲ ̲S̲E̲T̲T̲I̲N̲G̲S̲
̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲
̲
^ ^ ^ ^ ^ ^ ^ ^ ^
^
^ ̲P̲I̲N̲ ̲B̲L̲O̲C̲K̲ ̲N̲O̲.̲ ̲ ̲ ̲ ̲^̲ ̲1̲ ̲^̲ ̲2̲ ̲^̲ ̲3̲ ̲^̲ ̲4̲ ̲^̲ ̲5̲ ̲^̲ ̲6̲ ̲^̲ ̲7̲ ̲^̲ ̲8̲
̲^
^ ^ ^ ^ ^ ^ ^ ^ ^
^
^ ̲S̲T̲R̲A̲P̲ ̲L̲O̲C̲A̲T̲I̲O̲N̲ ̲ ̲ ̲^̲ ̲A̲ ̲^̲ ̲A̲ ̲^̲ ̲B̲ ̲^̲ ̲B̲ ̲^̲ ̲B̲ ̲^̲ ̲A̲ ̲^̲ ̲B̲ ̲^̲ ̲A̲
̲^
Her inds`ttes tegning
Her inds`ttes tegning
B̲A̲C̲K̲ ̲P̲L̲A̲N̲E̲ ̲C̲O̲N̲N̲E̲C̲T̲I̲O̲N̲
PIN LAYOUT for the MIDDLE CONNECTOR:
STI MAIN BUS
=
CR80 CHANNEL
BUS
B̲A̲C̲K̲ ̲P̲L̲A̲N̲E̲ ̲C̲O̲N̲N̲E̲C̲T̲I̲O̲N̲
PIN LAYOUT For the LOWER CONNECTOR:
HI-BUS
64 pol. flatcable
S̲W̲I̲T̲C̲H̲ ̲S̲E̲T̲T̲I̲N̲G̲
DEVICE ADDRESS: (DEVICE NO. in the TDX SYSTEM)
DIP SWITCH "S1"
̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲
CONTACT NO. ^ ̲1̲ ̲^̲ ̲2̲ ̲^̲ ̲3̲ ̲^̲ ̲4̲ ̲^
OPEN
OPEN = "1" (PRESS DOWN)
̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲
^ CONTACT NO. ^ ^ ^ ^ ^
^ ̲S̲T̲I̲ ̲L̲O̲C̲A̲T̲I̲O̲N̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲^̲ ̲1̲ ̲^̲ ̲2̲ ̲^̲ ̲3̲ ̲^̲ ̲4̲ ̲^
^ ^ ^ ^ ^ ^
^ Front Slot 18, PU#1 ^ 1 ^ 0 ^ 0 ^ 0 ^
^ Front Slot 18, PU#2 ^ 1 ^ 0 ^ 0 ^ 0 ^
^ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲^̲ ̲ ̲ ̲^̲ ̲ ̲ ̲^̲ ̲ ̲ ̲^̲ ̲ ̲ ̲^
LSB MSB
I/O ADDRESS: (Seen from the CR80)
DIP SWITCH "S2"
̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲
CONTACT NO. ^ ̲1̲ ̲^̲ ̲2̲ ̲^̲ ̲3̲ ̲^̲ ̲4̲ ̲^̲ ̲5̲ ̲^̲ ̲6̲ ̲^̲ ̲7̲ ̲^̲ ̲8̲ ̲^
OPEN
OPEN = "1" (PRESS DOWN)
̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲
̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲
^ CONTACT NO.^ ^ ^ ^ ^ ^ ^
^ ^
^S̲T̲I̲ ̲L̲O̲C̲A̲T̲I̲O̲N̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲^̲ ̲1̲ ̲^̲ ̲2̲ ̲^̲ ̲3̲ ̲^̲ ̲4̲ ̲^̲ ̲5̲ ̲^̲ ̲6̲ ̲^̲
̲7̲ ̲^̲ ̲8̲ ̲^
^ ^ ^ ^ ^ ^ ^ ^
^ ^
^ Front Slot 18, PU#1 ^ 1 ^ 1 ^ 0 ^ 0 ^ 0 ^ 1 ^
0 ^ 0 ^
^ Front Slot 18, PU#2 ^ 1 ^ 1 ^ 0 ^ 0 ^ 0 ^ 1 ^
0 ^ 0 ^
^ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲^̲ ̲ ̲ ̲^̲ ̲ ̲ ̲^̲ ̲ ̲ ̲^̲ ̲ ̲ ̲^̲ ̲ ̲ ̲^̲ ̲ ̲ ̲^̲
̲ ̲ ̲^̲ ̲ ̲ ̲^
^ LSB MSB ^ LSB
MSB ^
^ LOWER 4 BIT ^ UPPER
4 BIT ^
S̲T̲R̲A̲P̲S̲ ̲S̲E̲T̲T̲I̲N̲G̲S̲
̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲
̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲
^ ^ ^ ^ ^ ^ ^ ^ ^ ^
^ ^ ^
^ ̲P̲I̲N̲ ̲B̲L̲O̲C̲K̲ ̲N̲O̲.̲ ̲ ̲^̲ ̲1̲ ̲^̲ ̲2̲ ̲^̲ ̲3̲ ̲^̲ ̲4̲ ̲^̲ ̲5̲ ̲^̲ ̲6̲ ̲^̲ ̲7̲ ̲^̲ ̲8̲ ̲^̲
̲9̲ ̲^̲ ̲1̲0̲^̲ ̲1̲1̲^
^ ^ ^ ^ ^ ^ ^ ^ ^ ^
^ ^ ^
^ ̲S̲T̲R̲A̲P̲ ̲L̲O̲C̲A̲T̲I̲O̲N̲ ̲^̲ ̲B̲ ̲^̲ ̲B̲ ̲^̲ ̲B̲ ̲^̲ ̲B̲ ̲^̲ ̲X̲ ̲^̲ ̲X̲ ̲^̲ ̲A̲ ̲^̲ ̲Y̲ ̲^̲
̲X̲ ̲^̲ ̲X̲ ̲^̲ ̲B̲ ̲^
X = "DO NOT CARE"
Y = FIXED MOUNTED
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MT/RST 4:3:3 840620
L/L ADAPTORS & OPTO T/R L
1…0f…
L/L ADAPTOR OH1 To minimize cable emission when data is transferred
between the TDX UNITS and the peripherals,
the standard V24/V28 voltage levels of +/-12V
are reduced to +/-6V.
Also the wave shape of the signals are changed
(corners are rounded) to reduce harmonic
generation.
A "POWER-On" LED is mounted in the FRONT
PANEL.
Two types of L/L adaptors are connected to
the LTUX-S channels.
TYPE 1 OH2 Transfers the V24 signals of 4 channels (max.
1200 baud in CAMPS).
By means of straps the actual application
is selected.
TYPE 2 OH3 Transfers the V24 signals of 1 channel (max.
9600 baud).
By means of straps the actual application
is selected.
FIBER OPTIC OH4 To avoid emission from the cables
MODEM transferring data between the TDX UNITS and
(OPTO T/R) the peripherals, FIBER OPTIC CABLES are used.
By means of straps the actual application
is selected.
LEDS OH5 The five LEDS provide a continuous indication
of the status of the modem.
"PWR" LED P̲O̲W̲E̲R̲
(green)
This indicator should be ON continuously.
It indictes that the primary power is applied
to the MODEM and that the regulators are
operating satisfactorily.
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MT/RST 4:3:3 840620
L/L ADAPTORS & OPTO T/R L
2…0f…
"RCVL" LED R̲E̲C̲E̲I̲V̲E̲ ̲L̲E̲V̲E̲L̲
(red)
This indicator should be OFF during normal
operation.
If the LED is ON it indicates that the amplitude
of the receive signal does not meet the 3
dB requirement of the minimum acceptable
level; or that the frequency of the received
signal is not correct.
"RTS" LED R̲E̲Q̲U̲E̲S̲T̲ ̲T̲O̲ ̲S̲E̲N̲D̲
(yellow)
This indicator will be ON whenever the REQUEST
TO SEND input signal is present from the
associated device.
"CTS" LED C̲L̲E̲A̲R̲ ̲T̲O̲ ̲S̲E̲N̲D̲
(yellow)
This indicator will be ON whenever the CLEAR
TO SEND output signal is applied to the associated
device.
"SYNC" LED S̲Y̲N̲C̲H̲R̲O̲N̲I̲Z̲A̲T̲I̲O̲N̲
(red)
This indicator should be OFF during normal
operation.
If the LED is ON it indicates that the MODEM
is attempting to establish synchronization.
Further details about the OPTO T/R are described
in LESSON 6:3:1-2.
ADAPTOR The ADAPTORS must be supplied from a
POWER SUPPLY separate 18V AC power supply in the TDX-crate.
Rectifiers and regulators on the adaptor
boards provide the DC voltages of +5V, +/-12V.
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MT/RST 4:4:2 840620
TDX CRATES, WALL OUTLETS L
1…0f…
CRATE FUNCTIONS The TDX crate houses 25 slots in the
FRONT POSITIONS front side of the following modules:
OH 1 T̲D̲X̲ ̲m̲o̲d̲u̲l̲e̲s̲:̲
TDX Controller
BSM-X
LTUX-S
A̲D̲A̲P̲T̲O̲R̲ ̲m̲o̲d̲u̲l̲e̲s̲:̲
L/L Adaptors type 1 (4 channels)
L/L Adaptors type 2 (1 channel)
OPTO Transceivers (1 channel)
1̲ ̲P̲o̲w̲e̲r̲ ̲s̲u̲p̲p̲l̲y̲ for the TDX modules.
MOTHERBOARD OH 2 The modules are plugged into a TDX
motherboard which provides:
- interconnection between the LTUX-S and
adaptor modules via the I/O area.
- power distribution from the front side
PS to the TDX modules and the adaptor
modules (+5V +/-12V)
- communication lines between the BSM-X
and LTUX-S's
- power distribution from the rear side
PS to the adaptor modules (9V AC)
BACK POSITIONS OH 3 In the rear magazine
of the TDX crate, the
following may be mounted:
- Main power panel for mains supply
(mains filter, fuse)
- Adaptor power supply (2x9V AC)
- BP8 back panels.
- TSP (Temp. Supervision Panel)
- BSM-X PANEL
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MT/RST 4:4:2 840620
TDX CRATES, WALL OUTLETS L
2…0f…
INTERNAL OH 4 TDX CRATE internal cable connections.
Only one type of power supply, the 18V AC
adaptor PS in the rear magazine.
OH 5 TDX CRATE (with RESYNC. MODULE) internal
cable connections.
RESYNCHRONIZATION ALARM SIGNAL is monitored
by the CCA on the BSM-X as well as the TSP
signal (LESSON 4:4:3, OH11).
ADAPTOR CRATE OH 6 ADAPTOR CRATE housing only ADAPTORS, BACK
PANELS (BP8), and POWER SUPPLIES
TDX CABLES OH 7 The cable type used as the TDX bus is a two
core shielded RF cable (type T (M) 3078)
with a char. impedance of 100 Ohm.
One cable (two cores) is used as lower bus,
and one cable is used as upper bus.
TERMINATION To prevent reflections on the bus, all cables
must be terminated in b̲o̲t̲h̲ ̲e̲n̲d̲s̲ with a 100
Ohm resistor.
SCREEN To prevent ground loops, the shield must
only
GROUNDING be connected to ground in o̲n̲e̲ rack; normally
the CPU rack.
TDX OUTLET OH 7 Connects O̲N̲E̲ TDX bus - both upper and lower
FUNCTIONS (bus) - to the modules which communicate
via the TDX bus. In the CAMPS system, 2̲ ̲o̲u̲t̲l̲e̲t̲s̲
are connected to each BSM-X module but O̲N̲E̲
outlet is connected to each CTRL, and O̲N̲E̲
outlet is connected to each HOST I/F (TIA)
The termination of the bus cables and the
grounding of the screens are made directly
on the terminal block of the outlet box.
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MT/RST 4:4:2 840620
TDX CRATES, WALL OUTLETS L
3…0f…
OUTLET The bus cable connection on the terminal
CONNECTIONS block is like:
Black ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲^̲T̲R̲A̲N̲S̲M̲I̲T̲.̲(̲J̲1̲)̲^̲R̲E̲C̲E̲I̲V̲E̲.̲(̲J̲2̲)̲^̲
board ^̲C̲T̲R̲L̲ ̲O̲U̲T̲L̲E̲T̲ ̲ ̲ ̲ ̲ ̲^̲ ̲ ̲L̲O̲W̲E̲R̲ ̲B̲U̲S̲ ̲ ̲^̲ ̲ ̲U̲P̲P̲E̲R̲ ̲B̲U̲S̲
̲^̲
^̲O̲T̲H̲E̲R̲ ̲O̲U̲T̲L̲E̲T̲S̲ ̲ ̲ ̲^̲ ̲ ̲U̲P̲P̲E̲R̲ ̲B̲U̲S̲ ̲ ̲^̲ ̲ ̲L̲O̲W̲E̲R̲ ̲B̲U̲S̲
̲^̲
The outlet box contains circuits for signal
adaption to/from the CTRL/DEVICES and provides
galvanic isolation between the bus cable
and the communicating module, i.e. between
the different racks which contain TDX equipment.
BLOCK OH 8 T̲h̲e̲ ̲T̲X̲ ̲p̲a̲r̲t̲: The SPL-D coded data from the
PRINCIPLE transmitting module is transferred to the
TDX bus via tri-state, balanced (differential)
galvanically isolated (trafo) power drivers.
The DISAB (tri-state) signal controls the
driver to be in the high impedance condition.
T̲h̲e̲ ̲R̲X̲ ̲p̲a̲r̲t̲: The SPL-D coded receive data
is transferred from the bus via galvanic
isolators (capacitors) to a high impedance
input differential receiver.
S̲u̲p̲p̲l̲y̲ ̲V̲o̲l̲t̲a̲g̲e̲: The +5V lines, which are
fused on the TDX device modules, supply the
outlet box circuit with power.
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MT/RST 4:4:1 840620
POWER SUPPLIES, BP8 & TSP L
1…0f…
ADAPTOR PS OH1 TDX crates which contain Adaptor Modules
(L/L Adaptor TYP 1 & 2 and Fiber Optic Modems
TYP OM-2) are equipped with a Power Supply
(CR 1102S) which provides the 18V AC to the
modules. The 18V AC is led to the MODULES
via the TDX BACK PLANE MOTHERBOARD.
The Adaptor Power Supply is located in the
REAR MAGAZINE.
TDX PS The TDX modules (TDX CONTR., LTUX-S, and
BSM-X) are supplied with DC power (+5V, +/-12V)
from a Power Supply (CR8022). The DC voltages
are distributed to the MODULES via the TDX
BACK PLANE MOTHERBOARD.
The TDX Power Supply is located in the FRONT
MAGAZINE.
C̲h̲a̲r̲a̲c̲t̲e̲r̲i̲s̲t̲i̲c̲s̲:
+5V (max 32 A) Potmeter adj. to 4.5-5.8V
+12V (max 2.8 A)
-12V (max 1.2 A) …0e…not adjustable…0f…
- All outputs are short circuit protected
(constant current limiter)
- Overvoltage on the output results in immediate
shutdown
- +5V fused (primary) 3.15 A
+/-12V fused (primary) 0.63 A
- Presence of outputs is indicated on LEDs
on the front panel.
PB 8 OH2 The BACK PANEL type 8 interconnects any V24/V28
communicating devices. One PANEL serves 4
channels.
OH3 By means of ON-board straps, the lines can
be interchanged or disconnected.
TSP OH4 The Temperature Supervision Panel (Adaptor)
is used for the connection of a thermostate,
monitoring the temperature of the rack.
TSPs are placed in TDX UNIT No. 1, 3, 5,
7, 9, and 11.
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MT/RST 4:4:3 840620
CCA FUNCTIONS OF THE BSM-X L
1…0f…
CCB OH1 CONFIGURATION CONTROL BUS
OH2
The CONFIGURATION CONTROL BUS is physically
a 16 pol. FLAT CABLE where the serial communication
between the WATCH DOG PROCESSOR UNIT (WDP)
and the associated CRATE CONFIGURATION ADAPTOR
(CCA) on the BUS SWITCH MODULES (BSM-X) takes
place.
4:1:1 The FLAT CABLE is connected as a DAISY CHAIN
OH1 BUS between the respective CCB CONNECTORS
4:3:1 of the BSM-X PANELS.
OH2
4:3:1 15 "MODULE NO.s" are available for the
OH6 ADDRESSING of the CCA of the BSM-X MODULES
in the WATCH DOG SYSTEM.
(SLM: Figure 4.5.4-1)
CCA The CCA FUNCTIONS build in the BSM-X are
FUNCTIONS performed by executing the COMMUNICATION
CYCLES (SERIAL COMMUNICATION) described below.
The communication with the WD is a transmission
of "8 bit words" (serial) with a speed of
4800 baud via the CCB.
OH3 E̲a̲c̲h̲ COMMUNICATION CYCLE comprises four bus
transmissions:
1. The WD transmits ADDR.
(7 ADDR.bits + ADDR. identifier)
2. The WD transmits the COMMAND WORD (7 COMMAND
bits + COMMAND identifier)
3. The CCA transmits the ID WORD = DATA to
the WD (8 data bits)
4. The CCA transmits the COMMAND WORD just
received, to check the transmission (8
status bits).
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MT/RST 4:4:3 840620
CCA FUNCTIONS OF THE BSM-X L
2…0f…
Minimum three of the above COMMUNICATION
CYCLES are necessary to SEND DATA to a CCA:
COMMAND WORD OH4 1. The WD transmits a POINTER.
The 5 LSB of this COMMAND WORD define
the use of the following COMMAND WORD.
2. The WD transmits the COMMAND WORD with
actual DATA.
This COMMAND WORD will specify A/D CONVERSION,
RELAY 1 & 2 etc.
3. STROBE.
This COMMAND WORD (C…0f…6…0e… = "1") loads the
above DATA into the "POINTED" register.
When the bits C…0f…6…0e… and C…0f…5…0e… are logical "0",
then the COMMAND WORD is used as a POINTER
according to the contents of the bits C…0f…0…0e…
- C…0f…4…0e….
When the bits C…0f…6…0e… and C…0f…5…0e… are logical "0" and
"1" respectively, then DATA will be sent
to the BSM-X from the WD.
When the bit C…0f…6…0e… is "1", then the COMMAND
WORD is a STROBE.
COMMANDS OH5 SEL 1 and SEL 2 are TDX BUS SWITCHING
(SEND DATA) COMMANDS from the WD
Black ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲
board ^ ̲ ̲S̲E̲L̲ ̲1̲ ̲ ̲S̲E̲L̲ ̲2̲ ̲ ̲^̲ ̲ ̲B̲U̲S̲ ̲1̲ ̲ ̲B̲U̲S̲ ̲2̲ ̲ ̲^
^ ^ ^
^ "0" "0" ^ OFF OFF ^
^ "0" "1" ^ ON OFF ^
^ "1" "0" ^ OFF ON ^
^ "1" "1" ^ OFF OFF ^
^ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲^̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲^
OH5 BS, COMI 1 and COMI 2 are COMMAND SIGNALS
OH6 from the WD to the TDX CONTR VIA THE BSM-X
MODULE.
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MT/RST 4:4:3 840620
CCA FUNCTIONS OF THE BSM-X L
3…0f…
RELAY 1 OH7 ADDITIONAL OUTPUTS.
RELAY 2
By these two COMMAND SIGNALS from the WD
it is possible to activate the 2 RELAYS on
the BSM-X.
RELAY 1
AOUT 1
BOUT 1
The RELAYS are
RELAY 2 shown PASSIVE
AOUT 2
BOUT 2
(Not used in CAMPS)
A/D OH8-9 CHANNEL SELECT of the MUX on the BSM-X and
CONVERSION A/D CONVERSION of the selected voltage are
performed. The 10 bit information of the
voltage is sent to the WD.
STATUS OH10 Signals from the TDX CONTR. are sent to the
OF THE OH6 WD via the BSM-X together with the LSB
TDX CONTR. AD…0f…o…0e…-AD…0f…1…0e… of the A/D conversion.
AIN 1 OH11 The contents ("0" or "1") of these two
AIN 2 ADDITIONAL INPUTS are sent to the WD.
The "AIN 2" INPUT is connected to the TEMPERATURE
SUPERVISION PANEL (TSP).
The "AIN 1" INPUT is used for the RESYNCHRONIZATION
ALARM SIGNAL (LESSON 4:4:2, OH6).
STATUS OH12 This information is sent to the WD.
OF THE BSM-X
2793A 4:5:1-3
840209 2 of 2
PROGRESS TEST WEEK 4 CAMPS
7 Describe the main difference between the HDLC FRAME
format when TRANSMITTING on the LOWER TDX BUS and
the UPPER TDX BUS, respectively.
8 How does the WATCH DOG supervise the TDX CONTROLLER?
9 How is the TDX BUS connected to the TDX CONTROLLER?
10 How is the TDX BUS connected to the LTUX-S MODULES?
11 The STI indicates P.ERR! What is wrong?
12 Describe an easy method to check the correct switchsetting
(S2) in the STI without removing the module from
the crate.
13 Describe the main performances of the LOW LEVEL
ADAPTOR modules.
14 Describe the main difference between TYP 1 and
TYP 2 LOW LEVEL ADAPTOR.
2793A/rt
840620…02…
GENERAL ABBREVIATIONS
…02……02…CAMPS
DI Discussion
DE Demonstration
L Lecture
GW Group Work
T Test
I Informal Talk
S Self Study
EX Exercise
LG Laboratory Guide
OH Overhead/Handout
2793A
840620
WEEK SPECIFIC ABBREVIATIONS
WEEK NO. 4 CAMPS
HBK CR80 MINICOMPUTER HANDBOOK 82/83
SLM CPS/TCM/005 (SITE LEVEL MAINTENANCE MANUAL)
HWB CPS/SDS/017 (HARDWARE ASSY BREAKDOWN)
STB I CPS/TMA/005 (STUDENT TEXT BOOK, VOL. I)
STB II CPS/TMA/006 (STUDENT TEXT BOOK, VOL.II)
STB III CPS/TMA/024 (STUDENT TEXT BOOK, VOL. III)
SLG CPS/TMA/025 (STUDENT LABORATORY GUIDE)
2793A/rt…02…4:1:4-6
…02…NEN/840620…02……02…1
STUDENT LABORATORY GUIDE
…02… CAMPS
No exercise in Lesson 4:1:4-6
but Instructor Guided practice subjects as follows:
- TDX SYSTEM INTRODUCTION & DEMONSTRATION
- INTRODUCTION OF THE TDX RELATED SECTIONS OF THE
SLM & HWB.
2793A/rt…02…4:2:4-6
…02…NEN/840620…02……02…1
STUDENT LABORATORY GUIDE
…02… CAMPS
T̲D̲X̲ ̲S̲Y̲S̲T̲E̲M̲ ̲S̲T̲A̲T̲U̲S̲ ̲T̲E̲S̲T̲
OBJECTIVES: ENABLE the STUDENT to
- CONFIGURATE a VDU for TDX-CONTROLLER CONNECTION
- STATE the RELATIONSHIP of DEVICE ADDRESS and
LOCATION in the TDX UNITS
- STATE the DIFFERENCE between M&D TDX SYSTEM
TESTS and TDX SYSTEM STATUS TEST
- DESCRIBE the BSM-X BUS SWITCHING
- DESCRIBE the RELATIONSHIP OF BSM-X, TDX-BUS,
and TDX CONTROLLER
REFERENCE: CAMPS SITE LEVEL MAINTENANCE MANUAL, CPS/TCM/005
EXERCISE S̲L̲M̲:̲
GUIDE: SECTION 4.3.3.4, FIGURE 4.3.3.4-2
NOTE! This TEST PROGRAM is part of the APPLICATION
SOFTWARE stored in the TDX CONTROLLER MEMORY.
RESPONSE ON S̲L̲M̲:
THE VDU: SECTION 4.3.3.4, FIGURE 4.3.3.4-2
NOTE! "DEVICE NO." is DECIMAL NO. (See 4:1:1:OH5-7)…86…1
…02… …02… …02… …02…
2793A/rt…02…4:2:4-6
…02…NEN/840620…02……02…2
STUDENT LABORATORY GUIDE
…02… CAMPS
B̲O̲O̲T̲ ̲U̲P̲ ̲P̲R̲O̲C̲E̲D̲U̲R̲E̲S̲ ̲f̲o̲r̲ ̲t̲h̲e̲…01…M̲&̲D̲ ̲T̲D̲X̲ ̲S̲Y̲S̲T̲E̲M̲ ̲T̲E̲S̲T̲ ̲P̲R̲O̲G̲R̲A̲M̲S̲
OBJECTIVES: Enable the STUDENTS to BOOT UP the M&D TDX SYSTEM
TEST PROGRAMS from
- FLOPPY DRIVE (FD)
- STORAGE MODULE DRIVE (SMD)
REFERENCE: CAMPS S̲ITE L̲EVEL M̲AINTENANCE MANUAL, CPS/TCM/005
EXERCISE
GUIDE: The following COMMANDS will be entered from the
MAINTENANCE POSITION
l. SELECT an OFF-LINE PU
COMMAND: PU#1 ^ENTER^
or PU#2 ^ENTER^
2. RESET the selected PU
COMMAND: RSET ^ENTER^
3. ENABLE the selected PU
COMMAND: ENPU ^ENTER^
4. ENABLE the "TAKE OWNERSHIP" possibility of
the respective I/O Bus in the CU.
COMMAND: ENTO ^ENTER^
5. ENABLE the respective DISK CONTROLLER.
COMMAND: IR 1A .. ^CR^
MODULE ADDRESS (MA)
2793A/rt…02…4:2:4-6
…02…NEN/840620…02……02…3
STUDENT LABORATORY GUIDE
…02… CAMPS
6. BOOT UP from FLOPPY DRIVE (FD)
NOTE! The TEST PROGRAMS concerning the LTUX-S
MODULES associated one TDX UNIT are stored
in the respective DISKETTE labeled with
the TDX UNIT N̲O̲.
Each of these DISKETTES are also containing
the STI TEST PROGRAM and the TDX BUS TEST
PROGRAM.
6.1 INSERT the selected DISKETTE in FLOPPY DISK
DRIVE [ or 1.
6.2 Perform the BOOT COMMANDS according to S̲L̲M̲,̲
SECTION 4.7.2.1.8, STEP [.
7. BOOT UP from STORAGE MODULE DRIVE (SMD).
NOTE! The TEST PROGRAMS concerning the LTUX-S
MODULES associated one TDX UNIT are stored
in the FILE numbered with the BFD NO. according
to the table below.
Each of these FILES are also containing
the STI TEST PROGRAM and the TDX BUS TEST
PROGRAM.
TDX SYSTEM TEST PROGRAMS STORED ON THE
DISK PACK:
̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲
^ ̲ ̲T̲D̲X̲ ̲U̲N̲I̲T̲ ̲N̲O̲.̲ ̲^̲ ̲ ̲ ̲ ̲B̲F̲D̲ ̲N̲O̲.̲ ̲ ̲ ̲ ̲^
^ ^ ^
^ 1-5 ^ 2E6 ^
^ 6-A ^ 2E7 ^
^ B-F ^ 2E8 ^
^ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲^̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲^
7.1 INSTALL the DISK PACK in the SMD,
7.2 Perform the BOOT COMMANDS according to S̲L̲M̲,̲
SECTION 4.7.2.1.8, STEP [.
2793A/rt…02…4:2:4-6
…02…NEN/840620…02……02…4
STUDENT LABORATORY GUIDE
…02… CAMPS
S̲T̲I̲ ̲T̲E̲S̲T̲
OBJECTIVES: ENABLE the STUDENT to
- STATE the TDX DEVICES which are ACCESSED by
the TEST
- DESCRIBE the FUNCTION of the TEST
- BOOT UP the TEST PROGRAM
- FULFIL an ERROR FREE TEST
- STATE the RESPONSE appearing on the VDU
- STATE the ERROR CODES and MESSAGES
REFERENCE: CAMPS SITE LEVEL MAINTENANCE MANUAL, CPS/TCM/005
EXERCISE S̲L̲M̲:
GUIDE: SECTION 4.7.2.1.8, STEP 2-5
RESPONSE ON S̲L̲M̲:̲
THE VDU: SECTION 4.7.2.2, POINT g.2
ERROR CODES S̲L̲M̲:
AND MESSAGES: SECTION 4.7.2.2, POINTS g.8 and g.9
2793A/rt…02…4:3:4-6
…02…NEN/840620…02……02…1
STUDENT LABORATORY GUIDE
…02… CAMPS
T̲D̲X̲ ̲B̲U̲S̲ ̲T̲E̲S̲T̲
OBJECTIVES: ENABLE the STUDENT to
- STATE the TDX DEVICES which are ACCESSED by
the TEST
- DESCRIBE the FUNCTION of the TEST
- BOOT UP the TEST PROGRAM
- FULFIL an ERROR FREE TEST
- STATE the RESPONSE appearing on the VDU
- STATE the ERROR CODES and MESSAGES
REFERENCE: CAMPS S̲ITE L̲EVEL M̲AINTENANCE MANUAL, CPS/TCM/005
EXERCISE S̲L̲M̲:̲
GUIDE: SECTION 4.7.2.1.8, STEP 6-10
RESPONSE ON S̲L̲M̲:̲
THE VDU: SECTION 4.7.2.2, POINT g.3
ERROR CODES S̲L̲M̲:̲
AND MESSAGES: SECTION 4.7.2.2, POINTS g.8 and g.9
…0e…2793A/rt…02…4:3:4-6
…02…NEN/840229…02……02…2
STUDENT LABORATORY GUIDE
…02… CAMPS…0f…
L̲T̲U̲X̲ ̲S̲T̲A̲T̲U̲S̲ ̲T̲E̲S̲T̲
OBJECTIVES: ENABLE the STUDENT to
- STATE the TDX DEVICES which are ACCESSED by
the TEST
- DESCRIBE the FUNCTION of the TEST
- BOOT UP the TEST PROGRAM
- FULFIL an ERROR FREE TEST
- STATE the RESPONSE appearing on the VDU
- STATE the ERROR CODES and MESSAGES
REFERENCE : CAMPS S̲ITE L̲EVEL M̲AINTENANCE MANUAL, CPS/TCM/005
EXERCISE S̲L̲M̲:̲
GUIDE: SECTION 4.7.2.1.8, STEP 11-14
NOTE! The LTUX ̲STATUS "NO." is the respective
LTUX-S PORT ID. (See 4:1:1:OH5-7)
RESPONSE ON S̲L̲M̲:̲
THE VDU: SECTION 4.7.2.2, POINT g.4
ERROR CODES S̲L̲M̲:̲
AND MESSAGES: SECTION 4.7.2.2, POINTS g.8 and g.9
2793A/rt…02…4:4:4-6
…02…NEN/840620…02……02…1
STUDENT LABORATORY GUIDE
…02… CAMPS
T̲D̲X̲ ̲L̲T̲U̲X̲ ̲T̲E̲S̲T̲
OBJECTIVES: ENABLE the STUDENT to
- STATE the TDX DEVICES which are ACCESSED by
the TEST
- DESCRIBE the FUNCTION of the TEST
- BOOT UP the TEST PROGRAM
- FULFIL an ERROR FREE TEST
- STATE the RESPONSE appearing on the VDU
- STATE the ERROR CODES and MESSAGES
REFERENCE : CAMPS S̲ITE L̲EVEL M̲AINTENANCE MANUAL, CPS/TCM/005
EXERCISE S̲L̲M̲:̲
GUIDE: SECTION 4.7.2.1.8, STEP 15-18
NOTE! OPEN "NO." is the respective LINE PORT
ID.
(See 4:1:1:OH5-7)
RESPONSE ON S̲L̲M̲:̲
THE VDU: SECTION 4.7.2.2, POINT g.5
ERROR CODES S̲L̲M̲:̲
AND MESSAGES: SECTION 4.7.2.2, POINTS g.8 and g.9
2793A/rt…02…4:4:4-6
…02…NEN/840620…02……02…2
STUDENT LABORATORY GUIDE
…02… CAMPS
T̲D̲X̲ ̲L̲O̲O̲P̲ ̲T̲E̲S̲T̲
OBJECTIVES: ENABLE the STUDENT to
- STATE the TDX DEVICES, ADAPTORS, and PERIPHERALS,
which are ACCESSED by the TEST
- DESCRIBE the FUNCTION of the TEST
- BOOT UP the TEST PROGRAM
- FULFIL an ERROR FREE TEST
- STATE the RESPONSE appearing on the VDU
- STATE the ERROR CODES and MESSAGES
REFERENCE : CAMPS S̲ITE L̲EVEL M̲AINTENANCE MANUAL, CPS/TCM/005
EXERCISE S̲L̲M̲:̲
GUIDE: SECTION 4.7.2.1.8, STEP 19-22
NOTE! LOOP "NO." is the respective LINE PORT
ID.
(See 4:1:1:OH5-7)
RESPONSE ON S̲L̲M̲:̲
THE VDU: SECTION 4.7.2.2, POINT g.6
ERROR CODES S̲L̲M̲:̲
AND MESSAGES: SECTION 4.7.2.2, POINTS g.8 and g.9
…0e… 2793A/rt…02…4:5:4-6
…02…NEN/840620…02……02…1
STUDENT LABORATORY GUIDE
…02… CAMPS…0f…
T̲D̲X̲ ̲V̲D̲U̲ ̲I̲/̲O̲ ̲T̲E̲S̲T̲
OBJECTIVES: ENABLE the STUDENT to
- STATE the TDX DEVICES which are ACCESSED by
the TEST
- DESCRIBE the FUNCTION of the TEST
- BOOT UP the TEST PROGRAM
- FULFIL an ERROR FREE TEST
- STATE the RESPONSE appearing on the VDU
- STATE the ERROR CODES and MESSAGES
REFERENCE : CAMPS S̲ITE L̲EVEL M̲AINTENANCE MANUAL, CPS/TCM/005
EXERCISE S̲L̲M̲:̲
GUIDE: SECTION 4.7.2.1.8, STEP 23-26
NOTE! IO "NO." is the respective LINE PORT ID.
(See 4:1:1:OH5-7)
RESPONSE ON S̲L̲M̲:̲
THE VDU: SECTION 4.7.2.2, POINT g.7
ERROR CODES S̲L̲M̲:̲
AND MESSAGES: SECTION 4.7.2.2, POINTS g.8 and g.9
2793A/rt…02…4:5:4-6
…02…NEN/840620…02……02…2
STUDENT LABORATORY GUIDE
…02… CAMPS
C̲R̲A̲T̲E̲ ̲C̲A̲B̲L̲I̲N̲G̲
OBJECTIVES: ENABLE the STUDENT to identify all cables and cable
connections in the TDX SYSTEM.
REFERENCES: CAMPS HARDWARE ASSEMBLY BREAKDOWN/HARDWARE TREE
(CPS/SDS/017).
OH 4 & 5 of the LESSON 4:4:2.
EXERCISE
GUIDE: Switch OFF the MAINS POWER to the TDX CRATES.
Check all TDX CABLE CONNECTIONS according to this
LAB.GUIDE, page 3-7.
Check the INTERNAL CABLE CONNECTIONS according
the OH4 & 5 of the LESSON 4:4:2.
INSERT/CONNECT the MODULES/CABLES if any are REMOVED/DISCONNECTED.
Switch ON the MAINS POWER.
