top - download
⟦f3d43fd51⟧ Wang Wps File
Length: 22291 (0x5713)
Types: Wang Wps File
Notes: Spelunked
Names: »~ORPHAN70.00«
Derivation
└─⟦16539cad0⟧ Bits:30006110 8" Wang WCS floppy, CR 0175A
└─ ⟦this⟧ »~ORPHAN70.00«
WangText
…00……00……00……00…F…02……00……00…F
E…0a…E…00…E
E D…09…D…0f…D C…0a…C…0d…C…00…C B…08…B…0c…B…01…B…06…A…0a…A…0f…A @…09…@…0d…@…02…@…07…?…0c…?…01…?…07…>…0c…>…86…1 …02…
…02… …02…
…02…
…02…SRA/820527…02……02…#
REDIGERET TESTPROCEDURE 7/3
…02……02…CAMPS
3.7.4.3 T̲e̲s̲t̲ ̲P̲r̲o̲c̲e̲d̲u̲r̲e̲ ̲3̲
This testprocedure serves to verify the Watchdog Processor
System i.e. the Watchdog Processor Unit (WDP), the
Configuration Control Bus Adapter (CCBA), te Channel
Unit Control Panel (CUCP), the TDX Bus Switching Modules
(BSM-Xs) and the Configuration Control Adapters (CCAs).
The DSMT configuration under test is given in appendix
A.
3.7.4.3.1 T̲e̲s̲t̲ ̲S̲e̲t̲ ̲U̲p̲
One copy of the documents mentioned in sc 3.7.3 must
be present in the testroom.
The test is performed via an Operator Console (OC)
which is a printer and keyboard with V24/V28 interface,
a Medium Speed Printer (MSP) , a TEST VDU#1, a TEST
VDU#2, all with OPTO interface and a TEST VDU3 with
V24/V28 interface.
The above mentioned testequipment is connected to the
DSMT system as follows:
1. Substitute the leftmost OPTO transceiver in
the rack C Adapter crate with a V24/V28(L/L)
adapter (1 channel), and connect the OC to
the 24 connector on the front panel of the
adaptor.
2. Connect the MSP to the remaining OPTO transceiver
in the Adapter crate in rack C.
3. Remove the cable connected to the V24/V28(L/L)
adapter in the adapter crate pos. 18 and substitute
the adater with an OPTO transceiver. Connect
the TEST VDU#1 to this OPTO transceiver.
4. Remove the cable connected to the V24/V28(L/L)
adapter in the adapter crate pos. 17 and substitute
the adapter with an OPTO transceiver. Connect
the TEST VDU#2 to his OPTO transceiver.
5. Disconnect the two V24 cables connected to
the J1 and J2 connectors on the leftmost Back
Panel 8 located in the rear of the Adapter
crate.…86…1 …02… …02… …02… …02…
6. Disconnect the V24 cable connected to the MIA
in PU#1 and connect TESTCABLE#1 between above
mentioned (para. 5) J1 and the MIA.
7. Disconnect the V24 cable connected to theMIA
in PU#2 and connect TESTCABLE#2 between above
mentioned (para. 5) J2 and the MIA.
8. Disconnect the two V24 cables connected to
J1 and J2 respectively on the WCA front panel
in the rear crate of the WDP.
9. Connect TESTCABLE#3 between theabove mentioned
(para. 8) J1 and J2.
The testequipment is now connected to the DSMT system
as shown in fig. 3.7.4.3.1-1.
Carry out/control the following:
a) OC, TEST VDU#1, TEST VDU#2, TEST VDU#3 and MSP
set up:
The communication part of te OC and MSP is set
to:
1) Asynchronous communication
2) 7 bit character length
3) Even parity check/generation
4) 1 stop bit
5) 2400 Baud communication speed
The communication part of the TEST VDU#1, TEST
VDU#2 and TEST VDU#3 is set o:
1) Asynchronous communication
2) 7 bit character length
3) Even parity check/generation
4) 1 stop bit
5) 1200 Baud communication speed
b) Switch settings in PU#1 and PU#2 front crate modules:
1) The NRM/MAIN switch on the MAP modle front
panel is set to NRM.
2) The EN/DIS switch on the MAP module front panel
is set to EN.…86…1 …02… …02… …02… …02…
3) The host number switch (S1) on the PU#2 STI
is set to #01 as follows:
S1,4 : CLOSED
S1,3 : CLOSED
S1,2 : CLOSED
S1,1 : OPEN
c) Switch settings in PU#1 and PU#2 ear crate modules:
1) The Baudrate select switches 1-4 (S1) on the
MAP Interface Adapter (MIA) Printed Circuit
Board (PCB) is set to #7 which corresponds
to a transmission speed of 1200 Baud:
Switch 1: OPEN
Switch 2: OPEN
Switch 3: PEN
Switch 4: CLOSED…86…1 …02… …02… …02… …02…
FIGURE 3.7.4.3.1-1
C̲o̲n̲n̲e̲c̲t̲i̲o̲n̲ ̲o̲f̲ ̲t̲h̲e̲ ̲t̲e̲s̲t̲e̲q̲u̲i̲p̲m̲e̲n̲t̲…86…1 …02… …02… …02… …02…
2) a) The RESET switch on the Configuration Control
Adaptor (CCA) front panel is set away from
RESET.
b) PU#1:
The CCA address switch on the CCA printed
circuit board (PC) is set to 01 hexadecimal.
PU#2:
The CCA address switch on the CCA printed
circuit board (PCB) is set to 02 hexadecimal.
d) Switch settings in CU front crate modules.
1) Switches on the Channel Unit Control Panel
(CUCP) front panel isset as:
a) The CU Bus A Switch DIS/AUTO is set to
AUTO
b) The CU Bus B switch DIS/AUTO is set to
AUTO
c) The Disk Ctrl. No. 1 switch AAEN/AUTO/BAEN
is set to AUTO
d) The Disk Ctrl. No. 2 switch AAEN/AUTO/BAEN
is set to AUTO
e) Te Disk Ctrl. No. 3 switch AAEN/AUTO/BAEN
is set to AUTO
f) The LTU No. 1 switch AAEN/AUTO/BAEN is
set to AUTO
g) The LTU No. 2 switch AAEN/AUTO/BAEN is
set to AUTO
h) The LTU No. 3 switch AAEN/AUTO/BAEN is
set to AUTO
i) The LTU No.4 switch AAEN/AUTO/BAEN is set
to AUTO
k) The LTU No. 5 switch AAEN/AUTO/BAEN is
set to AUTO
l) The SD.FD.CTRL switch AAEN/AUTO/BAEN is
set to AUTO…86…1 …02… …02… …02… …02…
e) Switch settings in CU rear crate modules:
1) a) The RESET switch on the CCA module front
panel is set away from RESET
b) The CCA address switch on the CCA printed
circui board (PCB) is set to 03 hexadecimal.
f) Switch settings in WDP rear crate modules:
1) The EN/DIS switch on the front panel of the
CCBA is set to DIS.
g) Switch settings in TU modules
1) All BSM-Xs:
a) The AUTO/MAN/OFF switch is set o AUTO.
b) The BUS 1/Bus 2 switch is set to BUS 1.
c) The address switch on each BSM-X is set
to 1X hexadecimal, where X equals the number
of the TU in which the actual BSM-X is
situated. E. g. the BSM-X in TU#5 is given
the address 15 hexaecimal. (This should
be carried out prior to the test but can
be verified at this point).
2) All LTUX-Ss:
a) The CH 1 switch ON/OFF is set to ON
b) The CH 2 switch ON/OFF is set to ON
c) The CH 3 switch ON/OFF is set to ON
d) TheCH 4 switch ON/OFF is set to ON
h) Switch settings on frequency stabilizer rack:
1) The input power switch on all three stabilizers
are set to off.
2) The three rotary switches on the By-Pass panel
are all set to the Frequency Stabilizer poition.…86…1
…02… …02… …02… …02…
i) Setting of power switches in Computer racks:
1) Power switch (2) on each Mains switch is set
to "OFF".
2) Power switch (2) on the Disk Drive rear panel
is set to "ON"
) Power switch (1) on the Floppy Disk Drive rear
panel is set to "ON".
4) Power switch (1) on the Watchdog Processor
Unit rear panel is set to "ON".
5) Power switch (2) in the rear crate of PU#1
is set to "ON"
6) Power switch (2) in the rer crate of the CU
is set to "ON"
7) Power switch (2) in the rear crate of the PU#2
is set to "ON".
8) Power switch (2) in the rear panel of each
80D fan unit is set to "ON".
9) Power switch (2) in the rear crate of the Adaptor
Crate is setto "ON"
10) Power switch (1) in the rear panel of the 80S
Blower Unit is set to "ON"
11) Power switch (1) on each CR80D Power supply
(6 front crate mounted modules) is set to "ON".
k) Setting of Power Switche in Line Termination racks:
1 Power Switch (2) on each Mains Switch is set
to "OFF".
2) Power Switch (1) on the rear panel of each
80S Blower Unit is set to "ON".
3) Power Switch (2) in the rear crate of each
TU is set to "ON".…86…1 …02… …02… …02… …02…
4) Power Switch (1) on each CR80S Power Supply
(1 in the front crate of each TU) is set to
"ON".
k) PU#2 cable interchanges
Interchange the TIA#1 (rear crate, slot 15) TDX
cnnection and the TIA#2 (rear crate, slot 16) TDX
connection.
3.7.4.3.2 T̲e̲s̲t̲ ̲I̲n̲i̲t̲i̲a̲l̲i̲z̲a̲t̲i̲o̲n̲
The testengineers and testwitnesses are in the testroom
and ready to perform and supervise the test.
Power Up the DSMT System as follows (Refer to appenix
A):
a) Power Up all connected terminals i.e. VDUs, MSPs,
OC, Communication Analyzers, PTP/PTR, as applicable.
b) The input Power Switch on the front panel of each
Frequency Stabilizer is set to "ON".
c) The power switch (2) on Mains switchno. 1 is set
to "ON" wait 15 secs.
d) The power switch (2) on each of the remaining Mains
Switche is set to "ON".
e) Mount a Disk Pack with the DSMT test software in
Disk Drive no. 2, close the lid and push the drive
back in rack B. Activate th WRITE PROTECT pushbutton.
f) Activate "START" push button on Disk Drive No.
2 and wait until the "READY" indicator stays "ON".
g) Insert a scratch Floppy Disk in each of the two
drives in the Floppy Disk drive of rack B, and
close the lids.
.7.4.3.3 T̲e̲s̲t̲ ̲S̲t̲e̲p̲s̲
The teststeps for testgroup no. 7, testprocedure no.
3 (7/3), is given in the following preceded by a testoverview.
T̲E̲S̲T̲ ̲O̲V̲E̲R̲V̲I̲E̲W̲ T̲E̲S̲T̲ ̲N̲O̲.̲:̲ ̲7̲/̲3̲
F̲U̲N̲C̲T̲I̲O̲N̲:̲ ̲ ̲W̲a̲t̲c̲h̲d̲o̲g̲ ̲P̲r̲o̲c̲e̲s̲s̲o̲r̲ ̲F̲u̲n̲c̲t̲i̲o̲n̲a̲l̲ ̲C̲a̲p̲a̲b̲i̲l̲i̲t̲i̲e̲s̲
̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲
̲ ̲ ̲
Test Case/
Reference Action SRS Reference
̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲
̲ ̲ ̲ ̲
All WDP test N/A
1. WDP V24 interfaces N/A
2. WDP CCBA interfac N/A
3. PU#1 CCA test N/A
4. PU#2 CCA test N/A
5. CU CCA test N/A
6. TU#1 BSM-X test N/A
7. TU#2 BSM-X test N/A
8. TU#3 BSM-X test N/A
9. TU#4 BSM-X test N/A…86…1
…02…
…02…
T̲E̲S̲T̲ ̲O̲V̲E̲R̲V̲I̲E̲W̲ T̲E̲S̲T̲ ̲N̲O̲.̲:̲ ̲7̲/̲3̲
F̲U̲N̲C̲T̲I̲O̲N̲:̲ ̲ ̲W̲a̲t̲c̲h̲d̲o̲g̲ ̲P̲r̲o̲c̲e̲s̲s̲o̲r̲ ̲F̲u̲n̲c̲t̲i̲o̲n̲a̲l̲ ̲C̲a̲p̲a̲b̲i̲l̲i̲t̲i̲e̲s̲
̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲
̲ ̲ ̲
Test Case/
Reference Action SRS Reference
̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲
̲ ̲ ̲ ̲
10. TU#5 BSM-X test N/A
11. TU#6 BSM-X test N/A
12. TU#7 BS-X test N/A
13. TU#8 BSM-X test N/A
14. TU#9 BSM-X test N/A
15. TU#10 BSM-X test N/A
T̲E̲S̲T̲ ̲S̲T̲E̲P̲S̲ T̲E̲S̲T̲
̲N̲O̲.̲:̲
̲7̲/̲3̲/̲1̲
F̲U̲N̲C̲T̲I̲O̲N̲:̲ ̲ ̲W̲a̲t̲c̲h̲d̲o̲g̲ ̲P̲r̲o̲c̲e̲s̲s̲o̲r̲ ̲S̲y̲s̲t̲e̲m̲ ̲T̲e̲s̲t̲
S̲R̲S̲ ̲R̲E̲F̲E̲R̲E̲N̲C̲E̲:̲ ̲ ̲N̲/̲A̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲
̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲
Case Test
Step No. Station Action Expected Results
̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲
̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲
1.1 N/A The EN/DIS switch on N/A
the CCBA front panel
is set to EN
1.2 OC Exaine print out on Refer to appendix
D
the OC sec 5.1
1.3 N/A Examine TEST VDU#1 and Displays in compli-
TEST VDU#2 displays ance with appendix
D
sec. 1.1
1.4 OC Enter from the OC: Refer to appendix
D
PU1(CR) sec. 5.2
10 01 00 00
54 4553 54 0D 0A(CR)
̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲
̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲
Comments:
̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲
̲ ̲
T̲E̲S̲T̲ ̲W̲I̲T̲N̲E̲S̲S̲E̲S̲
TEST QA QAR…86…1
…02…
…02…
…02…
T̲E̲S̲T̲ ̲S̲T̲E̲P̲S̲ T̲E̲S̲T̲
̲N̲O̲.̲:̲
̲7̲/̲3̲/̲1̲
F̲U̲N̲C̲T̲I̲O̲N̲:̲ ̲ ̲W̲a̲t̲c̲h̲d̲o̲g̲ ̲P̲r̲o̲c̲e̲s̲s̲o̲r̲ ̲S̲y̲s̲t̲e̲m̲ ̲T̲e̲s̲t̲
S̲R̲S̲ ̲R̲E̲F̲E̲R̲E̲N̲C̲E̲:̲ ̲ ̲N̲/̲A̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲
̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲
Case Test
Step No. Station Action Expected Results
̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲
̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲
1.5 OC Enter from the OC: Refer to appendix
D
PU2(CR) sec. 5.3
10 02 00 00
5 45 53 54 0D 0A(CR)
1.6 OC Enter from the OC: Refer to appendix
D
LPR(CR) sec. 5.4
10 01 00 00 0D 0A MSP print out:
54 45 53 54 0D 0A(CR) (CR)(LF)TEST(CR)(LF)
̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲
̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲
Comments:
̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲
̲ ̲
T̲E̲S̲T̲ ̲W̲I̲T̲N̲E̲S̲S̲E̲S̲
TEST QA QAR…86…1
…02…
…02…
…02…
T̲E̲S̲T̲ ̲S̲T̲E̲P̲S̲ T̲E̲S̲T̲
̲N̲O̲.̲:̲
̲7̲/̲3̲/̲2̲
F̲U̲N̲C̲T̲I̲O̲N̲:̲ ̲ ̲W̲a̲t̲c̲h̲d̲o̲g̲ ̲P̲r̲o̲c̲e̲s̲s̲o̲r̲ ̲S̲y̲s̲t̲e̲m̲ ̲T̲e̲s̲t̲
S̲R̲S̲ ̲R̲E̲F̲E̲R̲E̲N̲C̲E̲:̲ ̲ ̲N̲/̲A̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲
̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲
Case Test
Step No. Station Action Expected Results
̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲
̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲
2.1 OC Enter from the OC: Refer to appendix
D
CCB(CR) sec. 6.1
A4 01 03(CR)
22 N/A The EN/DIS switch on N/A
the CCBA front panel
is set to DIS
2.3 OC Enter from the OC: Refer to appendix
D
CCB(CR) sec. 6.2
A4 01 03(CR)
2.4 N/A The EN/DIS switch on N/A
the CCBA front panel
is set to EN
̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲
̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲
Comments:
̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲
̲ ̲
T̲E̲S̲T̲ ̲W̲I̲T̲N̲E̲S̲S̲E̲S̲
TEST QA QAR…86…1
…02…
…02…
…02…
T̲E̲S̲T̲ ̲S̲T̲E̲P̲S̲ T̲E̲S̲T̲
̲N̲O̲.̲:̲
̲7̲/̲3̲/̲3̲
F̲U̲N̲C̲T̲I̲O̲N̲:̲ ̲ ̲W̲a̲t̲c̲h̲d̲o̲g̲ ̲P̲r̲o̲c̲e̲s̲s̲o̲r̲ ̲S̲y̲s̲t̲e̲m̲ ̲T̲e̲s̲t̲
S̲R̲S̲ ̲R̲E̲F̲E̲R̲E̲N̲C̲E̲:̲ ̲ ̲N̲/̲A̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲
̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲
Case Test
Step No. Station Action Expected Results
̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲
̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲
3.1 OC Enter from the OC: Refer to appendix
D
CCB(CR) sec. 7.1
A4 01 0E(CR)
32 OC Enter from the OC: Refer to appendix
D
CCB(CR) sec. 7.2
A4 01 01(CR)
3.3 OC Enter from the OC: Refer to appendix
D
CCB(CR) sec. 7.3
A4 01 02(CR)
3.4 OC Enter from the OC: Refer to appendix
D
CCB(CR) sec. 7.4
A4 01 03(CR)
3.5 OC nter from the OC: Refer to appendix
D
CCB(CR) sec. 7.5
A4 01 0F(CR)
3.6 OC Enter from the OC: Refer to appendix
D
CCB(CR) sec. 7.6
94 01 0F 00(CR)
̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲
̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲
Comments:
̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲
T̲E̲S̲T̲ ̲W̲I̲T̲N̲E̲S̲S̲E̲S̲
TEST QA QAR…86…1
…02…
…02…
…02…
T̲E̲S̲T̲ ̲S̲T̲E̲P̲S̲ T̲E̲S̲T̲
̲N̲O̲.̲:̲
̲7̲/̲3̲/̲3̲
F̲U̲N̲C̲T̲I̲O̲N̲:̲ ̲ ̲W̲a̲t̲c̲h̲d̲o̲g̲ ̲P̲r̲o̲c̲e̲s̲s̲o̲r̲ ̲S̲y̲s̲t̲e̲m̲ ̲T̲e̲s̲t̲
S̲R̲S̲ ̲R̲E̲F̲E̲R̲E̲N̲C̲E̲:̲ ̲ ̲N̲/̲A̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲
̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲
Case Test
Step No. Station Action Expected Results
̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲
̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲
3.7 OC Enter from the OC: Refer to appendix
D
CCB(CR) sec. 7.7
98 01 0F 00 00 0(CR)
3.8 Intentionally deleted
3.9 OC Enter from the OC: Refer to appendix
D
CCB(CR) sec. 7.8
98 01 0F 00 01 00(CR) (Disable PU#1)
3.10 OC Enter from the OC: Refer to appendix
D
CCB(CR) sec. 7.9
94 01 0F 00(CR)
3.11 OC Enter from theOC: Refer to appendix
D
CCB(CR) sec. 7.10
98 01 0F 00 04 00(CR) (Enable PU#1,
Maintenance mode)
̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲
̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲
Comments:
̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲
̲ ̲
T̲E̲S̲T̲ ̲W̲I̲T̲N̲E̲S̲S̲E̲S̲
TEST QA QR…86…1
…02…
…02…
…02…
T̲E̲S̲T̲ ̲S̲T̲E̲P̲S̲ T̲E̲S̲T̲
̲N̲O̲.̲:̲
̲7̲/̲3̲/̲3̲
F̲U̲N̲C̲T̲I̲O̲N̲:̲ ̲ ̲W̲a̲t̲c̲h̲d̲o̲g̲ ̲P̲r̲o̲c̲e̲s̲s̲o̲r̲ ̲S̲y̲s̲t̲e̲m̲ ̲T̲e̲s̲t̲
S̲R̲S̲ ̲R̲E̲F̲E̲R̲E̲N̲C̲E̲:̲ ̲ ̲N̲/̲A̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲
̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲
Case Test
Step No. Station Action Expected Results
̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲
̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲
3.12 OC Enter from the OC: Refer to appendix
D
CCB(CR) sec. 7.11
94 01 0F 00(C)
3.13 OC Enter from the OC: Refer to appendix
D
CCB(CR) sec. 7.12
98 01 0F 00 0C 00(CR) (Set Master Clear
PU#1, Maintenance
Mode)
3.14 N/A Depress both …08…CONTROL N/A
SHIFT…08… and …08…CLEAR…08…
on TEST VDU#1.
3.15 OC Enter from the OC: Refer to apendix
D
CCB(CR) sec. 7.13
98 01 0F 00 04 00(CR) (Release Master
Clear PU#1, Maintenance
Mode)
̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲
̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲
Comments:
̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲
̲ ̲
T̲E̲S̲T̲ ̲W̲I̲T̲N̲E̲S̲S̲E̲S̲
TEST QA QAR…86…1
…02…
…02…
…02…
T̲E̲S̲T̲ ̲S̲T̲E̲P̲S̲ T̲E̲S̲T̲
̲N̲O̲.̲:̲
̲7̲/̲3̲/̲3̲
F̲U̲N̲C̲T̲I̲O̲N̲:̲ ̲ ̲W̲a̲t̲c̲h̲d̲o̲g̲ ̲P̲r̲o̲c̲e̲s̲s̲o̲r̲ ̲S̲y̲s̲t̲e̲m̲ ̲T̲e̲s̲t̲
S̲R̲S̲ ̲R̲E̲F̲E̲R̲E̲N̲C̲E̲:̲ ̲ ̲N̲/̲A̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲
̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲
Case Test
Step No. Station Action Expected Results
̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲
̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲
3.16 OC Enter from the OC: Refer to appendix
D
CCB(CR) sec. 7.14
98 01 0F 00 0 00(CR) (PU#1 Normal
Mode)
3.17 OC Enter from the OC: Refer to appendix
D
CCB(CR) sec. 7.15
98 01 0F 00 08 00(CR) (Set Master Clear
PU#1, Normal
Mode)
3.18 N/A Depress both …08…CONTROL N/A
SHIFT…08… and …08…CLEAR…08…
on TEST VDU#1.
3.19 OC Enter fro the OC: Refer to appendix
D
CCB(CR) sec. 7.16
98 01 0F 00 00 00(CR) (Release Master
Clear PU#1, Normal
Mode)
3.20 N/A Examine TEST VDU#1 Display in accordance
Display with appendix
D sec. 1.1
̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲
̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲
Comments:
̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲
̲ ̲
T̲E̲S̲T̲ ̲W̲I̲T̲N̲E̲S̲S̲E̲S̲
TEST QA QAR…86…1
…02…
…02…
…02…
T̲E̲S̲T̲ ̲S̲T̲E̲P̲S̲ T̲E̲S̲T̲
̲N̲O̲.̲:̲
̲7̲/̲3̲/̲4̲
F̲U̲N̲C̲T̲I̲O̲N̲:̲ ̲ ̲W̲a̲t̲c̲h̲d̲o̲g̲ ̲P̲r̲o̲c̲e̲s̲s̲o̲r̲ ̲S̲y̲s̲t̲e̲m̲ ̲T̲e̲s̲t̲
S̲R̲S̲ ̲R̲E̲F̲E̲R̲E̲N̲C̲E̲:̲ ̲ ̲N̲/̲A̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲
̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲
Case Test
Step No. Station Action Expected Results
̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲
̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲
4.1 OC Enter from the OC: Refer to appendix
D
CCB(CR) sec. 8.1
A4 02 0E(CR)
42 OC Enter from the OC: Refer to appendix
D
CCB(CR) sec. 8.2
A4 02 01(CR)
4.3 OC Enter from the OC: Refer to appendix
D
CCB(CR) sec. 8.3
A4 02 02(CR)
4.4 OC Enter from the OC: Refer to appendix
D
CCB(CR) sec. 8.4
A4 02 03(CR)
4.5 OC nter from the OC: Refer to appendix
D
CCB(CR) sec. 8.5
A4 02 0F(CR)
4.6 OC Enter from the OC: Refer to appendix
D
CCB(CR) sec. 8.6
94 02 0F 00(CR)
̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲
̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲
Comments:
̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲
T̲E̲S̲T̲ ̲W̲I̲T̲N̲E̲S̲S̲E̲S̲
TEST QA QAR…86…1
…02…
…02…
…02…
T̲E̲S̲T̲ ̲S̲T̲E̲P̲S̲ T̲E̲S̲T̲
̲N̲O̲.̲:̲
̲7̲/̲3̲/̲4̲
F̲U̲N̲C̲T̲I̲O̲N̲:̲ ̲ ̲W̲a̲t̲c̲h̲d̲o̲g̲ ̲P̲r̲o̲c̲e̲s̲s̲o̲r̲ ̲S̲y̲s̲t̲e̲m̲ ̲T̲e̲s̲t̲
S̲R̲S̲ ̲R̲E̲F̲E̲R̲E̲N̲C̲E̲:̲ ̲ ̲N̲/̲A̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲
̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲
Case Test
Step No. Station Action Expected Results
̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲
̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲
4.7 OC Enter from the OC: Refer to appendix
D
CCB(CR) sec. 8.7
98 02 0F 00 00 0(CR)
4.8 Intentionally deleted
4.9 OC Enter from the OC: Refer to appendix
D
CCB(CR) sec. 8.8
98 02 0F 00 01 00(CR) (PU#2 disable)
4.10 OC Enter from the OC: Refer to appendix
D
CCB(CR) sec. 8.9
94 02 0F 00(CR)
4.11 OC Enter from the C: Refer to appendix
D
CCB(CR) sec. 8.10
98 02 0F 00 04 00(CR) (PU#2 enable,
Maintenance Mode)
̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲
̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲
Comments:
̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲
̲ ̲
T̲E̲S̲T̲ ̲W̲I̲T̲N̲E̲S̲S̲E̲S̲
TEST QA QA…86…1
…02…
…02…
…02…
T̲E̲S̲T̲ ̲S̲T̲E̲P̲S̲ T̲E̲S̲T̲
̲N̲O̲.̲:̲
̲7̲/̲3̲/̲4̲
F̲U̲N̲C̲T̲I̲O̲N̲:̲ ̲ ̲W̲a̲t̲c̲h̲d̲o̲g̲ ̲P̲r̲o̲c̲e̲s̲s̲o̲r̲ ̲S̲y̲s̲t̲e̲m̲ ̲T̲e̲s̲t̲
S̲R̲S̲ ̲R̲E̲F̲E̲R̲E̲N̲C̲E̲:̲ ̲ ̲N̲/̲A̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲
̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲
Case Test
Step No. Station Action Expected Results
̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲
̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲
4.12 OC Enter from the OC: Refer to appendix
D
CCB(CR) sec. 8.11
94 02 0F 00(C)
4.13 OC Enter from the OC: Refer to appendix
D
CCB(CR) sec. 8.12
98 02 0F 00 0C 00(CR) (Set Master Clear
PU#2, Maintenance
Mode)
4.14 N/A Depress both …08…CONTROL N/A
SHIFT…08… and …08…CLEAR…08…
on TEST VDU#2.
4.15 OC Enter from the OC: Refer to apendix
D
CCB(CR) sec. 8.13
98 02 0F 00 04 00(CR) (Release Master
Clear PU#2, Maintenance
Mode)
̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲
̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲
Comments:
̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲
̲ ̲
T̲E̲S̲T̲ ̲W̲I̲T̲N̲E̲S̲S̲E̲S̲
TEST QA QAR…86…1
…02…
…02…
…02…
T̲E̲S̲T̲ ̲S̲T̲E̲P̲S̲ T̲E̲S̲T̲
̲N̲O̲.̲:̲
̲7̲/̲3̲/̲4̲
F̲U̲N̲C̲T̲I̲O̲N̲:̲ ̲ ̲W̲a̲t̲c̲h̲d̲o̲g̲ ̲P̲r̲o̲c̲e̲s̲s̲o̲r̲ ̲S̲y̲s̲t̲e̲m̲ ̲T̲e̲s̲t̲
S̲R̲S̲ ̲R̲E̲F̲E̲R̲E̲N̲C̲E̲:̲ ̲ ̲N̲/̲A̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲
̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲
Case Test
Step No. Station Action Expected Results
̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲
̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲ ̲
4.16 OC Enter from the OC: Refer to appendix
D
CCB(CR) sec. 8.14
98 02 0F 00 0 00(CR) (PU#2 Normal
Mode)
4.17 OC Enter from the OC: Refer to appendix
D
CCB(CR) sec. 8.15
98 02 0F 00 08 00(CR) (Set Master Clear
PU#2, Normal
Mode)
4.18 N/A Depress both …08…CONTROL N/A
SHIFT…08… and …08…CLEAR…08…
on TEST VDU#2.
4.19 OC Enter fro2̲2̲0̲1̲A̲…00…Redigeringskopi tpr 7/3
…00…SRA …00…SRA
…00…M> ikke slettes …00…2̲7̲…00…0̲5̲…00…8̲2̲…00…0̲9̲…00…4̲6̲…00… ̲ ̲ ̲2̲…00…3̲5̲…00… ̲
̲5̲5̲0̲9̲…00…09…00…06…00…82…00…17…00…42…00… ̲ ̲ ̲ ̲…00…40…00… ̲ ̲1115…00…0̲9̲…00…0̲6̲…00…8̲2̲…00…1̲8̲…00…3̲2̲…00…10…00…06…00…82…00…09…00…16…00…0175A…00…
71…00… ̲ ̲ ̲3…00…15…00… 1164…00… ̲ ̲6624…00……09……00…(0…07……86……00…s…00……01……10……05…f…10……11……02……80…*̲J̲…15……05……00……00……00……00……00……00……00…B
e…01……01……00……00……00……00…@…02……00……00…@
?…0a…?…00…?
? >…09…>…0f…> =…0a…=…0d…=…00…=…05…<…09…<…0d…<…02…<…07…;…0b…;…00…;…05…:…0a…:…0e…:
9…08…9…0d…9…02…8…08…8…0d…8…86…1 …02…
…02… …02…
…02…
…02…SRA/820609…02……02…#
REDIGERET TESTPROCEDURE 7/3
…02……02…CAMPS
3.7.4.3 T̲e̲s̲t̲ ̲P̲r̲o̲c̲e̲d̲u̲r̲e̲ ̲3̲
This testprocedure serves to verify the Watchdog Processor
System i.e. the Watchdog Processor Unit (WDP), the
Configuration Control Bus Adapter (CCBA), te Channel
Unit Control Panel (CUCP), the TDX Bus Switching Modules
(BSM-Xs) and the Configuration Control Adapters (CCAs).
The DSMT configuration under test is given in appendix
A.
3.7.4.3.1 T̲e̲s̲t̲ ̲S̲e̲t̲ ̲U̲p̲
One copy of the documents mentioned in sc 3.7.3 must
be present in the testroom.
The test is performed via an Operator Console (OC)
which is a printer and keyboard with V24/V28 interface,
a Medium Speed Printer (MSP) , a TEST VDU#1, a TEST
VDU#2, all with OPTO interface and a TEST VDU3 with
V24/V28 interface.
The above mentioned testequipment is connected to the
DSMT system as follows:
1. Substitute the leftmost OPTO transceiver in
the rack C Adapter crate with a V24/V28(L/L)
adapter (1 channel), and connect the OC to
the 24 connector on the front panel of the
adaptor.
2. Connect the MSP to the remaining OPTO transceiver
in the Adapter crate in rack C.
3. Remove the cable connected to the V24/V28(L/L)
adapter in the adapter crate pos. 18 and substitute
the ada
