|
DataMuseum.dkPresents historical artifacts from the history of: Intel ISIS Floppy Disks |
This is an automatic "excavation" of a thematic subset of
See our Wiki for more about Intel ISIS Floppy Disks Excavated with: AutoArchaeologist - Free & Open Source Software. |
top - download
Length: 4313 (0x10d9)
Types: TextFile
Names: »DDP.USE«
└─⟦af81bc460⟧ Bits:30005550 8" CR80 Floppy CR80FD_0034 ( MATRIX Source and Abs-files )
└─⟦af81bc460⟧ Intel_ISIS_II
└─ ⟦this⟧ »DDP.USE«
LIST S\r ;\r PUBLIC SYSRAM,NOCH\r PUBLIC QHEADS,SPARE1\r PUBLIC START,ID1\r PUBLIC INISP\r PUBLIC CR80NO,PANCO,PANCOM\r PUBLIC ECOND1,ECOND2,ERRPAT\r PUBLIC LCRID,MCRID,EHSCAN\r PUBLIC CR80SS\r PUBLIC IGEPA,IDEPA,OGEPA,ODEPA\r PUBLIC COMM\r PUBLIC RECOV\r ;\r EXTRN SUBENQ,SUBDEQ,SCOMMON\r EXTRN EHINI,OD1\r EXTRN ETIMER\r EXTRN ICTC\r EXTRN HWINIT,DEVNOR\r ;\r S: EQU 16 ;SYSTEM PARAMETER S (NO. OF SPECIAL PROCESSES)\r LINK: EQU 0 ;SYSTEM PARAMETER LINK (NO EXTEND. SYS.)\r ;\r PROROM: EQU 3000H ;PROTOCOL ROUTINE ADDRESSES\r PRORAM: EQU 7400H\r COMM: DEFL PROROM+12H\r IGEPA: DEFL PROROM+9\r IDEPA: DEFL PROROM+3\r OGEPA: DEFL PROROM+6\r ODEPA: DEFL PROROM+0CH\r ;\r ACTC: DEFL 0B0H ;PORT ADDRESSES ON CPU (CTC)\r ;\r NOCH: DEFL 5 ;NO. OF CHANNELS IN LTUX I/F (CH. 0 & 1 INCL.)\r NOBUFIN DEFL 15 ;NO. OF TOTAL INGOING BUFFERS\r NOBUFOUT DEFL 12 ;NO. OF TOTAL OUTGOING BUFFERS\r NOBUF: DEFL 27 ;NO. OF SYSTEM BUFFERS IN LTUX I/F\r NUMMES: DEFL 5 ;NO. OF LEGAL MESSAGES TO BE SEND TO LTUX I/F\r ;\r CSEG\r \r ;NUMBER OF BUFFERS ASSIGNED TO EACH INGOING\r ;AND OUTGOING CHANNEL:\r ;---------------------\r CHSPEC: DB 5 ;NO. OF INGOING BUFFERS IN CH2\r DB 4 ;NO. OF OUTGOING BUFFERS IN CH2\r DB 5 ;NO. OF INGOING BUFFERS IN CH 3\r DB 4 ;NO. OF OUTGOING BUFFERS IN CH 3\r DB 5 ;NO. OF INGOING BUFFERS IN CH 4\r DB 4 ;NO. OF OUTGOING BUFFERS IN CH 4\r \r ;DISTRIBUTION TABLE:\r ;-------------------\r \r *******************************************************************************\r * LTUX DISTRIBUTION TABLE *\r *******************************************************************************\r \r EXTRN PQH5,PQH8\r ;------------------------------------------------------------------------------\r ; MESSAGE CODE LIST :\r \r TABL1: DB 80H ;ESTABLISH CROSSPOINT\r DB 84H ;DELETE CROSSPOINT\r DB 0E0H ;SEND TOTAL CROSSPOINT STATUS\r DB 0E1H ;SEND SINGLE DESTINATION STATUS\r DB 0F2H ;SEND ERROR CONDITION\r \r ;------------------------------------------------------------------------------\r ; PROCESS NO./ROUTINE ADDRESS LIST :\r \r DW 5\r DW 5\r DW 8\r DW 8\r DW ROUT1\r \r ;------------------------------------------------------------------------------\r ; PROCESS Q-HEAD ADDRESS LIST :\r \r DW PQH5\r DW PQH5\r DW PQH8\r DW PQH8\r DW 0\r \r ;------------------------------------------------------------------------------\r \r \r START: LD SP,INISP\r LD A,80H\r LD (PRORAM+30H),A ;LOAD PROTOCOL PARAMETER 'TPIO'\r ;\r CALL PROROM ;CALL PROTOCOL INITIALIZATION (SYNCHRONIZE)\r ;# CPUPIO IS INITALIZED\r ;# LTUX-M IS SYNCHRONIZED WITH FRONT-END\r ;# INTERRUPT VECTORS IS LOADED INTO SIO'S & CTC\r ;# INTERRUPT VECTOR IS LOADED INTO CPU, I REG.\r ;# CTC, CH.1 IS INITIALIZED FOR FRONT-END INTERRUPTS.\r ;\r ;\r LD HL,(ICTC) ;COPY VECTOR INTERRUPT-TABLE TO PROTOCOL RAM\r LD (PRORAM),HL ;(EXCEPT VECTOR FOR CTC, CH.1)\r LD HL,ICTC+4 ;\r LD DE,PRORAM+4 ;\r LD BC,44 ;\r LDIR ;\r ;\r ;\r CALL DEVNOR ;LOAD DEVICE NR.\r ;\r CALL INITQM ;INITIALIZE TQM\r ;\r ;=============================\r ;CREATE APPLICATION PROCESSES.\r ;=============================\r ;\r EXTRN CR80PR,KEYB,PANEL,STATPR,EXEC\r EXTRN SCANPR,TFMINI,IOMINI\r \r CREATE S,5,CR80PR ;CR80 COMMAND PROCESS\r CREATE S,6,KEYB ;KEYBOARD PROCESS\r CREATE S,7,PANEL ;PANEL PROCESS\r CREATE S,8,STATPR ;STATUS TRANSMITTING PROCESS\r CREATE S,9,EXEC ;EXECUTE PROCESS\r CREATE S,10,SCANPR ;INSPECTION PROCESS\r CREATE S,11,TFMINI ;TFK MATRIX PROCESS\r CREATE S,12,IOMINI ;VIDEO-,PULSE-,CAM DEL.- AND INTERCOM. MATRIX PRCESS\r \r ;\r JP GENINI ;GOTO GENERAL INITIALIZATION\r ;\r DDPROC MATRIX,16,4,0 ;CALL DDP MACRO\r ;# ING. & OUTG. TIMEOUT: 1-127 (1-7FH)\r ;# NOTE!!! 1K RAM'S MUST ALLOCATED TO THE LOWEST\r ;# RAM ADDRESSES.\r ;\r ;\r ;\r EXTRN TIMSCA,TIMOUT,TIMOCC,TIMIMP,SALOUT\r EXTRN IO1,IO2,IO3\r ;\r INITQM: TQMINT 12,1 ;INITIALIZE TQM TIMERS\r ;=============================================\r ;DEFINE ALL USER TQM TIMERS, USING THE TQMPR MACRO\r TQMPR R,1,TIMSCA ;\r TQMPR R,2,TIMOUT ;\r TQMPR R,3,TIMOCC ;\r TQMPR R,4,TIMIMP ;\r TQMPR R,5,SALOUT ;\r TQMPR S,6,12 ;\r TQMPR R,7,IO1 ;\r TQMPR R,8,IO2 ;\r TQMPR R,9,IO3 ;\r TQMPR S,10,10 ;\r TQMPR S,11,1 ;\r TQMPR R,12,ETIMER ;TIMER FOR ERROR HANDLING PROCESS MUST BE\r ;INCLUDED\r ;=============================================\r TQMEXI ;\r RET\r END