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RC3741: 300 lpm Band Printer.
RC3742: 600 lpm Band Printer.
RC3743: 900 lpm Band Printer.

. QUALITY PRINTER DESIGNED FOR LONG-LIFE
. ENDLESS BAND CONTAINING CHARACTER SET EASILY EXCHANGED
. NUMBER OF DIFFERENT CHARACTER SETS
. BUILT-IN FAULT DIAGNOSTICS
. LOW-NOICE OPERATION

G_E_N_E_R_A_L_
The RC3741/42/43 band printers represent unsurpassed printout
quality, combining high-speed performances and high reliability
in operation. The printers are designed and manufactured to
provide precise printing over a long life. Initial cost is low -
and so is the maintenance cost. The user>s choice in character
set options is manyfold.

C_H_A_R_A_C_T_E_R_I_S_T_I_C_S_
The character set is contained on (struck on) as an endless,
horizontally running band. Changing print bands is simple - all
adjustments are automatically performed by the printer. A number
of print bands (64 or 96 characters per character set and differ-
ent national alphabets) are available as standard. Further
options can be provided on request. Compressed character spacing
(15 cpi) can be obtained on the smaller models thereby reducing
paper use by 40 percent. Standard character spacing is 10 char-
acters per inch; line length 132 characters. Line spacing is 6 or
8 lines per inch. Paper is controlled by a 12-channel VFU, multi-
copy forms can be used and even on six-part forms a crisp, clean
printing is evident.

The printer is easily attended by the operator and all the prin-
ter operations are constantly monitored by the built-in fault
diagnostics. A test print facility enables a quick check of the
printer condition. The modular design of the printer logics per-
mits field replacement if required. The acoustic cabinet provides
quite operation. In addition, the print band motor is turned off
automatically after 30 seconds without printing.

S_P_E_C_I_F_I_C_A_T_I_O_N_S_ RC3741 RC3742 RC3743

No of characters
in character set: 64 96 64 96 64 96

Print speed, lpm,
nominal value: 300 222 600 440 900 660

Compressed char.-
space option: YES YES YES YES NO NO

Character spacing,
char./inch: 10 or 15 10 or 15 10

Line spacing: 6 or 8 lines per inch

Line length: 132 characters per line

Standard features: 12-channel VFU, fault diagnostics, test print,
dual line spacing pitch, towel ribbon,
paper basket, castors.

Paper width: 4 to 16 3/4 inches

Paper type: Multicopy, up to 6 copies

Power requirements: 220V AC, 1000W 220V AC, 1300W 220V AC, 1100W

Temperature, amb. 10-40C (50-104 F)

Humidity, rel.: 20-80 %, non-condensing

Heat Dissipation: 3600 kJ/t 4700 kJ/t 3950 kJ/t
(2410 BTU/h) (4435 BTU/h) (3746

Sound Level: 67 dB (A)

Mounting: Free-standing (interfaces with system
through 12 m signal cable)
\f

D_I_M_E_N_S_I_O_N_S_ 43

Height: 113 cm (44.5 in)

Width: 86.4 cm (34 in)

Depth: 61 cm (24 in)

Weight: 136 kg(300 lb) 136 kg(300 lb) 159 kg(350 lb)

RCSL No 42-i1565

RC3741: 300 lpm Båndprinter
RC3742: 600 lpm Båndprinter
RC3743: 900 lpm Båndprinter

. KVALITETSPRINTER
. ENDELØSE BÅND MED TEGNSÆT SKIFTES NEMT
. INDBYGGET FEJLFINDINGSUDSTYR
. STØJSVAG DRIFT

G_E_N_E_R_E_L_T_
RC3741/42/43 båndprinterne tilbyder en uovertruffen skriftkvali-
tet kombineret med en høj ydelse og en stor driftssikkerhed. Kon-
struktion og fremstilling af printerne er foregået specielt med
henblik på lang levetid og præsis udskrivning. Både investering
og driftsomkostninger er små. Brugernes valgmuligheder mellem
forskellige tegnsæt er mangfoldige.

K_A_R_A_K_T_E_R_I_S_T_I_K_A_
Tegnsættet er præget på et endeløst, vandret løbende bånd. Det er
en enkel sag at skifte printbånd - printeren udfører selv alle
nødvendige justeringer. Et stort antal printbånd tilbydes som
standard (64 eller 96 tegn per tegnsæt, forskellige nationale
alfabeter). Yderligere options kan tilbydes efter forespørgsel.
På de mindre modeller kan der leveres printbånd med større tegn-
tæthed (15 tegn pr. tomme) - derved kan papirforbruget reduceres
med indtil 40 procent. Standard tegntæthed er 10 tegn pr. tomme;
linielængden 132 tegn. Linietætheden er 6 eller 8 linier pr. tom-
me. Papiret styres af en 12-kanal VFU, flerlagspapir kan benyt-
tes - og selv på 6-lags kopier opnås et klart, rent skriftbil-
lede.

Printeren betjenes nemt af operatøren og alle printerens funk-
tioner overvåges løbende af det indbyggede fejlfindingsudstyr. En
printer-selvtest gør det muligt, hurtigt og nemt at efterprøve
printerens funktioner. Printerstyringens modulære design tillader
udskiftning på stedet, hvis det skulle blive nødvendigt at
erstatte en komponent. Printerkabinettet er bygget med støjsvag
drift for øje - desuden afbrydes motoren til printbåndet efter 30
sekunder uden udskriftsaktivitet.

S_P_E_C_I_F_I_K_A_T_I_O_N_E_R_RC3741 RC3742 RC3743

Tegnsæt, antal tegn: 64 96 64 96 64 96

Skrivehastighed, lpm,
nominel: 300 222 600 440 900 660

Reduceret tegnafstand,
option: JA JA JA JA NEJ NEJ

Tegntæthed, tegn/tomme: 10 eller 15 10 eller 15 10

Linietæthed: 6 eller 8 linier pr. tomme

Linielængde: 132 tegn per linie

Standard udstyr: 12-kanal VFU, fejlfindningsudstyr,
selvtest, to linietætheder, bred
farvebåndsrulle, papirkurv, hjul.

Papirbredde: 4 til 16 3/4 tommer

Papirtype: multi-copy, indtil 6 kopier

Strømforsyning: 220V AC, 1000W 220V AC, 1300W 220V AC, 1100W

Temperatur, omg. 10-40 C

Luftfugtighed, relativ: 20-80%, ikke kondenserende

Varmeafgivelse: 3600 kJ/t 4700 kJ/t 3950 kJ/t

Lydniveau: 67 dB (A)

Montering: fritstående (tilslutning til system
via 12 m kabel)
\f

D_I_M_E_N_S_I_O_N_E_R_

Højde: 113 cm

Bredde: 86,4 cm

Dybde: 61 cm

Vægt: 136 kg 136 kg 159 kg

RCSL 42-i 1566

T_A_B_L_E_ _O_F_ _C_O_N_T_E_N_T_S_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _P_A_G_E_

1. INTRODUCTION .......................................... 1

2. DESIGN OBJECTIVES ..................................... 3
2.1 Word Length ...................................... 3
2.2 Storage Addressing ............................... 3
2.3 Register Structure ............................... 4
2.4 Instruction Format ............................... 4
2.5 Input/Output Structure ........................... 5

3. COMPUTER ORGANIZATION ................................. 7
3.1 Data Formats ..................................... 7
3.2 Number Representation ............................ 7
3.3 Working Registers ................................ 8
3.4 Interruption System .............................. 9
3.5 Input/Output ..................................... 12
3.6 Basic Instruction Formats ........................ 16

4. ARITHMETIC AND LOGICAL INSTRUCTIONS ................... 17
4.1 Instruction Format 1 ............................. 17
4.2 Address and Operand Calculation .................. 18
4.3 Instruction List ................................. 20

5. BRANCH AND CONTINUE INSTRUCTIONS ...................... 25
5.1 Instruction Format 2 ............................. 25
5.2 Address and Operand Calculation .................. 26
5.3 Instruction List ................................. 26

6. SHIFT-ROTATE INSTRUCTIONS ............................. 32
6.1 Format 3 for Shift-Rotate Instructions ........... 32
6.2 Fetch Algorithm for Format 3 ..................... 32
6.3 Instruction List ................................. 33

7. INTERLEVEL INSTRUCTIONS ............................... 35
7.1 Format 3 for Interlevel Instructions ............. 35
7.2 Instruction List ................................. 36
\f

T_A_B_L_E_ _O_F_ _C_O_N_T_E_N_T_S_ _(_c_o_n_t_i_n_u_e_d_)_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _P_A_G_E_

8. INPUT/OUTPUT INSTRUCTIONS ............................. 37
8.1 Format 3 for Input/Output Instructions ........... 37
8.2 Instruction List ................................. 38

9. INSTRUCTION SET ....................................... 41
9.1 Arithmetic and Logical Instructions .............. 41
9.2 Branch and Continue Instructions ................. 42
9.3 Shift-Rotate Instructions ........................ 43
9.4 Interlevel Instructions .......................... 43
9.5 Input/Output Instructions ........................ 44

10. SWITCHES AND INDICATORS ............................... 45
10.1 Processor Front Panel ............................ 45
10.1.1 Switches .................................. 45
10.1.1.1 Bus Switches ..................... 46
10.1.1.2 Debug Mode Switch ................ 46
10.1.2 Indicators ................................ 47
10.1.3 Jack ...................................... 49
10.2 The Debug Console ................................ 49
10.2.1 Activation ................................ 49
10.2.2 Display Commands .......................... 50
10.2.3 Control Commands .......................... 51
10.2.4 Command Parameters ........................ 52
10.3 Installation ..................................... 52

11. INSTRUCTION EXECUTING TIMES ........................... 53
11.1 Address Calculation Times (AT) ................... 53
11.2 Execution Times (ET) ............................. 54
\f

F_1_._ _ _ _ _ _ _ _ _I_N_T_R_O_D_U_C_T_I_O_N_ 1.

The RC3503 is a small, general purpose 16-bit controller with an
outstanding interruption and input/output system. This makes the
computer especially suited for applications such as:

Data and media conversion systems
Communication terminal concentration systems
Front-end computer for larger computer systems
Process supervision and control systems
Controller for a number of medium to low-speed periph-
erals

The main features of the RC3503 are summarized below:

Storage:
The used memory is dynamical, MOS with cycle times of 580 ns. The
word length is 16 bits + 2 parity bits.

32 K words RAM memory is the max. address space.

Storage Addressing:
8-bit bytes and 16-bit words are directly addressable.

Arithmetic:
The arithmetic unit processes 16-bit binary integers in parallel
using twos complement notation.

Interruption Levels:
32 interruption levels are included in the basic version. Can be
expanded to 124 levels.

Working Registers:
The programmer has access to a set of 8 registers per interrup-
tion level. One of the registers in each set contains a program
counter and a carry indicator, whereas the remaining 7 are gene-
ral registers of which 3 are used both as accumulators and index
registers, and 4 as spare registers.
\f

Instruction Set:
The computer has a repertoire of 50 standard instructions of
which 34 refer to storage. All storage reference instructions can
also be specified to operate with their effective address as ope-
rand, i.e. immediate addressing. An instruction consists of 1, 2,
or 3 consecutive words.

Input/Output:
A number of input/output instructions governs the data transfer
between central processor and peripherals. Data transfer between
peripherals and CPU is performed in serial mode, but the data are
treated as parallel data, depending on the characteristics of the
external device in question. Peripherals having high transfer
rates communicate in blocks of words or bytes directly with main
storage. All input/output operations are directed by interrupt
signals. RC3503 is equipped with 32 serial I/O channels. The
number of I/O channels can optional be expanded to 124 channels.

Debug Facilities:
A TTY compatible device can be connected directly to RC3503, and
communicates with the micromachine in RC3503 to simulate a stan-
dard operator panel.

Real Time Clock:
RC3503 is equipped with an onboard Real Time Clock, the frequency
of which is controlled by the debugger. Default the Real Time
Clock frequency is set to 20 ms and connected to the interrupt
level 1.
\f

F_2_._ _ _ _ _ _ _ _ _D_E_S_I_G_N_ _O_B_J_E_C_T_I_V_E_S_ 2.

The primary design objectives of the RC3503 computer were to
construct a low cost computer with a flexible input/output system
and with a powerful instruction set for ease of programming. Fur-
thermore, peripheral devices should be connected to the computer
with a minimum of interfacing. Important considerations in meet-
ing the objectives are explained below.

2_._1_ _ _ _ _ _ _ _W_o_r_d_ _L_e_n_g_t_h_ 2.1

The bits for input/output devices ranges from 1 bit for tele-
communication up to 12 bits for card readers and analog-to-
digital converters. The basic arithmetic operands should there-
fore not be less than 12 bits, preferably a few bits longer; on
the contrary, a very much longer format serves no purpose since
the computer is not intended for administrative data processing.

Because the majority of peripheral equipment transfers 8 bits in
parallel at a time, the word length must also be a multiple of 8
bits in order to optimize the utilization of storage. Cost consi-
derations dictated that the smallest integer which satisfies afo-
resaid conditions should be used, and consequently a word length
of 16 bits was chosen.

2_._2_ _ _ _ _ _ _ _S_t_o_r_a_g_e_ _A_d_d_r_e_s_s_i_n_g_ 2.2

Data are handled most efficiently if they can be addressed di-
rectly, and because of the widespread use of 8-bit bytes, a byte
was adopted as the smallest addressable unit. From an addressing
point of view, the instructions are divided into two classes ac-
cording to whether the storage address refers to bytes or words.

2_._3_ _ _ _ _ _ _ _R_e_g_i_s_t_e_r_ _S_t_r_u_c_t_u_r_e_ 2.3

Internal registers of importance to the programmer are three 16-
bit general registers, one 15-bit program counter, and a carry
indication. The advantage of more than one general register is
that it reduces the number of storage references required in a
given program. The general registers of the RC3503 computer act
both as accumulators and index registers, for which reason the
full instruction set becomes available for address modifications.
The collection of the above-mentioned programable registers is
referred to as a set of working registers.

The computer has not only one set of working registers, but 32
sets, namely one for each interruption level. Hence, we have eli-
minated the storing of current status (program counter, carry,
and accumulators) and loading of new status whenever program
switching is demanded by the interruption system. The response
time for answering an interrupt is thus reduced to a minimum, and
the input/output system is designed to take full advantage of
this fact.

2_._4_ _ _ _ _ _ _ _I_n_s_t_r_u_c_t_i_o_n_ _F_o_r_m_a_t_ 2.4

In principle, an instruction consists of an operation part and an
address part. The operation part specifies an operand code, a re-
sult register (if more than one exists), and an address mode (in-
dexing, immediate, indirect, etc.). The address part is either a
full address or an abbreviated address used in conjunction with
either a fixed page scheme or as a displacement relative to an
index register or the program counter.

For a fixed 16-bit instruction format we have that if the operand
portion expands at the expense of the address, the number of in-
structions, result registers, and address modes taken together
increase, but the usefulness of these instructions is severely
affected due to the limited address range. Reversely, a large
address part reduces the instruction repertoire and its mode fea-
tures so that only a fraction of the entire instruction set may\f

fully utilize the improved address range. As a consequence of
this, it was decided to employ a variable instruction format,
where an instruction may occupy 1, 2, or 3 words.

2_._5_ _ _ _ _ _ _ _I_n_p_u_t_/_O_u_t_p_u_t_ _S_t_r_u_c_t_u_r_e_ 2.5

In the design particular emphasis was put on the construction of
an efficient and versatile input/output system. This is important
because a major part of small computer systems is used for real-
time control where the I/O capability has a profound influence on
the total effectiveness of the system.

A normal approach is to use two types of I/O data channels: (1) a
low speed channel to which character-oriented devices such as
typewriters, paper tape readers, etc. are connected; and (2) a
high-speed channel to which block-oriented devices such as magne-
tic tapes and display units are connected.

Character transfer, via the low-speed channel, is under program
control; and the program must either repeatedly test the channel
status to see when the device becomes available or the device
must respond with an interrupt when it is ready for transmission
of next character. The first approach implies that the central
processor can perform no other operations until all characters
are transmitted, which in many applications are unacceptable. The
efficiency of the second scheme is directly related to the time
it takes to switch from one program to another.

The high-speed channel transfers blocks of data at high rates di-
rectly between storage and I/O devices, independent of program
control once the transfer has been initiated. The transfer is
supervised by additional hardware, normally: (1) a counter for
current storage address; (2) a register for last storage address;
(3) a comparator to detect end of block; (4) facilities to pack
characters into word format and vice versa; and (5) logic to con-
trol the operation of storage during I/O transfers. The hardware
mentioned in (1) to (4) is placed in the device controller for
which reason the cost of the device is significantly increased.\f

The logic mentioned in (5) is incorporated in the central proces-
sor, but because of its complexity it is normally offered as an
option at an additional cost.

Looking at the low-speed channel, it is obvious that the most ad-
vantageous I/O system is one where I/O operations are initiated
by interrupts and program switching time is zero. With regard to
the high-speed channel, it is preferable to keep the block-mode
concept, but desirable to minimize cost. The RC3503 solution to
this problem is to have one data channel to which both low- and
high-speed peripheral equipment may be connected. I/O operations
are under program control and an interrupt signal is generated
whenever a character is ready for transmission. Each interrupt
signal is wired to its own set of working registers, and a fixed
priority order exists among the register sets. Switching from one
program to another is then reduced to merely move a pointer from
the current register set to the new one; and we have in fact an
ideal low-speed channel. Block-oriented devices make use of the
general registers and the inherent arithmetic capabilities of the
central processor, so no extra hardware is needed in the device
controllers. When no I/O operation is in progress, the working
registers are free for normal program execution. The time requi-
red to transmit one character in or out of storage is two storage
cycles, one to execute an I/O instruction and one to the actual
transfer. The maximum transfer rate is thus halved in relation
to a sophisticated high-speed channel, but this difference is
seldom of practical interest for small computers.

The available I/O instructions for data transfer are:

1. Transfer one word between working register W1 and
external device.

3. Transfer a block of words or bytes directly between
storage and external device.

F_ 3_._ _ _ _ _ _ _ _ _C_O_M_P_U_T_E_R_ _O_R_G_A_N_I_Z_A_T_I_O_N_ 3.

3_._1_ _ _ _ _ _ _ _D_a_t_a_ _F_o_r_m_a_t_s_ 3.1

Two data formats are recognized by the RC3503, an 8-bit byte and
a 16-bit word. A word consists of two bytes of which the left-
most byte must have an even storage address.

BYTE BYTE
0 7 8 15

WORD
0 15

Figure 3.1: Data formats.

Storage addresses are always expressed as byte addresses. The
byte locations are numbered consecutively starting with zero.

When an instruction refers to a word in storage, bit 15 in the
effective address is ignored. Thus it is irrelevant whether the
effective address refers to the left or right byte of a word.

3_._2_ _ _ _ _ _ _ _N_u_m_b_e_r_ _R_e_p_r_e_s_e_n_t_a_t_i_o_n_ 3.2

The arithmetic unit of the computer assumes that numerical data
are signed integers represented in twos complement form. In this
notation the left-most bit represents the sign. For positive num-
bers the sign bit is zero, for negative numbers one.

S
0 1 15

Figure 3.2: Integer word.

The negative of a number is obtained by complementing all bits,
including the sign bit, in the number and then adding a 1 to the\f

right-most bit. A signed integer represented by 16 bits is confi-
ned to the range

-32,768 <= integer word <= 32,767.

Other data formats such as various forms of packed data words,
multiple-length fixed-point, and floating-point representations
must be defined by appropriate software routines. The programming
of these routines is greatly simplified by a CARRY indication. If
a carry occurs out of bit 0 in an arithmetic instruction, CARRY
is set to 1, otherwise CARRY is reset to 0. A set of instructions
makes it possible explicitly to set and reset CARRY just as there
is a possibility for branching on the current value of CARRY.

3_._3_ _ _ _ _ _ _ _W_o_r_k_i_n_g_ _R_e_g_i_s_t_e_r_s_ 3.3

Figure 3.3. depicts the working registers, W0 to W3, associated
to each interruption level.

PROGRAM COUNTER CARRY

W0X0
0 14 15
W1 X1
0 15
W2 X2
0 15
W3 X3
0 15

Figure 3.3: A set of working registers.
\f

Registers W1 to W3 are used by the programmer both as accumula-
tors and index registers, in the latter case they are referred to
as X1 to X3. Register W0 occupies, in some respect, an exceptio-
nal position, because bits 0 to 14 specify the program counter,
PC, and bit 15 equals the value of CARRY. Fifteen bits are just
enough to locate any instruction in storage, since instructions
are always an integer number of full words.

Although there is a distinction in interpretation of W0 and the
other registers, they are all alike with respect to instruction
execution. By this we mean that any instruction is executed with
an operand in, say W2, also is executed if the operand were pla-
ced in W0. For example, a LOAD instruction may load any of the
W registers with a word from storage, but of course, loading of
W0 has the special effect of executing a program jump.

Inter register load and store instructions are also provided
which makes it possible to transfer information between W regis-
ters belonging to the same or different interruption levels.

3_._4_ _ _ _ _ _ _ _I_n_t_e_r_r_u_p_t_i_o_n_ _S_y_s_t_e_m_ 3.4

A program interrupt feature permits an automatic switching from
the current program sequence to another sequence in immediate re-
sponse to specific external or internal events. The efficiency of
an interruption system is directly related to the time it takes
the central processor to perform this switching. Therefore, in
the RC3503, we have associated a set of working registers to each
interruption level so switching is reduced to connect a new set
of working registers to the control and arithmetic unit; confer
figure 3.4.
\f

65534 65535
STORAGE
6 7
4 5
2 3
0 1

CONTROL AND
ARITHMETIC UNIT

PRIORITY SELECTION NETWORK

W0 W0 W0
W1 W1 W1
W2 W2 W2
W3 W3 W3

INTERRUPTION 1 31
LEVEL: 0

Figure 3.4: RC3503 block diagram.

The priority selection network contains a 32-bit interrupt req-
uester buffer, IR, of which bits 1 to 31 can collect up to 31
incoming interrupt signals. A one in a bit position corresponds
to an interrupt request, and bit N corresponds to the Nth inter-
ruption level. Bit 0 in register IR occupies an exceptional posi-
tion, because the value of this bit remains one equivalent to a
permanent interrupt request.

Connected to incoming interrupts

IR: 1 - - -
0 1 2 31

Figure 3.5: Interrupt request register.
\f

Simultaneous interrupt signals are served in order of priority
and the signal which is wired to the highest bit number in IR has
highest priority. Input/Output devices with a high transfer rate
should therefore have their interrupt lines wired to the right-
most bits of register IR. If all incoming interrupt signals are
honoured and no new requests arrive, interruption level 0 is au-
tomatically selected.

The interruption system is normally enabled, i.e. an interrupt
request having a priority higher than the current one, causes a
new set of working registers to be activated. In some cases, how-
ever, it is desirable to disable the interruption system for
shorter intervals. In disable mode, other interrupts are indeed
collected, but they cannot change the interruption level, i.e.
the current program proceeds. The two modes are under program
control, and the flip-flop ENABLE is 1 for enable mode, 0 for
disable. Register IR can be set under program control and we may
summarize the supervision of the interruption system as follows:

1. A bit in IR is set to 1 by a request from an I/O device

2. A bit in IR is set to 1 by a request from the program
by the instruction type

INTERLEVEL INSTRUCTIONS

3. The bit in IR, correspondiong to the c_u_r_r_e_n_t_ interrup-
tion level, is cleared by two instruction types

LOAD REGISTER CLEAR INTERRUPT AND ENABLE
I/O INSTRUCTIONS
4. ENABLE is set to 1 by three instruction types

LOAD REGISTER CLEAR INTERRUPT AND ENABLE
INTERLEVEL INSTRUCTIONS
I/O INSTRUCTIONS

5. ENABLE is cleared by the instruction type

INTERLEVEL INSTRUCTIONS

3_._5_ _ _ _ _ _ _ _I_n_p_u_t_/_O_u_t_p_u_t_ 3.5

Any peripheral is connected to the CPU by means of a 4 pairs
cable, which is transformer coupled at both ends secure a very
high noise immunity.

The transmission of data is performed in serial mode whether the
device connected is of parallel or of serial nature. The data
word transferred consists of a 4 bits header and 0 to 16
information bits.
\f

Header Data part

M_M_ "1" X X "1" 0 to 16 information bits
P_P_ 0 1

synchronizing bits

The header contains the following information:

TRANSMISSION F_R_O_M_ _C_P_U_ _T_O_ _P_E_R_I_P_H_E_R_A_L_

"OUTPUT 1 0 0 1 Read data
Header" 1 0 1 1 Read status
1 1 0 1 Write data
1 1 1 1 write control

TRANSMISSION T_O_ _C_P_U_ _F_R_O_M_ _P_E_R_I_P_H_E_R_A_L_

"INPUT 1 0 0 1 16 bits (word)
HEADER" 1 0 1 1 EOI (end of information)
1 1 0 1 8 bits (byte)
1 1 1 1 not used

CENTRAL
PROCESSOR
UNIT

I/O CHANNELS

DEVICE

STATUS

CONTROL

DATA IN

DATA OUT
\f

In principle each device contains 4 16-bit registers. The regis-
ters are 2 data registers (one for each direction of flow), one
control register and one status register. However, for actual de-
vices one or more of the registers may be omitted, some of the
registers may be combined to one, or the register length may be
shortened from 16 bits right down to 1 bit. The central processor
initiates an I/O instruction by selecting the I/O cable leading
to the device addresses whereafter the data are transferred.

Communication may be initiated either by program or by interrupt
from a device. An interrupt is detected on the data line when a
"1" bit is sent to the CPU, and it has not asked for data.

The data flow from the computer to the four device registers and
vice versa is illustrated by 4 general I/O commands. The commands
describe the possible patterns of execution for the I/O channel
and the device controllers, whereas specific details concerning
how data are stored in the computer is postponed to Chapter 8,
where the actual I/O instructions are defined.

Read Status:
The read status command is a request to the device to transfer
the contents of status to working register W1. The number of
status bits and their interpretation is device dependent, but the
following list indicates their nature.

Busy/Available, the busy mode signifies that the pre-
vious operation has not yet been com-
pleted, - available mode the opposite.

Disconnected, i.e. power to the device is switched
of.

Intervention, i.e. the operator has interferred manu-
ally with the device, e.g. he has
switched the typewriter to operate in
off-line mode.
\f

Timer, i.e. the device or the operator has not
completed an operation within a prede-
termined time.

Write Control:
The write control causes an immediate transfer of a control word
from working register W1 to the control register, and the compu-
ter proceeds to the next instruction. When the control operation
is completed, an interrupt is normally generated.

The individual bits in the control register specify commands,
which are executed by the device controller. Examples are:

Generate an interrupt request
Start or stop peripheral equipment
Check or generate parity
Operations such as for magnetic tapes rewind, erase,
upspace, file, etc.

Read Data:
The read data command causes an immediate transfer of information
from data buffer to working register W1 or directly into storage.
The computer is released as soon as this transfer is completed.
When the next character is ready in the device, it is normally
indicated by a new interrupt signal.

Write Data:
The write data command causes an immediate transfer from working
register W1 or directly from storage to the data buffer in the
selected device. The computer is released as soon as this trans-
fer is completed. When the device is ready to receive the next
character, it is normally indicated by a new interrupt. Transfer
of information is done in analogy with read data.

3_._6_ _ _ _ _ _ _ _B_a_s_i_c_ _I_n_s_t_r_u_c_t_i_o_n_ _F_o_r_m_a_t_s_ 3.6

There are three basic formats and the instructions are grouped
according to formats as follows:

Format 1: Arithmetic and Logical instructions
Format 2: Branch and Continue instructions
Format 3: Shift-Rotate, Interlevel, and Input/Output
instructions

The length of instruction Format 1 is one or two words, depending
on whether the 7-bit displacement is sufficient or not for speci-
fying a word in storage. Format 2 has a length of two or three
words also determined by the range of the displacement. Format 3
consists of one word or two words. The chapters to follow define
the RC3503 instruction set. Chapter 9 gives a complete instruc-
tion list with corresponding mnemonics.

F_ 4_._ _ _ _ _ _ _ _ _A_R_I_T_H_M_E_T_I_C_ _A_N_D_ _L_O_G_I_C_A_L_ _I_N_S_T_R_U_C_T_I_O_N_S_ 4.

4_._1_ _ _ _ _ _ _ _I_n_s_t_r_u_c_t_i_o_n_ _F_o_r_m_a_t_ _1_ 4.1

Format 1a: F W X D
0 5 7 9 15

Format 1b: 1 1 1 1 0 W X I n F
0 5 7 9 10 11 15

Format 1c: 1 1 1 1 1 W X I n F
0 5 7 9 10 11 15

A
0 15

Figure 4.1: Instruction format 1.

Format 1 is shown in Figure 4.1 and it is characterized by having
a function or operand code, F, where the left-most bit of the F
field equals 0. The remaining four bits specify therefore 16 ba-
sic instructions, having the numeric codes from 0 to 15.

Format 1a may be regarded as the basic format and the two others
as expansions with the sole purpose of extending the addressing
facilities. Format 1b is derived from the basic format by remo-
ving the original F field to the five right-most positions of the
word, and in the thus released positions the numeric code 30 is
inserted. Code 31 is used in a similar way to specify format 1c.
The length of formats 1a and 1b is one word, but two words are
used in case 1c.

The 2-bit W field specifies one of the four working registers as
the result register. Bits 7 to 8 constitute the X field and this
field selects the current index register, if any. Working regis-
ters W1, W2, and W3 act as index registers when the X field has
the values 1, 2, and 3, respectively, whereas no indexing is spe-
cified when the value is 0. The latter implies that W0 and with
that the program counter cannot be used for address modifica-
tions; in other words relative addressing is not available.
\f

The field D and A supply further information for calculating the
effective address. D specifies a displacement from -64 to 63 by-
tes within a contiguous storage area, and A can be used to di-
rectly address any byte in a page of maximum capacity of max 32
Kwords.

Immediate addressing is specified if the 1-bit I field equals 1.
If immediate addressing is employed, the operand is equal to the
calculated effective address and not to the contents of the loca-
tion to which the effective address points, as is the case when I
= 0.

The n bit (i.e. next) controls a count feature that automatically
increases the contents of the working register which is selected
by the X field. Register W0 is incremented if the X field equals
0. Incrementation takes place for n = 1, and the increment is 2
for instructions which refer to words and 1 for byte references.
The instruction list to follow defines the amount of
incrementation for each instruction.

4_._2_ _ _ _ _ _ _ _A_d_d_r_e_s_s_ _a_n_d_ _O_p_e_r_a_n_d_ _C_a_l_c_u_l_a_t_i_o_n_ 4.2

From the programmer>s point of view storage addresses are always
expressed as byte addresses. The byte locations are numbered con-
secutively from zero to maximum. The effective address, EA, is
calculated on basis of either a displacement, D, or a full
address, A, and probably an index register, X. Each of these
components are treated as signed integers, but when EA refers to
storage, ST, it is interpreted as an unsigned integer of 16 bits.
An example, the effective address -1 refers to storage location
65535.

Figure 4.2 shows the evaluation of the effective address and from
this it is obvious that Format 1c reduces to Format 1b when A e-
quals zero. As previously mentioned, the operand equals for I = 1
the effective address and for I = 0 the contents of the location
specified by EA. Since 1a does not have an I bit, the programmer\f

cannot specify immediate addressing as he wishes. By definition
we have immediate addressing for X field equal to zero, otherwise
not.

The program Counter, W0(0:14), is automatically incremented by
the central processor to point at the next word whenever an in-
struction or part of it is fetched from storage.

The calculation of the effective address and the operand i con-
densed into the following Fetch algorithm:

FORMAT 1a:

Operand
X field EA X field I=0 I=1
00 D 00 - D
01 X1+D 01 ST(X1+D) -
10 X2+D -64<_D<_63 10 ST(X2+D) -
11 X3+D 11 ST(X3+D) -

FORMATS 1b and 1c:
Operand
X field EA X field I=0 I=1
00 A 00 ST(A) A
01 X1+A -32,768<_ 01 ST(X1+A) X1+A
10 X2+A A<_32,767 10 ST(X2+A) X2+A
11 X3+A 11 ST(X3+A) X3+A

Figure 4.2: Address and operand calculation.

Fetch:
FR:= ST(W0); comment Fetch instruction, 1st word;
W0:= W0 + 2; comment Increase Program Counter;
if FR(0:5) < ' 30 and FR(0:5) < ' 31 then
begin comment Extend the displacement to a 16-bit signed
integer;
EA:= 9extFR(9)conFR(9:15)
end;
\f

if FR(0:5) = 30 then EA:= 0;
if FR(0:5) = 31 then
begin comment Fetch instruction, 2nd. word;
EA:=ST(W0); W0:= W0 + 2
end;
if FR(7,8) < ' 0 then EA:= EA + W(FR(7,8)); comment indexing;
Operand:= if I = 1 then EA else ST(EA);
go to Instruction Execution;

4_._3_ _ _ _ _ _ _ _I_n_s_t_r_u_c_t_i_o_n_ _L_i_s_t_ 4.3

This section defines arithmetic and logical instructions. The
CARRY bit is explicitly mentioned if it is altered by an instruc-
tion whose result register is different from W0.

LOAD REGISTER
Load the W register with the storage word addressed or for imme-
diate addressing the effective address of the instruction. The
contents of storage remain unchanged. If count is specified, the
contents of X are increased by 2.

W:= Operand;
if n = 1 then X:= X + 2;

LOAD COMPLEMENT
Load the W register with the twos complement of the storage word
addressed or for immediate addressing the effective address of
the instruction. The contents of storage remain unchanged. Com-
plementation of the maximum negative number yields the maximum
negative number, since it has no positive counterpart. CARRY is
set in accordance with the carry out of position zero. If count
is specified, the contents of X are increased by 2.

W:= - Operand;
CARRY:= carry;
if n = 1 then X:= X + 2;
\f

LOAD INDIRECT
Load the W register with the storage word addressed by the ope-
rand. The contents of storage remain unchanged. If count is spe-
cified, the contents of X are increased by 2.

W:= ST(Operand);
if n = 1 then X:= X + 2;

STORE REGISTER
Store the W register in the storage word addressed. For immediate
addressing and no indexing the W register is stored in the loca-
tion specified by the effective address. For immediate addressing
and indexing the W register is stored in the X register. The W
register remains unchanged. If count is specified, the contents
of X are increased by 2.

if l = 0 then ST(EA):= W;
if l = 1 and X field = 0 then ST(EA):= W;
if l = 1 and X field < ' 0 then X:= W;
if n = 1 then X:= X + 2;

STORE INDIRECT
Store the W register in the storage word addressed by the operand.
The register remains unchanged. If count is specified, the
contents of X are increased by 2.

ST(Operand):= W;
if n = 1 then X:= X + 2;

EXCHANGE STORE AND REGISTER
Store the W register in the storage addressed and the previous
contents of the storage word is loaded into the register. For im-
mediate addressing and no indexing the W register is stored in the
location specified by the effective address and the effective ad-
dress is loaded into the W register. For immediate addressing and
indexing the contents of W and X are exchanged. If count is spe-
cified, the contents of X are increased by 2.
\f

if l = 0 then begin A:= ST(EA); ST(EA):= W; W:= A end;
if l = 1 and X field = 0 then begin ST(EA):= W; W:= EA end;
if l = 1 and X field < ' 0 then begin A:= X; X:= W; W:= A end;
if n = 1 then X:= X + 2;

LOAD BYTE
Load the right half of the W register with the storage byte ad-
dressed and clear the left half of W. For immediate addressing,
the right half of W is loaded by either the left-most or right-
most 8 bits of the effective address of the instruction depending
on whether the effective address is even or odd. The contents of X
are increased by 1.

W(0:7):= 0;
W(8:15):= if EA(15) = 0 then Operand(0:7) else Operand(8:15);
if n = 1 then X:= X + 1;

STORE BYTE
Store the right half of the W register in the storage byte
addressed. The register remains unchanged. Immediate addressing
has the same effect. If count is specified, the contents of X are
increased by 1.

if EA(15) = 0 then ST(EA)(0:7):= W(8:15)
else ST(EA)(8:15):= W(8:15);
if n = 1 then X:= X + 1;

ADD INTEGER WORD
Add to the W register the storage word addressed or for immediate
addressing the effective address of the instruction. The contents
of storage remain unchanged. CARRY is set in accordance with the
carry out of position zero. If count is specified, the contents of
X are increased by 2.

W:= W + Operand;
CARRY:= carry;
if n = 1 then X:= X + 2;
\f

SUBTRACT INTEGER WORD
Subtract from the W register the storage word addressed or for
immediate addressing the effective address of the instruction. The
contents of storage remain unchanged. CARRY is set in accordance
with the carry out of position zero. If count is specified, the
contents of X are increased by 2.

W:= W - Operand;
CARRY:= carry;
if n = 1 then X:= X + 2;

LOGICAL AND
Form the logical AND operation of the W register and the storage
word addressed or for immediate addressing the effective address
of the instruction. The result is placed in the W register. The
contents of storage remain unchanged. If count is specified, the
contents of X are increased by 2.

W:= W and Operand;
if n = 1 then X:= X + 2;
LOGICAL OR
Form the logical OR operation of the W register and the storage
word addressed or for immediate addressing the effective address
of the instruction. The result is placed in the W register. The
contents of storage remain unchanged. If count is specified, the
contents of X are increased by 2.

W:= W or Operand;
if n = 1 then X:= X + 2;

LOGICAL EXCLUSIVE OR
Form the logical EXCLUSIVE OR operation of the W register and the
storage word addressed or for immediate addressing the effective
address of the instruction. The result is placed in the W regi-
ster. The contents of storage remain unchanged. If count is spe-
cified, the contents of X are increased by 2.

W:= W exclusive or Operand;
if n = 1 then X:= X + 2;
\f

LOAD REGISTER CLEAR INTERRUPT AND ENABLE
Load the W register with the operand and clear the current inter-
rupt bit. The interrupt system is enabled. The contents of sto-
rage remain unchanged. If count is specified, the contents of X
are increased by 2.

W:= Operand;
IR(current interrupt):= 0;
ENABLE:= 1;
if n = 1 then X:= X + 2;

READ SWITCHES
Load the W register with the contents of the Front Panel data
switches. If count is specified, the contents of X are increased
by 2.

W:= switches;
if n = 1 then X:= X + 2;

MOVE
Before execution of this instruction W1, W2, and W3 had to be
defined:

W1: Source module Destination module
0 8 15
W2: Source Address
0 15 Word address in
W3: Destination Address the area 0-32 KW
0 15

This instruction moves a word from source place in memory to the
destination place. The two addresses is not needed to be in the
same 64 K bytes memory module. The addressed W and X register is
not destroyed. B.+ 5 - 15 in the instruction are dummy.

The source/destination module in the W1 register has the
following layout:

0/8 4/12 7/15

module no.
0 =' RAM
1 =' ROM

F_ 5_._ _ _ _ _ _ _ _ _B_R_A_N_C_H_ _A_N_D_ _C_O_N_T_I_N_U_E_ _I_N_S_T_R_U_C_T_I_O_N_S_ 5.

5_._1_ _ _ _ _ _ _ _I_n_s_t_r_u_c_t_i_o_n_ _F_o_r_m_a_t_ _2_ 5.1

2a: F W X D
0 5 7 9 15

B
0 15

2b: 1 1 1 1 0 W X I n F
0 5 7 9 10 11 15

B
0 15

2c: 1 1 1 1 1 W X I n F
0 5 7 9 10 11 15

A
0 15

B
0 15

Figure 5.1: Instruction format 2.

Format 2 is shown in figure 5.1 and it is characterized by having
a function or operand code, F, where the left-most two bits of
the F field equal 10. The remaining three bits specify eight
branch instructions, i.e. instructions which break the normal
instruction sequence if a branch condition is satisfied. The
three variations of Format 2 are identical to the corresponding
Formats 1a, 1b, and 1c apart from two exceptions. First, the new
format is extended with one word, namely the B field; and second,
the n bit is interpreted differently.

The 16-bit B field contains a branch address to which the program
jumps if the specified condition is true. Fields X. D, A, and I\f

have no influence on the branch address, but are employed in de-
fining the effective address and the operand exactly as for For-
mat 1.

The n bit (i.e. not), if one, extends the branch instruction with
their logical counterparts, called the continue instructions. The
difference between the two instruction groups is obvious from the
following two algorithms:

Branch Instructions (n = 0):
if condition = true then branch else continue;

Continue Instructions (n = 1):
if condition = true then continue else branch;

A continue instruction, for example,
continue if p ' q
is, of course. equivalent to the branch instruction
branch if p <= q,
but we have preferred not to call them branch instructions since
they do not exist in Format 2a.

5_._2_ _ _ _ _ _ _ _A_d_d_r_e_s_s_ _a_n_d_ _O_p_e_r_a_n_d_ _C_a_l_c_u_l_a_t_i_o_n_ 5.2

The effective address is calculated exactly as defined in the
Fetch algorithm in Chapter 4.2; the same apply to the operand.

5_._3_ _ _ _ _ _ _ _I_n_s_t_r_u_c_t_i_o_n_ _L_i_s_t_ 5.3

This section defines Format 2 instructions. The CARRY bit is un-
altered if no branch occurs, otherwise it is explicitly set to 0
or 1 depending on whether the branch address is even or odd.
Branch instructions are defined for all Format 2 variations,
whereas continue instructions exist in Format 2b and 2c only.
\f

BRANCH IF GREATER
Compare the W register and the operand as signed integers. The
operand equals either the storage word addressed or for immediate
addressing the effective address of the instruction. If the re-
gister is greater than the operand, then branch to location B,
otherwise execute the next instruction in sequence.

W0:= if W ' Operand then B else W0 + 2;

BRANCH IF EQUAL
Compare the W register and the operand as signed integers. The
operand equals either the storage word addressed or for immediate
addressing the effective address of the instruction. If the re-
gister equals the operand, then branch to location B, otherwise
execute the next instruction in sequence.

W0:= if W = Operand then B else W0 + 2;

BRANCH IF LESS
Compare the W register and the operand as signed integers. The
operand equals either the storage word addressed or for immediate
addressing the effective address of the instruction. If the re-
gister is less than the operand, then branch to location B,
otherwise execute the next instruction in sequence.

W0:= if W < Operand then B else W0 + 2;

BRANCH IF GREATER THAN BYTE
Compare the W register and the byte operand extended at the ex-
treme left with zeroes. The byte operand equals the storage byte
addressed, except for immediate addressing where the byte operand
is the left- or right-most 8 bits of the effective address de-
pending on whether the effective address is even or odd. If the
register is greater than the positive operand, then branch to
location B, otherwise execute the next instruction in sequence.

A(0:7):= 0;
A(8:15)= if EA(15) = 0 then Operand(0:7) else Operand(8:15);
W0:= if W ' A then B else W0 + 2;
\f

BRANCH IF EQUAL TO BYTE
Compare the W register and the byte operand extended at the ex-
treme left with zeroes. The byte operand equals the storage byte
addresses; for immediate addressing the byte operand is the left-
or right-most 8 bits of the effective address of the instruction
depending on whether the effective address is even or odd. If the
register equals the extended operand, then branch to location B,
otherwise execute the next instruction in sequence.

A(0:7):= 0;
A(8:15):= if EA(15) = 0 then Operand(0:7) else Operand(8:15)
W0:= if W = A then B else W0 + 2;

BRANCH IF LESS THAN BYTE
Compare the W register and the byte operand extended at the ex-
treme left with zeroes. The byte operand equals the storage byte
addressed; for immediate addressing the byte operand is the left-
or right-most 8 bits of the effective address of the instruction
depending on whether the affective address is even or odd. If the
register is less than the extended operand, then branch to loca-
tion B, otherwise execute the next instruction in sequence.

A(0:7):= 0;
A(8:15):= if EA(15) = 0 then Operand(0:7) else Operand(8:15);
W0:= if W < A then B else W0 + 2;

BRANCH IF ALL SELECTED BITS ARE ZERO
Use the operand as a mask to test selected bits in the W register.
The operand equals either the storage word addressed or for imme-
diate addressing the effective address of the instruction. If all
the selected bits are zero, then branch to location B, otherwise
execute the next instruction in sequence.

A:= W and Operand;
W0:= if A = 0 then B else W0 + 2;
\f

BRANCH IF SELECTED BITS HAVE ODD PARITY
Use the operand as a mask to test selected bits in the W register.
The operand equals either the storage word addressed or for imme-
diate addressing the effective address of the instruction. If all
the selected bits consists of an odd number of ones, then branch
to location B, otherwise execute the next instruction in sequen-
ce.

A:= W and Operand;
W0:= if odd A then B else W0 + 2;

CONTINUE IF GREATER
Compare the W register and the operand as signed integers. The
operand equals either the storage word addressed or for immediate
addressing the effective address of the instruction. If the re-
gister is greater than the operand, then execute the next in-
struction in sequence, otherwise brandh to location B.

W0:= if W ' Operand then W0 + 2 else B;

CONTINUE IF EQUAL
Compare the W register and the operand as signed integers. The
operand equals either the storage word addressed or for immediate
addressing the effective address of the instruction. If the re-
gister equals the operand, then execute the next instruction in
sequence, otherwise branch to location B.

W0:= if W = Operand then W0 + 2 else B;

CONTINUE IF LESS
Compare the W register and the operand as signed integers. The
operand equals either the storage word addressed or for immediate
addressing the effective address of the instruction. If the re-
gister is less than the operand, then execute the next instruc-
tion in sequence, otherwise branch to location B.

W0:= if W < Operand then W0 + 2 else B;
\f

CONTINUE IF GREATER THAN BYTE
Compare the W register and the byte operand extended at the ex-
treme left with zeroes. The byte operand equals the storage byte
addressed; for immediate addressing the byte operand is the left-
or right-most 8 bits of the effective address of the instruction
depending on whether the effective address is even or odd. If the
register is greater than the extended byte operand, then execute
the next instruction in sequence, otherwise branch to location
B.

A(0:7):= 0;
A(8:15):= if EA(15) = 0 then Operand(0:7) else Operand(8:15);
W0:= if W ' A then W0 + 2 else B;

CONTINUE IF EQUAL TO BYTE
Compare the W register and the byte operand extended at the ex-
treme left with zeroes. The byte operand equals the storage byte
addresses; for immediate addressing the byte operand is the left-
or right-most 8 bits of the effective address of the instruction
depending on whether the effective address is even or odd. If the
register equals the extended operand, then execute the next in-
struction in sequence, otherwise branch to location B.

A(0:7):= 0;
A(8:15):= if EA(15) = 0 then Operand(0:7) else Operand(8:15);
W0:= if W = A then W0 + 2 else B;

CONTINUE IF LESS THAN BYTE
Compare the W register and the byte operand extended at the
extreme left with zeroes. The byte operand equals the storage byte
addressed; for immediate addressing the byte operand is the left-
or right-most 8 bits of the effective address of the instruction
depending on whether the effective address is even or odd. If the
register is less than the extended operand, then execute the next
instruction in sequence, otherwise branch to location B.

A(0:7):= 0;
A(8:15):= if EA(15) = 0 then Operand(0:7) else Operand(8:15);
W0:= if W < A then W0 + 2 else B;
\f

CONTINUE IF ALL SELECTED BITS ARE ZERO
Use the operand as a mask to test selected bits in the W register.
The operand equals either the storage word addressed or for
immediate addressing the effective address of the instruction. If
all the selected bits are zero, then execute the next instruction
in sequence, otherwise branch to location B.

A:= W and Operand;
W0:= if A = 0 then W0 + 2 else B;

CONTINUE IF SELECTED BITS HAVE ODD PARITY
Use the operand as a mask to test selected bits in the W
register. The operand equals either the storage word addressed or
for immediate addressing the effective address of the
instruction. If all the selected bits consists of an odd number
of ones, then execute the next instruction in sequence, otherwise
branch to location B.

A:= W and Operand;
W0:= if odd A then W0 + 2 else B;

F_ 6_._ _ _ _ _ _ _ _ _S_H_I_F_T_-_R_O_T_A_T_E_ _I_N_S_T_R_U_C_T_I_O_N_S_ 6.

6_._1_ _ _ _ _ _ _ _F_o_r_m_a_t_ _3_ _f_o_r_ _S_h_i_f_t_-_R_o_t_a_t_e_ _I_n_s_t_r_u_c_t_i_o_n_s_ 6.1

F W X CODE SHIFTS
0 5 7 9 12 15

Figure 6.1: Format 3 for shift-rotate instructions.

The shift-rotate group has a format as illustrated in Figure 6.1
with a function code equal to 28. SHIFTS is a positive integer in
the interval from 0 to 15 which defines the number of shifts if x
= 0. If the X < ' 0 then the shift value is taken from the regi-
ster specified by the x = field (x1, x2, x3) bit 12:15. The 3-bit
CODE field specifies the type of instruction to be executed as
follows
CODE INSTRUCTION

000 Rotate Right
001 Rotate Left
010 Logical Shift Right
011 Logical Shift Left
100 No carry rotate right
101 No carry rotate left
110 Arithmetic Shift Right
111 Undefined

6_._2_ _ _ _ _ _ _ _F_e_t_c_h_ _A_l_g_o_r_i_t_h_m_ _f_o_r_ _F_o_r_m_a_t_ _3_ 6.2

The Fetch algorithm for format 3 instructions becomes very simple
since this format consists of only one word.

Fetch:

FR:= ST(W0); comment Fetch instruction;
W0:= W0 + 2; comment Increase Program Counter;
go to Instruction Execution;

6_._3_ _ _ _ _ _ _ _I_n_s_t_r_u_c_t_i_o_n_ _L_i_s_t_ 6.3

This section defines shift-rotate instructions. The CARRY bit is
explicitly mentioned if it is altered by an instruction whose re-
sult register is different from W0. (The term "con" used in the
following list means "concatenate").

ROTATE RIGHT
Rotate right the contents of CARRY and the W register the number
of places specified by SHIFTS. CARRY is rotated into bit 0 of W,
bit 15 into CARRY.

for SHIFTS:= SHIFTS - 1 step - 1 until 0 do
CARRYconW(0:15):= W(15)conCARRYconW(0:14);

ROTATE LEFT
Rotate left the contents of CARRY and the W register the number
of places specified by SHIFTS. CARRY is rotated into bit 15 of W,
bit 0 into CARRY.

for SHIFTS:= SHIFTS - 1 step - 1 until 0 do
CARRYconW(0:15):= W(0:15)conCARRY;

LOGICAL SHIFT RIGHT
Shift right, with zero insertion in bit 0, the contents of the W
register the number of places specified by SHIFTS.

for SHIFTS:= SHIFTS - 1 step - 1 until 0 do
begin CARRY:= W(15); W(0:15):= 0conW(0:14) end;

LOGICAL SHIFT LEFT
Shift left, woth zero insertion in bit 15, the contents of the W
register the number of places specified by SHIFTS.

for SHIFTS:= SHIFTS - 1 step - 1 until 0 do
begin CARRY:= W(0); W(0:15):= W(1:15)con0 end;
\f

ARITHMETIC SHIFT RIGHT
Shift right, with sign extension in bit 0, the contents of the W
register the number of places specified by SHIFTS.

for SHIFTS:= SHIFTS - 1 step - 1 until 0 do
begin CARRY:= W(15); W(0:15):= W(0)conW(0:14) end;

NO CARRY ROTATE RIGHT
Rotate right the contents of W(0:15) the number of places
specified by SHIFTS. CARRY is not changed. Bit 15 is rotated into
bit 0.

for SHIFTS:= SHIFTS - 1 step - 1 until 0 do
W(0:15):= W(15) con W(0:14);

NO CARRY ROTATE LEFT
Rotate left the contents of W(0:15) the number of places
specified by SHIFTS. CARRY is not changed. Bit 0 is rotated into
bit 15.

for SHIFTS:= SHIFTS - 1 step - 1 until 0 do
W(0:15):= W(1:15) con W(0);

F_ 7_._ _ _ _ _ _ _ _ _I_N_T_E_R_L_E_V_E_L_ _I_N_S_T_R_U_C_T_I_O_N_S_ 7.

7_._1_ _ _ _ _ _ _ _F_o_r_m_a_t_ _3_ _f_o_r_ _I_n_t_e_r_l_e_v_e_l_ _I_n_s_t_r_u_c_t_i_o_n_s_ 7.1

3a: F W X CODE N
0 5 7 9 10 11 15

3c: W X CODE DUMMY
0 4 5 7 9 10 11 15

N < 124
0 8 15

Figure 7.1: Format 3 for interlevel instructions.

The purpose of interlevel instructions is to transfer information
between two working registers belonging to the same or to diffe-
rent interruption levels. They have a format as depicted in
Figure 7.1. W selects a working register in the current interrup-
tion level and X a register belonging to the interruption level
specified by the N field. The interlevel instructions may, in
addition to their normal execution, also control interruption
system. A letter D, E, or S is then used as a suffix to the basic
mnemonic code. The effects of the suffixes and the corresponding
D and E fields are as follows:

Suffix Code Effect on Interruption System
E 01 Enable the interruption system for all
interrupts
D 10 Disable the interruption system for all
interrupts
S 11 Set the interrupt level specified by
the N field

7_._2_ _ _ _ _ _ _ _I_n_s_t_r_u_c_t_i_o_n_ _L_i_s_t_ 7.2

INTERLEVEL LOAD
Load the W register with the working register specified by X from
interruption level N. The contents of X remain unchanged. Control
the status of the interruption system as follows:

W(current level):= X(Nth level);
if CODE = D then ENABLE:= 0;
if CODE = E then ENABLE:= 1;
if CODE = S then INTERRUPT(N):= 1;

INTERLEVEL STORE
Store the W register into the working register specified by X
from interrupt level N. The contents of W remain unchanged.
Control the status of the interruption system as follows:

X(Nth level):= W(current level);
if CODE = D then ENABLE.= 0;
if CODE = E then ENABLE:= 1;
if CODE = S then INTERRUPT(N):= 1;

F_ 8_._ _ _ _ _ _ _ _ _I_N_P_U_T_/_O_U_T_P_U_T_ _I_N_S_T_R_U_C_T_I_O_N_S_ 8.

8_._1_ _ _ _ _ _ _ _F_o_r_m_a_t_ _3_ _f_o_r_ _I_n_p_u_t_/_O_u_t_p_u_t_ _I_n_s_t_r_u_c_t_i_o_n_s_ 8.1

F W X M DEV. NO.
0 5 7 9 11 15

Figure 8.1: Format 3 for input/output instructions.

Figure 8.1 shows the input/output instruction format and it is
characterized by a function code where the left-most four bits
equal 1100. Hence, only two basic input/output instructions
exist. One of them, the read instruction, governs the data trans-
fer from a peripheral device to the computer, whereas the other,
the write instructions, controls the data path in opposite direc-
tion.

Bits 11 to 15 select the device that is to respond to the in-
struction. if bit (11:15) = 0 then the device number is set equal
to the value of current interrupt level. The M field consist of
two bits, which modify the execution of the basic instruction.
The remaining two fields, W and X, pick out two registers for
compare or address purpose, as it appears from the instruction
definitions to follow.

The operation of the device controllers is already explained in
Chapter 3.5, where we introduced four general I/O commands. This
explanation is also valid for the actual I/O instructions. But,
in the previous discussion, we did not define how incoming and
outgoing data are interpreted by the computer nor how data may
influence the instruction sequence. These questions are answered
in the instruction list to follow.

Tables 8.1 and 8.2 show the relations between the M field in the
instruction format and the actual I/O instructions. The second
column connects an I/O instruction to its equivalent general I/O
command; thereby the action taken by the device controllers for
various I/O instructions is determined.
\f

GENERAL I/O INSTRUCTIONS
M I/O COMMANDS
00 Read Data Read Word and Compare
01 Read Status Read Status and Compare
10 Read Data Read Block of bytes
11 Read Data Read Block of Words

Table 8.1: Modifications of basic read instruction.

GENERAL I/O INSTRUCTIONS
M I/O COMMANDS
00 Write Data Write Word and Compare
01 Write Control Write Control and Compare
10 Write Data Write Block of Bytes
11 Write Data Write Block of Words

Table 8.2: Modifications of basic write instruction.

8_._2_ _ _ _ _ _ _ _I_n_s_t_r_u_c_t_i_o_n_ _L_i_s_t_ 8.2

READ STATUS AND COMPARE
Transfer the contents of the STATUS buffer in the selected device
to working register W1. If the contents of register W and X
differ, and End of Information is zero, then clear the current
interrupt bit and repeat the read instruction; otherwise execute
the next instruction in sequence. In any event, the interruption
system is enabled.

A:= X;
W1:= STATUS;
if W < ' A and EOI = 0 then begin IR(current level):=0;
W0:= W0 - 2 end;
ENABLE:= 1;
\f

READ WORD AND COMPARE
Transfer a word from the DATA IN buffer in the selected device to
working register W1. If the contents of registers W and X differ,
and End of Information is zero, then clear the current interrupt
bit and repeat the read instruction; otherwise execute the next
instruction in sequence. In any event, the interruption system is
enabled.

A:= X;
W1:= DATA IN;
if W < ' A and EOI = 0 then begin IR(current level):= 0;
W0:= W0 - 2 end;
ENABLE:= 1;

READ BLOCK OF BYTES
Transfer a byte from the DATA IN buffer in the selected device to
a byte location in storage specified by register X. If X, after
being incremented by 1, differs from W, and End of Information is
zero, then clear the current interrupt and repeat the read
instruction; otherwise execute the next instruction in sequence.
In any event, the interruption system is enabled.

if X(15) = 0 then ST(X)(0:7):= DATA IN(8:15)
else ST(X)(8:15):= DATA IN(8:15);
X:= X + 1;
if W < ' X and EOI = 0 then begin IR(current level):=0;
W0:= W0 - 2 end;
ENABLE:= 1;

READ BLOCK OF WORDS
Transfer a word from the DATA IN buffer in the selected device to
a word location in storage specified by register X. If X, after
being incremented by 2, differs from W, and End of Information is
zero, then clear the current interrupt bit and repeat the read
instruction; otherwise execute the next instruction in sequence.
In any event, the interruption system is enabled.
\f

ST(X):= DATA IN;
X:= X + 2;
if W < ' X and EOI = 0 then begin IR(current level):= 0;
W0:= W0 - 2 end;
ENABLE:= 1;

WRITE CONTROL AND CLEAR
Transfer the contents of register W1 to the CONTROL buffer in the
selected device. If the X field of the instruction equals zero,then
clear the current interrupt bit and execute the next instruction in
sequence; otherwise just execute the next instruction in sequence.
In any event, the interruption system is enabled.

CONTROL:= W1;
if X field = 0 then begin IR(current level):= 0; end;
ENABLE:= 1;

WRITE WORD AND COMPARE
Transfer the contents of register W1 to the DATA OUT buffer in the
selected device. If the contents of register W and X differ, then
repeat the write instruction, otherwise execute the next instruc-
tion in sequence. In any event, the interruption system is en-
abled.

DATA OUT:= W1;
if W < ' X then begin IR(current level):= 0; W0:= W0 - 2 end;
ENABLE:= 1;

WRITE BLOCK OF BYTES
Transfer a byte from the byte location in storage specified by X to
the DATA OUT buffer in the selected device. If X, after being in-
cremented by 1, differs from W, then clear the current interrupt
bit and repeat the write instruction; otherwise execute the next
instruction in sequence. In any event, the interruption system is
enabled.

DATA OUT(8:15):= if X(15) = 0 then ST(X)(0:7) else ST(X)(8:15);
X:= X + 1;
if W < ' X then begin IR(current level):= 0; W0:= W0 - 2 end;
ENABLE:= 1;
\f

F_ 9_._ _ _ _ _ _ _ _ _I_N_S_T_R_U_C_T_I_O_N_ _S_E_T_ 9.

9_._1_ _ _ _ _ _ _ _A_r_i_t_h_m_e_t_i_c_ _a_n_d_ _L_o_g_i_c_a_l_ _I_n_s_t_r_u_c_t_i_o_n_s_ 9.1

Format 1a: F W X D
0 5 7 9 15

Format 1b: 1 1 1 1 0 W X I n F
0 5 7 9 10 11 15

1 1 1 1 1 W X I n F
Format 1c: 0 5 7 9 10 11 15
A

F0 F1 F2 F3 F4
ldr Load Register 0 0 0 0 0
ldc Load Complement 0 0 0 0 1
ldi Load Indirect 0 0 0 1 0
str Store Register 0 0 0 1 1
sti Store Indirect 0 0 1 0 0
xsr Exchange Store and Register 0 0 1 0 1
ldb Load Byte 0 0 1 1 0
stb Store byte 0 0 1 1 1
add Add Integer Word 0 1 0 0 0
sub Subtract Integer Word 0 1 0 0 1
and Logical AND 0 1 0 1 0
lor Logocal OR 0 1 0 1 1
xor Logical Exclusive OR 0 1 1 0 0
lce Load Register Clear Interrupt + Enable 0 1 1 0 1
mov Move Word between Memory Modules 0 1 1 1 0
rsw Read Switches 0 1 1 1 1

9_._2_ _ _ _ _ _ _ _B_r_a_n_c_h_ _a_n_d_ _C_o_n_t_i_n_u_e_ _I_n_s_t_r_u_c_t_i_o_n_s_ 9.2

F W X D
Format 2a: 0 5 7 9 15
B

1 1 1 1 0 W X I n F
Format 2b: 0 5 7 9 10 11 15
B

1 1 1 1 1 W X I n F
Format 2c: 0 5 7 9 10 11 15
A
B

F0 F1 F2 F3 F4
bgw Branch if Greater 1 0 0 0 0
bew Branch if Equal 1 0 0 0 1
blw Branch if Less 1 0 0 1 0
bgb Branch if Greater than Byte 1 0 0 1 1
beb Branch if Equal to Byte 1 0 1 0 0
blb Branch if Less than Byte 1 0 1 0 1
bsz Branch if All Selected Bits are Zero 1 0 1 1 0
bop Branch if Selected Bits have Odd Parity 1 0 1 1 1

Continue instructions as mentioned above, with the suffix
"n" added to the mnemonic code.

9_._3_ _ _ _ _ _ _ _S_h_i_f_t_-_R_o_t_a_t_e_ _I_n_s_t_r_u_c_t_i_o_n_s_ 9.3

Format 3:: F W X CODE SHIFTS
0 1 2 3 4 5 6 7 8 9 12 15

ror Rotate Right 0 0 0 1 1 1 0 0
rol Rotate Left 0 0 1 1 1 1 0 0
lsr Logical Shift Right 0 1 0 1 1 1 0 0
lsl Logical Shift Left 0 1 1 1 1 1 0 0
asr Arithmetic Shift Right 1 1 0 1 1 1 0 0
nrr No carry rotate right 1 0 0 1 1 1 0 0
nrl No carry rotate left 1 0 1 1 1 1 0 0
Undefined 1 1 1 1 1 1 0 0

9_._4_ _ _ _ _ _ _ _I_n_t_e_r_l_e_v_e_l_ _I_n_s_t_r_u_c_t_i_o_n_s_ 9.4

Format 3a: F W X CODE N
0 5 7 9 11 15

Format 3c: F W X CODE DUMMY
5 7 9 11

N < 124
8 15

ild Interlevel Load 1 1 0 1 0
ist Interlevel Store 1 1 0 1 1

Not used 1 1 1 0 1
Format b 1 1 1 1 0
Format c 1 1 1 1 1

9_._5_ _ _ _ _ _ _ _I_n_p_u_t_/_O_u_t_p_u_t_ _I_n_s_t_r_u_c_t_i_o_n_s_ 9.5

Format 3: F W X M Dev. No
0 5 7 9 11 15

F0 F1 F2 F3 F4
rsc Read Status and Compare 0 1 1 1 0 0 0
wcc Write Control and Clear 0 1 - 1 1 0 0 1
rwc Read Word and Compare 0 0 1 1 0 0 0
rbb Read Block of Bytes 1 0 1 1 0 0 0
rbw Read Block of Words 1 1 1 1 0 0 0
wwc Write Word and Compare 0 0 1 1 0 0 1
wbb Write Block of Bytes 1 0 1 1 0 0 1
wbw Write Block of Words 1 1 1 1 0 0 1

F_ 1_0_._ _ _ _ _ _ _ _S_W_I_T_C_H_E_S_ _A_N_D_ _I_N_D_I_C_A_T_O_R_S_ 10.

1_0_._1_ _ _ _ _ _ _P_r_o_c_e_s_s_o_r_ _F_r_o_n_t_ _P_a_n_e_l_ 10.1

The front panel of the processor board contains five switches,
five indicators, and a jack.

1_0_._1_._1_ _ _ _ _S_w_i_t_c_h_e_s_ 10.1.1

All switches are rotary switches with 16 positions, indicated by
the hexadecimal numbers 0 to F. The switches are set by means of
a screwdriver.

1_0_._1_._1_._1_ _ _B_u_s_ _S_w_i_t_c_h_e_s_ 10.1.1.1

The four switches marked BUS are used to supply the processor
with data. There is a switch for bits 0 to 3, 4 to 7, 8 to 11,
and 12 to 15.

1_0_._1_._1_._2_ _ _D_e_b_u_g_ _M_o_d_e_ _S_w_i_t_c_h_ 10.1.1.2

The switch marked MODE is used to select the baud rate for the
debug console (see section 10.1.3) and to control the execution
of the built-in test programs as follows:

M_ S_e_t_t_i_n_g_ B_a_u_d_ _R_a_t_e_ T_e_s_t_ _P_r_o_g_r_a_m_ _E_x_e_c_u_t_i_o_n_

0 , 8 300 bps run test loop
1 , 9 1200 bps run test loop

2 , A 300 bps skip test
3 , B 1200 bps skip test

4 , C 300 bps run test no loop
5 , D 1200 bps run test no loop

6 , E 300 bps skip test
P_ 7 , F 1200 bps skip test

Switch state 8-F same as 0-7, but with blocked terminal mode
("BELL" will not switch to Debug).

E_x_p_l_a_n_a_t_i_o_n_

run test The programs are executed whenever the autoload
button is pressed.

skip test The programs are not executed.

loop The programs are executed in an endless loop.

no loop The programs are executed once.

The test programs are described in the next subsection.

1_0_._1_._2_ _ _ _ _I_n_d_i_c_a_t_o_r_s_ 10.1.2

DI D_i_s_a_b_l_e_d_ _I_n_t_e_r_r_u_p_t_
This lamp, when lit, indicates that the processor is running
in the disabled interrupt mode.

OP O_p_e_r_a_t_i_o_n_
This lamp, when lit, indicates that the processor is running
normally; when it is extinguished, the processor is stopped.

LP L_e_f_t_ _P_a_r_i_t_y_ _E_r_r_o_r_
This lamp, when lit, indicates that a parity error has been
detected during a memory read in the left byte.

This lamp can be extinguished only by a power restart or
autoload.

RP R_i_g_h_t_ _P_a_r_i_t_y_ _E_r_r_o_r_
This lamp, when lit, indicates that a parity error has been
detected during a memory read in the right byte.

This lamp can be extinguished only by the power restart or
autoload.

TM T_e_s_t_ _M_o_d_e_
This lamp, when lit, indicates that the processor is exe-
cuted the built-in test programs.

T_h_e_ _O_P_,_ _L_P_,_ _R_P_,_ _a_n_d_ _T_M_ _l_a_m_p_s_ _i_n_d_i_c_a_t_e_ _t_h_e_ _n_u_m_b_e_r_ _o_f_ _t_h_e_ _t_e_s_t_
p_r_o_g_r_a_m_
TM is the least significant bit in the test program number.
\f

If an error is detected by a test program, one of the
following messages is displayed on the debug console:

1 8_0_8_5_ _C_o_m_m_u_n_i_c_a_t_i_o_n_ _T_e_s_t_
Message: err 1 <dummy' <dummy'
y<5d' gives 6 bytes transmitted data.
y<71' gives 6 bytes received data.

3 C_o_m_m_u_n_i_c_a_t_i_o_n_ _T_e_s_t_
Microprogram request to the debug microprocessor.
Message: none (i_n_d_i_c_a_t_o_r_s_ _o_n_l_y_).

5 W_o_r_k_i_n_g_ _R_e_g_i_s_t_e_r_ _A_d_d_r_e_s_s_ _T_e_s_t_
Message: err 5 <address' <data wanted'
w<address' gives data read.

7 W_o_r_k_i_n_g_ _R_e_g_i_s_t_e_r_ _D_a_t_a_ _T_e_s_t_
Message: err 7 <address' <data wanted'

9 M_e_m_o_r_y_ _A_d_d_r_e_s_s_ _T_e_s_t_
Message: err 9 <o_f_f_s_e_t_ address' <data wanted'
y<40' gives memory module number.
m<module.offset' gives data read.

B M_e_m_o_r_y_ _D_a_t_a_ _T_e_s_t_
Pattern 5555.
Message: err b <offset address' <data wanted'
y<40' gives memory module number.
m<module.offset' gives data read.

D M_e_m_o_r_y_ _D_a_t_a_ _T_e_s_t_
Pattern AAAA.
Message: err d <offset address' <data wanted'
y<40' gives memory module number.
m<module.offset' gives data read.

1_0_._1_._3_ _ _ _ _J_a_c_k_ 10.1.3

The jack, marked CONSOLE, is a 9-pin CANNON jack for connection
of a debug console (a_ _T_e_l_e_t_y_p_e_ _c_o_m_p_a_t_i_b_l_e_ _d_e_v_i_c_e_,_ _c_o_m_p_a_t_i_b_l_e_ _w_i_t_h_
R_C_8_2_2_).

The console must have the following characteristics:

8 data bits per character
No parity bit
1 stop bit
300 or 1200 bps.

The electrical/logical characteristics of the signals in the jack
must conform to Recommendation V.24.

The signals are as follows:

P_i_n_ _N_o_. S_i_g_n_a_l_ _N_a_m_e_
1 +5V
2 +12V
3 received data
4 -12V
5 0V
6 transmitted data
7 0V
8 (not used)
9 0V

1_0_._2_ _ _ _ _ _ _T_h_e_ _D_e_b_u_g_ _C_o_n_s_o_l_e_ 10.2

1_0_._2_._1_ _ _ _ _A_c_t_i_v_a_t_i_o_n_ 10.2.1

The debug console can be activated at any time (if the mode
switch is in the range 0-7) by pressing the BELL key ( CTRL G),
without stopping the instruction execution in the PU.

1_0_._2_._2_ _ _ _ _D_i_s_p_l_a_y_ _C_o_m_m_a_n_d_s_ 10.2.2

Display commands cause eight words of data to be displayed. These
commands are executed in two situations:

1. W_h_e_n_ _a_ _d_i_s_p_l_a_y_ _c_o_m_m_a_n_d_ _i_s_ _e_n_t_e_r_e_d_. Here one can modify the
displayed data by entering new data in its place. Pressing the
space bar will move the cursor one position to the right,
without changing data.

A display command is terminated by pressing one of the follo-
wing keys:

CR Carriage Return terminates the current display
command and causes the debug console to await the
next command.

+ Plus terminates the current display command and
executes a display command for the succeeding
eight words (M,Y) or the eight registers on the
succeeding level (W).

- Minus terminates the current display command and
executes a display command for the preceding eight
words or the eight registers on the preceding le-
vel.

ESC Terminates current command without changing any-
thing. (<ESC' is printed on the console).

2. W_h_e_n_ _a_ _c_o_n_t_r_o_l_ _c_o_m_m_a_n_d_ _i_s_ _t_e_r_m_i_n_a_t_e_d_, the last executed dis-
play command is repeated, but no modification of the displayed
data is allowed. Here the debug console awaits the next com-
mand.

The following display commands are available: (in capital
letters):

M <gadr' M_o_d_i_f_y_ _m_e_m_o_r_y_
Displays the contents of the 8 memory locations
starting at <gadr'.
\f

W <reg' M_o_d_i_f_y_ _w_o_r_k_i_n_g_ _r_e_g_i_s_t_e_r_s_
Displays the contents of the 8 working registers
starting at <reg'.

L <level' M_o_d_i_f_y_ _w_o_r_k_i_n_g_ _r_e_g_i_s_t_e_r_s_
Displays the level number and contents of the 8
working registers belonging to <level'.

Y <yadr' M_o_d_i_f_y_ _c_o_n_t_r_o_l_ _m_i_c_r_o_p_r_o_c_e_s_s_o_r_ _R_A_M_
Displays the contents of the 8 control micropro-
cessor RAM locations starting at <yadr'.

1_0_._2_._3_ _ _ _ _C_o_n_t_r_o_l_ _C_o_m_m_a_n_d_s_ 10.2.3

The following control commands are available (in capital letters):

R R_u_n_
Causes the PU to start instruction execution.

S I_n_s_t_r_u_c_t_i_o_n_ _s_t_o_p_
The PU will execute one instruction, stop, and re-
activate the debug console.

S <steps' M_u_l_t_i_-_i_n_s_t_r_u_c_t_i_o_n_ _s_t_e_p_
The PU will execute <steps' instructions, stop,
and reactivate the debug console.

C I_n_s_t_r_u_c_t_i_o_n_ _s_t_e_p_ _o_n_ _c_u_r_r_e_n_t_ _l_e_v_e_l_
Like S, but on the current level if possible.

C <steps' M_u_l_t_i_-_i_n_s_t_r_u_c_t_i_o_n_ _s_t_e_p_ _o_n_ _c_u_r_r_e_n_t_ _l_e_v_e_l_
Like S <steps', but on the current level if
possible.

1_0_._2_._4_ _ _ _ _C_o_m_m_a_n_d_ _P_a_r_a_m_a_t_e_r_s_ 10.2.4

All numbers entered and displayed are hexadecimal.

At any time the entering of an empty command (i.e. CR) will cause
the previous command to be repeated.

A global address <gadr' is entered in one of the two following
formats:

<base' : <disp'
: <disp'

where

<base' is the leftmost 16 bits of the 32-bit address.
Always 0000 (Hex) for RC3503.

<disp' is the displacement within the selected memory
module, i.e. the rightmost 16 bits of an address.

If the second format ( : <disp' ) is employed, the last entered
base is echoed and used.

<STEP' must always consist of 4 HEX digits.

1_0_._3_ _ _ _ _ _ _I_n_s_t_a_l_l_a_t_i_o_n_ 10.3

Console
jack (CBL 312 for RC822)
(CBL 588 for RC831)

TTY compatible device
(RC822 or RC831)
\f

F_ 1_1_._ _ _ _ _ _ _ _I_N_S_T_R_U_C_T_I_O_N_ _E_X_E_C_U_T_I_N_G_ _T_I_M_E_S_ 11.

In the following sections the following mnemonics mean:
NC (normal cycle) = 217 nS
MR (memory read cycle) = 434 nS
MW (memory write cycle) = 651 nS

1_1_._1_ _ _ _ _ _ _A_d_d_r_e_s_s_ _C_a_l_c_u_l_a_t_i_o_n_ _T_i_m_e_s_ _(_A_T_)_ 11.1

This scheme describes the execution times (AT) for the address
calculation dependent of the format and the index register
selected, and if immediate addressing is selected.

These times must be added to the times listed below for the
instructions to get the total time of an instruction.

Instruction execution time: T = AT + ET.

AT FORMAT 1 & 2 FORMAT 3
a b c
M_m_m_ X = X0 4NC+1MR 8NC+2MR cycles
I = 0
P_p_p_ X <' X0 4NC+1MR 4NC+1MR 8NC+2MR
M_m_m_ X = X0 2NC 2NC 5NC+1MR cycles
I = 1
P_p_p_ X <' X0 2NC 5NC+1MR cycles

FORMAT 3 6NC+1MR cycles

Note 1: All times in the scheme are for Disable mode.
If an enable and fetch on same level add 1NC.
If an enable and fetch on another level add 2NC. \f

1_1_._2_ _ _ _ _ _ _E_x_e_c_u_t_i_o_n_ _T_i_m_e_s_ _(_E_T_)_ 11.2

This scheme describes the times which must be added to the
ADDRESS CALCULATION TIMES (AT) to get the exact execution time
for an instruction.

FORMAT 1 & 2
ldr 2NC
ldc 4NC
ldi 5NC + 1MR
M_m_m_ I = 1 4NC
str
P_p_p_ I = 0 8NC + 1MW
sti 7NC + 1MW
M_m_m_ X <' X0 5NC
xsr
P_p_p_ X = X0 8NC + 1MW
ldb 6NC
stb 7NC + 1MW
add 4NC
sub 4NC
and 3NC
lor 3NC
xor 3NC
lce 9NC
rsw 9NC
Move 19NC + 1MR + 1MW

If count is specified 2NC must be added.

bgw 6NC For branch and continue
bew 3NC instructions the same timing is
blw 6NC valid, if the instruction, however,
bgb 12NC branches, 5NC + 1MR must be added.
beb 9NC
blb 12NC
bsz 3NC
bop 4NC
\f

FORMAT 3
ror
rol
lsr 9NC Add 1NC per shift
lsl
asr

ild 8NC
ist 8NC

rsc 27NC NOTE
wcc - 1,6NC
rwc 27NC NOTE
brr - 30NC NOTE
rbw - 30NC NOTE
wwc - 14NC
wbb - 22NC
wbw - 22NC

Note: add (2t + 4t + nt) uSec., where t is the bit length of the
selected device and n is the number of bits transferred.

T_A_B_L_E_ _O_F_ _C_O_N_T_E_N_T_S_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _P_A_G_E_

1. INTRODUCTION ........................................... 1

2. PROCESSING UNIT ........................................ 3

3. MEMORY ................................................. 4
3.1 EPROM/ROM ......................................... 4
3.2 Dual Port RAM ..................................... 4
3.2.1 On-Board Access to DPRAM ................... 5
3.2.2 Multibus Access to DPRAM ................... 5

4. I/O DEVICES ............................................ 7
4.1 Serial I/O Interface .............................. 7
4.2 DMA Controller .................................... 8
4.3 Interrupt Controllers ............................. 8
4.4 iSBX Connectors ................................... 9
4.5 Identification Switches ........................... 11

5. MULTIBUS INTERFACE ..................................... 12

ii
\f

1_._ _ _ _ _ _ _ _ _I_N_T_R_O_D_U_C_T_I_O_N_ 1.

The CPU601 is a complete 16-bit microprocessor system with 8086
CPU, 80130 OS firmware, RAM, EPROM, interrupt logic, DMA con-
troller, serial communications interface, iSBX connectors and
Multibus interface on a single printed circuit board. The board,
which measures 6.74x12.00 inches (171.5x304.8 mm), may be plugged
into a standard Multibus or IEEE P796 BUS backplane.

Fig. 1 shows the most important components and the data paths of
the CPU601.

Figure 1: CPU601 block diagram.
\f

F_ 2_._ _ _ _ _ _ _ _ _P_R_O_C_E_S_S_I_N_G_ _U_N_I_T_ 2.

The processing power for the CPU601 is delivered by an iAPX 86/
30, which is a combination of a 16-bit 8086 CPU and an 80130
Operating System Firmware (OSF) component.

The 80130 OSF contains 16 k bytes ROM, a system timer, a delay
timer, a baud rate generator and a programmable interrupt con-
troller with 8 interrupt request inputs. The 80130 ROM contains
code for a set of 35 operating system primitives, which are com-
patible with the Intel RMX86 operating system.

The 8086 CPU and the 80130 OSF operate at 8 MHz clock frequency,
corresponding to a 125 ns clock cycle period. The number of wait
states, which are inserted when on board ROM, RAM and I/O devices
are accessed are listed below.

A_C_C_E_S_S_ _T_O_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _W_A_I_T_ _S_T_A_T_E_S_
80130 ROM 0
EPROM 0
RAM 1
I/O devices 0
iSBX modules 1

The processing unit (iAPX 86/30) may be expanded with an optional
8087 Numeric Data Processor (NDP). For the present the 8087 NDP
is only available in a 5 MHz version. The processor clock fre-
quency must therefore be reduced from 8 MHz to 5 MHz, if the 8087
NDP is installed.

F_ 3_._ _ _ _ _ _ _ _ _M_E_M_O_R_Y_ 3.

The CPU601 on board memory consists of 16 to 64 k bytes of EPROM/
ROM, 16 k bytes of ROM located in the 80130 OSF chip and 128 or
256 k bytes of Dual Port RAM (DPRAM).

3_._1_ _ _ _ _ _ _ _E_P_R_O_M_/_R_O_M_ 3.1

The CPU601 board is provided with two 28-pin sockets which can
accept the following three types of EPROM (or ROM) with Intel/
JEDEC standard pinout:
8kx8 (2764), 16kx8 (27128) and 32kx8 (27256).

The highest memory addresses in the 1 M byte memory address space
are used for EPROM addressing. Addresses for the 80130 ROM are
located immediately below the EPROM addresses. Two switches are
used to select the address range for EPROM and 80130 ROM as shown
in the table below.

DEVICE CAPACITY ADDRESS RANGE
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _8_0_1_3_0_ _R_O_M_ _ _ _ _ _ _ _E_P_R_O_M_ _ _ _ _ _ _ _ _
2764 16 k bytes F8000 - FBFFF FC000 - FFFFF
27128 32 k bytes F4000 - F7FFF F8000 - FFFFF
27256 64 k bytes EC000 - EFFFF F0000 - FFFFF

3_._2_ _ _ _ _ _ _ _D_u_a_l_ _P_o_r_t_ _R_A_M_ 3.2

The CPU601 is provided with a dual port RAM (DPRAM), which is ac-
cessible from the on-board processors and from the Multibus. The
DPRAM array consists of 2x18 64kx1-bit dynamic RAM devices, 2x16
devices for data and 2x2 devices for parity. This provides the
board with a DPRAM capacity of 256 k bytes. If only half of the
RAM devices are mounted the DPRAM capacity is 128 k bytes. The
design of the dynamic RAM controller allows the 64kx1-bit RAM de-
vices to be replaced with 256kx1-bit devices, when they become
available. This will provide the CPU601 with a DPRAM capacity of
up to 1 M bytes in the future.
\f

The DPRAM is provided with parity check, 1 parity bit per byte.
If an error is detected, the parity control logic generates an
interrupt request, which is connected to the NMI input of the
8086 CPU. The interrupt request may be disabled by means of a
mask bit in a control register. Two LED's on the board indicate
parity errors for high and low bytes. Note that the parity error
interrupt also can occur, when the DPRAM is accessed from the
Multibus.

3_._2_._1_ _ _ _ _ _O_n_-_B_o_a_r_d_ _A_c_c_e_s_s_ _t_o_ _D_P_R_A_M_ 3.2.1

When the DPRAM is accessed from the on-board CPU and DMA control-
ler, it is located from address 0 and up in the 1 M byte memory
address space. The address range for 128 k and 256 k DPRAM sizes
are shown below.

R_A_M_ _S_I_Z_E_ _ _ _ _ _ _A_D_D_R_E_S_S_ _R_A_N_G_E_ _ _
128 k bytes 00000 - 1FFFF
256 k bytes 00000 - 3FFFF

3_._2_._2_ _ _ _ _ _M_u_l_t_i_b_u_s_ _A_c_c_e_s_s_ _t_o_ _D_P_R_A_M_ 3.2.2

The DPRAM address decoder can be strapped to decode a 24-bit (16
M bytes) or a 20-bit (1 M bytes) Multibus memory address. When
20-bit addressing is selected, the 4 unused (most significant)
address bits are forced to 0.

Part of the DPRAM may be configured as private resource, pro-
tected from Multibus access. The Multibus accessible part of the
DPRAM may be placed within 1 of 64 256 k byte segments in the 16
M byte Multibus memory address space. Offset from start of the
selected 256 k byte segment must be on a 32 k byte boundary. The
Multibus address range for access to the DPRAM may be selected as
shown below.
\f

DPRAM size: 128 or 256 k bytes
Segment base: 0 through 63x256 k bytes
Private size: 0, 32, 64, 96, 128, 160, 192, 256 k bytes
Offset: 0 through 7x32 k bytes

The following example shows the addresses for both on-board and
Multibus access to the DPRAM.

DPRAM size: 256 k bytes
Segment base: 3x256 k bytes
Private size: 64 k bytes
Offset: 0

O_N_-_B_O_A_R_D_ _A_D_D_R_._ M_U_L_T_I_B_U_S_ _A_D_D_R_._
_ _ _ _ _ _ _ _ _ _ _D_P_R_A_M_ _ _ _ _ _ _ _ _ _ _ _
3FFFF 0EFFFF
SHARED
192 k bytes
_ _ _ _ _ _ _ _ _ _ _ _ 0_C_0_0_0_0_ _
M_m_m_ PRIVATE
No access
P_p_p_ 0_0_0_0_0_ _ _ _ _6_4_ _k_ _b_y_t_e_s_ _

F_ 4_._ _ _ _ _ _ _ _ _I_/_O_ _D_E_V_I_C_E_S_ 4.

The following sections give a short description of the on-board
I/O devices. For a more detailed description is referred to the
relevant datasheets. The I/O devices are located in the I/O ad-
dress space and can only be accessed by the on-board processor.

4_._1_ _ _ _ _ _ _ _S_e_r_i_a_l_ _I_/_O_ _I_n_t_e_r_f_a_c_e_ 4.1

A programable communications interface using an 8251A Universal
Synchonous/Asynchronous Receiver/Transmitter (USART) is contained
on the CPU601 board. For asynchronous operation of the 8251A, the
baud rate generator (timer 2) in the 80130 OSF device is used as
clock source. For synchronous operation the 8251A will normally
be supplied with receive and transmit clocks from external equip-
ment (modem). A strap field is used to select external clock
sources. Optionally the transmit clock may be delivered by the
CPU601 (strap selection).

The interface between the 8251A and the external equipment fol-
lows the CCITT V.24/V.28 recommendations. The following signals
are supported by the CPU601:

C_I_R_C_U_I_T_ _N_O_ _ _ _ _ _ _ _ _ _ _ _ _S_I_G_N_A_L_ _N_A_M_E_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
102 Signal ground
103 Transmitted data
104 Received data
105 Request to send
106 Ready for sending
107 Data set ready
108/2 Data terminal ready
109 1) Data channel received line signal detector
113 Transmitter signal element timing (DTE)
114 Transmitter signal element timing (DCE)
115 Receiver signal element timing (DCE)
125 1) Calling indicator

1) These signals are not supported by the 8251A. They are avail-
able through a separate input port.

4_._2_ _ _ _ _ _ _ _D_M_A_ _C_o_n_t_r_o_l_l_e_r_ 4.2

The CPU601 contains an 8237-2 DMA controller, which supports DMA
data transfers between iSBX controller modules and on-board mem-
ory. The DMA controller may e.g. be used to support the iSBX218
flexible disk controller. The DMA controller can only be used to
support 8-bit I/O devices.

The 16-bit address range of the 8237-2 has been extended to 20-
bits (1 M byte) by means of a 4-bit page register. This divides
the 1 M byte memory address space into 16 64 k byte pages. A DMA
block cannot cross a 64 k byte boundary. The maximum block size
is 64 k bytes.

The DMA controller uses the local CPU bus for data transfers.
When the DMA controller is operated in the block transfer mode,
(for maximum throughput), it will hold the local bus for the time
required to transfer a block of data. During this time the CPU
cannot access memory and I/O. This drawback may be avoided by
using the single transfer mode at the expense of throughput.

The approximate DMA transfer rates are:
Block transfer mode: 1.25 /byte, 800 K bytes/sec.
Single transfer mode: 2.25 /byte

4_._3_ _ _ _ _ _ _ _I_n_t_e_r_r_u_p_t_ _C_o_n_t_r_o_l_l_e_r_s_ 4.3

Interrupt requests from on-board devices and from the Multibus
interrupt lines are handled by two programable interrupt control-
lers and by the Non Maskable Interrupt (NMI) request input of the
8086. This gives a total of 16 interrupt request inputs. The in-
terrupt controller contained in the 80130 OSF operates as master
controller and an 8259A interrupt controller operates as a slave
controller. The interrupt request sources are assigned to the
interrupt inputs as shown in the table below.
\f

I_N_T_E_R_R_U_P_T_ _I_N_P_U_T_ _ _ _ _ _ _I_N_T_E_R_R_U_P_T_ _S_O_U_R_C_E_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
NMI Power fail and RAM parity error

Master Level 0 Systick timer (80130 OSF)
Master Level 1 Reserved (80130 delay timer)
Master Level 2 8251A USART receiver
Master Level 3 8251A USART transmitter
Master Level 4 Reserved for 8287 NDP
Master Level 5 8259A slave interrupt controller
Master Level 6 Multibus INT6 2)
Master Level 7 Multibus INT7 2)

Slave Level 0 iSBX1 - MINTR0, iSBX1 - MINTR1 1)
Slave Level 1 iSBX2 - MINTR0, iSBX2 - MINTR1 1)
Slave Level 2 iSBX1 - MINTR1, Multibus INT0 1)
Slave Level 3 iSBX2 - MINTR1, Multibus INT1 1)
Slave Level 4 Multibus INT2
Slave Level 5 Multibus INT3
Slave Level 6 Multibus INT4
Slave Level 7 Multibus INT5

1) Interupt source is selected by jumper.
2) These inputs support bus vectored interrupts.

4_._4_ _ _ _ _ _ _ _i_S_B_X_ _C_o_n_n_e_c_t_o_r_s_ 4.4

The CPU601 contains two iSBX connectors (J3 and J4) for on board
I/O expansion by means of iSBX modules. The connectors will ac-
cept 1 single (J3) and 1 double (J4) or 2 single (J3, J4) iSBX
modules. Both 8-bit and 16-bit (jumper selection) modules are
supported by the on board 8086 CPU. The 8237 DMA controller sup-
ports only 8-bit iSBX modules. Up to two DMA channels may be as-
signed to each iSBX connector.

Fig. 2 shows the iSBX connector pin assignments. Apart from the
signals MPST, MINTR1, MINTR0, MWAIT, MCS1, MCS0, TDMA, OPT1,
OPT0, MDACK and MDRQT are all signals common to the two connect-
ors.
\f

F_ P_I_N_ _ _ _M_N_E_M_O_N_I_C_ _ _ _C_P_U_6_0_1_ _S_O_U_R_C_E_/_D_E_S_T_I_N_A_T_I_O_N_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
1 +12V +12 volts
3 GND Signal Ground
5 MRESET Master reset
7 MA2 Address bit 3
9 MA1 Address bit 2
11 MA0 Address bit 1
13 IOWRT/ Advanced I/O write command
15 IORD/ I/O read command
17 GND Signal Ground
19 MD7 Data bit 7
21 MD6 Data bit 6
23 MD5 Data bit 5
25 MD4 Data bit 4
27 MD3 Data bit 3
29 MD2 Data bit 2
31 MD1 Data bit 1
33 MD0 Data bit 0
35 GND Signal ground
37 MDE Data bit E
39 MDC Data bit C
41 MDA Data bit A
43 MD8 Data bit 8

2 -12V -12 volts
4 +5V +5 volts
6 MCLK 9.8304 MHz clock signal
8 MPST/ Chip select decoder input
10
12 MINTR1 Interrupt controller input
14 MINTR0 Interrupt controller input
16 MWAIT/ Wait state logic input
18 +5V +5 volts
20 MCS1/ Chip select decoder output
22 MCS0/ Chip select decoder output
24 - Reserved
26 TDMA 8237 EOP/ input (jumper)
28 OPT1 Function selected by jumpers
30 OPT0 Function selected by jumpers
32 MDACK/ 8237 DMA acknowledge
34 MDRQT 8237 DMA request
36 +5V +5 volts
38 MDF Data bit F
40 MDD Data bit D
42 MDB Data bit B
44 MD9 Data bit 9

Figure 2: iSBX connector pin assignments.
\f

The function of the option signals OPT1 and OPT0 can be selected
as described below.

OPT1: 8237 DMA acknowledge (additional channel).
No connection.
OPT0: 8237 DMA request (additional channel).
8237 Terminal Count (TC) output.
No connection.

4_._5_ _ _ _ _ _ _ _I_d_e_n_t_i_f_i_c_a_t_i_o_n_ _S_w_i_t_c_h_e_s_ 4.5

The CPU601 contains 2x8 switches, which can be sensed through an
input port. The switches can e.g. be used to provide the CPU601
with an address, when it is used in distributed systems.

F_ 5_._ _ _ _ _ _ _ _ _M_U_L_T_I_B_U_S_ _I_N_T_E_R_F_A_C_E_ 5.

The CPU601 interfaces directly to the standard Intel Multibus and
the IEEE P796 BUS. All adddress (24-bits), data (16-bits) and
control signals conform to the specifications for these busses.
The CPU601 provides full multimaster arbitration control logic,
which allows up to 16 masters to share the bus using a parallel
priority resolution technique. The more simple serial priority
resolution technique allows up to 3 masters to share the bus.

The CPU601 generates and recognizes the Multibus 'LOCK' signal.
When asserted, the LOCK signal prevents a CPU from accessing its
on board dual port RAM.

When the on board CPU generates an address outside the on board
memory or I/O address ranges the CPU601 uses the Multibus to ac-
cess the addressed location. When the CPU601 is Multibus master,
the contents of the 4-bit Multibus page register are used as the
4 most significant address bits (14, 15, 16 and 17 hex). The low-
er 20 bits of the address are generated directly by the on board
8086 CPU.

The CPU601 is able to generate interrupt request on any of the 8
Multibus interrupt lines by means of a programmable output port.
\f

ET TILBUD TIL ALLE RC BRUGERE
Regnecentralens træningscenter - beliggende på hovedsædet i
Ballerup udenfor København - tilbyder et omfattende trænings- og
undervisningsprogram indenfor områderne datamaskinel og -program-
mel. Hos RC ophører kundeservicen ikke med underskrivningen af
salgskontrakten. Som led i den løbende service vil kunderne finde
træningscenterets kursusprogram - et vægtigt tilbud til alle
brugere af RC udstyr.

HØJT KVALIFICEREDE INSTRUKTØRER
Programmører og teknikere fra hele verden undervises på trænings-
centeret. Der er altid en række af de nyeste datateknologiske
emner på programmet. Det er således store krav, der stilles til
instruktørerne, både med hensyn til omfang og kvalitet. De fleste
instruktører er da også uddannet på universitetsniveau forud for
deres videregående edb-uddannelse.

OMFATTENDE KURSUSPROGRAM
Det er mindst lige så vigtigt, at nye brugere får en grundig
introduktion til maskinel og programmel, som det er, at undervise
i specialiserede discipliner indenfor datamatikken. Kursuspro-
grammet omfatter således generelle kurser for dem, der ikke
tidligere har beskæftiget sig med edb, - eller dem, der ønsker at
lære noget om metoder. Desuden kurser, der er rettet mod den
fundamentale viden omkring programmering; samt kurser, der
fokuserer specielt på datamat-teknik. Sidstnævnte programpunkt
henvender sig især til elektronik-uddannede, der ikke tidligere
har beskæftiget sig direkte med edb. Hertil kommer specielle
kurser og seminarer, der dækker undervisnings- og træningsbehovet
indenfor avancerede edb-anvendelsesområder, eksempelvis
datanetværksstrukturer og -applikationer.

LØBENDE KUNDESERVICE
Som tidligere nævnt ophører kundeservicen ikke med underskriv-
ningen af salgskontrakten. Det er således muligt idag at deltage
i kurser, der vedrører maskinel og programmel som blev introdu-
ceret for adskillige år siden. Denne kontinuitet i undervisnings-
programmet værdsættes i høj grad af brugere, der ansætter nye
edb-medarbejdere - hvadenten disse skal arbejde som programmører
eller operatører.
\f

MODERNE KURSUSFACILITETER
Træningscenteret er indrettet i rummelige og venlige omgivelser.
Maskinparken omfatter alle typer af udstyr som RC fremstiller og
markedsfører. Kursusmaterialet - og undervisning i klasselokalet
- er dels engelskproget, dels dansksproget; det afhænger af det
enkelte kursus og fremgår af kursusprogrammet. I undervisningen
anvendes de nyeste metoder i instruktionsteknik; desforuden be-
tragtes en virklighedstro arbejdsmåde som særdeles vigtig - in-
struktørstaben pålægges således jævnligt arbejdsopgaver "i
marken" for derigennem at bevare den praktiske sans for bruger-
problemer og for en effektiv og tilfredstillende løsning af dem.

INTERN UNDERVISNING
Det faktum, at træningscenteret også er ansvarlig for den interne
undervisning og træning af RC>s danske og udenlandske teknikere,
borger ligeledes for instruktørernes færdigheder. Det primære
sigte med de interne kurser er en stadig effektivisering af ved-
ligeholdelsesstrategier samt opfølgning omkring den løbende pro-
duktudvikling.
\f

ÅRLIGT OMFANG
Programlægningen i træningscenteret baserer sig til enhver tid på
10 heltidsansatte instruktører, der arbejder cirka 1000
person-dage direkte med kunde-træning svarende til 150 trænings-
kurser. En belastningsgrad der sikrer, at instruktørerne får
optimal mulighed for kursusforberedelse samt personlig træning og
uddannelse.

Træningscenterets kursusprogram revideres og udsendes hvert
halvår og kan rekvireres hos RC.

RCSL 42-i1567
\f

RC868
Typehjulsprinter

. KVALITETSUDSKRIFTER - TEKSTBEHANDLING

. UDSKIFTELIGE TYPEHJUL

. ALSIDIGE FACILITETER

. NYUDVIKLET DESIGN

. FASTE FORMATINDSTILLINGER - ELLER PROGRAMSTYRET

. BENYTTES SAMMEN MED RC850 OG RC700 SYSTEMER

. TRAKTOR OG ARKFØDER SOM EKSTRAUDSTYR
\f

GENERELT
RC868 typehjulsprinteren byder på udskrifter med samme skriftkva-
litet som kendes fra de bedste skrivemaskiner. Typehjul med fuldt
formede tegn samt styring af udskriftsprocessen med mikroproces-
sor, sikrer udskrifter i egen særklasse. Udskiftelige typehjul og
alsidige, programstyrede faciliteter klarer de mest krævende op-
gaver. Et helt nyudviklet design ligger bagved: enkelt, pålide-
ligt og slidstærkt - få vedligeholdelseskrav.

RC868 kan tilkobles RC850 og RC700 systemer og er især velegnet i
forbindelse med tekstbehandlingsopgaver på disse anlæg. Som
ekstraudstyr fås: TF219 traktor og TF220 arkføder, der kan
indstilles til både høj- og tværformat.

KARAKTERISTIKA
RC868 skriver serielt med en hastighed på 55 tegn pr. sek. An-
slagskraft og farvebåndsfremføring reguleres efter tegnstørrelse,
automatisk eller programmeret. Når printerens automatik benyttes,
indstilles alle funktioner bekvemt på betjeningspanelet; ved pro-
grammeret styring kan værtssystemet direkte kontrollere facilite-
ter såsom: fed-skrift, skygge-skrift og forskellige understreg-
ningsmåder - for ikke at nævne den absolutte kontrol med papir-
og typehjulsbevægelserne, der faktisk tillader tegnearbejde.

Typehjulet kan nemt skiftes af brugeren. Standard typehjul med 96
tegn findes i et stort udvalg af skriftyper og nationale tegnsæt.
Udskriftsformatet kan vælges med faste indstillinger for tegn- og
linieafstand eller kan programstyres på basis af grundbevægelser-
ne.

Printeren kan benytte enkeltark såvel som kanthullet papir i ba-
ner. Enkeltark fremføres af skrivevalsen og kan ilægges automa-
tisk med arkføderen. Kanthullet papir i baner fremføres af trak-
toren. Både traktor og arkføder kan på-/afmonteres uden værktøj,
idet forberedelser og justeringer blot skal udføres første gang.
Snaplåsholder til farvebåndskassette samt farvebånd-/papir-slut
registrering er andre faciliteter, der gør betjeningen let og
ligetil.
\f

SPECIFIKATIONER
Skrivehastighed: 55 tegn/sek. - normal bladet tekst.
Fremføringshastighed: To-vejs bevægelser:
Typehjul: 40 tommer/sek., maks.
Papir: 5 tommer/sek., maks.
Skrivemåde: Fuldt formede tegn på typehjul. An-
slagskraft efter tegnstørrelse.
Seriel udskrivning. Programstyrede
udskriftsfaciliteter.
Tegnsæt: Udskiftelige typehul med 96 tegn.
Forskellige skrifttyper og
nationale tegnsæt.
Udskriftsformat: Horisontalt:
- faste indstillinger: 10-12-15 tegn/tomme (svarende til
132-158-198 skrivepositioner).
- programstyret: Grundbevægelse: 120 delinger/tomme;
mask. bevægelse: 13,2 tommer.
Vertikalt:
- faste indstillinger: 3-6-8 linier/tomme
- programstyret: Grundbevægelse: 48 delinger/tomme *);
maks. bevægelse: 21,3 tommer.
*) kan øges til 144 delinger/tomme.
Papirfremføring: Enkeltark: friktionsvalse; automa-
tisk ilægning ved brug af arkføder
(TF220). Papirbane (kanthullet):
traktor (TF219).
Papirtype: Enkeltark eller kanthullet papir i
baner. Bredde, maks.: 15 tommer
(arkføder: 12 tommer). Formatlæng-
de: 3-3,5-4-5,5-6-7-8-8,5-11-11
2/3-12-14 tommer (trinvis indstil-
bar). Multi-copy indstilling.
Farvebånd: Snaplås-kassette; bånd-slut føler;
automatisk eller programstyret
fremføring efter tegnstørrelse. \f

Kontakter/indikatorer: RESET, CARRIER DETECT, READY, COMM
ERROR, LINESPACE, PITCH, WPS
ON/OFF, SET TOF, FORM LENGTH, FORM
FEED, PAUSE.
Værtsmaskinetilslutning: CCITT V.24 (RS 232 C). Kabellængde:
5 meter. Konfigurationstilpasning
med interne kontakter.
Strømforsyning: 220 V AC, 50 Hz, 150 W
Temperatur, omg.: 10-40C
Luftfugtighed: 10-90% RH, ikke-kondenserende
Varmeafgivelse: 540 kJ/t (130 kcal/t)
Montage: Bordmodel

DIMENSIONER
Højde: 17,2 cm
Bredde: 61,7 cm
Dybde: 42,6 cm
Vægt: 20,5 kg

RCSL Nr. 42-i2095

«eof»

DataMuseum.dk

CP/M

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Derivation

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