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T_A_B_L_E_ _O_F_ _C_O_N_T_E_N_T_S_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _P_A_G_E_
1. INTRODUCTION ........................................... 1
2. FUNCTIONAL DESCRIPTION ................................. 2
2.1 CPU821 Data Paths ................................. 2
2.1.1 General Registers .......................... 2
2.1.2 Q-Register ................................. 2
2.1.3 Arithemetic Logic Unit ..................... 4
2.1.4 Scratchpad ................................. 4
2.1.5 Constant Memory ............................ 4
2.1.6 Immediate Operand .......................... 4
2.1.7 Loop Counter ............................... 5
2.1.8 Half Word Manipulator ...................... 5
2.1.9 Exception Control .......................... 5
2.1.10 Instruction Counter ........................ 6
2.1.11 Displacement Register ...................... 6
2.1.12 Relative Address Register .................. 6
2.1.13 Switch Register ............................ 6
2.1.14 CPU Status Register ........................ 7
2.1.15 Control Output Register .................... 7
2.1.16 Logical Address Status Register ............ 8
2.1.17 CPU Bus .................................... 9
2.2 CPU822 Data Paths ................................. 9
2.2.1 Bus and Cache Interface Unit ............... 9
2.2.1.1 Logical Address Register .......... 9
2.2.1.2 Unit Function Register ............ 9
2.2.1.3 Base Register ..................... 12
2.2.1.4 Address Limit Registers ........... 12
2.2.1.5 Prefetch Instruction Counter ...... 13
2.2.1.6 System Bus Address Register ....... 13
2.2.1.7 Data Out Register ................. 13
2.2.1.8 Data In Register .................. 13
2.2.1.9 Prefetch Instruction Register ..... 14
2.2.1.10 I/O Status Register ............... 14
2.2.1.11 CAM Control Register .............. 16
2.2.2 Interrupt Control Unit ..................... 17
2.2.2.1 Interrupt Limit Registers ......... 17
2.2.2.2 Interrupt Level Register .......... 17
2.2.2.3 Interrupt Register ................ 18 \f
ii
T_A_B_L_E_ _O_F_ _C_O_N_T_E_N_T_S_ _(_c_o_n_t_i_n_u_e_d_)_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _P_A_G_E_
2.2.3 Real Time Clock ............................ 18
2.2.3.1 Real Time Clock Register .......... 18
2.2.4 Technician Console Interface ............... 19
2.2.4.1 Technician Console Status Register 19
2.2.4.2 Technician Console Data In Register 20
2.2.4.3 Technician Console Data Out
Register .......................... 20
2.3 Microprogram Control Unit ......................... 20
2.3.1 Microinstruction Address Register .......... 21
2.3.2 Subroutine Return Stack .................... 21
2.3.3 Microprogram Jump Address .................. 23
2.3.4 Microprogram Interrupt Address ............. 23
2.3.5 Address Calculation Decoding Map ........... 23
2.3.6 Instruction Execution Decoding Map ......... 24
2.4 Microinstructions ................................. 24
2.4.1 P Field = MIR(0) ........................... 25
2.4.2 NEXT Field = MIR(1:4) ...................... 25
2.4.3 CL Field = MIR(5,6) ........................ 27
2.4.4 F Field = MIR(7:9) ......................... 28
2.4.5 ALU-D Field = MIR(10,11) ................... 28
2.4.6 ALU-OP Field = MIR(12:14) .................. 28
2.4.7 ALU-FUNC Field = MIR(15:17) ................ 29
2.4.8 ALU-C Field = MIR(18,19) ................... 29
2.4.9 A Field = MIR(20:24) ....................... 29
2.4.10 B Field = MIR(25:29) ....................... 30
2.4.11 UNIT FUNC/TEST Field = MIR(30:25) .......... 30
2.4.12 INT/EXT REG DEST Field = MIR(42:47) ........ 31
2.4.13 T Field = MIR(30) .......................... 32
2.4.14 COND SELECT Field = MIR(31:35) ............. 33
2.4.15 Format 0 : Read/Load Scratchpad ............ 34
2.4.16 Format 1 : Read/Load Register .............. 34
2.4.17 Format 2 : Read Constant ................... 35
2.4.18 Format 3 : Read External Register .......... 36
2.4.19 Format 4 : Half-Word Manipulator ........... 37
2.4.20 Format 5 : Load Immediate .................. 38
2.4.21 Format 6 : Conditional Jump ................ 38
2.4.22 Format 7 : Shift, Multiply and Divide ...... 39 \f
iii
T_A_B_L_E_ _O_F_ _C_O_N_T_E_N_T_S_ _(_c_o_n_t_i_n_u_e_d_)_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _P_A_G_E_
3. BLOCK DIAGRAMS ......................................... 43
4. LOGIC DIAGRAMS ......................................... 51
4.1 CPU821 Logic Diagrams ............................. 51
4.2 CPU822 Logic Diagrams ............................. 127
5. TIMING DIAGRAMS ........................................ 199
5.1 CPU821 Timing Diagrams ............................ 199
5.2 CPU822 Timing Diagrams ............................ 207
6. PROM's ................................................. 214
6.1 Microprogram PROM Position List ................... 214
6.2 ROA307 Listing .................................... 215
6.3 ROA308, ROA309 and ROA310 Listing ................. 216
6.4 ROA311 Listing .................................... 217
6.5 ROA312 Listing .................................... 218
6.6 ROA313 Listing .................................... 220
7. PLUG LISTS AND CABLES .................................. 222
7.1 CPU821 Plug Lists ................................. 222
7.2 CPU822 Plug Lists ................................. 226
7.3 Internal Cables, CBL826 and CBL904 ................ 231
8. ASSEMBLY DRAWINGS ...................................... 233
\f
iv
\f
1_._ _ _ _ _ _ _ _ _I_N_T_R_O_D_U_C_T_I_O_N_ 1.
CPU820, which is the basic processing unit for RC8000 Model 50
and Model 55, consists of two modules (printed circuit boards),
CPU821 and CPU822. The performance of the CPU820 may be increased
by extending it with a cache memory module, CAM801/803, and/or a
floating point unit, FPU801, as shown on fig. 1.
Figure 1: CPU820 extended with cache memory and floating point
unit.
The processing unit modules are interconnected by means of a PCB
backplane bus consisting of a 24-bit bidirectional data bus
(CPUBUS), a 24-bit instruction bus and a number of control
signals. Communication between the processing unit, the main
memory and the device controllers takes place via the RC8000
System Bus.
This manual describes the CPU820 modules, CPU821 and CPU822. The
CAM801/803 and FPU801 modules are described in separate manuals.
\f
F_ 2_._ _ _ _ _ _ _ _ _F_U_N_C_T_I_O_N_A_L_ _D_E_S_C_R_I_P_T_I_O_N_ 2.
2_._1_ _ _ _ _ _ _ _C_P_U_8_2_1_ _D_a_t_a_ _P_a_t_h_s_ 2.1
The principal data paths in the CPU821 are 24-bit wide and are
shown on the block diagram on fig. 2. An array of 6 IDM2901A-1
4-bit slice processing elements constitutes the kernel of the
CPU821 data path structure. It contains the General Registers
(accumulators), the Q-register, and an arithmetic logic unit. The
2901 array receives data from external registers and operators
via the SBUS (Source Bus), which is a tri-state bus. Data to
external registers and operators are transferred via the DBUS
(Destination Bus).
The following subsections give a short description of the CPU821
registers and operators.
2_._1_._1_ _ _ _ _ _G_e_n_e_r_a_l_ _R_e_g_i_s_t_e_r_s_ 2.1.1
The 16 General Registers are located in a dual-port RAM in the
2901. The contents of 2 General Registers may simultaneously be
accessed via the A-port, GRA, and the B-port, GRB. GRA and GRB
may be used as inputs to the ALU and GRA may be transferred
directly to the DBUS. The General Register may be loaded with the
output from the ALU. A shift network at the input to the General
Registers may pass or shift the ALU output 1 bit position left or
right before it is loaded.
2_._1_._2_ _ _ _ _ _Q_-_R_e_g_i_s_t_e_r_ 2.1.2
The Q-Register which is located in the 2901 may be used as an
accumulator and as an extension to the General Registers in shift
operations for shifting 48-bit operands. In the latter case Q
holds the least significant 24-bit of the 48-bit operand. It is
only possible to shift Q in conjunction with a General Register.
\f
F_
Figure 2: CPU821 data paths.
\f
2_._1_._3_ _ _ _ _ _A_r_i_t_h_e_m_e_t_i_c_ _L_o_g_i_c_ _U_n_i_t_ 2.1.3
The Arithmetic Logic Unit, ALU, inside the 2901 can perform 3
arithmetic and 5 logic operations on 2 operands. The General
Registers, the Q-Register, the SBUS and ZERO can be selected as
operands for the ALU in 8 different combinations. The ALU output,
F, can be transferred to the General Registers, the Q-Register
and the DBUS.
2_._1_._4_ _ _ _ _ _S_c_r_a_t_c_h_p_a_d_ 2.1.4
The Scratchpad (SCRATCHP) is a register file with 16 24-bit
words. It can be used as both source and destination but not
within the same microcycle. When it is used as source the
c_o_m_p_l_e_m_e_n_t_ of the data loaded into the addressed location is
transferred to the SBUS.
2_._1_._5_ _ _ _ _ _C_o_n_s_t_a_n_t_ _M_e_m_o_r_y_ 2.1.5
The Constant Memory (CONSTANT) is a read only memory with 32
24-bit words, which is used to hold frequently used constants. It
can only be used as a source.
2_._1_._6_ _ _ _ _ _I_m_m_e_d_i_a_t_e_ _O_p_e_r_a_n_d_ 2.1.6
Bits (20:43) of the Microinstruction Register (MIR) may be
transferred to the SBUS and used as a 24-bit immediate operand in
the current microinstruction.
SBUS(0:23) = MIR(20:43)
\f
2_._1_._7_ _ _ _ _ _L_o_o_p_ _C_o_u_n_t_e_r_ 2.1.7
The Loop Counter is a 24-bit counter addressable as both source
and destination register. The primary function of LC is to count
the number of times a microprogram loop is executed. Execution of
a microinstruction where the NEXT-field specifies a LOOP RETURN
will increment LC by 1. The most significant bit of LC LC(0), is
a test condition.
An 8-bit counter, LCMAX(0:7), is associated LC. This counter may
be used to control that a loop is executed maximum 49 times.
LCMAX cannot be adddressed from the microprogram. It is loaded
with -48 (dec.) when LC is loaded and incremented by 1
simultaneously with LC. The testcondition MAXLOOP indicates that
LC >= 0 or LCMAX >= 0.
MAXLOOP = LC(0)! -,LCMAX(0)
2_._1_._8_ _ _ _ _ _H_a_l_f_ _W_o_r_d_ _M_a_n_i_p_u_l_a_t_o_r_ 2.1.8
The Half Word Manipulator (HWM) is a combinatorial network which
performs operations on data from the DBUS and transfers the
result to the SBUS. The HWM performs such operations as 12-bit
sign extension, half word swapping, and half word masking. One of
the microinstruction formats is assigned to control the operation
of the HWM.
2_._1_._9_ _ _ _ _ _E_x_c_e_p_t_i_o_n_ _C_o_n_t_r_o_l_ 2.1.9
Exception Control (EXC) is a combinatorial network which is used
to insert various status bits into bit positions 22 and 23 of a
24-bit word. EXC receives input from the DBUS and transfers the
modified word to the SBUS. EXC is addressable as 4 source
registers. Each of the addresses defines an operation.
\f
2_._1_._1_0_ _ _ _ _I_n_s_t_r_u_c_t_i_o_n_ _C_o_u_n_t_e_r_ 2.1.10
The Instruction Counter (IC) is a 24-bit counter/register
addressable as both source and destination. IC(0) and IC(23) is
always 0. Execution of a microinstruction where the NEXT field
specifies EXECUTE, MIR(1:4) = 1111, will increment IC by 2.
2_._1_._1_1_ _ _ _ _D_i_s_p_l_a_c_e_m_e_n_t_ _R_e_g_i_s_t_e_r_ 2.1.11
The Displacement Register (DISP) is a 24-bit source register.
DISP contains the displacement of the RC8000 instruction which is
being executed. Execution of a microinstruction where the NEXT
field specifies NEXT INSTR transfers the instruction displacement
from the Instruction Bus, INSTRBUS, to DISP.
DISP(0:23): = 12 ext INSTRBUS(12) con INSTRBUS(12:23)
2_._1_._1_2_ _ _ _ _R_e_l_a_t_i_v_e_ _A_d_d_r_e_s_s_ _R_e_g_i_s_t_e_r_ 2.1.12
The Relative Address Register (RELADDR) is a 24-bit source
register containing DISP+IC. Execution of a microinstruction with
the NEXT field = NEXT INSTR will load RELADDR.
RELADDR: = 12 ext INSTRBUS(12) con INSTRBUS(12:23) + IC.
2_._1_._1_3_ _ _ _ _S_w_i_t_c_h_ _R_e_g_i_s_t_e_r_ 2.1.13
The Switch Register (SWITCH) is an 8-bit pseudo register which
contains the state of the MODE switches, the TEST switch and the
availability signals from other modules in the CPU chassis. The
bits are assigned in the following way.
\f
SWITCH(16) = POWER RESTART MODE
SWITCH(17) = POWER-UP TEST MODE
SWITCH(18) = CONTINOUS TEST MODE
SWITCH(19) = CONSOLE TC MODE
SWITCH(20) = TEST ON
SWITCH(21) = CPU822 NOT AVAILABLE
SWITCH(22) = CAM801 NOT AVAILABLE
SWITCH(23) = FPU801 NOT AVAILABLE
SWITCH is only addressable as a source register, and the contents
are transferred to the SBUS as defined below.
SBUS(0:15) is undefined
SBUS(16:23) = SWITCH > 16:23)
2_._1_._1_4_ _ _ _ _C_P_U_ _S_t_a_t_u_s_ _R_e_g_i_s_t_e_r_ 2.1.14
The CPU Status Register (CPUST) is a 6-bit destination register.
CPUST is used to hold a copy of bits from the CPU Status Word
which are used in the instruction decoding and for control
purposes. CPUST is loaded from the DBUS as defined below.
MON MODE: = DBUS(0)
ESC MODE: = DBUS(1)
AFTER AM: = DBUS(2)
AFTER ESC: = DBUS(3)
INT MASK: = DBUS(4)
DISABLE: = DBUS(20)
2_._1_._1_5_ _ _ _ _C_o_n_t_r_o_l_ _O_u_t_p_u_t_ _R_e_g_i_s_t_e_r_ 2.1.15
The Control Output Register (CONTROLOUT) is an 8-bit destination
register which is used for different control purposes. The re-
gister is loaded with DBUS(16:23). The contents of the register
are used in the following way:
\f
B_I_T_ _ _ _C_O_N_T_R_O_L_ _F_U_N_C_T_I_O_N_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
16 CPUSYSRST. Controls the SYSTEM RESET signal on the System
Bus.
17 RUN. Controls the RUN lamp on the Operators Control Panel
(OCP).
18 AUTOLOADING. Controls the AUTOLOAD lamp on the OCP.
19 -,SINGLEINSTR. Used to control single instruction
execution. The signal generates an interrupt (CPUINTR) when
it is 0.
20 -,RSTREMAUTO. A 0 resets the Remote Autoload interrupt
flip-flop.
21 -,CPULAMP. Controls the lamp, CPU, on the CPU821 front
panel.
22 -,MEMLAMP. Controls the lamp, MEMORY, on the CPU821 front
panel.
23 -,CACHELAMP. Controls the lamp, CACHE, on the CPU821 front
panel.
2_._1_._1_6_ _ _ _ _L_o_g_i_c_a_l_ _A_d_d_r_e_s_s_ _S_t_a_t_u_s_ _R_e_g_i_s_t_e_r_ 2.1.16
The Logical Address Status Register (LASTAT) is a 5-bit
destination register, which is used to store status information
concerning the logical address. LASTAT is automatically updated
when the Logical Address Register (LOGADDR) on the CPU822 is
loaded. In addition it has its own destination address. The
following status bits are stored in the register:
-,WADDR: = if F(0:20) = 0 then 0 else 1.
F is the result from the 2901 ALU.
EA(0): = DBUS(0)
EA(21): = DBUS(21)
EA(22): = DBUS(22)
ODD: = DBUS(23)
\f
2_._1_._1_7_ _ _ _ _C_P_U_ _B_u_s_ 2.1.17
The CPU Bus (CPUBUS) is a 24-bit bidirectional backplane bus
which is used to transfer data between modules (CPU, Cache
Memory, Floating Point Unit) installed in the CPU chassis. Data
may be transferred from the CPUBUS to the SBUS and from the DBUS
to the CPUBUS. Within the same microinstruction it is only
possible to transfer data in one direction on the CPUBUS. The
data flow on the CPUBUS is controlled from the CPU821, which
transfers source and destination addresses to other modules.
Source and destination addresses are generated by microinstruc-
tion fields.
2_._2_ _ _ _ _ _ _ _C_P_U_8_2_2_ _D_a_t_a_ _P_a_t_h_s_ 2.2
The CPU822 consists of 4 functional units which operate asynchro-
nously compared to the microinstruction execution. The units are:
the Bus and Cache Interface Unit, the Interrupt Control Unit, the
Real Time Clock and the Technicians Console Interface. Fig. 3
shows the CPU822 data paths.
2_._2_._1_ _ _ _ _ _B_u_s_ _a_n_d_ _C_a_c_h_e_ _I_n_t_e_r_f_a_c_e_ _U_n_i_t_ 2.2.1
The Bus and Cache Interface Unit (BCI) perform address limit
check, convert logical addresses to physical addresses, perform
memory and I/O read operations and prefetch instructions. If the
Cache Memory (CAM) is installed in the system the BCI will auto-
matically direct memory read operations and instruction pre-
fetches to the CAM. The BCI registers and the operation of the
BCI are described in the following subsections.
2_._2_._1_._1_ _ _ _L_o_g_i_c_a_l_ _A_d_d_r_e_s_s_ _R_e_g_i_s_t_e_r_ 2.2.1.1
The Logical Address Register (LOGADDR) is a 24-bit destination
register which is used to hold the logical address during memory
and I/O accesses.
\f
2_._2_._1_._2_ _ _ _U_n_i_t_ _F_u_n_c_t_i_o_n_ _R_e_g_i_s_t_e_r_ 2.2.1.2
The unit Function Register (UFR) is a 5-bit register, which is
loaded with the contents of the Unit Function field of the micro-
instruction. UFR is loaded simultaneously with the Logical Ad-
dress Register.
UFR(1:5): = MIR(31:35)
\f
F_
Figure 3: CPU822 data paths.
\f
The contents of UFR together with special deoded control signals
from the CPU821 control the operation of the BCI. The contents of
UFR are used in the following way.
B_I_T_ _ _ _C_O_N_T_R_O_L_ _F_U_N_C_T_I_O_N_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
1 START. Starts a memory or I/O operation.
2 CONDITIONAL START. A memory operation is started if the
current RC8000 instruction is a memory reference
instruction.
3 JUMP. The word fetched from the addressed location is
loaded into the Prefetch Instruction Register (PREFIR), and
the Prefetch Instruction Counter (PREFIC) is loaded with
the physical address.
4 WRITE. The contents of the Data Out Register (DATAOUT) are
stored in the addressed location.
5 PHYSICAL ADDRESS. The logical address is used directly as a
physical without limit check and base address relocation.
2_._2_._1_._3_ _ _ _B_a_s_e_ _R_e_g_i_s_t_e_r_ 2.2.1.3
The Base Register (BASE) is a 24-bit destination register. The
contents of BASE may be added to LOGADDR to form the physical
address.
2_._2_._1_._4_ _ _ _A_d_d_r_e_s_s_ _L_i_m_i_t_ _R_e_g_i_s_t_e_r_s_ 2.2.1.4
Access to main memory is controlled by 3 limit registers, the
Lower Limit Register (LLIM), the Upper Limit Register (ULIM) and
the CPA Limit Register (CPA). All three registers are 24-bit de-
stination registers. The LLIM and ULIM registers define the l_o_g_i_-
c_a_l_ address limits of the memory are, where both read and write
access is permitted. The CPA register defines the upper limit
(physical address) of the non relocatable memory area, where only
read access is permitted.
\f
2_._2_._1_._5_ _ _ _P_r_e_f_e_t_c_h_ _I_n_s_t_r_u_c_t_i_o_n_ _C_o_u_n_t_e_r_ 2.2.1.5
The Prefetch Instruction Counter (PREFIC) is a 22-bit counter,
which is used as address source for instruction prefetch. Execu-
tion of a microinstruction, where the NEXT field specifies NEXT
INSTRUCTION, will increment PREFIC by 2 and normally start an
instruction fetch (prefetch may be inhibited). The PREFIC is not
directly accessible from the microprogram. It may be loaded with
the Physical Address (PHYSADDR) by specifying a JUMP in the UNIT
FUNCTION field.
PREFIC(1:22): = PHYSADDR(1:22)
2_._2_._1_._6_ _ _ _S_y_s_t_e_m_ _B_u_s_ _A_d_d_r_e_s_s_ _R_e_g_i_s_t_e_r_ 2.2.1.6
The System Bus Address Register (SBADDR) is a 23-bit register,
used to hold the System Bus address during memory and I/O acces-
ses via the System Bus. SBADDR is not accessible from the micro-
program.
2_._2_._1_._7_ _ _ _D_a_t_a_ _O_u_t_ _R_e_g_i_s_t_e_r_ 2.2.1.7
The Data Out Register (DATAOUT) is a 24-bit destination register
which is used to hold data to be transferred from the CPU to the
addressed destination. Once an output operation has been started
the contents of the register must not be altered before termina-
tion of the operation.
2_._2_._1_._8_ _ _ _D_a_t_a_ _I_n_ _R_e_g_i_s_t_e_r_ 2.2.1.8
The Data In Register (DATAIN) is a 24-bit source register used as
buffer register for data received via the System Bus in input
operations initiated by the CPU. The contents of the register are
undefined from the start of an input operation until termination.
\f
If termination is caused by a NACK or a TIME OUT, DATAIN will be
loaded with the current data on the System Bus. DATAIN responds
to two source addresses, one of which always selects the CPU822
DATAIN register. The other address is common to the address of a
corresponding 'DATAIN' register on the cache memory module. When
the cache is installed the DATAIN register on this module will
automatically respond to the common address, otherwise the CPU822
DATAIN responds to the common address.
Execution of a microinstruction, which addresses DATAIN, will be
delayed until termination of the memory or I/O operation, if
CL >= 1. CL is the Cycle Length field of the microinstruction.
2_._2_._1_._9_ _ _ _P_r_e_f_e_t_c_h_ _I_n_s_t_r_u_c_t_i_o_n_ _R_e_g_i_s_t_e_r_ 2.2.1.9
The Prefetch Instruction Register (PREFIR) is a 24-bit register
used as buffer register for the prefetched instruction. The con-
tents of PREFIR are transferred to the CPU821 via the Instruction
Bus (INSTRBUS). If the cache memory module is installed, a cor-
responding instruction register on this module, is automatically
selected as source for the INSTRBUS. PREFIR is not addressable
from the microprogram.
2_._2_._1_._1_0_ _ _I_/_O_ _S_t_a_t_u_s_ _R_e_g_i_s_t_e_r_ 2.2.1.10
The I/O Status Register (IOSTAT) is a 16-bit source register
containing status information about instruction prefetch and
memory and I/O accesses. The contents of IOSTAT are transferred
to the CPUBUS as described below.
CPUBUS(0:3), CPUBUS(16:19) are undefined
CPUBUS(4:15): = IOSTAT(4:15)
CPUBUS(20:23): = IOSTAT(20:23)
\f
IOSTAT responds to two source addresses one of which uncondition-
ally selects IOSTAT. The other address is common to IOSTAT and a
corresponding status register on the cache memory module,
CAMSTAT. If the cache is installed the common address selects
CAMSTAT, otherwise it selects IOSTAT. Note that only bits (21:23)
of IOSTAT and CAMSTAT have the same meaning. Execution of a mi-
croinstruction, which addresses IOSTAT (or CAMSTAT) will be de-
layed until termination of the current memory or I/O operation if
CL >= 1. CL is the Cycle Length field of the microinstruction.
The contents of IOSTAT are described below.
B_I_T_ _ _ _D_E_S_C_R_I_P_T_I_O_N_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
4:9 Shows the address selected by the CPU device address
selection switches.
IOSTAT(4:8) = ADDRESS(16:20)
IOSTAT(9) = ADDRESS PARITY
10 LOGADDR < ULIM or LOGADDR < CPA. Output from the comparator
which compares LOGADDR and ULIM/CPA. Undefined during
memory and I/O operations.
11 LOGAADR < LLIM. Output from the comparator which compares
LOGADDR and LLIM. Undefined during memory and I/O
operations.
12:15 PREFETCH STATUS. Valid after termination of an instruction
fetch.
IOSTAT(12) = 0
IOSTAT(13) = PARITY ERROR
IOSTAT(14) = TIME OUT
IOSTAT(15) = NACK
20:23 I/O STATUS. Valid after termination of a memory or I/O
operation.
IOSTAT(20) = LIMIT VIOLATION
IOSTAT(21) = PARITY ERROR
IOSTAT(22) = TIME OUT
IOSTAT(23) = NACK
\f
F_ 2_._2_._1_._1_1_ _ _C_A_M_ _C_o_n_t_r_o_l_ _R_e_g_i_s_t_e_r_ 2.2.1.11
The CAM Control Register (CAMCNTR) is a 1-bit destination
register, which generates the control signal, BYPASSCAM.
BYPASSCAM: = CPUBUS(23)
When BYPASSCAM = 1 the system will act as if the cache memory is
not installed.
\f
2_._2_._2_ _ _ _ _ _I_n_t_e_r_r_u_p_t_ _C_o_n_t_r_o_l_ _U_n_i_t_ 2.2.2
The Interrupt Control Unit (ICU) receives interrupt requests via
the System Bus and sets the corresponding bit in the Interrupt
Register (IR). A priority encoder generates an Interrupt Level
(ILEV) corresponding to the bit in IR with the highest priority.
Lowest bit numbers have highest priority. The contents of ILEV
are compared with the contents of one of the two Interrupt Limit
registers (INTRLIM). If ILEV <= INTRLIM the ICU interrupts the
CPU.
From the microprogram is it possible to load the Interrupt Limit
Registers, read the Interrupt Level Register and clear bits in
IR.
2_._2_._2_._1_ _ _ _I_n_t_e_r_r_u_p_t_ _L_i_m_i_t_ _R_e_g_i_s_t_e_r_s_ 2.2.2.1
The Interrupt Disable Limit Register (IDLIM) and the Interrupt
Enable Limit Register (IELIM) are two 8-bit registers addressable
as one 16-bit destination register from the microprogram.
IDLIM(0:7): = CPUBUS(4:11)
IELIM(0:7): = CPUBUS(16:23)
The DISABLE bit in the CPU Status Register selects IDLIM or IELIM
as the current interrupt limit (ILIM).
if DISABLE = 1 then ILIM = IDLIM
else ILIM = IELIM
2_._2_._2_._2_ _ _ _I_n_t_e_r_r_u_p_t_ _L_e_v_e_l_ _R_e_g_i_s_t_e_r_ 2.2.2.2
The Interrupt Level Register (INTRLEV) is an 8-bit register
addressable as both source and destination register. When INTRLEV
is addressed as source the contents are transferred to the
CPUBUS.
CPUBUS(0:15) is undefined
CPUBUS(16:23) = INTRLEV(16:23)
\f
Addressing INTRLEV as destination will cause it to be loaded with
ILEV. Because this operation must be synchronized with the
internal ICU clock, it is necessary to insert a delay between the
microinstruction which loads INTRLEV and the microinstruction
which reads the contents of INTRLEV. This delay must be >= 700
ns.
2_._2_._2_._3_ _ _ _I_n_t_e_r_r_u_p_t_ _R_e_g_i_s_t_e_r_ 2.2.2.3
The Interrupt Register (IR) is a 58-bit register in which
interrupt requests are stored.
IR(6): POWER LOW interrupt
IR(7): INTERVAL TIMER interrupt
IR(8:63): DEVICE CONTROLLER interrupts.
Level 0 to 5 are not available as hardware interrupts. IR is only
addressable as a destination register. Execution of a microin-
struction with IR as destination will reset the interrupt request
bit selected by CPUBUS(18:23). The delay from the execution of a
microinstruction resetting an IR bit to the CPU interrupt is af-
fected is max:
900 ns + execution time for one microinstr.
Microinstructions used to reset IR bits must be separated by at
least 700 ns.
2_._2_._3_ _ _ _ _ _R_e_a_l_ _T_i_m_e_ _C_l_o_c_k_ 2.2.3
The Real Time Clock consists of a 16-bit counter which is incre-
mented by 1 every 0.1 ms. and counts modulo 65536. The value of
the counter may be read under microprogram control. In addition
the counter is used to generate an interrupt every 25.6 ms. (In-
terval Timer Interrupt).
2_._2_._3_._1_ _ _ _R_e_a_l_ _T_i_m_e_ _C_l_o_c_k_ _R_e_g_i_s_t_e_r_ 2.2.3.1
The Real Time Clock Register (RTC) is a 16-bit register address-
able as both source and destination register. The current value\f
of the RTC counter is transferred to RTC, when it is addressed as
destination (LOAD command). The contents of RCT are valid max.
200 ns. after the LOAD command. The contents of RTC are transfer-
red to the CPUBUS when addressed as source.
CPUBUS(0:23) = 8 ext 0 con RTC(8:23)
2_._2_._4_ _ _ _ _ _T_e_c_h_n_i_c_i_a_n_ _C_o_n_s_o_l_e_ _I_n_t_e_r_f_a_c_e_ 2.2.4
The Technician Console (TC) is a V.24 compatible terminal
connected to the CPU through an asynchronous serial I/O port
controlled by an UART (Universal Asynchronous Receiver/Trans-
mitter). Three registers are used for communication between the
UART and the microprogram.
2_._2_._4_._1_ _ _ _T_e_c_h_n_i_c_i_a_n_ _C_o_n_s_o_l_e_ _S_t_a_t_u_s_ _R_e_g_i_s_t_e_r_ 2.2.4.1
The Technician Console Status Register (TCSTAT) is a 3-bit source
register used to control communication with TC. The contents of
TCSTAT are transferred to CPUBUS when addressed as source.
CPUBUS(0:20) is undefined
CPUBUS(21:23) = TCSTAT(21:23)
TCSTAT has the following status bits:
B_I_T_ _ _ _D_E_S_C_R_I_P_T_I_O_N_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
21 -,DATASETRDY. A 0 indicates that TC is connected and is
ready to use.
22 DATAAVAIL. A 1 indicates that a character has been received
by the UART and is available in the TCDAIN register.
Addressing TCDAIN as destination resets DATAAVAIL.
23 TCOUTFULL. A 0 indicates that the UART transmitter is ready
to accept a character. TCOUTFULL changes to 1 when TCDAOUT
is loaded.
\f
The state of TCSTAT(22) and TCSTAT(23) is delayed one microcycle
relative to microinstructions controlling their state.
2_._2_._4_._2_ _ _ _T_e_c_h_n_i_c_i_c_a_n_ _C_o_n_s_o_l_e_ _D_a_t_a_ _I_n_ _R_e_g_i_s_t_e_r_ 2.2.4.2
The Technicican Console Data In Register (TCDAIN) is an 8-bit
source register containing characters received by the UART. The
contents of TCDAIN are transferred to CPUBUS when addressed as
source.
CPUBUS(0:15) is undefined
CPUBUS(16:23) = TCDAIN(16:23)
2_._2_._4_._3_ _ _ _T_e_c_h_n_i_c_i_a_n_ _C_o_n_s_o_l_e_ _D_a_t_a_ _O_u_t_ _R_e_g_i_s_t_e_r_ 2.2.4.3
The Technician Console Data Out Register (TCDAOUT) is an 8-bit
destination register. Characters loaded into TCDAOUT are
outputted to the Technician Console.
TCDAOUT(0:7): = CPUBUS(16:23)
2_._3_ _ _ _ _ _ _ _M_i_c_r_o_p_r_o_g_r_a_m_ _C_o_n_t_r_o_l_ _U_n_i_t_ 2.3
The microprogram control unit, which is located on the CPU821
printed circuit board, is built around the 2911A microprogram
sequencer as shown on fig. 4.
The Control Store (CS) is addressed via a 12-bit tri-state bus,
the Control Store Address Bus. The contents of the addressed CS
location are loaded into the Microinstruction Register (MIR),
which holds the microinstruction during its execution. The next
microinstruction to be executed is fetched from CS during the
execution of the current microinstruction in order to minimize
microinstruction cycle time. The Control Store Address (CSADDR)
may be selected from a number of sources as described in the
following subsections.
\f
2_._3_._1_ _ _ _ _ _M_i_c_r_o_i_n_s_t_r_u_c_t_i_o_n_ _A_d_d_r_e_s_s_ _R_e_g_i_s_t_e_r_ 2.3.1
The Microinstruction Address Register (MAR) is part of the 2911A
sequencer and is used for sequential microprogram addressing. In
each microcycle MAR is loaded with CSADDR+1.
2_._3_._2_ _ _ _ _ _S_u_b_r_o_u_t_i_n_e_ _R_e_t_u_r_n_ _S_t_a_c_k_ 2.3.2
The Subroutine Return Stack (STACK) is a 4 word x 12 bit register
file operating as a push-pop stack, i.e. last in/first out (LIFO)
structure. The STACK is used for saving of subroutine return
addresses and for microprogram loop control. Associated with the
STACK is a stack pointer (SP), pointing at the word on the top of
the STACK.
\f
F_
Figure 4: Microprogram control unit.
\f
2_._3_._3_ _ _ _ _ _M_i_c_r_o_p_r_o_g_r_a_m_ _J_u_m_p_ _A_d_d_r_e_s_s_ 2.3.3
The CSADDR for microprogram jumps may be selected from two
sources: the Microinstruction Register, MIR(36:47) and the
Destination Bus, DBUS(12:23). The last possibility makes it
possible to use the General Registers and the Q-register as
address sources. This may e.g. be useful for table look-up.
2_._3_._4_ _ _ _ _ _M_i_c_r_o_p_r_o_g_r_a_m_ _I_n_t_e_r_r_u_p_t_ _A_d_d_r_e_s_s_ 2.3.4
In case of microprogram interrupt the CSADDR is generated by an
8-input priority encoder. Depending on the priority of the
interrupt condition, the Interrupt Address (TEST) will address
one of the first eight CS locations.
2_._3_._5_ _ _ _ _ _A_d_d_r_e_s_s_ _C_a_l_c_u_l_a_t_i_o_n_ _D_e_c_o_d_i_n_g_ _M_a_p_ 2.3.5
RC8000 instructions are executed in two steps. The first step is
calculation of the effective address (EA). Microprogram start
addresses for the EA calculation routines are generated by the
Address Calculation Decoding Map (ADDRMAP), which is a 512 words
x 12 bits PROM. The entry address for ADDRMAP is generated as
described below.
E_N_T_R_Y_ _A_D_D_R_ _B_I_T_ S_O_U_R_C_E_ _ _ _ _ _ _ _ _ _
0 PREFETCH ERROR
1 0, not used
2 ESCAPE MODE
3 AFTER ESCAPE
4 AFTER AM
5 INSTRBUS(8)
6 (9)
7 (10)
8 (11)
\f
2_._3_._6_ _ _ _ _ _I_n_s_t_r_u_c_t_i_o_n_ _E_x_e_c_u_t_i_o_n_ _D_e_c_o_d_i_n_g_ _M_a_p_ 2.3.6
Second step in the execution of a RC8000 instruction is execution
of the instruction itself. Microprogram start addresses for the
instruction execution routines are generated by the Instruction
Execution Decoding Map (EXECMAP), which is a 1 K words x 12 bit
PROM. The entry address for EXECMAP is generated as described
below.
E_N_T_R_Y_ _A_D_D_R_ _B_I_T_ S_O_U_R_C_E_ _ _ _ _ _ _ _ _
0 ESCAPE MODE
1 FPU AVAILABLE
2 INSTRBUS(6)
3 (7)
4 INSTRBUS(0)
5 (1)
6 (2)
7 (3)
8 (4)
9 (5)
The microprogram address generated by EXECMAP is saved in a
register, EXECADDR, because execution of the current instruction
is overlapped with the decoding of the next instruction. EXECADDR
is used as CSADDR source.
2_._4_ _ _ _ _ _ _ _M_i_c_r_o_i_n_s_t_r_u_c_t_i_o_n_s_ 2.4
The CPU820 microinstruction repertoire comprises 8 different
formats as shown in fig. 5. The microinstructions are 48 bits
wide and consist of a number of fields. Microinstruction fields
common to two or more formats are described in the following sub-
sections. Fields referring to a single format are described in
connection with that format.
\f
2_._4_._1_ _ _ _ _ _P_ _F_i_e_l_d_ _=_ _M_I_R_(_0_)_ 2.4.1
The P field is the parity bit for the microinstruction. Odd
parity is used. In case of parity error the processor stops
immediately and the indicator 'CS PARITY ERROR' will be lit. MIR
contains the faulty microinstruction, which is not executed.
CSADDR depends on the NEXT field of the faulty microinstruction.
In order to proceed after control store parity error it is
necessary to turn power off and then on again.
2_._4_._2_ _ _ _ _ _N_E_X_T_ _F_i_e_l_d_ _=_ _M_I_R_(_1_:_4_)_ 2.4.2
The NEXT field defines CSADDR for the next microinstruction to be
executed. The following abbreviations are used to describe the
function of the NEXT field.
CSADDR: control store address.
MAR: microinstruction address register.
STACK: subroutine return stack.
SP: stack pointer for STACK.
ADDRMAP: address calculation decoding map.
EXECMAP: instruction execution decoding map.
EXECADDR: buffer register for EXECMAP.
TESTCOND: condition selected by 'COND SEL' field.
PREFEN: control signal generated by instruction decoding
logic.
PREFIR: prefetch instruction register.
PREFIC: prefetch instruction counter.
DISP: displacement register.
RELADDR: relative address register.
MEM(A): contents of main memory location A.
\f
F_
Figure 5: Microinstruction formats.
\f
F_ N_E_X_T_ F_U_N_C_T_I_O_N_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
0000 POP and CONTINUE.
CSADDR: = MAR; MAR: = MAR+1; SP: = SP-1
0001 PUSH and CONTINUE (loop set-up).
CSADDR: = MAR; SP: = SP+1; STACK(SP): = MAR, MAR: = MAR+1
0011 CONTINUE.
CSADDR: = MAR; MAR: = MAR+1;
1000 SUBROUTINE RETURN.
CSADDR: = STACK(SP); MAR: = STACK(SP)+1; SP: = SP-1;
1011 CONDITIONAL LOOP RETURN.
SELCOND = 0: CSADDR: = STACK(SP); MAR: = STACK(SP)+1;
SELCOND = 1: CSADDR: = MAR; SP: = SP-1; MAR: = MAR+1;
1110 NEXT INSTRUCTION.
CSADDR: = ADDRMAP; MAR: = ADDRMAP+1;
EXECADDR: = EXECMAP;
DISP: = 12 ext PREFIR(12) con PREFIR(12:23);
RELADDR: = 0 con IC(1:22) con 0 +
12 ext PREFIR(12) con PREFIR(12:23);
PREFIC: = PREFIC + 2;
if PREFEN = 1 then PREFIR: = MEM(PREFIC);
1111 EXECUTE.
CSADDR: = EXECADDR; MAR: = EXECADDR+1;
IC: = IC+2;
2_._4_._3_ _ _ _ _ _C_L_ _F_i_e_l_d_ _=_ _M_I_R_(_5_,_6_)_ 2.4.3
CL controls the microinstruction cycle length.
C_L_ C_Y_C_L_E_ _L_E_N_G_T_H_ _
00 150 ns.
01 200 ns.
10 250 ns.
11 300 ns.
\f
Most microinstructions may be executed in 150 ns. Certain
combinations of format, ALU function, source and destination
addresses require a longer cycle length.
2_._4_._4_ _ _ _ _ _F_ _F_i_e_l_d_ _=_ _M_I_R_(_7_:_9_)_ 2.4.4
The F field defines the microinstruction format and thereby the
usage of bit(20:47) of the microinstruction.
2_._4_._5_ _ _ _ _ _A_L_U_-_D_ _F_i_e_l_d_ _=_ _M_I_R_(_1_0_,_1_1_)_ 2.4.5
The ALU-D field selects destination for the ALU output (F).
A_L_U_-_D_ F_U_N_C_T_I_O_N_ _ _ _ _ _ _ _ _ _ _ _ _ _ _
00 Q: = F; DBUS: = F;
01 DBUS: = F;
10 GRB: = F; DBUS: = GRA;
11 GRB: = F; DBUS: = F;
2_._4_._6_ _ _ _ _ _A_L_U_-_O_P_ _F_i_e_l_d_ _=_ _M_I_R_(_1_2_:_1_4_)_ 2.4.6
The ALU-OP field selects the two operands, R and S, for the ALU.
A_L_U_-_O_P_ O_P_E_R_A_N_D_ _R_ O_p_e_r_a_n_d_ _S_ _
000 GRA Q
001 GRA GRB
010 ZERO Q
011 ZERO GRB
100 ZERO GRA
101 SBUS GRA
110 SBUS Q
111 SBUS ZERO
\f
2_._4_._7_ _ _ _ _ _A_L_U_-_F_U_N_C_ _F_i_e_l_d_ _=_ _M_I_R_(_1_5_:_1_7_)_ 2.4.7
The ALU can perform three arithmetic and five logic functions.
The ALU-FUNC field selects one of these functions. Cin is the
carry input to the least significant position of the ALU
controlled by the ALU-C field.
A_L_U_-_F_U_N_C_ A_L_U_ _F_U_N_C_T_I_O_N_ _
000 R+S+Cin
001 -R+S-1+Cin
010 R-S-1+Cin
011 R!S
100 R&S
101 -,R&S
110 R exor S
111 -,(R exor S)
2_._4_._8_ _ _ _ _ _A_L_U_-_C_ _F_i_e_l_d_ _=_ _M_I_R_(_1_8_,_1_9_)_ 2.4.8
The ALU-C field controls the carry input, Cin, to the ALU.
A_L_U_-_C_ C_i_n_ _ _ _ _ _
00 0
01 1
10 CARRY
11 ADDCOND
2_._4_._9_ _ _ _ _ _A_ _F_i_e_l_d_ _=_ _M_I_R_(_2_0_:_2_4_)_ 2.4.9
The A field addresses the A port of the general registers, GRA.
MIR(20) is used to select direct or indirect addressing of GRA.
\f
M_I_R_(_2_0_)_ M_I_R_(_2_3_,_2_4_)_ G_R_A_ _A_D_D_R_E_S_S_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
0 00 MIR(21,22) con WFIELD(0,1)
0 01 MIR(21,22) con WPRE(0,1)
0 10 MIR(21,22) con XFIELD(0,1)
0 11 MIR(21,22) con EA(21,22)
1 - MIR(21:24)
2_._4_._1_0_ _ _ _ _B_ _F_i_e_l_d_ _=_ _M_I_R_(_2_5_:_2_9_)_ 2.4.10
The B field addresses the B port of the general registers, GRB.
The B field is also used as destination address for the general
registers. MIR(25) is used to select direct or indirect address-
ing of GRB.
M_I_R_(_2_5_)_ M_I_R_(_2_8_,_2_9_)_ G_R_B_ _A_D_D_R_E_S_S_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
0 00 MIR(26,27) con WFIELD(0,1)
0 01 MIR(26,27) con WPRE(0,1)
0 10 MIR(26,27) con XFIELD(0,1)
0 11 MIR(26,27) con EA(21,22)
1 - MIR(26:29)
2_._4_._1_1_ _ _ _ _U_N_I_T_ _F_U_N_C_/_T_E_S_T_ _F_i_e_l_d_ _=_ _M_I_R_(_3_0_:_3_5_)_ 2.4.11
This field has two functions controlled by MIR(30).
MIR(30) = 0: MIR(31:35) may be used as a UNIT FUNCTION to control
units connected to the CPBUS. The interpretation of the field
depends on the unit concerned.
UNIT FUNCTION(0:5) = 0 con MIR(31:35).
MIR(30) = 1: MIR(31:35) is used as mask bits for microprogram
interrupt conditions. MASK BIT = 1 enables the interrupt condi-
tion. When one or more of the enabled conditions are 1, one of
the first eight CS locations, will be selected as the next CS
address independant of the NEXT field. The address is generated
by a priority encoder and the condition corresponding to CS
location 0 has the highest priority.
\f
C_S_ _L_O_C_A_T_I_O_N_ I_N_T_R_._ _C_O_N_D_I_T_I_O_N_ _ _ _ _ _ M_A_S_K_ _B_I_T_ _ _
0 POWER UP UNMASKABLE
1 CPU INTR MIR(31)
2 LIMIT VIOLATION MIR(35)
3 I/O ERROR MIR(32)
4 OVFL & INT. MASK MIR(33)
5 SHIFT OVFL & INT MASK MIR(34)
6 EXT INTR MIR(31)
7 UNUSED
CPU INTR indicates interrupt from one or more of the following
sources, which may be tested individually by conditional jumps.
SINGLE INSTRUCTION INTR.
TC INPUT
AUX. INTR. (unused)
CAM ERROR
OCP AUTOLOAD
REMOTE AUTOLOAD
EXT INTR indicates interrupt from a device connected to the
SYSTEM BUS. EXT INTR is generated by the Interrupt Control Unit
on the CPU822.
2_._4_._1_2_ _ _ _ _I_N_T_/_E_X_T_ _R_E_G_ _D_E_S_T_ _F_i_e_l_d_ _=_ _M_I_R_(_4_2_:_4_7_)_ 2.4.12
This field is used to address destination registers located on
the CPU821 and on modules connected to the CPUBUS.
INT/EXT
R_E_G_ _D_E_S_T_ C_P_U_8_2_1_ _D_E_S_T_I_N_A_T_I_O_N_ _R_E_G_I_S_T_E_R_S_ _ _ _ _ _ _ _ _ _ _ _
00 No load.
01 Logical Address Status (LASTAT).
02 Scratchpad (SCRATCHP). Format(0) only.
03 Instruction Counter (IC).
04 Loop Counter (LC).
05 CPU Status (CPUST).
06 Control Output (CONTROLOUT).
07 Not used.
\f
INT/EXT
R_E_G_ _D_E_S_T_ C_P_U_8_2_2_ _D_E_S_T_I_N_A_T_I_O_N_ _R_E_G_I_S_T_E_R_S_ _ _ _ _ _ _ _ _ _ _ _ _
10 Not used.
11 Logical Address (LOGADDR) & LASTAT.
12 Data Out (DATAOUT).
13 Base (BASE).
14 Lower Limit (LLIM).
15 Upper Limit (ULIM).
16 CPA Limit (CPA).
17 Real Time Clock (RTC), load command.
20 Clear Intr. Reg. (IR) bit.
21 Interrupt Limit (IDLIM & IELIM).
22 Interrupt Level (INTRLEV), load command.
23 Techn. Console Data Out (TCDAOUT).
24 CAM Bypass Control.
25 Clear TC interrupt & TCSTAT(22).
C_A_M_8_0_1_/_8_0_3_ _D_E_S_T_I_N_A_T_I_O_N_ _R_E_G_I_S_T_E_R_S_ _ _ _ _ _ _ _ _
40 CAM Test Data
41 CAM Control
F_P_U_8_0_1_ _D_E_S_T_I_N_A_T_I_O_N_ _R_E_G_I_S_T_E_R_S_ _ _ _ _ _ _ _ _ _ _ _ _
70 FPU FRACTION(0:23)
71 FPU FRACTION(24:35) con EXP(0:11)
2_._4_._1_3_ _ _ _ _T_ _F_i_e_l_d_ _=_ _M_I_R_(_3_0_)_ 2.4.13
The T field is used to specify whether the true or the complemen-
ted value of the condition selected by the COND SELECT field is
assigned SELCOND.
T=0: SELCOND = complemented value of condition.
T=1: SELCOND = true value of condition.
\f
2_._4_._1_4_ _ _ _ _C_O_N_D_ _S_E_L_E_C_T_ _F_i_e_l_d_ _=_ _M_I_R_(_3_1_:_3_5_)_ 2.4.14
The COND SELECT field selects 1 of the 24 conditions listed
below.
COND
S_E_L_E_C_T_ S_E_L_E_C_T_E_D_ _C_O_N_D_I_T_I_O_N_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
00 ZERO
01 NEG: DBUS(0)
02 NZERO: F <> 0
03 OVFL: arithm. overflow
04 CARRY: carry from ALU bit(0)
05 SIGN: F(0) exor OVR 1)
06 NORMO: DBUS(0) <> DBUS(1)
07 NORM1: DBUS(1) <> DBUS(2)
10 DIVOVFL: SHLINK <> CARRY 2)
11 LC(0)
12 MAXLOOP: -,LC(0)!-,LCMAX(0)
13 -,WADDR
14 EA(0)
15 Not used
16 MONMODE
17 ESCMODE
20 CPUINTR
21 EXTINTR: device interrupt
22 -,TC INPUT READY
23 -,AUXINTR: unused
24 -,CAMERROR
25 -,OCP AUTOLOAD
26 -,REMOTE AUTOLOAD
27 POWER LOW
Notes:
1) OVR is the overflow signal from the 2901.
2) SHLINK is the bit shiftet out by a shift microinstruction.
\f
The conditions: NEG, NZERO, OVFL, CARRY, SIGN, SHLINK, NORMO,
NORM1 and DIVOVFL are updated by all microinstruction formats
with the exception of format 6, conditional jump. These condi-
tions are delayed one microcycle compared to the microinstruc-
tions which generate them.
2_._4_._1_5_ _ _ _ _F_o_r_m_a_t_ _0_ _:_ _R_e_a_d_/_L_o_a_d_ _S_c_r_a_t_c_h_p_a_d_ 2.4.15
Format 0 operates on the Scratchpad (SCRATCHP). The SCRATCHP ADDR
field = MIR(38:41) addresses one of the 16 locations. The
complemented contents of the addressed location are transferred
to the SBUS.
SBUS = -,SCRATCHP(SCRATCHP ADDR)
The addressed SCRATCHP location is loaded with the contents of
DBUS when the INT/EXT REG DEST field, MIR(42:47), specifies
SCRATCHP as destination.
SCRATCHP(SCRATCHP ADDR): = DBUS
The SCRATCHP cannot be used as both source and destination within
the same microcycle.
2_._4_._1_6_ _ _ _ _F_o_r_m_a_t_ _1_ _:_ _R_e_a_d_/_L_o_a_d_ _R_e_g_i_s_t_e_r_ 2.4.16
Source registers located on the CPU821 (internal source re-
gisters) may be accessed by means of format 1 microinstruc-
tions. The contents of the register addressed by the INT REG
source field, MIR(36:41), are transferred to the SBUS.
INT REG
S_O_U_R_C_E_ _ S_O_U_R_C_E_ _R_E_G_I_S_T_E_R_/_F_U_N_C_T_I_O_N_ _
00 Displacement (DISP)
10 Instruction Counter (IC)
20 DISP + IC
30 Loop Counter (LC)
\f
40 DBUS(0:21) con OVFL con CARRY
41 DBUS(0:21) con SHIFTOVFL con 0
42 DBUS(0:21) con 0 con 0
43 DBUS(0:21) con 0 con 0
50 Switch Register (SWITCH)
2_._4_._1_7_ _ _ _ _F_o_r_m_a_t_ _2_ _:_ _R_e_a_d_ _C_o_n_s_t_a_n_t_ 2.4.17
Constants in the Constant Memory (CONST) are addressed by the
CONSTANT ADDR field, MIR(36:41). The addressed constant is
transferred to the SBUS.
SBUS = CONST(CONSTANT ADDR)
CONSTANT
A_D_D_R_ _ _ _ _ C_O_N_S_T_A_N_T_,_ _o_c_t_a_l_ _
00 0000 7000
01 0000 7760
02 0000 0046
03 0000 7777
04 0000 0027
05 0000 0026
06 0000 0025
07 0000 0017
10 0000 0016
11 0000 0014
12 0000 0013
13 0000 0012
14 0000 0003
15 0000 0004
16 0000 0020
17 0000 0040
\f
CONSTANT
A_D_D_R_ _ _ _ _ C_O_N_S_T_A_N_T_,_ _o_c_t_a_l_ _
20 0000 0100
21 0000 0200
22 0000 1000
23 0000 4000
24 0020 0000
25 0040 0000
26 0100 0000
27 0200 0000
30 0000 0006
31 0400 0000
32 1000 0000
33 2000 0000
34 0000 0007
35 4000 0000
36 0000 0010
37 0000 0001
2_._4_._1_8_ _ _ _ _F_o_r_m_a_t_ _3_ _:_ _R_e_a_d_ _E_x_t_e_r_n_a_l_ _R_e_g_i_s_t_e_r_ 2.4.18
When this format is used the SBUS receives data from the CPUBUS.
The format may therefore be used to access source registers
connected to the CPUBUS. The register address is specified by the
EXT REG SOURCE field, MIR(36:41).
EXT REG
S_O_U_R_C_E_ _ C_P_U_8_2_2_ _S_O_U_R_C_E_ _R_E_G_I_S_T_E_R_S_ _ _ _ _ _ _ _ _ _
00 Data In (DATAIN)
01 I/O Status (IOSTAT)
02 Real Time Clock (RTC)
03 Interrupt Level (INTRLEV)
04 Techn. Console Data In (TCDAIN)
05 Techn. Console Status (TCSTAT)
\f
EXT REG
S_O_U_R_C_E_ _ _ C_A_M_8_0_1_/_8_0_3_ _-_ _C_P_U_8_2_2_ _S_O_U_R_C_E_ _R_E_G_I_S_T_E_R_S_ _
40 Data In (DATAIN) 1)
41 I/O Status (IOSTAT) 1)
F_P_U_8_0_1_ _S_O_U_R_C_E_ _R_E_G_I_S_T_E_R_S_ _ _ _ _ _ _ _
70 FRACTION(0:23)
71 FRACTION(24:35) con EXP(0:11)
72 EXCEPTION(22,23)
1) The DATAIN and IOSTAT registers on the CAM respond automati-
cally to the common addresses when the CAM is installed,
otherwise the registers on the CPU822 respond to the addres-
ses.
2_._4_._1_9_ _ _ _ _F_o_r_m_a_t_ _4_ _:_ _H_a_l_f_-_W_o_r_d_ _M_a_n_i_p_u_l_a_t_o_r_ 2.4.19
When this format is used the SBUS receives data from the
Half-Word Manipulator, HWM. The operation of the HWM is
controlled by the MANIPULATOR FUNCTION field, MIR(36:41), and the
ODD bit in the LASTAT register.
MANIP.
F_U_N_C_T_I_O_N_ O_D_D_ S_B_U_S_(_0_:_1_1_)_ _ _ _ _ _ S_B_U_S_(_1_2_:_2_3_)_ _
00 0 12 ext 0 DBUS(0:11)
00 1 12 ext 0 DBUS(12:23)
01 0 12 ext DBUS(0) DBUS(0:11)
01 1 12 ext DBUS(12) DUBS(12:23)
02 0 DBUS(12:23) 12 ext 0
02 1 12 ext 0 DBUS(12:23)
03 0 12 ext 0 12 ext 1
03 1 12 ext 1 12 ext 0
04 x 12 ext DBUS(12) DBUS(12:23)
05 x DBUS(12:23) DBUS(0:11)
06 x 12 ext 0 DBUS(0:11)
07 x DBUS(12:23) 12 ext 0
\f
When the HWM is used, the ALU-D field must be controlled in the
following way.
ALU-D = 10: DBUS: = GRA; GRB: = F;
2_._4_._2_0_ _ _ _ _F_o_r_m_a_t_ _5_ _:_ _L_o_a_d_ _I_m_m_e_d_i_a_t_e_ 2.4.20
The 24-bit IMMEDIATE OPERAND field, MIR(20:43), is transferred to
the SBUS. The Q-register is the only register, which can be used
in format 5 microinstructions.
2_._4_._2_1_ _ _ _ _F_o_r_m_a_t_ _6_ _:_ _C_o_n_d_i_t_i_o_n_a_l_ _J_u_m_p_ 2.4.21
This microinstruction format executes conditional jumps and
conditional subroutine calls. The S field, MIR(28), is used to
specify subroutine call. The JUMP ADDRESS field, MIR(36:47), or
DBUS(12:23) may be selected as address source. The X field,
MIR(29), selects address source. The condition (SELCOND)
specified by the T and the COND SELECT fields determines the
address of the next microinstruction to be executed.
SELCOND = 0: NEXT field selects CSADDR.
SELCOND = 1: CSADDR is controlled by the S and X fields as
described below.
S_,_X_ F_U_N_C_T_I_O_N_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
00 JUMP
CSADDR: = JUMP ADDR; MAR: = JUMP ADDR+1;
01 INDEXED JUMP.
CSADDR: = DBUS(12:23); MAR: = DBUS(12:23)+1;
10 CALL.
CSADDR: = JUMP ADDR; SP: = SP+1;
STACK(SP): = MAR; MAR: = JUMP ADDR + 1
11 INDEXED CALL.
CSADDR: = DBUS(12:23); SP: = SP+1;
STACK(SP): = MAR; MAR: = DBUS(12:23)+1;
\f
A format 6 microinstruction with NEXT = 1110 (NEXT INSTRUCTION)
will start an instruction prefetch regardless of the current
value of PREFEN (PREFETCH ENABLE). This feature may be used for
the skip case of an RC8000 skip instruction.
2_._4_._2_2_ _ _ _ _F_o_r_m_a_t_ _7_ _:_ _S_h_i_f_t_,_ _M_u_l_t_i_p_l_y_ _a_n_d_ _D_i_v_i_d_e_ 2.4.22
This format is especially intended for support of shift, multiply
and divide instructions.
The NS field, MIR(36), is used in connection with the ALU-D field
to control shift operations as specified below.
N_S_ A_L_U_-_D_ F_U_N_C_T_I_O_N_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
0 00 GRB con Q: = SHIN con F con Q(0:22);
0 01 GRB: = SHIN con F(0:22);
0 10 GRB con Q: = F(1:23) con Q con SHIN;
0 11 GRB: = F(1:23) con SHIN;
1 00 Q: = F; DBUS: = F;
1 01 DBUS: = F;
1 10 GRB: = F; DBUS: = GRA;
1 11 GRB: = F; DBUS: = F;
The SI field, MIR(37,38), controls the input (SHIN) to the
vacated position in shifts.
S_I_ S_H_I_N_,_ _r_i_g_h_t_ _s_h_i_f_t_ S_H_I_N_,_ _l_e_f_t_ _s_h_i_f_t_ _
00 ZERO ZERO
01 SHLINK SHLINK
10 F(0) ADDCOND
11 SIGNEXT NOT USED
SIGNEXT = sign extension.
The M field, MIR(40), in connection with the ALU-OP field and the
condition, ADDCOND, are especially intended to be used in multi-
plication routines.
\f
M_ A_L_U_-_O_P_ A_D_D_C_O_N_D_ O_P_E_R_A_N_D_ _R_ O_P_E_R_A_N_D_ _S_ _
0 000 X GRA Q
0 001 X GRA GRB
0 010 X ZERO Q
0 011 X ZERO GRB
0 100 X ZERO GRA
0 101 X SBUS GRA
0 110 X SBUS Q
0 111 X SBUS ZERO
1 0X0 0 GRA Q
1 0X0 1 ZERO Q
1 0X1 0 GRA GRB
1 0X1 1 ZERO GRB
1 1X0 0 ZERO GRA
1 1X0 1 SBUS Q
1 1X1 0 SBUS GRA
1 1X1 1 SBUS ZERO
The D field, MIR(41), in connection with the ALU-FUNC field and
ADDCOND are especially intended for use in division routines.
D_ A_L_U_-_F_U_N_C_ A_D_D_C_O_N_D_ A_L_U_ _F_U_N_C_T_I_O_N_ _
0 000 X R+S+Cin
0 001 X -R+S-1+Cin
0 010 X R-S-1+Cin
0 011 X R!S
0 100 X R&S
0 101 X -,R&S
0 110 X R exor S
0 111 X -,(R exor S)
1 00X 0 R+S+Cin
1 00X 1 -R+S-1+Cin
1 01X 0 R-S-1+Cin
1 01X 1 R!S
1 10X 0 R&S
1 10X 1 -,R&S
1 11X 0 R exor S
1 11X 1 -,(R exor S)
\f
The TST field, MIR(42,43), controls the conditions, ADDCOND and
DIVCOND. These conditions are only affected by format 7
microinstructions.
T_S_T_ F_U_N_C_T_I_O_N_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
00 DIVSIGN: = F(0)
01 ADDCOND: = F(0) exor -,DIVSIGN
10 ADDCOND: = -,Q(23)
11 CONDITIONS UNCHANGED
The shift overflow condition, SHIFTOVFL, can only be set by
execution of a format 7 microinstruction.
Set SHIFTOVFL = FORMAT 7 & (DBUS(0) exor DBUS(1))
Once SHIFTOVFL has been set it remains set until execution of a
format 0,1,2,3,4 or 5 microinstruction, which clears it.
\f
F_
RC NET
General Information
Third Edition
A/S REGNECENTRALEN af 1979 October 1979
Information Department 42-i 1277\f
AUTHOR: Erik Lilholt/Herbert Jessen
KEYWORDS: RC 3600, RC 3502, RC 8000, Computer Network,
Communication
ABSTRACT: This manual describes in an introductory manner the
concepts and facilities of the computer network RC NET.
Copyright 1979 A/S Regnecentralen af 1979/RC Computer
Printed by A/S Regnecentralen af 1979, Copenhagen \f
Table of Contents
Introduction Page7
1 RC NET OVERVIEW 8
1.1 Main Structure 8
1.2 The Packet Switch 9
1.2.1 Nodes 9
1.2.2 Communication Lines 9
1.2.3 Regions10
1.2.4 Connection of Networks 10
1.3 Hosts 11
1.3.1 RC NET Packet Transporter 13
1.3.2 RC NET Message Transporter 14
1.3.3 Network Interface Implementation 14
1.3.3.1 RC 8000 Network Interface 14
1.3.3.2 Foreign Computer Network Interface 14
1.3.4 External and Internal Hosts 14
1.3.4.1 External Host 14
1.3.4.2 Internal Host 15
1.4 Summary 15
2 RC NET COMPONENTS 17
2.1 Hardware Components 17
2.1.1 RC 8000 17
2.1.2 RC 3600 17
2.1.3 RC 3502 18
2.2 Software Components 18
2.2.1 RC NET Packet Switch 18
2.2.2 RC NET Line and Channel Protocols 18
2.2.3 Network Control Facilities 19
2.2.4 Network Access Facilities 19
2.3 Functional Components 20
2.3.1 RC 3600 Network Node 20
2.3.2 RC 8000 Access to RC NET 21
2.3.2.1 X.25 Virtual Channel Access 21
2.3.2.2 RC 8000 Device Control Protocol 22
2.3.3 RC NET Node with X.25 Access 23
2.3.4 RC NET Node with Synchronous PAD>s 23
2.3.5 Network Operational Center 24
3 RC NET PACKET SWITCH 26
3.1 Network Topology 26
3.1.1 Nodes and Communication Lines 26\f
3.1.2 Alternate Paths 27
3.1.3 Regions 28
3.1.4 Region Identification 29
3.1.5 Node identification 29
3.2 Hosts 29
3.2.1 Host Identification 29
3.2.2 Host Attributes 30
3.2.2.1 HOME-REGION 30
3.2.2.2 CURRENT-REGION30
3.2.2.3 CURRENT-NODE30
3.3 Packet Format31
3.3.1 Format of the Packet Header31
3.3.2 Content of the Packet Header32
3.3.2.1 FORMAT32
3.3.2.2 PACKET TEXT LENGTH32
3.3.2.3 PACKET HEADER LENGTH33
3.3.2.4 USER HEADER LENGTH33
3.3.2.5 STATE33
3.3.2.6 PRIORITY33
3.3.2.7 RECEIVER CURRENT-REGION33
3.3.2.8 RECEIVER CURRENT-NODE33
3.3.2.9 SENDER CURRENT-REGION33
3.3.2.10 SENDER CURRENT-NODE33
3.3.2.11 RECEIVER NET-ID33
3.3.2.12 SENDER NET-ID33
3.3.2.13 RECEIVER HOME-REGION33
3.3.2.14 SENDER HOME-REGION33
3.3.2.15 RECEIVER HOST-ID33
3.3.2.16 SENDER HOST-ID33
3.3.2.17 FACILITY MASK33
3.3.2.18 IDENTIFICATION33
3.3.3 The Packet Text34
4 RC NET PACKET TRANSPORTER35
4.1 Position in the Network Protocols35
4.2 Method of Control35
4.3 Pipelines36
5 RC NET MESSAGE TRANSPORTER38
5.1 Position in the Network Procotols38
5.2 Method of Control39
5.3 Relations to Pipelines40
6 RC NET DEVICE CONTROL PROTOCOL41
6.1 Links41\f
6.2 Device Specification41
6.3 Master-Slave Relation42
7 RC NET VOCUBULARY43
References46\f
F_ INTRODUCTION
RC NET is a computer network developed and marketed by RC Compu-
ter.
RC NET offers a general transportation service based on packet
switching technology.
RC NET offers standard modules for interfacing the network to
user programs executed on RC computers and for interfacing to RC
marketed peripheral equipment. The modules allow standard access
methods to be utilized by user programs when communicating
through RC NET.
RC NET offers facilities for interfacing to a number of mainframe
systems.
The information in this manual is intended to give a reader, fa-
miliar with general network principles, a knowledge of the struc-
ture of RC NET, the concepts laid down in the design and the ter-
minology used.
The manual does not contain sufficient detail to allow it to be
used as a reference manual. Reference information can be found in
the manuals describing the relevant RC NET systems, e.g. RC NET
Level 1. References 2 and 3 contain further information.
\f
F_ 1 RC NET Overview
This section gives a summary description of RC NET.
At this stage it may provide the reader with enough information
to allow him to omit the rest of the manual, yet having given him
an impression of RC NET capabilities.
Later chapters contain more detailed explanations of the concepts
presented.
1.1 Main Structure
Basically RC NET is divided into a P_a_c_k_e_t_ _S_w_i_t_c_h_ and attached
h_o_s_t_s_.
In this context an addressable location of the packet switch is
denoted a h_o_s_t_. The P_a_c_k_e_t_ _T_r_a_n_s_p_o_r_t_e_r_ and the M_e_s_s_a_g_e_ T_r_a_n_s_p_o_r_-
t_e_r_ are two protocols offered by RC NET for the exchange of in-
formation between hosts.
Figure 1.1 RC NET Structure \f
F_ 1.2 The Packet Switch
The RC NET Packet Switch functions as a self-contained packet
switching network offering the basic transportation service
needed in a computer network (datagram service).
The Packet Switch is made up of nodes, in the form of RC 3600 or
RC 3502 processing units.
The addressable unit of the Packet Switch is a h_o_s_t_. Each host is
assigned a unique identification, the H_O_S_T_-_I_D_.
1.2.1 N_o_d_e_s_
The main function of the Packet Switch nodes is to keep track of
the hosts currently connected and their locations in the network.
The Packet Switch accepts p_a_c_k_e_t_s_ from the connected hosts. Part
of the packet contains the HOST-ID of the host to which the
packet is sent.
Based on the r_o_u_t_i_n_g_ _a_l_g_o_r_i_t_h_m_ implemented in the Packet Switch,
the packet is forwarded from node to node until it reaches a node
to which the receiving host is connected.
The routing algorithm is based on r_o_u_t_i_n_g_ _t_a_b_l_e_s_ maintained in
the nodes and a s_t_r_a_t_e_g_y_ for updating these tables. This strategy
may range from no changes of the routing tables (fixed routing)
through changes due to network reconfigurations (node or line
failure) to dynamic changes taking into account line load and
queuing estimates.
1.2.2 C_o_m_m_u_n_i_c_a_t_i_o_n_ _L_i_n_e_s_
The nodes are connected by means of communication lines. The
protocol adopted by RC NET for synchronous lines is the HDLC-
protocol (X.25 LAP B). Please refer to Ref. 1 and 4.
For use on existing BSC controllers, RC NET encounters a slightly
modified HDLC-protocol, where the frame-format is changed, but
the content of the address, control and information fields remain
unchanged.
Also high-speed channel connections between node systems are sup-
ported as RC NET communication lines.
\f
1.2.3 R_e_g_i_o_n_s_
The nodes of RC NET are collected into logical entities denoted
r_e_g_i_o_n_s_.
For a specific network the region structure is intended to be
defined in such a way, that there is a much larger exchange of
information within a region than between regions.
N: Nodes
L: Communication Lines
R: Regions
Figure 1.2 The Region concept.
The routing tables of a node will in detail describe the struc-
ture of the region to which the node belongs. Other regions will,
however, be regarded as "black boxes" whose internal structure is
not known.
Note that the region concept does not prohibit communication be-
tween hosts in different regions.
1.2.4 C_o_n_n_e_c_t_i_o_n_ _o_f_ _N_e_t_w_o_r_k_s_
RC NET is prepared for network interconnection.
Each network is assigned an identification, NET-ID, so that each
host has a NET-ID in addition to its HOST-ID. \f
The HOST-ID must be unique within a network. In case of connected
networks, NET-ID together with HOST-ID forms a unique identifica-
tion. NET-ID is included in the packet-format together with HOST-
ID.
A format field in the packet allows the packet-structure of for-
eign networks to be utilized with RC NET.
1.3 Hosts
As stated, a host is the unit which may be addressed by the Pac-
ket Switch.
A more user-oriented viewpoint is to regard a host as a collec-
tion of processes which, within a network, is seen as a separate
entity and should be addressed as such.
Figure 1.3 The host as a collection of processes.
The service a user expects from a transportation network is based
on its capability to receive and transmit information of any con-
tent and (nearly) any length via the network (with the identifi-
cation of the receiving host). In RC NET such information is cal-
led a message.
As the Packet Switch only performs the routing and switching
functions, it is the responsibility of the hosts to implement an
end-to-end check on the information exchanged. End-to-end check-
ing means that the transmitting host expects an acknowledgement\f
signal to be returned from the receiving host when some informa-
tion has passed through the network. If this signal is not re-
ceived within a specified time, an error recovery procedure is
activated which may cause retransmission of the information.
This means that a host can be regarded as being divided into a
N_e_t_w_o_r_k_ _I_n_t_e_r_f_a_c_e_ _P_a_r_t_ and an A_p_p_l_i_c_a_t_i_o_n_ _P_a_r_t_.
The Network Interface performs a conversion of formats known in
the Application Part to the formats required by the Packet
Switch. Part of this is the conversion between messages and pac-
kets.
The Network Interface Part corresponds to protocol level 4 as
described in Ref. 5.
Figure 1.4 HOST structure
RC NET will offer standard protocols for communication between
Network Interfaces in different hosts. The protocol implement
layers of responsibility.
The R_C_ _N_E_T_ _P_a_c_k_e_t_ _T_r_a_n_s_p_o_r_t_e_r_ is based directly on the services
offered by the Packet Switch. The R_C_ _N_E_T_ _M_e_s_s_a_g_e_ _T_r_a_n_s_p_o_r_t_e_r_
again utilizes the functions of the Packet Transporter.
\f
T_
&_ Figure 1.5 Network Interface Structure
1.3.1 R_C_ _N_E_T_ _P_a_c_k_e_t_ _T_r_a_n_s_p_o_r_t_e_r_
This protocol implements the end-to-end functions needed to en-
sure that packets entered into the Packet Switch actually reach
the specified receiving host, provided it is currently connected
to the network.
The method of control is very much similar to the one adopted in
the HDLC-protocol. Packets are sequentially numbered and the num-
ber is included in the packet. They also carry the number of the
last packet that (along with earlier packets) has been correctly
received.
Though this makes the Packet Switch look very much like a commu-
nication line, some differences exist.
For instance, packets are not necessarily delivered from the net-
work in the sequence in which they are received. This is espe-
cially the case when packets with different priorities are en-
tered into the network.
For this reason, the Packet Transporter implements a number of
logical channels, called p_i_p_e_l_i_n_e_s_. On each pipeline the packets
are independently numbered and acknowledged. The pipelines may be
utilized in such a way that a specific pipeline is used for pac-
kets having a certain priority.
\f
1.3.2 R_C_ _N_E_T_ _M_e_s_s_a_g_e_ _T_r_a_n_s_p_o_r_t_e_r_
This protocol implements the functions needed to control the dis-
assembling of messages into packets at the transmitting host and
the reassembling of the message at the receiving host.
The packets are individually transmitted through the Packet
Switch utilizing the end-to-end check of the Packet Transporter.
The Message Transporter adds the message>s sequential number, the
packet>s sequential number within the message and the number of
packets in the message to each packet of the message.
Examples of a Message Transporter is outlined in Ref. 6 and 7.
1.3.3 N_e_t_w_o_r_k_ _I_n_t_e_r_f_a_c_e_ _I_m_p_l_e_m_e_n_t_a_t_i_o_n_
An important feature of RC NET is that the abovementioned proto-
cols are not restricted to use on a specific computer. They
should simply be considered as logical levels in the network
which may be implemented in different ways.
The idea is illustrated by two examples.
1.3.3.1 R_C_ _8_0_0_0_ _N_e_t_w_o_r_k_ _I_n_t_e_r_f_a_c_e_. When an RC 8000 is connected to RC
NET, the Network Interface Part resides partly in the RC 8000,
partly in the Device Controller connected to the RC 8000. The
actual separation of functions is done so as to ensure the most
efficient use of the hardware and to reduce the buffer require-
ments as much as possible.
1.3.3.2 F_o_r_e_i_g_n_ _C_o_m_p_u_t_e_r_ _N_e_t_w_o_r_k_ _I_n_t_e_r_f_a_c_e_. When a foreign computer is
connected to RC NET, all Network Interface functions will typi-
cally reside in the node computer. This is in turn connected to
the foreign computer by a standard interface, normally some sort
of communication line (PAD>s).
This approach eliminates the need for modifications of the for-
eign computer. Alternatively, channel connections (e.g. to IBM,
CDC) are used if a high performance is required.
1.3.4 E_x_t_e_r_n_a_l_ _a_n_d_ _I_n_t_e_r_n_a_l_ _H_o_s_t_s_
RC NET distinquishes between two kinds of addressable units in
the packet switch, external and internal hosts.
1.3.4.1 E_x_t_e_r_n_a_l_ _H_o_s_t_ is used to designate a user of the network trans-
portation service. The host is assigned a HOST-ID, which bears no
relation to the physicl connection between the network and the
host. \f
1.3.4.2 I_n_t_e_r_n_a_l_ _H_o_s_t_ is used to designate certain modules executing net-
work-related functions. The internal hosts are associated with
the nodes, which means that it is possible to address a certain
function at a certain node.
The HOST-ID of an internal host is made up of the NODE-ID of the
corresponding node and the function which the internal host per-
forms.
The HOST-ID of an internal host may, however, be used to address
the host through the network in exactly the same way, and utili-
zing the same mechanisms, as when communicating with an external
host.
1.4 Summary
By means of the layers of protocols defined, RC NET offers the
transportation service level needed by the application system in
question.
Protocols are defined in terms of their functions rather than in
terms of the hardware on which they are executed. This allows the
functions to be implemented at the network location and on the
hardware best suited.
At the lowest levels RC NET takes advantage of packet switching
technology. On communication lines RC NET utilizes the HDLC-pro-
tocol.
For an application, utilizing the high-level protocols, RC NET
provides a safe transportation service which accepts any infor-
mation together with an identification of the receiver. RC NET
ensures that either the information reaches its destination or
that the sender will be informed if the receiver is no longer
connected to the network.
Where appropriate RC NET uses network protocols which have been
standardized internationally, e.g. CCITT X.25, IFIP Transport
Station, ISO HDLC.
Figure 1.6 summarizes the levels of protocols, that may be re-
cognized in RC NET.
\f
T_
&_ Figure 1.6 RC NET Protocol Levels
\f
F_ 2 RC NET Components
This chapter defines a number of components that may be tied to-
gether in various ways to make up an instance of RC NET.
It will be seen, that there is no fixed relationship between a
function to be performed and the hardware and/or software actual-
ly doing the work.
We wish to point out, that new components may be added as the
need arises.
Three major groups of components can be distinguished:
- Hardware components
- Software components
- Functional components.
2.1 Hardware Components
RC NET encompasses a wide range of hardware. This section, how-
ever, describes only the computers involved.
2.1.1 R_C_ _8_0_0_0_
A medium-scale computer suitable for general purpose data pro-
cessing.
It has software for administrtive purposes such as payroll, pro-
duction and stock control. These systems utilize a general data
base management system.
It has compilers for the high level languages ALGOL and FORTRAN.
User jobs are executed under the time-sharing operating system
BOSS 2.
Access to RC NET is realized either via the Link Driver or via
the FDLC channel link (X.25 Virtual Call Access).
2.1.2 R_C_ _3_6_0_0_
A minicomputer, which includes a multiprogramming system. A large
range of peripheral equipment is available as well as communica-
tion equipment. Software is available for emulating most existing
RJE terminals. \f
RC NET realized on the RC 3600 system is denoted RC NET Level 1.
2.1.3 R_C_ _3_5_0_2_
The RC3502 is a communication processor including software for
multiprogramming. It is particularly suited to handle a large
number of fast communication lines. In RC NET it is used as a
node, especially when an RC 8000 is connected to a network with a
high demand on throughput capacity.
The RC 3502 is a multiprocessor system where each CPU performs
specific tasks. RC NET items on the RC 3502 processor are denoted
RC NET Level 2.
2.2 Software Components
RC NET includes a number of individual software modules, each
maintaining specific tasks within RC NET.
The modules fall into one of the following groups:
1. RC NET packet switch
2. RC NET line and channel protocols
3. Network control facilities
4. Network access facilities.
2.2.1 R_C_ _N_E_T_ _P_a_c_k_e_t_ _S_w_i_t_c_h_
The packet switch functions are realized through the RC NET ROU-
TER module which is available on the RC 3600 (RC NET Level 1) and
RC 3502 (RC NET Level 2) systems.
The ROUTER implements the routing and switching functions needed
in RC NET and adds furthermore the facility of the internetwork
virtual channel facility (pipelines). The ROUTER contains automa-
tic updating functions, which dynamically adapt the routing and
host tables if new communication lines, nodes or external hosts
are added.
2.2.2 R_C_ _N_E_T_ _L_i_n_e_ _a_n_d_ _C_h_a_n_n_e_l_ _P_r_o_t_o_c_o_l_s_
On the link level the ROUTER may access the following types of
links:
a) HDLC link, realized through a micro-programmed HDLC controller
running the X.25 LAP B protocol (equivalent to the ISO HDLC
class BA options 2, 8, 11 and 12). \f
b) RCLC link, a modified HDLC protocol adapted to existing BSC
(byte synchronous) hardware.
c) FDLC link, a full duplex, symmetrical byte channel protocol
between any two RC systems (RC 8000/3600/3502).
Both communication links accomodate transmission speeds up to 48
Kbps whereas the FDLC link operates at a speed up to 500 Kbytes/
sec.
2.2.3 N_e_t_w_o_r_k_ _C_o_n_t_r_o_l_ _F_a_c_i_l_i_t_i_e_s_
The operation of a larger network system requires extended net-
work control and monitoring primitives. These primitives are lo-
cated in each network component and their activities are coordi-
nated from a Network Operational Center (NOC).
The NOC is not required for the basic functioning of RC NET, but
offers additional supervisory facilities for the network manage-
ment.
The network control functions within RC NET covers the following
types:
a) Control of RC NET hardware elements such as nodes and communi-
cation lines.
b) State/statistics gathering from each individual software com-
ponent. The information retrieved contain accumulated traffic
volumes, error rates, load figures, network user connections
and hardware component states.
c) Report generating within RC NET, caused by specific events,
such as hardware malfunctions, change in network topology,
change in user connections or increase of error rates.
d) RC NET Remote Load. The RC 3600/3502 systems can be operated
without any local program load medium. Instead the network
lines can be used for downline load, autoload as well as
module load, executed by the NOC.
2.2.4 N_e_t_w_o_r_k_ _A_c_c_e_s_s_ _F_a_c_i_l_i_t_i_e_s_
The access to RC NET can be provided through a number of techni-
ques, some of them may be characterized as standard access me-
thods whereas others are dedicated to specific host/terminal adap-\f
tions. The standard access facilities include:
- RC 8000 access via the Network Control Program (NCP).
- X.25 DCE access via HDLC lines.
- Synchronous access via PAD (Packet Assembly/Disassembly) faci-
lities for BSC communication such as IBM 3271, IBM 360/25 WS,
IBM 3780/2780 or compatible units.
- Asynchronous access via PAD>s according to the guidelines in
CCITT recommendation X.28, allowing start-stop type of termi-
nals (TTY) to access the network.
The access is expandable beyond the above mentioned standard me-
thods and may accomodate channel and communication links to other
mainframes such as IBM, UNIVAC and CDC. Likewise the terminal at-
tachment may include local peripherals on the node as well as fo-
reign terminal systems connected via communication lines.
2.3 Functional Components
The above mentioned hardware and software items may be combined
to establish a number of functional components.
As examples the following components are illustrated:
- RC 3600 Network Node
- RC 8000 Access to RC NET
- X.25 Access Node
- Synchronous Access Node (PAD)
- Network Operational Center (NOC).
2.3.1 R_C_ _3_6_0_0_ _N_e_t_w_o_r_k_ _N_o_d_e_
A node is the functional component that accepts packets from
other nodes or from hosts. The destination stated in the packets
directs them towards the receiver. If the receiver is in direct
connection with the node, the packet is delivered. Otherwise, a
routing algorithm is used to determine the next node to receive
the packet.
The node may support any mix of the links described in 2.2.2
Furthermore the node contains network control functions (NC uti-\f
lities) which communicate with the NOC.
T_
&_ Figure 2.3.1 An RC NET Node
2.3.2 R_C_ _8_0_0_0_ _A_c_c_e_s_s_ _t_o_ _R_C_ _N_E_T_
RC 8000 may utilize RC NET in basically two ways:
- With an X.25 Virtual Channel access.
- With the Device Control Protocol used for remote device access
(NCP).
The X.25 access offers a symmetrical and international standar-
dized interface between the RC 8000 and RC NET, whereas the asym-
metrial Device Control Protocol is specially adopted to RC 8000
in a way that remote devices may be accessed as if they were lo-
cal RC 8000 devices.
2.3.2.1 X_._2_5_ _V_i_r_t_u_a_l_ _C_h_a_n_n_e_l_ _A_c_c_e_s_s_. The physical connection is according
to the CCITT recommendation an HDLC link (X.25 LAP B) but in the
interconnection between RC equipment the X.25 level 2 protocol
can be substituted by the FDLC channel protocol.
An example of using FDLC and X.25 logical access between RC 8000
and RC NET is shown in fig. 2.3.2.
\f
Figure 2.3.2 X.25 Virtual Channel Access to RC NET.
2.3.2.2 R_C_ _8_0_0_0_ _D_e_v_i_c_e_ _C_o_n_t_r_o_l_ _P_r_o_t_o_c_o_l_. This network protocol enables
userprograms in the RC 8000 to access devices located on a net-
work node, denoted remote device controller. The device control
protocol is an asymmetrical protocol which is realized by the
Network Control Program (NCP) in the RC 3600 and the Link Drivers
(LD) in the RC 8000.
Figure 2.3.3 Network Access via NCP \f
2.3.3 R_C_ _N_E_T_ _N_o_d_e_ _w_i_t_h_ _X_._2_5_ _A_c_c_e_s_s_
The layout shown on fig. 2.3.1 can be extended to cover X.25
access which is illustrated in fig. 2.3.4.
Figure 2.3.4 RC NET Node with X.25 Access.
2.3.4 R_C_ _N_E_T_ _N_o_d_e_ _w_i_t_h_ _S_y_n_c_h_r_o_n_o_u_s_ _P_A_D_>_s_
The attachment of synchronous terminal equipment requires that
the node is equipped with special program modules which adapts
the terminal type in question to RC NET.
Because of compatibility to the previously mentioned X.25 access
possibilities, the PAD>s should convert the terminal formats into
X.25 formats and vise versa.
This is illustrated on fig. 2.3.5.
\f
T_
&_ Fig. 2.3.5 RC 3600 Network Node with Synchronous PAD
2.3.5 N_e_t_w_o_r_k_ _O_p_e_r_a_t_i_o_n_a_l_ _C_e_n_t_e_r_
The NOC function as the center for all network control activities
within the network. The presence of the NOC is not required for
the basic functioning of the network.
Typical tasks of a NOC include:
- Remote Control of network items.
- Statistics and reports gathering.
- Processing of reports and statistics.
- Network operator interface.
- Collecting/processing of accounting information.
- Remote load of network processors.
As the NOC is addressed as a network user, the NOC processes can
be located either in an RC 3600 or an RC 8000 system. Fig. 2.3.6
illustrates a NOC system located in RC 8000.
\f
T_
&_ Figure 2.3.6 NOC in an RC 8000.
The NOC Host within the RC 3600 functions as the interface
between RC NET NC utilities and the RC 8000 NOC processes.
\f
F_ 3 RC NET Packet Switch
The Packet Switch provides the switching and routing functions of
RC NET.
Information is accepted in the form of p_a_c_k_e_t_s_ consisting of a
p_a_c_k_e_t_ _h_e_a_d_e_r_ and an optional p_a_c_k_e_t_ _t_e_x_t_.
The identification of the receiving host of the packet is, in ad-
dition to other information, stated in the packet header.
From the sending to the receiving host, the packet may pass
through a number of intermediate nodes. Each node uses the iden-
tification of the receiver to determine the next node to receive
the packet. The algorithm which selects the next node is normally
called the r_o_u_t_i_n_g_ _a_l_g_o_r_i_t_h_m_.
3.1 Network Topology
The following describes the topology of the network as determined
by the Packet Switch.
3.1.1 N_o_d_e_s_ _a_n_d_ _C_o_m_m_u_n_i_c_a_t_i_o_n_ _L_i_n_e_s_
A number of n_o_d_e_s_ are connected by a number of c_o_m_m_u_n_i_c_a_t_i_o_n_
l_i_n_e_s_. There is no requirement that nodes should be connected
directly. A path from one node to another may very well pass
through a number of other nodes.
Figure 3.1 overleaf illustrates that the nodes N1, N2, and N3 may
all communicate directly. Traffic from N1 or N2 to N4 must, how-
ever, pass N3, and traffic from N1 or N2 to N5 must pass both N3
and N4.
\f
T_
N1, ..., N5: Network nodes
L1, ..., L5: Communication lines
&_ Figure 3.1 Example of a network structure.
3.1.2 A_l_t_e_r_n_a_t_e_ _P_a_t_h_s_
Depending on the communication lines, nodes may be connected by
more than one path. This may be accomplished either by the pre-
sence of more than one communication line between two nodes or by
paths going through different intermediate nodes.
T_
N1, N2, N3: Network nodes
L1, ..., L4: Communication lines
&_ Figure 3.2 Network with alternate paths. \f
Figure 3.2 illustrates, that traffic from node N2 to N3 may use
either the direct communication lines L3 or L4 or the path
through node N1 using the communication lines L1 and L2.
When more than one path exist between nodes, these paths are de-
signated a_l_t_e_r_n_a_t_e_ _p_a_t_h_s_.
3.1.3 R_e_g_i_o_n_s_
Nodes are grouped into r_e_g_i_o_n_s_. The region structure is defined
individually for each network.
The purpose of the regions is to divide the network logically in-
to a number of clusters in such a way that, within each region,
there is a frequent exchange of information, but between regions
only a limited exchange of information takes place.
T_
R1, R2, R3: Regions
N1, ..., N9: Network nodes
L1, ..., L10: Communication lines
&_ Figure 3.3 Example of region structure. \f
Figure 3.3 illustrates that nodes N1, N2 and N3 constitute region
R1, nodes N4 and N5 constitute region R2 and nodes N6, N7 , N8
and N9 constitute region R3. It also illustrates that regions may
be connected by zero, one, or more communication lines. Traffic
between regions R1 and R2 has to pass one or more nodes in region
R3.
The region concept reduces the amount of information needed in
each node to describe the current topology of the network. Nodes
will maintain detailed information on how to reach other nodes
within the s_a_m_e_ _r_e_g_i_o_n_. They will, however, only maintain infor-
mation on how to reach a_n_o_t_h_e_r_ _r_e_g_i_o_n_, but not on how to reach a
specific node within that region.
The (logical) region topology can not be arbitrarily imposed on
the (physical) node topology. From one node it should, in fact,
be possible to reach all other nodes in the same region without
having to pass nodes in another region.
3.1.4 R_e_g_i_o_n_ _I_d_e_n_t_i_f_i_c_a_t_i_o_n_
Each region is assigned an identification, REGION-ID, which can
take a value from 1 to 225.
3.1.5 N_o_d_e_ _I_d_e_n_t_i_f_i_c_a_t_i_o_n_
Each node within a region is assigned an identification, NODE-ID,
which can take a value from 1 to 225. The complete identification
of a node within the network consists of its REGION-ID followed
by its NODE-ID within that region.
3.2 Hosts
The addressable unit of the Packet Switch is called a h_o_s_t_. A
host may deliver packets destined for other hosts to the Packet
Switch and it may receive packets from other hosts.
3.2.1 H_o_s_t_ _I_d_e_n_t_i_f_i_c_a_t_i_o_n_
Each host is assigned its own unique identification, HOST-ID,
within the network. When a host connects to the Packet Switch it
states its own HOST-ID.
It should be noted that HOST-ID does not in any way relate a host
to a certain node in the network. In fact, a host may connect to
any node in the network and even to more than one node at a time,
and still use the same HOST-ID on all connections. \f
T_
N1, N2: Network nodes
&_ Figure 3.4 Host with double connection to the network.
Figure 3.4 illustrates a host, which is connected to the network
through nodes N1 and N2. The same HOST-ID is used towards both
nodes.
In order to be prepared for connection of networks, possibly of
different types, the HOST-ID is extended with an identification
of the network to which the host belongs. This identification is
denoted NET-ID.
3.2.2 H_o_s_t_ _A_t_t_r_i_b_u_t_e_s_
The identification of a host may be extended with some attri-
butes. They do not influence the uniqueness of a HOST-ID as the
identification of a host within the network, but merely serve to
locate the host in the network.
3.2.2.1 H_O_M_E_-_R_E_G_I_O_N_ of a host is the identification of a region, which
will know the current location of the host if it is connected to
the network, even when connected to a different region.
3.2.2.2 C_U_R_R_E_N_T_-_R_E_G_I_O_N_ of a host is defined only when the host is con-
nected to the network. It then holds the REGION-ID of one of the
regions to which it is connected.
3.2.2.3 C_U_R_R_E_N_T_-_N_O_D_E_ of a host, like CURRENT-REGION, is defined only when
the host is connected to the network. It then holds the NODE-ID
of one of the nodes (within CURRENT-REGION) to which it is
connected.
\f
T_
H1: Host
R1, R2: Regions
N1: Network node
Figure 3.5 The concepts HOME-REGION, CURRENT-REGION and
&_ CURRENT-NODE
Figure 3.5 illustrates a host, H1, which has region R2 as HOME-
REGION, but which is currently connected to region R1, node N1.
Thus in region R2, information will be maintained, stating that
CURRENT-REGION and CURRENT-NODE for H1 is R1 and N1.
3.3 Packet Format
The following describes in short the format of a packet.
A packet consists of two parts: a p_a_c_k_e_t_ _h_e_a_d_e_r_ and a p_a_c_k_e_t_
t_e_x_t_.
3.3.1 F_o_r_m_a_t_ _o_f_ _P_a_c_k_e_t_ _H_e_a_d_e_r_
Figure 3.6 overleaf shows the format of the packet header as it
will appear in a computer with 16 bits per word.
\f
T_
&_ Figure 3.6 Format of packet header.
3.3.2 C_o_n_t_e_n_t_ _o_f_ _t_h_e_ _P_a_c_k_e_t_ _H_e_a_d_e_r_
The following is a short description of the fields in the packet
header.
3.3.2.1 F_O_R_M_A_T_. May be used to distinguish between packets of different
formats if, for example, other networks> packet formats are to be
allowed within RC NET.
3.3.2.2 P_A_C_K_E_T_ _T_E_X_T_ _L_E_N_G_T_H_. The length of the packet text part, counted
in characters of 8 bits each. Though the size of this field al-
lows a packet text size of up to 4095 characters, a smaller maxi-
mum size may be imposed on the network.
\f
3.3.2.3 P_A_C_K_E_T_ _H_E_A_D_E_R_ _L_E_N_G_T_H_: The length of the packet header in charac-
ters of 8 bits each.
3.3.2.4 U_S_E_R_ _H_E_A_D_E_R_ _L_E_N_G_T_H_: The number of 8-bit characters from the be-
ginning of the packet text that should be retained if the packet
is returned to the sending host.
3.3.2.5 S_T_A_T_E_. Determines whether the packet is on its way towards the
receiving host, or whether the Packet Switch is returning it to
the sender.
3.3.2.6 P_R_I_O_R_I_T_Y_. Packets may be transmitted through the network with 4
different priorities. Each node will transmit packets to the next
node in order of priority.
3.3.2.7 R_E_C_E_I_V_E_R_ _C_U_R_R_E_N_T_-_R_E_G_I_O_N_. The CURRENT-REGION of the receiving
host.
3.3.2.8 R_E_C_E_I_V_E_R_ _C_U_R_R_E_N_T_-_N_O_D_E_. The CURRENT-NODE of the receiving host.
3.3.2.9 S_E_N_D_E_R_ _C_U_R_R_E_N_T_-_R_E_G_I_O_N_. The CURRENT-REGION of the sending host,
e.g. the region in which the packet entered the network.
3.3.2.10 S_E_N_D_E_R_ _C_U_R_R_E_N_T_-_N_O_D_E_. The CURRENT-NODE of the sending host, e.g.
the node in which the packet entered the network.
3.3.2.11 R_E_C_E_I_V_E_R_ _N_E_T_-_I_D_. The NET-ID of the receiving host.
3.3.2.12 S_E_N_D_E_R_ _N_E_T_-_I_D_. The NET-ID of the sending host, e.g the network,
where the packet was entered.
3.3.2.13 R_E_C_E_I_V_E_R_ _H_O_M_E_-_R_E_G_I_O_N_. The HOME-REGION of the receiving host.
3.3.2.14 S_E_N_D_E_R_ _H_O_M_E_-_R_E_G_I_O_N_. The HOME-REGION of the sending host.
3.3.2.15 R_E_C_E_I_V_E_R_ _H_O_S_T_-_I_D_. The HOST-ID of the receiving host.
3.3.2.16 S_E_N_D_E_R_ _H_O_S_T_-_I_D_. The HOST-ID of the sending host.
3.3.2.17 F_A_C_I_L_I_T_Y_ _M_A_S_K_. A mask which is used to signal that certain test
and tracing procedures should be applied to the packet in the
nodes passed.
3.3.2.18 I_D_E_N_T_I_F_I_C_A_T_I_O_N_. A field that is unchanged by the Packet Switch
and used exclusively by the host. \f
3.3.3 T_h_e_ _P_a_c_k_e_t_ _T_e_x_t_
The optional packet text occupies as many 8-bit characters as
stated in the field PACKET TEXT LENGTH. It is left completely
unchanged by the Packet Switch except for certain test and tra-
cing packets.
However, if a packet can not reach the host stated as its recei-
ver, the Packet Switch will attempt to return it to the transmit-
ting host. In this case the field USER HEADER LENGTH is inspected
to determine how many 8-bit characters, from the beginning of the
packet text, that should be retained. The rest of the packet text
is discarded.
T_ Figure 3.7 illustrtes the concept of the user header.
&_ Figure 3.7 The user header in a packet. \f
F_ 4 RC NET Packet Transporter
The purpose of the Packet Transporter protocol is to control that
packets entered into the Packet Switch actually reach their de-
stination. A time-out situation will be detected, if the receiver
has not acknowledged the packet within a certain time.
4.1 Position in the Network Protocols
The Packet Transporter protocol is a host protocol, meaning that
it is not part of the Packet Switch. RC NET offers standard soft-
ware for implementing this protocol. It is executed in an RC 3502
or an RC 3600 also when these act as front-end computers for RC
8000.
Figure 4.1 Position of the Packet Transporter in the network.
4.2 Method of Control
The end-to-end check is implemented by a double, independent,
numbering scheme, similar to the one defined in HDLC.
The packets are independently numbered in each direction. Each
packet normally includes two counters, TRANSMIT SEQUENCE COUNT
and RECEIVE SEQUENCE COUNT. \f
TRANSMIT SEQUENCE COUNT is the number of this packet in the di-
rection from sender to receiver.
RECEIVE SEQUENCE COUNT signals from sender to receiver that all
packets up to, but not including, this number have been received
in the reverse direction and are thus acknowledged.
As the HDLC-protocol, both counters are included in normal data
packets.
This means that only if the traffic is currently unidirectional
must the receiving host generate dummy packets, containing the
RECEIVE SEQUENCE COUNT. As these packets do not otherwise carry
any information they are not themselves numbered (no TRANSMIT
SEQUENCE COUNT).
The counters take the values, 0, 1, ..., 255, 0, 1, ... This in-
terval, which is significantly greater than the one used in HDLC
(0, 1, ..., 7, 0, 1, ...), has been chosen because of the greater
delay that may be expected to occur between transmission of a
packet and acknowledgement. The interval determines the number of
outstanding packets (here 225).
4.3 Pipelines
The sequence-count method described above is best suited for
traffic, where the items arrive at the receiver in the same order
as they were transmitted.
This can not normally be expected in a network where priority me-
chanisms and dynamic routing algorithms may change the order of
the packets. The very idea of assigning priority is to be able to
change the order of the packets even after they have been delive-
red to the Packet Switch.
In RC NET this has led to the concept of p_i_p_e_l_i_n_e_s_. A pipeline is
a logical link from one host to another through the Packet
Switch. A number of pipelines may be established between two
hosts.
\f
T_
U1, U2, U3: User processes
P1, P2: Pipelines
&_ Figure 4.2 The pipeline concept
Pipelines are dynamically created and removed as the need arises.
On each pipeline an independent set of TRANSMIT SEQUENCE COUNT
and RECEIVE SEQUENCE COUNT is maintained and added to the pac-
kets. This means that the traffic on each pipeline may flow with
its own speed, independent of the other pipelines, without in-
troducing the sequencing problem described above.
One way of allocating the pipelines will be to use one pipeline
for each priority level, as packets with the same priority level
are handled in the nodes in order of arrival.
Once again it should be noted that the Packet Transporter is a
host protocol. This means that the pipeline concept only exists
within hosts, not within the Packet Switch. The pipelines have no
relation to the physical network topology or to the routing me-
thods applied to the packets. Packets transmitted on the same
pipeline may very well find different ways through the network,
and may even be entered into the destination host from different
nodes. \f
F_ 5 RC NET Message Transporter
The Message Transporter protocol controls the division of mes-
sages into packets. These packets are then handed over to the
Packet Transporter for transmission through the network. The Mes-
sage Transporter does not have to control the transmission of the
individual packets as this is done by the Packet Transporter. If,
for some reason, the packets can not reach their destination -
due to line failure, for example - the Packet Transporter noti-
fies the Message Transporter.
At the receiver, the Message Transporter will receive the indivi-
dual packets and assemble them to form the original message.
The Message Transporter constitutes the network end-to-end proto-
col between two network users. The RC 8000 Device Control Proto-
col and the RC 8000 IFIP Transport Station are examples of two
different Message Transporters.
5.1 Position in the Network Protocols
The Message Transporter is a host protocol. As with the Packet
Transporter, RC NET offers standard software for the implemen-
tation of this protocol on RC 3502/RC 3600, also when these act
as front-end computers for RC 8000.
Figure 5.1 Position of the Message Transporter in the network. \f
As can be seen from Figure 5.1, the work of the Message Transpor-
ter is actually shared between RC 3502/RC 3600 and the RC 8000.
This is for reasons of efficiency and reduced buffer require-
ments. This implementation is one of the outcomes of the separa-
tion between logical protocol levels and the physical implementa-
tions.
The Message Transporter forms the outermost level of the trans-
portation network. Utilizing this protocol, messages of nearly
infinite length may be transmitted through the network to a spe-
cified host. The sender will be assured that the message reaches
the receiver, or else he will be notified that the receiver is
not accessible.
5.2 Method of Control
Messages are sequentially numbered. Each packet includes three
fields, MESSAGE NUMBER, PACKETS IN MESSAGE, PACKET NUMBER IN
MESSAGE.
MESSAGE NUMBER is the sequential number assigned to the message
from which this packet derives.
PACKETS IN MESSAGE is the number of packets into which this mes-
sage has been divided. Each packet except the last has a fixed
length.
PACKET NUMBER IN MESSAGE is the number of this packet within the
message.
The field PACKETS IN MESSAGE is included instead of a LAST PACKET
flag, because it allows the receiver to determine the buffer
space needed for this message as soon as at least one packet has
been received.
Another concrete example of a Message Protocol is described in
IFIP Paper INWG 96.1, Proposal for an internetwork End-to-End
Transport Protocol, denoted as the IFIP Transport Station.
\f
T_ 5.3 Relations to Pipelines
All packets of a message are transmitted on the same pipeline.
This is because the MESSAGE NUMBER is not intended to ensure cor-
rect sequencing of messages, but only to identify the message to
&_ which a packet belongs.
Thus a MESSAGE NUMBER is maintained for each pipeline active, and
no confusion can arise if packets having equal values of MESSAGE
NUMBER are received on different pipelines.
\f
F_ 6 RC NET Device Control Protocol
The RC NET Device Control Procotol is used when a number of devi-
ces residing at one host are accessed and controlled by other
hosts in the network.
The protocol is a "user protocol" in the sense that it is inten-
ded to function parallel with other - maybe user defined - Mes-
sage Protocols utilizing the transportation service of the Mes-
sage Transporter.
6.1 Links
A fundamental concept in this protocol is the l_i_n_k_. It is a lo-
gical path through RC NET, tieing together a device at one host
and a process at another host.
Links are created and removed upon request.
Links are, among other things, used to ensure indivisible access
to a device for a certain period. Requests for link creation,
arriving at a device which is already occupied by another link,
may be queued for a time specified in the request.
N_o_t_e_:_ Links have no relation to pipelines. Packets from different
links (or from other protocols) may share the same pipeline.
6.2 Device Specification
The device to which a link is created, is specified in terms of
some characteristics which should be satisfied. These specifica-
tions are interpreted by the host on which the devices reside.
The characteristics are:
- Device type (e.g. printer, card reader, etc.)
- Device name
- Buffer resources needed (among which is the maximum
acceptable buffer size).
\f
T_ 6.3 Master-Slave Relation
The Device Control Protocol is a strict master-slave protocol in
the sense that initiative for input or output operations origi-
&_ nates in the program.
The device itself will not take any action apart from reporting
that some specific events have occurred.
\f
F_ 7 RC NET Vocabulary
This is an alphabetic list of definitions of terms assigned a
specific meaning within RC NET.
Within each definition, the first occurrence of a term defined
elsewhere in the vocabulary is u_n_d_e_r_l_i_n_e_d_.
COMMUNICATION LINE
A physical connection between computers on which information may
be exchanged. The Designation L_i_n_k_ is also used, but should not
be confused with the Logical Links used by the Device Control
Protocol.
CURRENT-NODE
An attribute associated with each h_o_s_t_ while connected to the
network. It is the N_O_D_E_-_I_D_ of a n_o_d_e_ to which the host is connec-
ted.
CURRENT-REGION
An attribute associated with each h_o_s_t_ while connected to the
network. It is the R_E_G_I_O_N_-_I_D_ of a n_o_d_e_ to which the hoss is con-
nected.
DEVICE CONTROL PROTOCOL
A M_e_s_s_a_g_e_ _P_r_o_t_o_c_o_l_ within RC NET. It is used, when one h_o_s_t_ con-
trols devices of another host.
DEVICE HOST
A concept within the D_e_v_i_c_e_ _C_o_n_t_r_o_l_ _P_r_o_t_o_c_o_l_. It is a designation
for the h_o_s_t_ at which the devices reside. Cf. J_o_b_h_o_s_t_.
EXTERNAL HOST
A h_o_s_t_, whose H_O_S_T_-_I_D_ is not related to a specific n_o_d_e_.
HOME REGION
An attribute associated with each h_o_s_t_. It is the R_E_G_I_O_N_-_I_D_ of a
r_e_g_i_o_n_ in which information about the current location of the
host in the network is maintained.
HOST
The addressable unit of the P_a_c_k_e_t_ _S_w_i_t_c_h_. Each host is identi-
fied by N_E_T_-_I_D_ and H_O_S_T_-_I_D_. \f
HOST-ID
Within a network a unique identification of a certain h_o_s_t_.
INTERNAL HOST
A h_o_s_t_ that is related to a specific n_o_d_e_. The corresponding
N_O_D_E_-_I_D_ may be derived from the host>s H_O_S_T_-_I_D_._
JOBHOST
A concept within the D_e_v_i_c_e_ _C_o_n_t_r_o_l_ _P_r_o_t_o_c_o_l_. It is a designation
for the h_o_s_t_ at which programs are executed, accessing devices at
the D_e_v_i_c_e_ _h_o_s_t_.
LINK
A concept within the D_e_v_i_c_e_ _C_o_n_t_r_o_l_ _P_r_o_t_o_c_o_l_. It is a logical
connection between a process executed at a J_o_b_h_o_s_t_ and a device
at a D_e_v_i_c_e_ _h_o_s_t_. The links serve reservation, sequencing and
resource control purposes.
MESSAGE
The name for the information accepted by the M_e_s_s_a_g_e_ _T_r_a_n_s_p_o_r_t_e_r_.
MESSAGE CONTROL INFORMATION
The information added by p_r_o_t_o_c_o_l_s_ to the original m_e_s_s_a_g_e_ sup-
plied by the user.
MESSAGE PROTOCOL
A p_r_o_t_o_c_o_l_ utilizing the service offered by the M_e_s_s_a_g_e_ _T_r_a_n_s_p_o_r_-
t_e_r_. The D_e_v_i_c_e_ _C_o_n_t_r_o_l_ _P_r_o_t_o_c_o_l_ is a Message Protocol.
MESSAGE TRANSPORTER
A p_r_o_t_o_c_o_l_ level within RC NET. It forms the basis for implemen-
tation of M_e_s_s_a_g_e_ _P_r_o_t_o_c_o_l_s_. It accepts information of (nearly)
any length and of any content, and controls its transmission
through the network to the specified h_o_s_t_.
NET-ID
An identification associated with a network. NET-ID together with
H_O_S_T_-_I_D_ forms the unique identification of a h_o_s_t_ when networks
are tied together.
NODE
A functional unit within the P_a_c_k_e_t_ _S_w_i_t_c_h_, taking part in the
r_o_u_t_i_n_g_ of p_a_c_k_e_t_s_.
\f
NODE-ID
The identification of a n_o_d_e_ within a r_e_g_i_o_n_. The total identifi-
cation of a node within the network consists of R_E_G_I_O_N_-_I_D_ to-
gether with NODE-ID.
PACKET
The basic unit of information exchanged with and within the P_a_c_-
k_e_t_ _S_w_i_t_c_h_.
PACKET SWITCH
A p_r_o_t_o_c_o_l_ within RC NET. It accepts p_a_c_k_e_t_s_ from h_o_s_t_s_ and
r_o_u_t_e_s_ them towards the host specified as receiver.
PACKET TRANSPORTER
A p_r_o_t_o_t_o_l_ within RC NET. The protocol is implemented in h_o_s_t_s_.
It controls the transmission of p_a_c_k_e_t_s_ through the P_a_c_k_e_t_ _S_w_i_t_c_h_
and includes mechanisms to detect the loss of a packet.
PIPELINE
A concept within the P_a_c_k_e_t_ _T_r_a_n_s_p_o_r_t_e_r_. A pipeline is a logical
pipe from one h_o_s_t_ to another through the P_a_c_k_e_t_ _S_w_i_t_c_h_. The
pipelines are part of the end-to-end check implemented by the
Packet Transporter.
PROTOCOL
A set of rules, formats and procedures agreed upon by the parti-
cipants in an exchange of information.
REGION
The n_o_d_e_s_ within a network may be grouped into a number of re-
gions. Each region is assigned a R_E_G_I_O_N_-_I_D_.
REGION-ID
The identification of a r_e_g_i_o_n_ within a network.
ROUTING
The procedure applied to p_a_c_k_e_t_s_ when passing a n_o_d_e_. The proce-
dure determines the next node to receive the packet.
TRANSPORT STATION
A common name of the network access process (ISO Level 4) which
offers a network independent service to the user. Is often used
for the IFIP defined End-to-End protocol.
\f
References
1. CCITT Recommendation X.25 (Orange Book)
2. Herbert L. Jessen, A/S Regnecentralen
Introduction to RC NET Level 1.
3. Ole Kragh Hansen/Herbert L. Jessen/Erik L. Petersen,
A/S Regnecentralen
RC NET Level 1 - Systems Description
4. ISO Document TC97 N6256
HDLC Class BA.
5. ISO Document
ISO/TC97/SC16 N117
Reference Model of Open Systems Architecture
6. ISO Document
ISO/TC97/SC16 N24 and SC6 N1557
IFIP INWG 96.1
Proposal for an internetwork End-to-End Transport Protocol
7. Erik Lilholt, A/S Regnecentralen
RC NET, Device Control Protocol.
Reference Manual. \f
i
T_A_B_L_E_ _O_F_ _C_O_N_T_E_N_T_S_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _P_A_G_E_
1. INTRODUCTION ........................................... 1
2. INSTALLATION ........................................... 2
2.1 Installation with a Predefined RC702 or RC855
Configuration ..................................... 2
2.2 Installation with a Special Configuration ......... 3
A_P_P_E_N_D_I_C_E_S_:
A. REFERENCES ............................................. 5
B. CONFIG REPLY SUMMARIES ................................. 6
B.1 Config Reply Summaries for RC702 .................. 6
B.2 Config Reply Summaries for RC855 .................. 8
C. EXAMPLE OF NORMAL INSTALLATION OF CIS COBOL 4.5......... 10
\f
ii
\f
F_ 1_._ _ _ _ _ _ _ _ _I_N_T_R_O_D_U_C_T_I_O_N_ 1.
This manual describes the implementation of CIS COBOL 4.5 on the
RC702/RC855 Microcomputer System.
CIS COBOL is designed to run under the control of the CP/M
Operating System, which is assumed to have been installed on your
RC702/RC855 Microcomputer System.
The CIS COBOL package you have received consists of the following
items:
- CIS COBOL Issue Disk
- C_I_S_ _C_O_B_O_L_ _f_o_r_ _t_h_e_ _R_C_7_0_2_/_R_C_8_5_5_ _M_i_c_r_o_c_o_m_p_u_t_e_r_ _S_y_s_t_e_m_,_ _I_n_-_
s_t_a_l_l_a_t_i_o_n_ _G_u_i_d_e_
- C_I_S_ _C_O_B_O_L_ _O_p_e_r_a_t_i_n_g_ _G_u_i_d_e_
- C_I_S_ _C_O_B_O_L_ _L_a_n_g_u_a_g_e_ _R_e_f_e_r_e_n_c_e_ _M_a_n_u_a_l_
- C_I_S_ _C_O_B_O_L_ _P_o_c_k_e_t_ _G_u_i_d_e_
- Micro Focus Warranty Acknowledgement
Your copy of C_I_S_ _C_O_B_O_L_ _f_o_r_ _t_h_e_ _R_C_7_0_2_/_R_C_8_5_5_ _M_i_c_r_o_c_o_m_p_u_t_e_r_ _S_y_s_t_e_m_
has been provided with a serial number, and it is only to be used
in accordance with the Software License Agreement. You are kindly
requested to fill in and return the warranty acknowledgement to
Micro Focus Ltd.
\f
2_._ _ _ _ _ _ _ _ _I_N_S_T_A_L_L_A_T_I_O_N_ 2.
Start by making 2 copies of your CIS COBOL diskette for backup
purposes.
Transfer all CIS COBOLfiles to a system diskette.
If you want your CIS COBOL system to have a predefined RC702 or
RC855 configuration, follow the procedure outlined in section
2.1.
On the other hand, if you require a special configuration, follow
the procedure outlined in section 2.2.
For more details on how to get started with CIS COBOL, see the
C_I_S_ _C_O_B_O_L_ _O_p_e_r_a_t_i_n_g_ _G_u_i_d_e_, chapter 1.
2_._1_ _ _ _ _ _ _ _I_n_s_t_a_l_l_a_t_i_o_n_ _w_i_t_h_ _a_ _P_r_e_d_e_f_i_n_e_d_ _R_C_7_0_2_ _o_r_ _R_C_8_5_5_ _C_o_n_f_i_g_u_r_a_t_i_o_n_ 2.1
You can install the CIS COBOL systemby simply following the
example in appendix C. For a more detailed description, consult
chapter 1 of the C_I_S_ _C_O_B_O_L_ _O_p_e_r_a_t_i_n_g_ _G_u_i_d_e_, and note the
following changes:
- The file CONFIG.COM includes predefined configurations for
the RC702 and RC855.
- The file FILEMARK.COM is included and described in appendix
F of the C_I_S_ _C_O_B_O_L_ _O_p_e_r_a_t_i_n_g_ _G_u_i_d_e_.
Appendix B summarizes the characteristics of a predefined RC702
or RC855 configuration.
The implementation of the CRT cursor keys is shown in fig. 1.
This is an extension of table 3-2 in the C_I_S_ _C_O_B_O_L_ _O_p_e_r_a_t_i_n_g_
G_u_i_d_e_.
\f
The highlight facility has been configured with the inverse
video attribute for the RC702 and the display for the intensified
RC855. This attribute can be activated with the CIS COBOL
statement DISPLAY, provided you specify: U_P_O_N_ _C_R_T_-_U_N_D_E_R_.
On the RC702, this attribute will fill one position on the
screen when switched on or off.
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
_F_u_n_c_t_i_o_n_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _K_e_y_s_ _ _ _
Home
Tab forward a field
Tab backward a field
Forward Space
Backward Space
Column Tab
Left Zero 1)
_R_e_t_u_r_n_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
1) The "." for left zero fill is a ","
when DECIMAL-POINT IS COMMA
_ _ _ _i_s_ _s_p_e_c_i_f_i_e_d_ _i_n_ _t_h_e_ _u_s_e_r_ _p_r_o_g_r_a_m_ _ _ _ _ _
Figure 1: CRT cursor control keys.
2_._2_ _ _ _ _ _ _ _I_n_s_t_a_l_l_a_t_i_o_n_ _w_i_t_h_ _a_ _S_p_e_c_i_a_l_ _C_o_n_f_i_g_u_r_a_t_i_o_n_
If you require a special configuration, you should refer to
chapter 5 of the C_I_S_ _C_O_B_O_L_ _O_p_e_r_a_t_i_n_g_ _G_u_i_d_e_. A description of the
character codes for the RC702/RC855 keyboard may be found in
reference 1.
\f
F_
\f
F_ A_._ _ _ _ _ _ _ _ _R_E_F_E_R_E_N_C_E_S_ A.
1 RCSL No 42-i2131:
CP/M for the RC702 Microcomputer System
User's Guide
or
RCSL No 42-i1687:
RC855 Work Station, User's Guide
\f
F_ B_._ _ _ _ _ _ _ _ _C_O_N_F_I_G_ _R_E_P_L_Y_ _S_U_M_M_A_R_I_E_S_ B.
B_._1_ _ _ _ _ _ _ _C_O_N_F_I_G_ _R_E_P_L_Y_ _S_U_M_M_A_R_I_E_S_ _F_O_R_ _R_C_7_0_2_
CRT TYPE
S_u_m_m_a_r_i_z_e_d_ _P_r_o_m_p_t_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _R_C_7_0_2_ _ _ _
RTS TO BE TAILORED? Y
CRT TYPE Z
DIRECT OR STEP ADDRESSING D
LEADING CONTROL CHARS 06
NEXT CHARACTER VERT OR HORIZ H
CONTROL CHARACTERS BETWEEN? N
TRAILING CHARACTERS? N
INCREMENT TO BINARY ADDRESS Y
INCREMENT CHARACTERS 20, 20
NO. OF LINES ON SCREEN 25
CHARACTERS PER LINE 80
AUTOMATIC ECHO ON KEY-INS N
CARRIAGE RETURN CODE 0D
BACKSPACE ONE CHARACTER CODE 08
FORWARD ONE CHARACTER CODE 18
BACKSPACE ONE FIELD CODE 05
FORWARD ONE FIELD CODE 09
BACKSPACE TO 'HOME' CODE 01
COLUMN TAB CODE 09
ESCAPE CODE 1B
ABOVE CODES PRECEDED BY ESCAPE? N
CLEAR SCREEN CHARACTER? Y
CLEAR SCREEN CHARACTER CODE 0C
'HOMING' (TOP LEFT OF SCREEN) CHAR 1D
ALTER CTR ACCEPT/DISPLAY HOMING N
\f
CRT TYPE
S_u_m_m_a_r_i_z_e_d_ _P_r_o_m_p_t_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _R_C_7_0_2_ _ _ _
HIGHLIGHT FACILITY? Y
HIGHLIGHT BIT TO SET 00
'HIGHLIGHT ON' CHARACTER? Y
'HIGHLIGHT ON' CHARACTER CODE 1)
'HIGHLIGHT ON' SCREEN POSN? Y
'HIGHLIGHT OFF' CHARACTER? Y
'HIGHLIGHT OFF' CHARACTER CODE 80
AUDIBLE ALARM FEATURE? Y
AUDIBLE ALARM CHARACTER CODE 07
CRT DEF'N TO BE ADDED TO LIST? Y/N 2)
USE I-O PORTS DIRECTLY? N
OPTIONAL BIT INVERSION N
CHANGE KEYBOARD TOP BIT MASK N
TAB STOP MODIFICATION? Y/N 3)
ASSEMBLER CODE INCLUSION Y/N 4)
1) The "Highlight facility" is a selection of the following
attributes (see ref. 1, appendix B.11):
- Underline
- Semigraphic
- Inverse video
- Blinking
The chosen attribute will be active in the CIS COBOL statement
"DISPLAY", if you specify U_P_O_N_ _C_R_T_-_U_N_D_E_R_.
2) Disk file name requested for new CONFIG program if Y entered.
3) Tab positions requested if Y entered.
4) Size and position for assembler code requested if Y entered.
\f
F_ B_._2_ _ _ _ _ _ _ _C_O_N_F_I_G_ _R_E_P_L_Y_ _S_U_M_M_A_R_I_E_S_ B.2
CRT TYPE
S_u_m_m_a_r_i_z_e_d_ _P_r_o_m_p_t_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _R_C_8_5_5_ _ _ _
RTS TO BE TAILORED? Y
CRT TYPE Z
DIRECT OR STEP ADDRESSING D
LEADING CONTROL CHARS 06
NEXT CHARACTER VERT OR HORIZ H
CONTROL CHARACTERS BETWEEN? N
TRAILING CHARACTERS? N
INCREMENT TO BINARY ADDRESS Y
INCREMENT CHARACTERS 20, 20
NO. OF LINES ON SCREEN 25
CHARACTERS PER LINE 80
AUTOMATIC ECHO ON KEY-INS N
CARRIAGE RETURN CODE 0D
BACKSPACE ONE CHARACTER CODE 08
FORWARD ONE CHARACTER CODE 18
BACKSPACE ONE FIELD CODE 05
FORWARD ONE FIELD CODE 09
BACKSPACE TO 'HOME' CODE 01
COLUMN TAB CODE 09
ESCAPE CODE 1B
ABOVE CODES PRECEDED BY ESCAPE? N
CLEAR SCREEN CHARACTER? Y
CLEAR SCREEN CHARACTER CODE 0C
'HOMING' (TOP LEFT OF SCREEN) CHAR 1D
ALTER CTR ACCEPT/DISPLAY HOMING N
\f
CRT TYPE
S_u_m_m_a_r_i_z_e_d_ _P_r_o_m_p_t_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _R_C_8_5_5_ _ _ _
HIGHLIGHT FACILITY? Y
HIGHLIGHT BIT TO SET 00
'HIGHLIGHT ON' CHARACTER? Y
'HIGHLIGHT ON' CHARACTER CODE 1)
'HIGHLIGHT ON' SCREEN POSN? Y
'HIGHLIGHT OFF' CHARACTER? Y
'HIGHLIGHT OFF' CHARACTER CODE 80
AUDIBLE ALARM FEATURE? Y
AUDIBLE ALARM CHARACTER CODE 07
CRT DEF'N TO BE ADDED TO LIST? Y/N 2)
USE I-O PORTS DIRECTLY? N
OPTIONAL BIT INVERSION N
CHANGE KEYBOARD TOP BIT MASK N
TAB STOP MODIFICATION? Y/N 3)
ASSEMBLER CODE INCLUSION Y/N 4)
1) The "Highlight facility" is a selection of the following
attributes (see ref. 1, appendix B.11):
- Underline
- Semigraphic
- Inverse video
- Blinking
The chosen attribute will be active in the CIS COBOL statement
"DISPLAY", if you specify U_P_O_N_ _C_R_T_-_U_N_D_E_R_.
2) Disk file name requested for new CONFIG program if Y entered.
3) Tab positions requested if Y entered.
4) Size and position for assembler code requested if Y entered.
\f
C_._ _ _ _ _ _ _ _ _E_X_A_M_P_L_E_ _O_F_ _N_O_R_M_A_L_ _I_N_S_T_A_L_L_A_T_I_O_N_ _O_F_ _C_I_S_ _C_O_B_O_L_ _4_._5_: C.
The example below shows how to install CIS COBOL with a
predefined RC702 or RC855 configuration.
It is assumed that CIS COBOL has been copied and transferred to a
system diskette. Please note that the following notation is used
in the example: All keyboard entries to be made by you are
underlined. A "cr" indicates that you are to push the RETURN key.
Comments are preceded by a semicolon. The CIS COBOL prompt symbol
will be represented by the symbol ">", the CP/M prompt symbol by
"A>".
E_x_a_m_p_l_e_
A> C_O_N_F_I_G_ _c_r_
CIS COBOL RUN TIME SYSTEM (RTS) CONFIGURATOR V3.00
COPYRIGHT (C) 1979, 1982 MICRO FOCUS LTD
ENTER THE FILE NAME OF THE RTS TO BE CONFIGURED
>R_U_N_A_._C_O_M_ _c_r_ ; All entries must be made in capital letters.
VERSION 4.5 REVISION 001 USER REFERENCE NUMBER BG/0000/BL
THE RTS IS SUPPLIED WITH AN INTERACTIVE CRT PACKAGE DESIGNED TO
BE USED VIA THE "ACCEPT" AND "DISPLAY" VERBS IN CIS COBOL. THIS
PROGRAM ENABLES YOU TO TAILOR THE RTS TO YOUR CRT
DOES THIS RTS NEED TO BE TAILORED?
INPUT ONE OF THE FOLLOWING:- 'YES' 'Y' 'NO' 'N'
>Y_ _c_r_
THE FOLLOWING CRTS ARE PREDEFINED:-
A - ADM3A
B - RC702
C - RC855
PLEASE ENTER THE LETTER AGAINST YOUR CRT IF IT IS SHOWN - ELSE
TYPE Z
>C_ _c_r_ ; To configure for RC702, press B instead of C.
\f
THE RTS NORMALLY ACCESES THE CRT USING THE STANDARD CONSOLE
ROUTINES. ALTERNATIVELY IT IS CAPABLE OF DRIVING THE IO PORTS
DIRECTLY.
DO YOU WANT THE RTS TO USE THE IO PORTS DIRECTLY?
INPUT ONE OF THE FOLLOWING:- 'YES' 'Y' 'NO' 'N'
>_N_ _c_r_
THE RTS WILL OPTIONALLY INVERT ALL BITS, IS THIS REQUIRED?
INPUT ONE OF THE FOLLOWING:- 'YES' 'Y' 'NO' 'N'
>_N_ _c_r_
THE RTS WILL MASK OUT THE TOP BIT OF ALL KEYBOARD INPUT/OUTPUT
CHARACTERS.
DO YOU WISH TO CHANGE THIS?
INPUT ONE OF THE FOLLOWING: - 'YES' 'Y' 'NO' 'N'
>_N_ _c_r_
THE RTS IS SUPPLIED WITH COLUMN TAB STOPS IN COLUMNS:-
08, 16, 24, 32, 40, 48, 56, 64, 72
DO YOU WISH TO MODIFY THESE?
INPUT ONE OF THE FOLLOWING: - 'YES' 'Y' 'NO' 'N'
>_N_ _c_r_ ; You may also answer Y - if you do, consult the CIS
; COBOL OPERATING GUIDE.
THE RTS PROVIDES THE FACILITY TO INCORPORATE ASSEMBLER CODE THAT
MAY BE ENTERED BY YOU FROM THE COBOL "CALL" VERT.
DO YOU WISH TO INCLUDE SUCH CODE?
INPUT ONE OF THE FOLLOWING:- 'YES' 'Y' 'NO' 'N'
>_N_ _c_r_ ; You may also answer Y - if you do, consult the CIS
; COBOL Operating Guide.
YOUR RUN TIME SYSTEM HAS BEEN CONFIGURED
\f
\f
\f
M_I_C_R_O_P_R_O_G_R_A_M_ _P_R_O_M_ _P_O_S_I_T_I_O_N_ _L_I_S_T_
P_R_O_M_ _N_O_ P_O_S_I_T_I_O_N_ T_Y_P_E_ _ _ _ _
ROA 330 345 6353-1
331 341 -
332 337 -
333 333 -
334 329 -
335 325 -
336 321 -
337 317 -
338 313 -
339 309 -
340 305 -
341 301 -
ROA 342 346 6353-1
343 342 -
344 338 -
345 334 -
346 330 -
347 326 -
348 322 -
349 318 -
350 314 -
351 310 -
352 306 -
353 302 -
ROA 354 347 6353-1
355 343 -
356 339 -
357 335 -
358 331 -
359 327 -
360 323 -
361 319 -
362 315 -
363 311 - 3
364 307 -
365 303 -
ROA 366 105 6306-1
367 104 -
368 103 -
ROA 369 101 6353-1
370 91 -
371 81 -
ROA 372 111 6306-1
\f
R_O_A_ _3_0_7_,_ _D_E_S_T_I_N_A_T_I_O_N_ _A_D_D_R_._ _D_E_C_O_D_I_N_G_ _P_R_O_M_
O_C_T_A_L_ _A_D_D_R_ 0_1_ 0_2_ 0_3_ 0_4_ 0_5_ 0_6_ 0_7_ 0_8_
0 0 0 0 0 1 1 0 0
1 0 0 0 1 1 1 0 0
2 1 0 0 0 1 1 0 0
3 0 0 0 0 0 1 0 0
4 0 0 0 0 1 0 0 0
5 0 1 0 0 1 1 0 0
6 0 0 1 0 1 1 0 0
7 0 0 0 0 1 1 0 0
10 0 0 0 0 1 1 0 0
11 0 0 0 1 1 1 0 0
12 0 0 0 0 1 1 0 0
13 0 0 0 0 1 1 0 0
14 0 0 0 0 1 1 0 0
15 0 0 0 0 1 1 0 0
16 0 0 0 0 1 1 0 0
17 0 0 0 0 1 1 0 0
20 0 0 0 0 1 1 0 0
21 0 0 0 0 1 1 0 0
22 0 0 0 0 1 1 0 0
23 0 0 0 0 1 1 0 0
24 0 0 0 0 1 1 0 0
25 0 0 0 0 1 1 0 0
26 0 0 0 0 1 1 0 0
27 0 0 0 0 1 1 0 0
30 0 0 0 0 1 1 0 0
31 0 0 0 0 1 1 0 0
32 0 0 0 0 1 1 0 0
33 0 0 0 0 1 1 0 0
34 0 0 0 0 1 1 0 0
35 0 0 0 0 1 1 0 0
36 0 0 0 0 1 1 0 0
37 0 0 0 0 1 1 0 0
01 = ENCPSCRATCHP
02 = ENCPCPUSTATUS
03 = ENCPCONTROUT
04 = ENCPEASTAT
05 = -,LOADIC
06 = -,LOADLC
07 = UNUSED
08 = UNUSED
\f
R_O_A_ _3_0_8_,_ _R_O_A_ _3_0_9_ _a_n_d_ _R_O_A_ _3_1_0_ _C_O_N_S_T_A_N_T_ _P_R_O_M_s_
OCTAL ROA 308 CONTENTS ROA 309 CONTENTS ROA 310 CONTENTS
A_D_D_R_E_S_S_ _ _ _ _ _0_1_-_0_8_ _ _ _ _ _ _ _ _ _ _ _0_1_-_0_8_ _ _ _ _ _ _ _ _ _ _ _0_1_-_0_8_ _ _ _ _ _ _
0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 0 0 0 0 0 0 0 0 0
1 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0
2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 1 0
3 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1
4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 1 1
5 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 1 0
6 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 1
7 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1
10 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 0
11 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0
12 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 1
13 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0
14 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1
15 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0
16 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0
17 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0
20 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0
21 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0
22 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0
23 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0
24 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
25 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
26 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
27 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
30 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0
31 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
32 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
33 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
34 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1
35 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
36 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0
37 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1
\f
R_O_A_ _3_1_1_,_ _H_A_L_F_-_W_O_R_D_ _M_A_N_I_P_U_L_A_T_O_R_ _C_O_N_T_R_O_L_ _P_R_O_M_
O_C_T_A_L_ _A_D_D_R_ O_C_T_A_L_ _C_O_N_T_E_N_T_S_
0 000
1 001
2 000
3 001
4 002
5 001
6 003
7 002
10 001
11 001
12 000
13 000
14 000
15 000
16 002
17 002
20 000
21 000
22 000
23 000
24 000
25 000
26 000
27 000
30 000
31 000
32 000
33 000
34 000
35 000
36 000
37 000
\f
R_O_A_ _3_1_2_,_ _H_A_L_F_-_W_O_R_D_ _M_A_N_I_P_U_L_A_T_O_R_ _P_R_O_M_,_ _B_I_T_S_(_0_:_1_1_)_
A_0_ _=_ _0_ _ _ _ _,_ _A_D_D_R_E_S_S_E_S_ _0_-_7_7_7_
A_1_:_A_5_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _A_6_:_A_9_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
_0_ _1_ _2_ _3_ _4_ _5_ _6_ _7_ 1_0_ 1_1_ 1_2_ 1_3_ 1_4_ 1_5_ 1_6_ 1_7_
0 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
1 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
2 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
3 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
4 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
5 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
6 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
7 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
10 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
11 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
12 17 17 17 17 17 17 17 17 17 17 17 17 17 17 17 17
13 17 17 17 17 17 17 17 17 17 17 17 17 17 17 17 17
14 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
15 17 17 17 17 17 17 17 17 17 17 17 17 17 17 17 17
16 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
17 17 17 17 17 17 17 17 17 17 17 17 17 17 17 17 17
20 00 01 02 03 04 05 06 07 10 11 12 13 14 15 16 17
21 00 01 02 03 04 05 06 07 10 11 12 13 14 15 16 17
22 00 01 02 03 04 05 06 07 10 11 12 13 14 15 16 17
23 00 01 02 03 04 05 06 07 10 11 12 13 14 15 16 17
24 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
25 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
26 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
27 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
30 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
31 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
32 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
33 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
34 17 17 17 17 17 17 17 17 17 17 17 17 17 17 17 17
35 17 17 17 17 17 17 17 17 17 17 17 17 17 17 17 17
36 17 17 17 17 17 17 17 17 17 17 17 17 17 17 17 17
37 17 17 17 17 17 17 17 17 17 17 17 17 17 17 17 17
Addresses: octal
Contents: octal
\f
R_O_A_ _3_1_2_,_ _H_A_L_F_-_W_O_R_D_ _M_A_N_I_P_U_L_A_T_O_R_ _P_R_O_M_,_ _B_I_T_S_(_0_:_1_1_)_
A_0_ _=_ _1_ _ _ _ _,_ _A_D_D_R_E_S_S_E_S_ _1_0_0_0_-_1_7_7_7_
A_1_:_A_5_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _A_6_:_A_9_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
_0_ _1_ _2_ _3_ _4_ _5_ _6_ _7_ 1_0_ 1_1_ 1_2_ 1_3_ 1_4_ 1_5_ 1_6_ 1_7_
0 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
1 17 17 17 17 17 17 17 17 17 17 17 17 17 17 17 17
2 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
3 17 17 17 17 17 17 17 17 17 17 17 17 17 17 17 17
4 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
5 17 17 17 17 17 17 17 17 17 17 17 17 17 17 17 17
6 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
7 17 17 17 17 17 17 17 17 17 17 17 17 17 17 17 17
10 00 01 02 03 04 05 06 07 10 11 12 13 14 15 16 17
11 00 01 02 03 04 05 06 07 10 11 12 13 14 15 16 17
12 00 01 02 03 04 05 06 07 10 11 12 13 14 15 16 17
13 00 01 02 03 04 05 06 07 10 11 12 13 14 15 16 17
14 00 01 02 03 04 05 06 07 10 11 12 13 14 15 16 17
15 00 01 02 03 04 05 06 07 10 11 12 13 14 15 16 17
16 00 01 02 03 04 05 06 07 10 11 12 13 14 15 16 17
17 00 01 02 03 04 05 06 07 10 11 12 13 14 15 16 17
20 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
21 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
22 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
23 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
24 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
25 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
26 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
27 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
30 00 01 02 03 04 05 06 07 10 11 12 13 14 15 16 17
31 00 01 02 03 04 05 06 07 10 11 12 13 14 15 16 17
32 00 01 02 03 04 05 06 07 10 11 12 13 14 15 16 17
33 00 01 02 03 04 05 06 07 10 11 12 13 14 15 16 17
34 00 01 02 03 04 05 06 07 10 11 12 13 14 15 16 17
35 00 01 02 03 04 05 06 07 10 11 12 13 14 15 16 17
36 00 01 02 03 04 05 06 07 10 11 12 13 14 15 16 17
37 00 01 02 03 04 05 06 07 10 11 12 13 14 15 16 17
Addresses: octal
Contents: octal
\f
R_O_A_ _3_1_3_,_ _H_A_L_F_-_W_O_R_D_ _M_A_N_I_P_U_L_A_T_O_R_ _P_R_O_M_,_ _B_I_T_S_(_1_2_:_2_3_)_
A_0_ _=_ _0_ _ _ _ _,_ _A_D_D_R_E_S_S_E_S_ _0_-_7_7_7_
A_1_:_A_5_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _A_6_:_A_9_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
_0_ _1_ _2_ _3_ _4_ _5_ _6_ _7_ 1_0_ 1_1_ 1_2_ 1_3_ 1_4_ 1_5_ 1_6_ 1_7_
0 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
1 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
2 02 02 02 02 02 02 02 02 02 02 02 02 02 02 02 02
3 03 03 03 03 03 03 03 03 03 03 03 03 03 03 03 03
4 04 04 04 04 04 04 04 04 04 04 04 04 04 04 04 04
5 05 05 05 05 05 05 05 05 05 05 05 05 05 05 05 05
6 06 06 06 06 06 06 06 06 06 06 06 06 06 06 06 06
7 07 07 07 07 07 07 07 07 07 07 07 07 07 07 07 07
10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10
11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11
12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12
13 13 13 13 13 13 13 13 13 13 13 13 13 13 13 13 13
14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14
15 15 15 15 15 15 15 15 15 15 15 15 15 15 15 15 15
16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16
17 17 17 17 17 17 17 17 17 17 17 17 17 17 17 17 17
20 00 01 02 03 04 05 06 07 10 11 12 13 14 15 16 17
21 00 01 02 03 04 05 06 07 10 11 12 13 14 15 16 17
22 00 01 02 03 04 05 06 07 10 11 12 13 14 15 16 17
23 00 01 02 03 04 05 06 07 10 11 12 12 13 15 16 17
24 00 01 02 03 04 05 06 07 10 11 12 13 14 15 16 17
25 00 01 02 03 04 05 06 07 10 11 12 13 14 15 16 17
26 00 01 02 03 04 05 06 07 10 11 12 13 14 15 16 17
27 00 01 02 03 04 05 06 07 10 11 12 13 14 15 16 17
30 00 01 02 03 04 05 06 07 10 11 12 13 14 15 16 17
31 00 01 02 03 04 05 06 07 10 11 12 13 14 15 16 17
32 00 01 02 03 04 05 06 07 10 11 12 13 14 15 16 17
33 00 01 02 03 04 05 06 07 10 11 12 13 14 15 16 17
34 00 01 02 03 04 05 06 07 10 11 12 13 14 15 16 17
35 00 01 02 03 04 05 06 07 10 11 12 13 14 15 16 17
36 00 01 02 03 04 05 06 07 10 11 12 13 14 15 16 17
37 00 01 02 03 04 05 06 07 10 11 12 13 14 15 16 17
Addresses: octal
Contents: octal
\f
R_O_A_ _3_1_3_,_ _H_A_L_F_-_W_O_R_D_ _M_A_N_I_P_U_L_A_T_O_R_ _P_R_O_M_,_ _B_I_T_S_(_1_2_:_2_3_)_
A_0_ _=_ _1_ _ _ _ _,_ _A_D_D_R_E_S_S_E_S_ _1_0_0_0_-_1_7_7_7_
A_1_:_A_5_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _A_6_:_A_9_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
_0_ _1_ _2_ _3_ _4_ _5_ _6_ _7_ 1_0_ 1_1_ 1_2_ 1_3_ 1_4_ 1_5_ 1_6_ 1_7_
0 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
1 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
2 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
3 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
4 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
5 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
6 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
7 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
10 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
11 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
12 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
13 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
14 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
15 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
16 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
17 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
20 17 17 17 17 17 17 17 17 17 17 17 17 17 17 17 17
21 17 17 17 17 17 17 17 17 17 17 17 17 17 17 17 17
22 17 17 17 17 17 17 17 17 17 17 17 17 17 17 17 17
23 17 17 17 17 17 17 17 17 17 17 17 17 17 17 17 17
24 17 17 17 17 17 17 17 17 17 17 17 17 17 17 17 17
25 17 17 17 17 17 17 17 17 17 17 17 17 17 17 17 17
26 17 17 17 17 17 17 17 17 17 17 17 17 17 17 17 17
27 17 17 17 17 17 17 17 17 17 17 17 17 17 17 17 17
30 17 17 17 17 17 17 17 17 17 17 17 17 17 17 17 17
31 17 17 17 17 17 17 17 17 17 17 17 17 17 17 17 17
32 17 17 17 17 17 17 17 17 17 17 17 17 17 17 17 17
33 17 17 17 17 17 17 17 17 17 17 17 17 17 17 17 17
34 17 17 17 17 17 17 17 17 17 17 17 17 17 17 17 17
35 17 17 17 17 17 17 17 17 17 17 17 17 17 17 17 17
36 17 17 17 17 17 17 17 17 17 17 17 17 17 17 17 17
37 17 17 17 17 17 17 17 17 17 17 17 17 17 17 17 17
Addresses: octal
Contents: octal
\f
C_P_U_ _8_2_1_ _C_O_N_N_E_C_T_O_R_ _1_0_0_1_
P_I_N_ _A_ _R_O_W_ _ _ _ _ _ _B_ _R_O_W_ _ _ _ _ _ _ _ _ _ _ _ _ _ _C_ _R_O_W_ _ _ _ _ _ _
S_I_G_N_A_L_ _ _ G_E_N_ _ _ _ S_I_G_N_A_L_ _ _ _ _ _ G_E_N_ _ _ S_I_G_N_A_L_ _ _
1 +5 VOLTS +5 VOLTS +5 VOLTS
2 0 VOLT -,SELIN(0)
3 - 1001B2 -,SELOUT(0)
4 - -,SELIN(1)
5 - 1001B4 -,SELOUT(1)
6 -
7 -
8 -
9 -
10 -
11 -
12 -
13 -
14 -
15 -
16 -
17 -
18 -
19 -
20 -
21 -
22 -
23 -
24 -
25 -
26 -
27 -
28 -
29 -
30 -
31
32 +5 VOLT +5 VOLTS +5 VOLTS
\f
C_P_U_ _8_2_1_ _C_O_N_N_E_C_T_O_R_ _1_0_0_2_
P_I_N_ _A_ _R_O_W_ _ _ _ _ _ _ _ _ _ _B_ _R_O_W_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _C_ _R_O_W_ _ _ _ _ _ _ _ _ _ _ _ _
S_I_G_N_A_L_ _ _ _ _ _ G_E_N_ _ _ _ S_I_G_N_A_L_ _ _ _ _ _ G_E_N_ _ _ _ S_I_G_N_A_L_ _ _ _ _ _ _
1 +5 VOLTS +5 VOLTS +5 VOLTS
2 0 VOLT
3 -
4 -
5 -
6 -
7 -
8 - -,CPU2AVAIL
9 - -,CAMAVAIL -,FPUAVAIL
10 - 145-12 -,READ(0) 145-11 -,READ(1)
11 - 145-10 -,READ(2) 145-9 -,READ(3)
12 - LIMVIOL I/O ERROR
13 - UNITRDY
14 -
15 - INSTRRDY
16 - PREFERROR PC<8
17 - INSTRBUS(0) INSTRBUS(1)
18 - (2) (3)
19 - (4) (5)
20 - (6) (7)
21 - (8) (9)
22 - (10) (11)
23 - (12) (13)
24 - (14) (15)
25 - (16) (17)
26 - (18) (19)
27 - (20) (21)
28 - (22) (23)
29 - 76-10 MASTERLOCK 156-6 CPULOCK
30 - 2-14 SYSTEMRST 2-12 -,LOAD
31
32 +5 VOLT +5 VOLTS +5 VOLTS
\f
C_P_U_ _8_2_1_ _C_O_N_N_E_C_T_O_R_ _1_0_0_3_
P_I_N_ _A_ _R_O_W_ _ _ _ _ _ _ _ _ _B_ _R_O_W_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _C_ _R_O_W_ _ _ _ _ _ _ _ _ _ _
S_I_G_N_A_L_ _ _ _ _ _ G_E_N_ _ _ _ S_I_G_N_A_L_ _ _ _ _ _ G_E_N_ _ _ _ _ S_I_G_N_A_L_ _ _ _ _ _
1 +5 VOLTS +5 VOLTS +5 VOLTS
2 0 VOLT POWEROK PINT
3 - 71-18 CPUBUS(0) 71-16 CPUBUS(1)
4 - 71-14 (2) 71-12 (3)
5 - 61-18 (4) 61-16 (5)
6 - 61-14 (6) 61-12 (7)
7 - 51-18 (8) 51-16 (9)
8 - 51-14 (10) 51-12 (11)
9 - 41-18 (12) 41-16 (13)
10 - 41-14 (14) 41-12 (15)
11 - 31-18 (16) 31-16 (17)
12 - 31-14 (18) 31-12 (19)
13 - 21-18 (20) 21-16 (21)
14 - 21-14 (22) 21-12 (23)
15 - 166-11 -,NEXTINSTR 111-11 ENPREF
16 - 102-2 ENOPFETCH 102-5 ENJMPFETCH
17 - 0 VOLT
18 - 0 VOLT
19 - DEVINTR 2-3 DISABLE
20 - -,TCPINTR -,SPAREINTR
21 - -,CAMFAULT 2-5 -,WADDR
22 - 2-7 CBUNITF(0) 2-9 CBUNITF(1)
23 - 12-18 (2) 12-16 (3)
24 - 12-14 (4) 12-12 (5)
25 - 12-3 CBSOURCE(0) 12-5 CBSOURCE(1)
26 - 12-7 (2) 12-9 (3)
27 - 1-18 (4) 1-16 (5)
28 - 1-14 CBDEST(0) 1-12 CBDEST(1)
29 - 1-3 (2) 1-5 (3)
30 - 1-7 (4) 1-9 (5)
31
32 +5 VOLT +5 VOLTS +5 VOLTS
\f
C_P_U_ _8_2_1_ _C_O_N_N_E_C_T_O_R_ _1_0_0_5_
P_I_N_ G_E_N_ _ _ _ S_I_G_N_A_L_ _ _ _ _ _ _ _ _ _ _ P_I_N_ G_E_N_ _ _ _ S_I_G_N_A_L_ _ _ _ _ _ _ _ _ _
A1 AUTOLOAD NC B1 0 VOLT AUTOLOAD C
A2 AUTOLOAD NO B2 0 VOLT AUTOLOAD C
A3 200-2 POWEROKLAMP- B3 R52 POWEROKLAMP+
A4 200-7 RUNLAMP- B4 R49 RUNLAMP+
A5 200-9 AUTOLOADLAMP- B5 R48 AUTOLOADLAMP+
A6 -,REMOTEAUTOLOAD B6 0 VOLT
A7 UNUSED B7 UNUSED
A8 - B8 -
A9 - B9 -
A10 - B10 -
A11 - B11 -
A12 - B12 -
A13 - B13 -
A14 - B14 -
A15 - B15 -
A16 - B16 -
A17 - B17 -
A18 - B18 -
A19 - B19 -
A20 - B20 -
A21 - B21 -
A22 - B22 -
A23 - B23 -
A24 - B24 -
A25 B25 -
\f
C_P_U_ _8_2_2_ _C_O_N_N_E_C_T_O_R_ _1_0_0_1_
P_I_N_ _A_ _R_O_W_ _ _ _ _ _ _ _ _ _B_ _R_O_W_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _C_ _R_O_W_ _ _ _ _ _ _ _ _ _ _
S_I_G_N_A_L_ _ _ _ _ _ G_E_N_ _ _ _ _ S_I_G_N_A_L_ _ _ _ _ _ G_E_N_ _ _ _ S_I_G_N_A_L_ _ _ _ _ _
1 +5 VOLTS +5 VOLTS +5 VOLTS
2 0 VOLT -,SELIN(0) -,BUSREQ(0)
3 - 1001B2 -,SELOUT(0) 211-15 -,BUSREQ(1)
4 - -,SELIN(1) -,COMSEL
5 - 211-2 -,SELOUT(1) 201-15 -,SELACK
6 - 201-9 -,SYSRESET POB
7 - 191-15 -,DATARDY 191-9 -,BUSBUSY
8 - 191-7 -,ACK POK
9 - 201-7 -,NACK -,PINT
10 - 182-15 -,ADDR(0) 182-9 -,ADDR(1)
11 - 181-15 (2) 181-9 (3)
12 - 181-7 (4) 181-2 (5)
13 - 182-7 (6) 182-2 (7)
14 - 172-15 (8) 172-9 (9)
15 - 171-15 (10) 171-9 (11)
16 - 171-7 (12) 171-2 (13)
17 - 172-7 (14) 172-2 (15)
18 - 162-15 (16) 162-9 (17)
19 - 161-15 (18) 161-9 (19)
20 - 161-7 (20) 161-2 (21)
21 - 162-7 (22) 162-2 -,ADDRPAR
22 - 152-15 -,DATA(0) 152-9 -,DATA(1)
23 - 151-15 (2) 151-9 (3)
24 - 151-7 (4) 151-2 (5)
25 - 152-7 (6) 152-2 (7)
26 - 142-15 (8) 142-9 (9)
27 - 141-15 (10) 141-9 (11)
28 - 141-7 (12) 141-2 (13)
29 - 142-7 (14) 142-2 (15)
30 - 132-15 (16) 132-9 (17)
31 +12 VOLTS +12 VOLTS +12 VOLTS
32 +5 VOLTS +5 VOLTS +5 VOLTS
\f
C_P_U_ _8_2_2_ _C_O_N_N_E_C_T_O_R_ _1_0_0_2_
P_I_N_ _A_ _R_O_W_ _ _ _ _ _ _ _ _ _ _B_ _R_O_W_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _C_ _R_O_W_ _ _ _ _ _ _ _ _ _ _
S_I_G_N_A_L_ _ _ _ _ _ _ G_E_N_ _ _ _ S_I_G_N_A_L_ _ _ _ _ _ _ G_E_N_ _ _ _ S_I_G_N_A_L_ _ _ _ _ _ _
1 +5 VOLTS +5 VOLTS +5 VOLTS
2 0 VOLT 131-15 -,DATA(18) 131-9 -,DATA(19)
3 - 131-7 (20) 131-2 (21)
4 - 132-7 (22) 132-2 (23)
5 - 123-15 -,DATAPAR(0) 123-9 -,DATAPAR(1)
6 - 123-7 (2) 123-2 -,DATAOUT
7 -
8 - 0 VOLT -,CPU2AVAIL
9 - -,CAMAVAIL
10 - -,READ(0) -,READ(1)
11 - -,READ(2) -,READ(3)
12 - 24-9 LIMITVIOL 31-11 I/O ERROR
13 - 31-8 UNITRDY
14 -
15 22-15 BYPASSCAM 31-3 INSTRRDY
16 - 31-6 PREFERROR 0 VOLT PC<8
17 - 111-2 INSTRBUS(0) 111-5 INSTRBUS(1)
18 - 111-6 (2) 111-9 (3)
19 - 111-12 (4) 111-15 (5)
20 - 111-16 (6) 111-19 (7)
21 - 112-2 (8) 112-5 (9)
22 - 112-6 (10) 112-9 (11)
23 - 112-12 (12) 112-15 (13)
24 - 112-16 (14) 112-19 (15)
25 - 103-2 (16) 103-5 (17)
26 - 103-6 (18) 103-9 (19)
27 - 103-12 (20) 103-15 (21)
28 - 103-16 (22) 103-19 (23)
29 - MASTERLOCK CPUCLOCK
30 - -,LOAD
31 -12 VOLTS -12 VOLTS -12 VOLTS
32 +5 VOLTS +5 VOLTS +5 VOLTS
\f
C_P_U_ _8_2_2_ _C_O_N_N_E_C_T_O_R_ _1_0_0_3_
P_I_N_ _A_ _R_O_W_ _ _ _ _ _ _ _ _ _B_ _R_O_W_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _C_ _R_O_W_ _ _ _ _ _ _ _ _ _
S_I_G_N_A_L_ _ _ _ _ _ G_E_N_ _ _ S_I_G_N_A_L_ _ _ _ _ _ G_E_N_ _ _ S_I_G_N_A_L_ _ _ _ _ _
1 +5 VOLTS +5 VOLTS +5 VOLTS
2 0 VOLTS 13-6 POWEROK 201-3 PINT
3 - 71-18 CPUBUS(0) 71-16 CPUBUS(1)
4 - 71-14 (2) 71-12 (3)
5 - 71-3 (4) 71-5 (5)
6 - 71-7 (6) 71-9 (7)
7 - 72-18 (8) 72-16 (9)
8 - 72-14 (10) 72-12 (11)
9 - 72-3 (12) 72-5 (13)
10 - 72-7 (14) 72-9 (15)
11 - 63-18 (16) 63-16 (17)
12 - 63-14 (18) 63-12 (19)
13 - 63-3 (20) 63-5 (21)
14 - 63-7 (22) 63-9 (23)
15 - -,NEXTINSTR ENPREF
16 - ENOPFETCH ENJUMPFETCH
17 -
18 -
19 - 24-5 DEVINTR DISABLE
20 - 21-11 -,TCPINTR
21 - -,WADDR
22 - UNITFUNC(0) UNITFUNC(1)
23 - (2) (3)
24 - (4) (5)
25 - CBSOURCE(0) CBSOURCE(1)
26 - (2) (3)
27 - (4) (5)
28 - CBDEST(0) CBDEST(1)
29 - (2) (3)
30 - (4) (5)
31
32 +5 VOLTS +5 VOLTS +5 VOLTS
\f
C_P_U_ _8_2_2_ _C_O_N_N_E_C_T_O_R_ _1_0_0_4_
P_I_N_ G_E_N_ S_I_G_N_A_L_ _ _ _ _ _ _ _ P_I_N_ G_E_N_ S_I_G_N_A_L_ _ _ _ _ _ _
A1 0 VOLT B1 7-7 -,TRANSMDATA
A2 0 VOLT B2 -,RECDATA
A3 0 VOLT B3 DATASETRDY
A4 0 VOLT B4 7-6 DATATERMRDY
A5 UNUSED B5 UNUSED
A6 - B6 -
A7 - B7 -
A8 - B8 -
A9 - B9 -
A10 - B10 -
A11 - B11 -
A12 - B12 -
A13 - B13 -
A14 - B14 -
A15 - B15 -
A16 - B16 -
A17 - B17 -
A18 - B18 -
A19 - B19 -
A20 - B20 -
A21 - B21 -
A22 - B22 -
A23 - B23 -
A24 - B24 -
A25 - B25 -
\f
C_P_U_ _8_2_2_ _C_O_N_N_E_C_T_O_R_ _1_0_0_5_
P_I_N_ G_E_N_ _ _ _ S_I_G_N_A_L_ _ _ _ _ _ P_I_N_ G_E_N_ _ _ _ S_I_G_N_A_L_ _ _ _ _ _
A1 220-12 CAMADDR(22) B1 0 VOLT
A2 220-9 (21) B2 -
A3 220-7 (20) B3 -
A4 220-4 (19) B4 -
A5 209-12 (18) B5 -
A6 209-9 (17) B6 -
A7 209-7 (16) B7 -
A8 209-4 (15) B8 -
A9 208-12 (14) B9 -
A10 208-9 (13) B10 -
A11 208-7 (12) B11 -
A12 208-4 (11) B12 -
A13 207-12 (10) B13 -
A14 207-9 (9) B14 -
A15 207-7 (8) B15 -
A16 207-4 (7) B16 -
A17 217-12 (6) B17 -
A18 217-9 (5) B18 -
A19 217-7 (4) B19 -
A20 217-4 (3) B20 -
A21 216-12 (2) B21 -
A22 216-9 (1) B22 -
A23 ACCEPT B23 -
A24 128-9 -,READCAM B24 -
A25 139-10 OPERAND B25 -
\f
C_B_L_ _8_2_6_ _O_C_P_ _a_n_d_ _R_E_M_O_T_E_ _A_U_T_O_L_O_A_D_ _C_A_B_L_E_
J_1_ J_1_0_0_5_ S_I_G_N_A_L_ _ _ _ _ _ _ _ _
A2 A1 AUTOLOAD NC
A3 B1 AUTOLOAD C
A4 A2 AUTOLOAD NO
A5 B2 AUTOLOAD C
A6 A3 POWEROKLAMP-
A7 B3 POWEROKLAMP+
B7 A4 RUNLAMP-
B6 B4 RUNLAMP+
B5 A5 AUTOLOADLAMP-
B3 B5 AUTLOADLAMP+
J_2_
A2 A6 -,REMOTEAULOAD
A3 B6 0 VOLT
C_B_L_ _9_0_4_ _T_E_C_H_N_I_C_I_A_N_ _C_O_N_S_O_L_E_ _C_A_B_L_E_
J_1_0_0_4_ J_1_ J_2_ S_I_G_N_A_L_ _ _ _ _ _ _
B1 2 6 -,TRANSMDATA
A1
B2 3 3 -,RECDATA
A2
B3 6 5 DATASETRDY
A3
B4 20 1 DATATERMRDY
A4 7 9 0 VOLT
\f
«eof»