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S_k_a_l_ _u_d_s_k_r_i_v_e_s_ _m_e_d_ _f_r_i_c_t_i_o_n_-_f_e_e_d_ _*_*_*_b_ø_r_ _i_k_k_e_ _o_m_b_r_y_d_e_s_ _u_d_e_n_
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Specieltegn skal tegnes på siderne 108, 109, 114, 115 og 116
KH
BE
\f
RC3803 CPU
Programmer>s Reference Manual
August 1980
A/S Regnecentralen af 1979 RCSL 42-i 1008 \f
Author: Knud Henningsen
Technical Editor: Knud Erik Hansen
KEY WORDS: RC3803, CPU 720, Revision 0.
ABSTRACT: This paper describes the logical structure of the
RC3803 Central Processor Unit.
Reservation
Copyright A/S Regnecentralen af 1979
Printed by A/S Regnecentralen af 1979, Copenhagen \f
i
T_A_B_L_E_ _O_F_ _C_O_N_T_E_N_T_S_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _P_A_G_E_
1. RC3803 SPECIFICATIONS ................................ 1
1.1 Central Processor Unit .......................... 1
1.2 Memory .......................................... 1
1.3 Input/Output .................................... 2
1.4 Interrupt Capability ............................ 2
1.5 Data Channel .................................... 3
1.6 Power Fail/Auto Restart ......................... 3
1.7 Real Time Clock ................................. 3
1.8 Diagnostic Front Panel .......................... 4
2. INTERNAL CONFIGURATION ............................... 5
2.1 Introduction .................................... 5
2.2 Program Structure ............................... 5
2.2.1 Program Execution ........................ 5
2.2.2 Program Flow Alteration .................. 6
2.2.3 Program Size ............................. 8
2.2.4 Program Flow Interruption ................ 8
2.3 Information Formats ............................. 9
2.3.1 Fundamental Concepts ..................... 10
2.3.2 Bit Numbering ............................ 10
2.3.3 Binary Representation .................... 11
2.3.4 Octal Representation ..................... 13
2.3.5 Hexadecimal Notation ..................... 14
2.4 Numerical Quantities ............................ 14
2.4.1 Integers ................................. 14
2.4.2 Logical Quantities ....................... 17
2.5 Addressing ...................................... 17
2.5.1 Word Addressing .......................... 17
2.5.2 Byte Addressing .......................... 21
3. INSTRUCTIONS ......................................... 23
3.1 Introduction .................................... 23
3.2 Instruction Formats ............................. 23
3.3 Mnemonic Description ............................ 23 \f
ii
T_A_B_L_E_ _O_F_ _C_O_N_T_E_N_T_S_ _(_c_o_n_t_i_n_u_e_d_)_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _P_A_G_E_
3.4 Program Flow Control ............................ 24
3.4.1 JUMP ..................................... 25
3.4.2 JUMP TO SUBROUTINE ....................... 26
3.4.3 INCREMENT AND SKIP IF ZERO ............... 27
3.4.4 DECREMENT AND SKIP IF ZERO ............... 27
3.5 Data Transfer Operation ......................... 28
3.5.1 LOAD ACCUMULATOR ......................... 29
3.5.2 STORE ACCUMULATOR ........................ 29
3.6 Integer Arithmetic and Logical Operations ....... 30
3.6.1 ADD ...................................... 36
3.6.2 SUBTRACT ................................. 37
3.6.3 NEGATE ................................... 38
3.6.4 ADD COMPLEMENT ........................... 39
3.6.5 MOVE ..................................... 39
3.6.6 INCREMENT ................................ 40
3.6.7 COMPLEMENT ............................... 40
3.6.8 AND ...................................... 41
3.6.9 Examples ................................. 41
4. INPUT/OUTPUT ......................................... 45
4.1 Introduction .................................... 45
4.2 Operation of I/O Devices ........................ 46
4.3 Interrupt System ................................ 46
4.4 Priority Interrupts ............................. 48
4.5 Direct Memory Access Data Channel ............... 50
4.6 I/O Instructions ................................ 51
4.6.1 DATA IN A ................................ 52
4.6.2 DATA IN B ................................ 53
4.6.3 DATA IN C ................................ 53
4.6.4 DATA OUT A ............................... 54
4.6.5 DATA OUT B ............................... 54
4.6.6 DATA OUT C ............................... 55
4.6.7 I/O SKIP ................................. 55
4.6.8 NO I/O TRANSFER .......................... 56 \f
iii
T_A_B_L_E_ _O_F_ _C_O_N_T_E_N_T_S_ _(_c_o_n_t_i_n_u_e_d_)_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _P_A_G_E_
4.7 Central Processor Functions ..................... 56
4.7.1 INTERRUPT ENABLE ......................... 58
4.7.2 INTERRUPT DISABLE ........................ 58
4.7.3 READ SWITCHES ............................ 59
4.7.4 INTERRUPT ACKNOWLEDGE .................... 59
4.7.5 MASK OUT ................................. 60
4.7.6 I/O RESET ................................ 60
4.7.7 HALT ..................................... 61
4.7.8 CPU SKIP ................................. 61
5. PROCESSOR FEATURES ................................... 62
5.1 Introduction .................................... 62
5.2 Power Fail ...................................... 63
5.3 MEMORY EXTENSION ................................ 64
5.4 CPU IDENTIFY .................................... 65
5.5 Byte Manipulation ............................... 65
5.5.1 LOAD BYTE ................................ 66
5.5.2 STORE BYTE ............................... 67
5.6 BYTE MOVE ....................................... 68
5.7 WORD MOVE ....................................... 69
5.8 SEARCH ITEM ..................................... 70
5.9 SEARCH FREE ..................................... 73
5.10 PROCESS LINK .................................... 74
5.11 PROCESS REMOVE .................................. 76
5.12 PROCESS LINK PRIORITY ........................... 78
5.13 INSTRUCTION FETCH (MUSIL) ....................... 81
5.14 TAKE ADDRESS (MUSIL) ............................ 82
5.15 TAKEVALUE (MUSIL) ............................... 84
5.16 COMPARE Byte Strings ............................ 86
6. PROCESSOR OPTIONS .................................... 88
6.1 Real Time Clock ................................. 88
6.2 Teletype Controller ............................. 89
6.2.1 Instructions ............................. 89
6.2.2 Programming .............................. 92
6.2.3 Programming Examples ..................... 93
\f
iv
T_A_B_L_E_ _O_F_ _C_O_N_T_E_N_T_S_ _(_c_o_n_t_i_n_u_e_d_)_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _P_A_G_E_
7. PROGRAM LOADING ...................................... 97
7.1 Introduction .................................... 97
7.2 Automatic Loading ............................... 98
8. SWITCHES AND INDICATORS .............................. 103
8.1 Switches ........................................ 103
8.1.1 ENABLE TCP ............................... 103
8.1.2 AUTOLOAD DEVICE SELECT ................... 104
8.1.3 PARITY ERROR ............................. 104
8.1.4 MEMORY EXTENSION SELECT .................. 105
8.2 Indicators ...................................... 106
8.2.1 PARITY ERROR ............................. 106
8.2.2 CPU-STATUS ............................... 106
A_P_P_E_N_D_I_C_E_S_:
A. I/O DEVICE CODES AND MNEMONIC ........................ 108
B. ASCII CHARACTER CODES ................................ 111
C. DOUBLE PRECISION ARITHMETIC .......................... 117
D. INSTRUCTION USE, EXAMPLES ............................ 119
E. INSTRUCTION EXECUTION TIMES .......................... 126
\f
1_._ _ _ _ _ _ _ _ _R_C_3_8_0_3_ _S_P_E_C_I_F_I_C_A_T_I_O_N_S_ 1.
1_._1_ _ _ _ _ _ _ _C_e_n_t_r_a_l_ _P_r_o_c_e_s_s_o_r_ _U_n_i_t_ 1.1
The RC3803 Central Processor Unit is a micro-programmed, general
purpose stored-program computer with four accumulators. The CPU
works on the basis of a unit of information called a word which
consists of 16 bits. Arithmetic and logical operations are per-
formed on operands held in the accumulators, which consequently
also are 16 bits in length. Two of the accumulators can be used
as index registers for addressing purposes.
1_._2_ _ _ _ _ _ _ _M_e_m_o_r_y_ 1.2
The main memory is available in two alternative modules:
RC3608 is a core memory with a capacity of 32K words and a cycle
time of 750 ns.
RC3609 is a core memory with a capacity of 16K words and a cycle
time of 650 ns.
The CPU can directly address 32K words of core memory and
provides for base page, relative, indexed and multi-level
indirect addressing modes. By the use of a special instruction
the CPU can be switched to a mode which will allow it to work
with up to 64K words of core memory.
Word length in memory is 16 + 2 = 18 bits. The two extra bits are
parity check bits. They are generated during each memory write
cycle and are checked during each memory read cycle. The detect-
ion of a parity error can affect the operation of the CPU in two
alternative ways: the error can be indicated on the front frame
of the CPU board while processing continues uninterrupted or pro-
cessing can be brought to a halt. The selection of either possi-
bility is left to the operator>s choice by means of a switch also
located on the CPU frame.
\f
1_._3_ _ _ _ _ _ _ _I_n_p_u_t_/_O_u_t_p_u_t_ 1.3
All peripheral devices are connected to the CPU through the
Input/Output bus. This consists of a six-line device selection
network, interrupt circuitry, command circuitry, and sixteen data
transmission lines. Each individual Input/Output device has a
unique six-bit device code and will only respond to commands if
its own device code is transmitted through the device selection
network of the Input/Output bus.
The six bits in the device code allows for 64 separate codes. A
number of these codes are reserved for specific uses, but the re-
maining codes make it possible to obtain an extremely flexible
handling of Input/Output devices.
1_._4_ _ _ _ _ _ _ _I_n_t_e_r_r_u_p_t_ _C_a_p_a_b_i_l_i_t_y_ 1.4
The interrupt circuitry included in the Input/Output bus provides
the capability for any peripheral device to interrupt normal pro-
gram execution whenever the device is in need of attention. When
a peripheral device has requested an interrupt the processor will
transfer control of operations to the main interrupt service rou-
tine, which will handle the servicing of the device. The inter-
rupt service routine will establish the source of the interrupt
either by polling all Input/Output devices connected to the CPU
or it can use a special instruction to identify the device in
question.
The interrupt system also provides the capability of implementing
up to sixteen levels of priority in connection with interrupts,
so that each individual peripheral device is associated with a
specific priority level. A standard priority assignment is imple-
mented by Regnecentralen, but the programmer can change these as-
signments according to his own choice.
\f
1_._5_ _ _ _ _ _ _ _D_a_t_a_ _C_h_a_n_n_e_l_ 1.5
Data transfers between peripheral devices and main memory under
program control occupy processor time and retard the rate of in-
formation transfer.
To avoid this restriction the Input/Output bus contains cir-
cuitry allowing high-speed access direct to memory through the
data channel, this permits a peripheral device to transfer data
directly into/out of memory using a minimum of processor time. At
the maximum transfer rate the data channel effectively stops the
processor, but at lower rates processing continues while the data
transfer takes place.
1_._6_ _ _ _ _ _ _ _P_o_w_e_r_ _F_a_i_l_/_A_u_t_o_ _R_e_s_t_a_r_t_ 1.6
The RC3803 computer incorporates a feature providing for auto-
matic restart in the event of an unexpected power loss. The delay
between the initial decrease of voltage and the actual automatic
shut-down of the processor is utilized to bring the interrupt
service routine into action. This routine will under these cir-
cumstances use the available interval of time to store the con-
tents of accumulators, the program restart address and other in-
formation that will be necessary for restart and continued opera-
tion when the power supply again has been restored.
The Power Fail feature is entirely automatic and will restart
operations on its own whenever power is again available.
1_._7_ _ _ _ _ _ _ _R_e_a_l_ _T_i_m_e_ _C_l_o_c_k_ 1.7
A Real Time Clock can optionally be included in the RC3803 com-
puter. This clock will generate a train of pulses independently
of processor timing, this will allow the interrupt system to be
activated at precisely spaced intervals of time. The pulse train
frequency can be selected by the programmer among the following
four possibilities: 10 Hz, 50 Hz, 100 Hz, and 1000 Hz. \f
1_._8_ _ _ _ _ _ _ _D_i_a_g_n_o_s_t_i_c_ _F_r_o_n_t_ _P_a_n_e_l_ 1.8
A Diagnostic Front Panel can be connected to the CPU even during
program execution. This will allow external, manual control of
the CPU and will thus facilitate error detection and correction.
The Diagnostic Front Panel is not described in detail in this
manual, for further information concerning this consult the
Reference Manual for the Diagnostic Front Panel - RCSL 52-AA542.
\f
2_._ _ _ _ _ _ _ _ _I_N_T_E_R_N_A_L_ _C_O_N_F_I_G_U_R_A_T_I_O_N_ 2.
2_._1_ _ _ _ _ _ _ _I_n_t_r_o_d_u_c_t_i_o_n_ 2.1
This chapter and the following deal in some detail with the basic
concepts underlying the actual modus operandi of the RC3803 CPU.
A more intimate knowledge of this subject is not strictly neces-
sesary for ordinary everyday use of the computer, because the
high-level programming languages available are designed to allow
symbolic programs to be written without reference to the more
specific information contained in this manual. Thus the intention
is not to establish guidelines for actual programming, for which
purpose separate manuals are available, but to provide a source
of background information for the programmer and/or operator.
2_._2_ _ _ _ _ _ _ _P_r_o_g_r_a_m_ _S_t_r_u_c_t_u_r_e_ 2.2
Information about the type of operation - arithmetical or other
- which the computer at any particular time must perform, is
given to the CPU in the shape of an "instruction". The CPU will
carry out successive instructions in strict sequence according
to the order in which the instructions have been specified. The
complete set of instructions is called a "program" and this must
at the time of execution reside in main memory in order to be
accessible to the CPU.
2_._2_._1_ _ _ _ _ _P_r_o_g_r_a_m_ _E_x_e_c_u_t_i_o_n_ 2.2.1
Each individual instruction occupies a space in memory called a
"word" and although these words will usually occupy adjacent
physical locations in memory, the program may incorporate in-
structions with the specific purpose of altering the sequence in
which the instructions should be carried out. \f
Thus the CPU must be able to locate the correct word at the cor-
rect point in the sequence in order to execute the program
properly. The actual physical location of a word is called its
"address" and consequently the establishing of location is called
"addressing".
Addressing the instructions is arranged by incorporating a count-
ing circuit called the "program counter". The program counter
contains one integer number, which always indicates the memory
address of the instruction currently being carried out. When the
operation specified by that particular instruction has been com-
pleted, the number in the program counter is incremented by one
and the CPU will then retrieve the next instruction to be carried
out from the memory location now being indicated by the number in
the program counter. Succeeding addresses will thus form a
strictly ascending numerical sequence and this method of oper-
ation is consequently called "sequential operation".
2_._2_._2_ _ _ _ _ _P_r_o_g_r_a_m_ _F_l_o_w_ _A_l_t_e_r_a_t_i_o_n_ 2.2.2
The programmer can however purposely arrange to deviate from the
strict sequential operation. This is done by using the appropri-
ate program flow control instructions which will make it possible
to achieve two distinctly different types of program flow varia-
tion.
The "jump" type instruction will cause an arbitrary new number -
either larger or smaller than the current one - to be inserted
in the program counter. Thus when the jump instruction has been
executed, the next instruction to be located can have any of all
the possible addresses.
\f
The "conditional skip" type instruction will first determine
whether a specified test condition is true or not. If true, it
will then cause the program counter to be increased by one, if
false, nothing further will be done. When the conditional skip
instruction has been executed, the program counter will be in-
creased by one as in the usual sequential operation and thus the
next instruction to be located will have either of the two fol-
lowing addresses depending on the outcome of the test. Normal
sequential operation will be resumed after the completion of
either type of instruction - using the updated value of the pro-
gram counter - and will continue until the next program flow
alteration occurs. An illustration showing the two types of pro-
gram flow alteration appears in fig. 2.2.2.
SEQUENTIAL
PROGRAM
FLOW
INCREASING
ADDRESSES
I JUMP
N PROGRAM
S FLOW
T
R
U
C
T
I SKIP
O PROGRAM
N FLOW
S
Figur 2.2.2
\f
2_._2_._3_ _ _ _ _ _P_r_o_g_r_a_m_ _S_i_z_e_ 2.2.3
The integer number contained in the program counter will have a
magnitude between 0 and 32, 767 (both included) and will thus
make it possible to address 32,768 separate memory locations
which is then the maximum program size. The program need not
necessarily start in memory location 0, but if the program
counter reaches the value 32,767 the next incrementation will
produce the value 0 and sequential operation will then continue
from here as previously explained. Notice should be taken of the
fact, that no indication whatsoever of this particular situation
will be given.
N_O_T_E_: The proceeding outlined above will change if Memory
Extension has been selected (cf. Section 5.3).
2_._2_._4_ _ _ _ _ _P_r_o_g_r_a_m_ _F_l_o_w_ _I_n_t_e_r_r_u_p_t_i_o_n_ 2.2.4
During the normal running of a program a variety of situations
may arise which will make it necessary to interrupt the normal
program flow, i.e. to stop ordinary processing temporarily. This
may be due to either quite normal occurrences - for instance the
necessity of performing an Input/Output operation - or it may be
due to exceptional occurrences - external or internal faults or
malfunctions.
In both cases the address of the next sequential instruction is
saved by the CPU while the interrupt condition lasts. On ter-
mination of the interrupt condition the address saved by the CPU
is placed in the program counter anew and the interrupted program
resumes operation at the correct point in the sequence.
\f
An illustration showing this variation in program flow appears in
fig. 2.2.4.
SEQUENTIAL
PROGRAM
FLOW
INCREASING I/O
ADDRESSES INTERRUPT
I OCCURS
N
S
T JUMP
R
U
C
T SKIP
I
O
N CONTINUED
S PROGRAM RETURN
FLOW
Figur 2.2.4
2_._3_ _ _ _ _ _ _ _I_n_f_o_r_m_a_t_i_o_n_ _F_o_r_m_a_t_s_ 2.3
In any computer information is basically represented by some
physical quantity - usually electric current or magnetism. The
actual nature of this quantity as well as its magnitude carries
no importance with respect to use of the computer; the important
property is that the relevant quantity can either be present or
not present.
\f
2_._3_._1_ _ _ _ _ _F_u_n_d_a_m_e_n_t_a_l_ _C_o_n_c_e_p_t_s_ 2.3.1
The two possible - but mutually exclusive - states as mentioned
above form the basis for all considerations of information pro-
cessing. The two states are normally indicated by the numerals 0
(zero) and 1 (one) and the nucleus of information thus represented
is called a "binary digit" - usually shortened to "bit".
In the RC3603 computer the standard unit of information is how-
ever the "word", which is a string of 16 individual bits. As each
bit can attain either of two different states, the string of 16
bits can represent 2UU16DD = 65,536 different pieces of information,
for instance the integer numbers from 0 up to 65,535. It should
here be noted, that although the wellknown mathematical symbolism
- i.e. numbers - is often used to describe the information con-
tent of a word (or a part of a word), this is in reality only a
matter of convenience and does not restrict the actual meaning of
the information to this particular subject; nor does it restrict
the use to which it may be put. Although the word is the standard
unit of information handled by the RC3803 computer it can at
times be convenient to subdivide a word into two parts of 8 bits
each. Such a half-word is called a "byte" and is capable of re-
presenting 2UU8DD = 256 different pieces of information.
2_._3_._2_ _ _ _ _ _B_i_t_ _N_u_m_b_e_r_i_n_g_ 2.3.2
When considering the information contained in bytes or words it
is convenient to establish a definite method of referencing the
individual bits of the byte or word. This is done simply by ordi-
nary numbering of the bits within the word or byte.
The numbering always proceeds from left to right, i.e. the left-
most bit in a word is bit 0 while the rightmost bit in a word is
bit 15. Similarly the leftmost bit in a byte is bit 0 while the
rightmost bit in a byte is bit 7. Notice that the numbering al-
ways starts with bit 0.
\f
The convention adopted here is illustrated in fig. 2.3.2.
WORD WORD
BYTE BYTE BYTE BYTE
0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
Figur 2.3.2
It should also be noted that the adoption of this convention
means, that if for instance the word contains a number then the
highest-order digit will have the lowest bit number while the
lowest-order digit will have the highest bit number.
2_._3_._3_ _ _ _ _ _B_i_n_a_r_y_ _R_e_p_r_e_s_e_n_t_a_t_i_o_n_ 2.3.3
If the conventional mathematical notation is adopted by using
the numerical values 0 and 1 to indicate the two possible states
of the bit, then a word will be read simply as an ordinary 16-
digit number - although the number will be written in somewhat
unusual manner which in mathematics is called "binary notation".
From our everyday lives we are accustomed to use of numbers in
very many contexts; take for instance an arbitrary number like
315. The important feature of a number like this is that the
actual value of the individual digit depends on its p_o_s_i_t_i_o_n_ in
the written number. In effect the way the number is written is
just a convenient short-hand way of indicating the magnitude:
3 x 100 + 1 x 10 + 5 x 1 = 3 x 10uU2dD + 1 x 10uU1dD + 5 x 10uU0dD.
This is called "decimal notation" or "base 10" representation
because successive digit positions in the number form a sequence
of increasing powers of 10.
\f
To indicate that a number is written in base 10 representation a
subscript is used whenever there exists a possibility of confu-
sion:
315dD10uU.
It is obvious that decimal notation will require ten different
symbols to indicate the possible values of the individual digits,
namely the symbols: 0, 1, 2, 3, 4, 5, 6, 7, 8, and 9.
Binary notation - or base 2 representation - is in exactly the
same way a positional system, the only difference being that in
this case successive positions in the number form a sequence of
powers of 2. Whereas base 10 representation required ten different
symbols for the individual digits base 2 representation will only
require two different symbols, namely 0 and 1; this is of course
the reason for its dominant position in all aspects of computer
technology.
A binary number can of course be used to indicate any magnitude
just as well as a decimal number; consequently a binary number can
always be converted to the equivalent decimal number and vice
versa. Thus:
100111011dD2uU =
1 x 2UU8DD + 0 x 2UU7DD + 0 x 2UU6DD + 1 x 2UU5DD + 1 x 2UU4DD + 1 x 2UU3DD +
0 x 2UU2DD + 1 x 2UU1DD + 1 x 2UU0DD =
1 x 256dD10uU + 0 x 128dD10uU + 0 x 64dD10uU + 1 x 32Dd10uU + 1 x 16dD10uU +
1 x 8dD10uU + 0 x 4dD10uU + 1 x 2dD10uU + 1 x 1dD10uU =
256dD10uU + 32dD10uU + 16dD10uU + 8dD10uU + 2dD10uU + 1dD10uU =
315dD10uU.
\f
2_._3_._4_ _ _ _ _ _O_c_t_a_l_ _R_e_p_r_e_s_e_n_t_a_t_i_o_n_ 2.3.4
Internally the CPU will only recognize information given in base
2 representation, but from the example given above it will be
clear that the simplicity of binary numbers, owing to the limited
number of different symbols used, is counteracted by the neces-
sity of using more digit positions to indicate any given magni-
tude, i.e. binary numbers tend to become rather long and un-
wieldy.
Extensive application of binary notation in a manual like this can
therefore be somewhat awkward and might even lead to confusion. It
cannot be completely avoided, but very often numerical representa-
tion to yet another base is used instead.
Noting that a three-digit binary number can represent numerical
values from 000dD2uU = 0dD10uU to 111dD2uU = 7Dd10uU it is easily realised,
that each group of three bits can be uniquely represented by the
eight digits 0, 1, 2,....6 and 7. Therefore the use of a repre-
sentation to base 8 - so-called octal notation - will retain the
basic structure of the binary format, but it will on the other
hand only require one third of the positional places needed in
pure binary notation.
Expressing the example used on the preceding page in octal
notation will yield:
315dD10uU = 100111011dD2uU = 473dD8uU.
Thus by dividing any string of bits into groups of three and
using octal notation a fairly compact and convenient represen-
tation is achieved. The subdivision of the string alway starts
with the rightmost group of three bits and proceeds towards the
left. If the number of places in the binary number is not divis-
ible by three the leftmost group will contain only one or two
bits. This is however of no particular consequence: conversion to
octal notation will take place as outlined above on the addition-
al assumption that the leftmost group is filled-up to three
digits by prefixing the necessary one or two zeroes.
\f
2_._3_._5_ _ _ _ _ _H_e_x_a_d_e_c_i_m_a_l_ _N_o_t_a_t_i_o_n_ 2.3.5
In some cases still another base is used to represent binary in-
formation, namely base 16 - also called hexadecimal notation
("hex"). Just as in the case of octal notation the binary number
is formed into groups, but each group will consist of four bits.
These four bits can express the numerical values from 0000Dd2uU = 0Dd10uU
to 1111dD2uU = 15dD10uU, and in "hex" it will consequently be necessary
to use sixteen individually different symbols for the digits. The
numerals from 0 to 9 are of course still used to represent their
usual values, whereas the values from 10dD10uU to 15dD10uU will be repre-
sented by the initial six letters of the alphabet: A to F. The
example previously used will then yield:
315Dd10Uu = 100111011dD2uU = 473dD8uU = 13BdD16uU.
2_._4_ _ _ _ _ _ _ _N_u_m_e_r_i_c_a_l_ _Q_u_a_n_t_i_t_i_e_s_ 2.4
The CPU does not intrinsically recognize one type of information
as being different from another, but it is quite obvious that in
terms of application of the computer numerical quantities do ap-
pear in the majority of situations. Numerical quantities basical-
ly accepted by the CPU can be either integers or logical quanti-
ties.
2_._4_._1_ _ _ _ _I_n_t_e_g_e_r_s_ 2.4.1
Operations on integer quantities can be performed on signed or un-
signed binary numbers, which may be carried by the CPU in either
single or multiple precision. Single precision integers are two
bytes long (16 bits), while multiple precision integers are four
or more bytes long.
\f
Unsigned integers use all available bits to represent the magni-
tude of the number; thus an unsigned, single precision integer can
range in value from 0dD10uU to 65,535Dd10uU (2UU16DD - 1) corresponding to
the sixteen bits available. Similarly two words taken together as
an unsigned, double precision integer can range in value from
0dD10uU to 4,294,967,295dD10uU (2uU32dD - 1) corresponding to the thirtytwo
bits available.
Signed integers use bits 1 to 15 to represent the magnitude of the
number while bit 0 is reserved for use as sign bit. The aforesaid
assumes single precision; if multiple precision is employed the
first (leftmost) word will be structured in this same way while
the following word(s) will use all available bits to represent
numerical information.
For positive numbers the sign bit is 0 and the remaining bits re-
present the magnitude of the number in standard binary notation as
explained above.
For negative numbers the sign bit is 1 and the remaining bits re-
present the magnitude of the number in complemented binary nota-
tion (also called two>s complement form).
Complementing a number - whether in decimal, binary, or any other
notation - simply means writing the negative number as the sum of
two numbers: a large negative number which is a power of the base
plus that positive number which will yield the original number
when added to the large negative one. For instance in decimal
notation:
- 315 = - 1,000,000,000 + 999,999,685.
The advantage of this form is that when working within a set num-
ber of digit positions, the large negative number will "vanish" -
leaving simply a row of zeroes.
To produce the complement - "mechanically" speaking - of a decimal
number just subtract the individual digit from 9 to give the digit
value of the complement - and then finally add 1 to the last digit.
\f
Thus:
315DD10UU = 0 000 000 100 111 011
1 111 111 011 000 100 - complementation
+______________________1_
- 315DD10UU = 1 111 111 011 000 101
Note that the complementation of a negative number will of
course produce the positive of that number.
Complementing zero will produce a carry out of the leftmost bit
and leave the number again as zero:
0 000 000 000 000 000 - zero
1 111 111 111 111 111 - complementation
+_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _1_
0 000 000 000 000 000 - zero
Note that zero is a positive number!
As shown above complementation of zero will again produce zero
and there will thus always be one more negative number than there
are non-negative numbers within the given range of digit posi-
tions. The numerically largest negative number is a number with
the sign bit 1 and all remaining bits 0. The positive value of
this number cannot be represented in the same number of digit
positions as used to represent the negative number.
Thus a single precision signed integer can lie in the range from
- 32,768 to + 32,767 while a double precision signed integer can
lie in the range from - 2,147,483,648 to + 2,147,483,647.
Note that addition and subtraction of signed numbers in two>s
complement form is identical to the same operations on unsigned
numbers; the CPU just treats the sign bit as the most significant
(highest-order) magnitude bit.
\f
2_._4_._2_ _ _ _ _ _L_o_g_i_c_a_l_ _Q_u_a_n_t_i_t_i_e_s_ 2.4.2
Operations on logical quantities can be performed on individual
bits, bytes, or words. In all cases the quantities operated on
are treated as simple un-structured binary quantities. The logi-
cal value "true" is represented by 1 while the logical value
"false" is represented by 0. Two logical quantities are identical
if and only if they have identical values in corresponding bit
positions
The number of bits, bytes, or words operated on will depend on
the instruction actually being used.
2_._5_ _ _ _ _ _ _ _A_d_d_r_e_s_s_i_n_g_ 2.5
It has already been mentioned in the section "Program Execution"
(section 2.2.1) that the CPU must be able to locate the instruc-
tions stored in main memory. Similarly the CPU must be able to
locate the data involved in the operation to be performed - the
address of which data will usually be indicated in the instruc-
tion.
2_._5_._1_ _ _ _ _ _W_o_r_d_ _A_d_d_r_e_s_s_i_n_g_ 2.5.1
Main memory is subdivided into a number of words - the actual
magnitude of which depends on the CPU configuration actually
being employed. Every single word in memory has a definite ad-
dress, which is given as a number: the first word in memory has
the address 0, the next word has the address 1, the next word has
the address 2, and so on. It will be recalled that the address of
the instruction currently in effect is held in the one-word
program counter during the execution of a program. The
instruction itself must contain information about the address of
data to be used during the execution of that particular
instruction.
\f
In contrast to the address held in the program counter the ad-
dress information contained in the instruction will not always
directly specify the necessary address but may form the basis for
a calculation whose result will be the desired address. This cal-
culation is called "effective address calculation" and the result
of this is the "effective address".
The six instructions which directly reference memory in this way
use eleven bits of the word containing the instruction for ef-
fective address calculation. The format of these six instructions
is shown below:
IN-
@ DEX DISPLACEMENT
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
The eleven bits concerned are bits 5 to 15; of these bit 5 is
called the indirect bit, bits 6 and 7 are called the index bits
and the remaining eight bits (bits 8 to 15) are called the dis-
placement bits.
There are four essentially different modes of effective
address calculation available:
Page zero addressing
Relative addressing
Index Register addressing
Indirect addressing
2_._5_._1_._1_ _ _P_a_g_e_ _Z_e_r_o_ _A_d_d_r_e_s_s_i_n_g_ 2.5.1.1
Page zero addressing is indicated by the index bits being 00.
Then the displacement bits are taken as an ordinary unsigned in-
teger number indicating directly the effective address. An 8-bit
number will lie in the range from 0 to 255dD10uU; this first block
of 256dD10uU words in memory, which can be addressed directly in
this way way, is known as page zero.
\f
2_._5_._1_._2_ _ _ _R_e_l_a_t_i_v_e_ _A_d_d_r_e_s_s_i_n_g_ 2.5.1.2
Relative addressing is signified by the index bits being 01. In
this case the displacement bits are taken as a signed, two>s
complement integer number. This number is added to the address -
contained in the program counter - of the instruction currently
in effect; the result of the addition is the effective address.
By this means the effective address can be any address in memory
accessible to the program as it is defined relative to the ad-
dress of the instruction. A signed 8-bit number will lie in the
range from -128dD10uU to +127dD10uU relative addressing therefore gives
access to a block of 256Dd10uU words distributed evenly on either
side of the instruction.
2_._5_._1_._3_ _ _ _I_n_d_e_x_ _R_e_g_i_s_t_e_r_ _A_d_d_r_e_s_s_i_n_g_ 2.5.1.3
Index register addressing is signified by the index bits being
either 10 or 11. If they are 10 then accumulator 2 is used as an
index register; if they are 11 then accumulator 3 is similarly
used.
In both cases the displacement bits are taken as a signed, two>s
complement integer number; this number is added to the number
contained in the accumulator indicated by the choice of index
bits. The result of the addition is the effective address.
N_O_T_E_: The addition performed in relative and index register
addressing is clipped to 15 bits, i.e. the high-order
bit (bit 0) of the resulting address is set to 0. For
example:
if the displacement bits are 01 001 111 and (in rela-
tive addressing) the program counter stands at 111 111
110 101 011, then the addition should produce the re-
sult: 1 000 000 000 011 010, but bit 0 will be set to 0
so that the result reads:
0 000 000 000 011010.
If however Memory Extension has been selected the procedure out-
lined in this note will not apply (for further details see sec-
tion 5.3).
\f
When index register addressing is used the addition of the dis-
placement to the number contained in the accumulator does not
change the value contained in the accumulator.
2_._5_._1_._4_ _ _ _I_n_d_i_r_e_c_t_ _A_d_d_r_e_s_s_i_n_g_ 2.5.1.4
While discussing the three addressing modes hitherto covered it
has been tacitly assumed, that the indirect bit (bit 5) of the
instruction was 0, since only then will the result of the address
calculation be the effective address.
If the indirect bit is 1 then the word addressed by either of
the three previously mentioned address calculations is expected
in itself to contain an address (level 1 indirection). The word
concerned will of course contain the usual 16 bits of which now
bit 0 will be the indirect bit and bits 1 to 15 will contain the
address proper.
If now the indirect bit in the level 1 indirection address is 0
then the address contained in bits 1 to 15 is assumed to be the
effective address, but if the indirect bit is 1 then the level 1
indirection address is again expected to contain a further ad-
dress (level 2 indirection). This procedure will then be repeated
until an address is eventually retrieved where bit 0 is 0 and
bits 1 to 15 consequently will be taken to be the effective ad-
dress.
It should be noted that there is no limit to the levels of in-
direction accepted by the CPU. Neither is there any indication if
the chain of indirect addresses due to an error should form a
closed loop thus continuing indefinitely.
N_O_T_E_: Multi-level indirect addressing mode is disabled
if Memory Extension has been selected (section 5.3).
\f
r2_._5_._1_._5_ _ _ _A_u_t_o_ _L_o_c_a_t_i_o_n_s_ 2.5.1.5
Two areas of main memory are reserved for special addressing
purposes.
Locations in the range from 20dD8uU to 27dD8uU are autoincrement loca-
tions, which means that if an indirect addressing chain refer-
ences an address in this range then the word in that location
will be retrieved, the number contained in the word will be in-
cremented by one and this will then be written back into the lo-
cation. The updated value is then used to continue the chain of
indirect addresses.
Locations in the range from 30Dd8uU to 37dD8uU are autodecrement loca-
tions. Exactly the same procedure as outlined above applies here
except that the contents of the location will be decremented
instead of incremented.
N_O_T_E_: When autoincrement or autodecrement locations are ref-
erenced in an indirection chain the state of bit 0
b_e_f_o_r_e_ the incrementation or decrementation will be the
condition determining the continuation of the chain.
For example:
if an autoincrement location containing the number
177777dD8uU is referenced during an indirection chain
then the next address in the chain will be location
000000Dd8uU - and it will be assumed that this location
in itself will contain an address due to the fact, that
the original word contained in the autoincrement location
(177777dD8uU) had a 1 bit in bit 0.
2_._5_._2_ _ _ _ _ _B_y_t_e_ _A_d_d_r_e_s_s_i_n_g_ 2.5.2
Although the ordinary addressing routines will only allow addres-
sing of complete 16-bit words in memory a convenient programming
method is available which will allow handling of individual by-
tes.
\f
This method involves the use of a "byte pointer" which is a word
containing in bits 0 to 14 the address of a normal two-byte word
in memory and where bit 15 is the "byte indicator". If the byte
indicator is 0 the referenced byte will be the leftmost byte
(containing bits 0 to 7) of the word whose address is given in
bits 0 to 14 of the byte pointer; if the byte indicator is 1 the
referenced byte will correspondingly be the rightmost byte (con-
taining bits 8 to 15).
Programming routines to handle individual bytes in this way are
listed in Appendix D of this manual.
Byte addressing cannot be used when locations in the extended
memory area are manipulated.
\f
F_3_._ _ _ _ _ _ _ _ _I_N_S_T_R_U_C_T_I_O_N_S_ 3.
3_._1_ _ _ _ _ _ _ _I_n_t_r_o_d_u_c_t_i_o_n_ 3.1
The complete set of operation instructions available for RC3803
CPU is divided into four subsets. These are instruction sets for
program flow control, data transfer operations, integer arithme-
tic, and logical operations and a special subset for programming
the processor functions plus the optional features: Real Time
Clock, Power Fail/Auto-restart, and Memory Extension.
3_._2_ _ _ _ _ _ _ _I_n_s_t_r_u_c_t_i_o_n_ _F_o_r_m_a_t_s_ 3.2
All instructions in the set are one 16-bit word in length but the
lay-out will differ depending on the type of operation to be per-
formed; more specifically this will bear on the number of accumu-
lators employed in the execution of the instruction. In the fol-
lowing description of the different subsets a discussion of the
general format in each separate case will appear initially fol-
lowed by a description of the individual instructions which make
up that particular subset.
3_._3_ _ _ _ _ _ _ _M_n_e_m_o_n_i_c_ _D_e_s_c_r_i_p_t_i_o_n_ 3.3
In the description of individual instructions the specific form
of the instruction is given in the following generalized format:
MNEMONIC <optional mnemonic' OPERAND STRING <optional operands'
The main mnemonic is a group of letter symbols which must be used
to initiate the operation concerned in the instruction. To this
may in some cases be appended the optional mnemonics, which will
cause a modification of the execution of the instruction.
The operand string consists of the actual operands necessary to
the execution of the instruction. To this may likewise be appen-
ded optional operands.
\f
The symbols <' and == are used as an aid in defining the
specific form of each individual instruction:
< ' indicates optional mnemonics or operands
==== used as underlining to identify where definite substi-
tution is required, i.e. where the actual identifica-
tion of accumulator, address, name, number, or mnemonic
must be inserted in the instruction string.
The following abbreviations are used throughout this manual:
AC Accumulator
ACD Destination accumulator
ACS Source accumulator.
3_._4_ _ _ _ _ _ _ _P_r_o_g_r_a_m_ _F_l_o_w_ _C_o_n_t_r_o_l_ 3.4
Program flow control operations are handled by way of the program
counter - as outlined in section 2.2.1 - and thus do not explicit-
ly utilize any of the available accumulators. The instruction
lay-out in this subset is as follows:
OP In-
0 0 0 Code @ dex DISPLACEMENT
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
In this format bits 0, 1, and 2 are 000, bits 3 and 4 contain the
operation code and bits 5 to 15 contain the memory address as de-
scribed in section 2.5.1.
The symbol @ - placed anywhere in the effective address operand
string - will set the indirect bit (bit 5) to 1.
\f
The index bits (bit 6 and 7) are set by a comma followed by one
of the digits 0 to 3 as the last operand of the operand string.
If no index is coded, the index bits are automatically set to
00. The index bits can be set to 01 by using the character
"period" (.) at the beginning of the effective address operand
string. When the period is used, it is followed by either a plus
or a minus sign and the appropriate displacement, e.g. ".+7" or
".-2".
The subset contains the following four instructions: JUMP, JUMP
TO SUBROUTINE, INCREMENT AND SKIP IF ZERO, and DECREMENT AND SKIP
IF ZERO.
3_._4_._1_ _ _ _ _ _J_U_M_P_ 3.4.1
JMP <@' displacement < ,index'
=================
In-
0 0 0 0 0 @ dex DISPLACEMENT
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
The instruction will cause the effective address to be computed
and subsequently placed in the program counter. Sequential op-
eration will then continue with the word addressed by this new
value of the program counter.
\f
3_._4_._2_ _ _ _ _ _J_U_M_P_ _T_O_ _S_U_B_R_O_U_T_I_N_E_ 3.4.2
JSR <@' displacement < ,index '
=================
In-
0 0 0 0 1 @ dexDISPLACEMENT
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
The instruction will cause the effective address to be computed.
The current value of the program counter is incremented by one
and this number is placed in AC3, whereupon the previously cal-
culated effective address is placed in the program counter and
sequential operation then continues with the word addressed by
this new value of the program counter.
N_O_T_E_: The computation of the effective address is completed
before the incremented value in the program counter is
written into AC3. This means that if the effective ad-
dress calculation involves AC3 as an index register,
the original value contained in this register will be
used in the calculation before it is overwritten with
the incremented program counter.
As this instruction saves the incremented value of the program
counter in AC3 the use of this instruction for subroutine calls
makes the return to the proper point in the main program extreme-
ly simple necessitating only the instruction JMP 0,3.
\f
3_._4_._3_ _ _ _ _ _I_N_C_R_E_M_E_N_T_ _A_N_D_ _S_K_I_P_ _I_F_ _Z_E_R_O_ 3.4.3
ISZ <@' displacement <,index'
=================
In-
0 0 0 1 0 @ dex DISPLACEMENT
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
This instruction will cause the effective address to be computed.
The word in this location is incremented by one and the result is
written back into the original location. If the result of the
incrementation is zero then the next sequential instruction is
skipped.
3_._4_._4_ _ _ _ _ _D_E_C_R_E_M_E_N_T_ _A_N_D_ _S_K_I_P_ _I_F_ _Z_E_R_O_ 3.4.4
DSZ <@' displacement <,index'
=================
In-
0 0 0 1 1 @ dexDISPLACEMENT
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
This instruction will cause the effective address to be computed.
The word in this location is decremented by one and the result is
written back into the location. If the result of the decrementation
is zero then the next sequential instruction will be skipped.
\f
3_._5_ _ _ _ _ _ _ _D_a_t_a_ _T_r_a_n_s_f_e_r_ _O_p_e_r_a_t_i_o_n_ 3.5
Data transfer operations always involve one of the available ac-
cumulators as terminal point for the operation (except when the
Direct Memory Access feature is utilized, see section 4.5). There
are however slight differences in the instruction format depen-
ding on whether the data transfer is internal (between main memo-
ry and accumulator) or external (between peripheral device and
accumulator). This section will only describe the instructions
pertaining to internal data transfers, while external transfer
will be dealt with in chapter 4: Input/Output.
Internal data transfer instructions use the following lay-out:
OP In-
0 codeAC @dexDISPLACEMENT
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
In this format bit 0 is 0, bits 1 and 2 contain the operation
code, bits 3 and 4 specify the accumulator to be used in the ope-
ration, and bits 5 to 15 contain the memory address as outlined
in section 2.5.1.
The symbol @ - placed anywhere in the effective address operand
string - will set the indirect bit to 1.
The index bits (bits 6 and 7) are set by a comma followed by one
of the digits 0 to 3 as the last operand of the operand string.
If no index is coded, the index bits are automatically set to 00.
The index bits can be set to 01 by using the character "period"
(.) at the beginning of the effective address operand string.
When the period is used it is followed by either a plus or a
minus sign and the appropriate displacement, e.g. ".+7" or ".-2".
The internal data transfer subset comprises the following two
instructions: LOAD ACCUMULATOR and STORE ACCUMULATOR.
\f
3_._5_._1_ _ _ _ _ _L_O_A_D_ _A_C_C_U_M_U_L_A_T_O_R_ 3.5.1
LDA ac,<@'displacement <,index'
== =================
In-
0 0 1 AC @ dexDISPLACEMENT
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
This instruction will cause the effective address to be computed
and the word contained in this location will then be retrieved
and subsequently written into the accumulator specified. The pre-
vious contents of that accumulator will be lost; the contents of
the location addressed will remain unchanged.
3_._5_._2_ _ _ _ _ _S_T_O_R_E_ _A_C_C_U_M_U_L_A_T_O_R_ 3.5.2
STA ac,<@'displacement <,index'
== ====================
In-
0 1 0 AC @ dexDISPLACEMENT
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
This instruction will cause the effective address to be computed
and the word presently located in the accumulator specified will
be retrieved and subsequently written into the main memory loca-
tion indicated by the result of the effective address calcula-
tion. The previous contents of this location will be lost; the
contents of the accumulator will remain unchanged.
\f
3_._6_ _ _ _ _ _ _ _I_n_t_e_g_e_r_ _A_r_i_t_h_m_e_t_i_c_ _a_n_d_ _L_o_g_i_c_a_l_ _O_p_e_r_a_t_i_o_n_s_ 3.6
Arithmetical and logical operations always use two of the avail-
able accumulators - usually designated "source accumulator" and
"destination accumulator" - to hold the operands involved. In-
structions in this subset have the following lay-out:
OP
1 ACS ACD Code SH C # SKIP
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
In this format bit 0 is 1, bits 1 and 2 specify the source accu-
mulator, bits 3 and 4 specify the destination accumulator, bits 5
to 7 contain the operation code, bits 8 and 9 specify the action
of the shifter, see fig. 3.6, bits 10 and 11 specify the initi-
alizing value of the carry, bit 12 indicates whether the result
of the operation must be loaded into the destination accumulator
or not, and finally bits 13 to 15 specify the skip test.
All operations initiated by instructions in this subset are per-
formed by way of an arithmetic unit whose logical organisation is
illustrated in fig. 3.6:
\f
ORGANIZATION OF ARITHMETIC UNIT
17 BITS
FUNCTIONSHIFTER
GENERATOR
17 BITS
1 BIT ACS ACD
16 16SKIP SENSOR
CARRY BITSBITS
Initializer
CARRY Accumulators
1 ACD17
BIT 16 BITS BITS
LOAD NO LOAD
Figur 3.6
The instruction specifies two accumulators containing the two
operands which will have to be supplied to the function generator.
This then performs the desired function as specified in bits 5 to
7 of the instruction. In addition to the actual function result
the function generator will produce a carry bit, whose value de-
pends on three quantities: an initial value specified by the in-
struction, the input operands themselves and the function actual-
ly performed.
The initial value of the carry bit may be derived from a previous
value of same or a completely independent value may be specified
via the instruction.
The 17-bit output from the function generator - made up of the
carry bit and the 16-bit function result - is then placed in the
shifter. Here the 17-bit result can be shifted one place either
to the right or to the left; alternatively the two 8-bit halves
of the function result can be swapped without affecting the car-
ry bit. The output from the shifter can then be tested for a
skip. The skip sensor will test whether the carry bit or the
function result itself is equal to zero or not.
\f
After the skip test the output may be loaded into the carry bit
and the destination accumulator respectively. Note however that
loading is not an absolute necessity.
The diagrams below illustrate the possible actions taken by the
shifter:
Optional Shifter
Mnemonic Operation
L All bits are moved one position to the left.
Hereby bit 0 is shifted into the carry position
while the carry bit is shifted into bit 15.
C 0-15
R All bits are moved one position to the right.
Hereby bit 15 is shifted into the carry position
while the carry bit is shifted into bit 0.
C 0-15
S The two halves of the 16-bit function result
change places bit by bit. The carry bit is not
affected by this operation.
C 0-7 8-15
C 0-7 8-15
\f
The following table lists the various options available for use
with the instruction format embodying the two-accumulator
multiple operation. The characters in the column headed "Class
Abbreviation" refer to the specific fields of the instruction
format as given at the beginning of this section. The characters
in the column headed "Optional Mnemonics" are those which may
optionally by appended to the main mnemonic. The binary numbers
in the column headed "Bit Settings" show the actual bits which
will appear in the appropriate field of the instruction word.
The comments in the column headed "Operation" describe the re-
sultant action of the option in question.
\f
Class Optional Bit
A_b_b_r_e_v_i_a_t_i_o_n_ _ _ _M_n_e_m_o_n_i_c_ _ _ _S_e_t_t_i_n_g_s_ _ _ _ _ _ _ _ _ _O_p_e_r_a_t_i_o_n_ ____________
C 00 Do not initialize the carry
(Carry bit.
Preset) Z 01 Initialize the carry bit to
0.
O 10 Initialize the carry bit to
1.
C 11 Initialize the carry bit to
the complement of its
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _p_r_e_s_e_n_t_ _v_a_l_u_e_._ _ _ ___________
SH 00 Leave the result of the
(Shifter) arithmetic or logical
operation unaffected.
L 01 Combine the carry and the
16-bit result into a 17-bit
number and shift it one bit
to the left.
R 10 Combine the carry and the
16-bit result into a 17-bit
number and shift it one bit
to the right.
S 11 Exchange the two 8-bit
halves of the 16-bit result
without affecting the carry
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _b_i_t_._ _______________________
# 0 Load the result of the
(Load) shift operation into ACD.
# 1 Do not load the result of
the shift operation into
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _A_C_D_._ _______________________\f
SKIP 000 Never skip.
SKP 001 Always skip.
SZC 010 Skip if carry equal to
zero.
SNC 011 Skif if carry not equal to
zero.
SZR 100 Skip if result equal to
zero.
SNR 101 Skip if result not equal to
zero.
SEZ 110 Skip if either carry or
result equal to zero.
SBN 111 Skip if both carry and
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _r_e_s_u_l_t_ _n_o_t_ _e_q_u_a_l_ _t_o_ _z_e_r_o_._
The instruction subset pertaining to integer arithmetic and logi-
cal operations include the following instructions: ADD, SUBTRACT,
NEGATE, ADD COMPLEMENT, INCREMENT, and MOVE, all of which refer
to arithmetical operations, and the logical operations COMPLEMENT
and AND.
Integer arithmetic is performed in fixed point mode on 16-bit,
signed or unsigned operands in the accumulators. Logical opera-
tions are performed on 16-bit unstructured binary operands in the
accumulators.
\f
3_._6_._1_ _ _ _ _ _A_D_D_ 3.6.1
ADD<c'<sh'<#'acs,acd<,skip'
= == === === ====
1 ACS ACS 1 1 0 SH C # SKIP
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
This instruction will first initialize the carry bit to the spe-
cified value. Then the number in ACS is added to the number in
ACD and the result is placed in the shifter. If the addition pro-
duces a carry = 1 out of the high-order bit (bit 0) the carry bit
will be complemented, i.e. this will happen if the sum of the two
numbers being added is greater than 65,535dD10uU.
The specified shift operation is then performed and the result of
this is placed in ACD provided that the load bit of the instruc-
tion has been set to 0. If the skip test demanded results in the
condition being true the next sequential instruction will be
skipped.
\f
3_._6_._2_ _ _ _ _ _S_U_B_T_R_A_C_T_ 3.6.2
SUB<c'<sh'<#'acs,acd<,skip'
= == === === ====
1 ACS ACS 1 0 1 SH C # SKIP
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
This instruction will first initialize the carry bit to the
specified value. Then the number in ACS is subtracted from the
number in ACD (the actual operation being performed by first
forming the two>s complement of the number in ACS and then adding
this to the number in ACD) and the result of the subtraction pla-
ced in the shifter. If the operation produces a carry = 1 out of
the high-order bit (bit 0) the carry bit will be complemented,
i.e. this will happen if the number in ACS is less than or equal
to the number in ACD. The specified shift operation is performed
and the result of this is placed in ACD provided that the load
bit of the instruction has been set to 0. If the skip test de-
manded results in the condition being true the next sequential
instruction will be skipped.
\f
3_._6_._3_ _ _ _ _ _N_E_G_A_T_E_ 3.6.3
NEG<c'<sh'<#'acs,acd<,skip,
= == === === ====
1 ACS ACD 0 0 1 SH C #SKIP
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
This instruction will first initialize the carry bit to the spe-
cified value. Then the two>s complement of the number in ACS will
be formed and placed in the shifter. If the complementation pro-
duces a carry out of the high-order bit (bit 0) the carry bit
will be complemented, i.e. this happens if the number in ACS is
zero. The specified shift operation is performed and the result
of this is placed in ACD provided that the load bit of the in-
struction has been set to 0. If the skip test demanded results in
the condition being true the next sequential instruction will be
skipped.
\f
3_._6_._4_ _ _ _ _ _A_D_D_ _C_O_M_P_L_E_M_E_N_T_ 3.6.4
ADC<c'<sh'<#'acs,acd<,skip'
= == === === ====
1 ACS ACD 1 0 0 SH C # SKIP
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
This instruction will first initialize the carry bit to the spe-
cified value. Then the logical complement of the number in ACS is
added to the number in ACD and the result is placed in the shift-
er. If the addition produces a carry out of the highorder bit
(bit 0) the carry bit will be complemented, i.e. this happens if
the number in ACS is less than the number in ACD. The specified
shift operation is performed and the result is placed in ACD pro-
vided that the load bit of the instruction has been set to 0. If
the skip test demanded results in the condition being true the
next sequential instruction will be skipped.
3_._6_._5_ _ _ _ _ _M_O_V_E_ 3.6.5
MOV<c'<sh'<#'acs,acd<,skip'
= == === === ====
1 ACS ACD 0 1 0 SH C # SKIP
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
This instruction will first initialize the carry bit to the spe-
cified value. Then the number in ACS is placed in the shifter,
the specified shift operation is performed and the result of this
is placed in ACD provided that the load bit of the instruction
has been set to 0. If the skip test demanded results in the test
condition being true the next sequential instruction will be
skipped.
\f
3_._6_._6_ _ _ _ _ _I_N_C_R_E_M_E_N_T_ 3.6.6
INC<c'<sh'<#'acs,acd<,skip'
= == === === ====
1 ACS ACD 0 1 1 SH C # SKIP
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
This instruction will first initialize the carry bit to the spe-
cified value. Then the number in ACS is incremented by one and
the result is placed in the shifter. If the incrementation pro-
duces a carry out of the high-order bit (bit 0) the carry bit
will be complemented, i.e. this will happen if the number in ACS
is 177777dD8uU. The specified shift operation is performed and the
result of this placed in ACD provides that the load bit of the
instruction has been set to 0. If the skip test demanded results
in the test condition being true the next sequential instruction
will be skipped.
3_._6_._7_ _ _ _ _ _C_O_M_P_L_E_M_E_N_T_ 3.6.7
COM<c'<sh'<#z,cs,acd<,skip'
= == === === ====
1 ACS ACD 0 0 0 SH C # SKIP
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
This instruction will first initialize the carry bit to the spe-
cified value. The logical complement of the binary quantity in
ACS is formed and placed in the shifter. The specified shift
operation is performed and the result of this is placed in ACD
provided that the load bit of the instruction has been set to 0.
If the skip test demanded results in the test condition being
true the next sequential instruction will be skipped.
\f
3_._6_._8_ _ _ _ _ _A_N_D_ 3.6.8
AND<c'<sh'<#'acs,acd<,skip'
= == === === ====
1 ACS ACD 1 1 1 SH C # SKIP
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
This instruction will first initialize the carry bit to the spe-
cified value. Then the logical "and" of the two binary quantities
in ACS and ACD is formed and placed in the shifter. Each bit pla-
ced in the shifter is 1 if and only if the two corresponding bits
in ACS and ACD respectively are both 1; in all other cases the
result bit placed in the shifter will be 0. The specified shift
operation is performed and the result of this is placed in ACD
provided that the load bit of the instruction has been set to 0.
If the skip test demanded results in the test condition being
true the next sequential instruction will be skipped.
3_._6_._9_ _ _ _ _ _E_x_a_m_p_l_e_s_ 3.6.9
To show how these different instructions may be used under vari-
ous circumstances consider the following examples:
3_._6_._9_._1_ _ _ _D_e_c_i_d_i_n_g_ _t_h_e_ _S_i_g_n_ _o_f_ _a_ _N_u_m_b_e_r_ 3.6.9.1
To determine whether an integer contained in an accumulator is
positive or negative can be done in several ways, but the most
efficient will be to use the MOVE instruction and thus the in-
herent power of the two-accumulator multiple-operation format.
\f
Assume that the number in question is contained in AC3. Use of
the instruction:
MOVL#3,3,SZC
will place the number in the shifter and shift the number one
place to the left. This will place the original sign bit in the
carry bit position and the skip test can then be used to deter-
mine whether this bit is 0 or 1. The two following instructions
in the program must of course be chosen in such a way that the
appropriate action is taken in either case.
Note that by using the optional mnemonic # the load bit is set
to 1; thus the output from the shifter will not be loaded back
into AC3 and the original number contained herein will therefore
be retained for further use.
3_._6_._9_._2_ _ _ _D_i_v_i_d_i_n_g_ _a_ _N_u_m_b_e_r_ _b_y_ _a_ _P_o_w_e_r_ _o_f_ _T_w_o_ 3.6.9.2
To divide a binary number by 2 is simply equivalent to shifting
all digits one position to the right (compare with decimal nota-
tion where division with 10 - i.e. the base - is readily acknow-
ledged to be produced by this expedient). The fact that the
rightmost bit of the original number will be discarded after the
shift means that the result of the division will be rounded down
to the nearest integer.
The division can be performed simply and efficiently by employing
the MOVE instruction as follows:
MOVL# 2,2,SZC
MOVOR 2,2,SKP
MOVZR 2,2,SKP
MOVOR 2,2,SKP
MOVOR 2,2
\f
The number being divided is supposed to be placed in AC2. The
first instruction is simply a repetition of the previous example
of deciding the sign of the number. If the number is positive the
second instruction will be skipped and operations will continue
with the third instruction. This will shift the number one place
to the right thus resulting in the division by 2, while at the
same time initializing the carry bit to 0, so that when this bit
is shifted into the sign bit position the number will remain po-
sitive. Note that after division the number is now loaded into AC2
so that this accumulator now holds the result of the division.
Finally the fourth instruction is skipped and the fifth repeats
the division once more - following which there is no further skip.
The repetition means that the end effect will be that the original
number has been divided by four. If the number is negative exactly
the same sequence of operations are performed with the appropriate
alterations to cope with the negative sign - the instructions now
in force being the second and fourth.
\f
3_._6_._9_._3_ _ _ _C_h_a_n_g_i_n_g_ _L_o_c_a_t_i_o_n_s_ _S_i_m_u_l_t_a_n_e_o_u_s_l_y_ _I_n_v_e_r_t_i_n_g_ _t_h_e_ _O_r_d_e_r_ 3.6.9.3
Assume that a block of 30dD10uU words, which at present occupy
locations 2000dD8uU to 2035dD8uU, must be moved to locations 5150dD8uU
to 5205Dd8uU in such a way that the order of the individual words
in the block will be inverted.
To do this a section of a program is set up which will autoin-
crement through one set of locations, autodecrement through the
other set and decrement a control count to determine, when the
block transfer has been completed. The program section listed
below wil accomplish this:
LDA 0,CNT ;comment: set up
STA 0,21 ; autoincrement location
LDA 0,CNT + 1 ; set up
STA 0,35 ; autodecrement location
LOOP: LDA 0, @ 21 ; get a word
STA 0, @ 35 ; store it
DSZ CNT + 2 ; count down word count
JMP LOOP ; jumb back for next word,
skip to here when count
is zero
.
.
.
CNT: 001777 ; 1 before source block
+ 1: 005206 ; 1 after destinationblock
+ 2: 36 ; word count
\f
4_._ _ _ _ _ _ _ _ _I_N_P_U_T_/_O_U_T_P_U_T_ 4.
4_._1_ _ _ _ _ _ _ _I_n_t_r_o_d_u_c_t_i_o_n_ 4.1
All useful information processing to be performed by the computer
depends on the existence of some means of communication between
the CPU and the outside world. For this purpose the CPU is con-
nected to a number of peripheral or Input/Output devices the ac-
tual type, size, and number of which is completely independent of
the internal logical structure of CPU.
The program must of course contain instructions designed to
handle the external data transfer operations; these are all nor-
mally termed Input/Output - usually shortened to I/O - operations
and allow for the transfer of information in units of bits,
bytes, words, or groups of words called "records" depending on
the device in use.
All instructions in the I/O subset are basically similar to the
previously mentioned internal transfer instructions (section 3.5)
except for the fact that addressing as such is not relevant; on
the other hand the CPU must have information as to which periph-
eral unit is to be employed for the actual data transfer and
secondly there must be instituted some means of allocating the
necessary time for the transfer.
To handle the control of peripheral devices - of which there may
be several units of widely differing types connected to the CPU
at any given time - the RC3803 CPU is equipped with a six-line
device selection network. To initiate operation on a specific de-
vice a signal must be transmitted on the selection network, but
each individual peripheral device will only respond to this sig-
nal if it is identical to the device>s own device code. The de-
vice code is a six-bit integer number corresponding to the lines
in the selection network.
\f
4_._2_ _ _ _ _ _ _ _O_p_e_r_a_t_i_o_n_ _o_f_ _I_/_O_ _D_e_v_i_c_e_s_ 4.2
In general all operations on individual I/O devices are handled
by manipulation of two control bits which are called the "Busy"
and "Done" flags respectively. If the Busy and Done flags are
both 0 the device is idle and cannot perform any operation. To
initiate operation on a device the Busy flag must be set to 1,
and if the Done flag is not already 0 it must be set to this va-
lue. When the device has finished its operation it will itself
set the Busy flag to 0 and the Done flag to 1. (If the Busy and
Done flags are both - erroneously - set to 1 the situation is
meaningless and will produce unpredictable effects.)
Thus to initiate operation on a particular device the program
must first determine whether that device is currently performing
an operation or not, i.e. it must check the state of the Busy
and Done flags. If the Busy and Done flags are 0 and 1 respective-
ly, the program will be able to start the operation by setting
Busy to 1 and Done to 0 as described above. When the operation
has been completed the device will reset the two flags and will
thus be available for another operation whenever necessary.
There are two ways in which the program can test the state of the
Busy and Done flags. One is to use the instruction I/O SKIP (cf.
section 4.6.7), the other is to employ the Interrupt System which
is standard on the RC3803.
4_._3_ _ _ _ _ _ _ _I_n_t_e_r_r_u_p_t_ _S_y_s_t_e_m_ 4.3
The interrupt system consists of an interrupt request line to
which each I/O device is connected, an Interrupt On flag in the
CPU and a 16-bit interrupt priority mask.
\f
An interrupt is initiated by an I/O device at the time when it
completes its operation and resets the Busy and Done flags; si-
multaneously the device places an interrupt request on the inter-
rupt request line provided that the bit in the interrupt priority
mask, which corresponds to the priority level on the device, is 0
(cf. section 4.4). If that particular bit of the mask is 1, the
device will still set the flags, but it will not place an inter-
rupt request on the line.
The Interrupt On flag controls the state of the interrupt system
in the sense that if the Interrupt On flag is set to 1 the CPU
will respond to the process interrupt requests; if the Interrupt
On flag is set to 0 it will not do so but will simply go on with
normal sequential execution of the program.
The CPU responds to an interrupt request by immediately setting
the Interrupt On flag to 0 so that no further interrupts can in-
terfere with the interrupt service routine. The CPU then places
the program counter in memory location 0 and executes a "jump
indirect" to memory location 1 on the underlying assumption, that
this location contains the address - direct or indirect - of the
interrupt service routine.
When control has been transferred to the interrupt service rou-
tine this routine will first ensure, that the contents of accumu-
lators to be used by the routine are saved, so that these values
again can be made available when control is eventually returned
to the program proper. The same applies to the carry bit. When
this has been accomplished the routine will determine which de-
vice requested the interrupt; following this it will proceed with
the operations relevant to the servicing of the interrupt.
The determination of which device is in need of service can be
accomplished through either the I/O SKIP instruction or the
INTERRUPT ACKNOWLEDGE instruction. This last-mentioned instruc-
tion returns the six-bit device code of the device requesting the
interrupt, thereby initiating operation of that particular device.
If more than one device has requested an interrupt, the code re-
turned will be that belonging to the device which is physically
closest to the CPU on the I/O bus.
\f
When the I/O device has completed its operation, the interrupt
service routine will restore all previously saved values, set
the Interrupt On flag to 1 and finally return control to the in-
terrupted program. For this purpose the instruction, that will
set the Interrupt On flag to 1, will allow the processor to exe-
cute one further instruction before the next interrupt can take
place. This extra instruction must be the instruction which re-
turns control to the main program; otherwise the interrupt ser-
vice routine may go into a loop. However, since the updated value
of the program counter - as related above - was placed in loca-
tion 0 upon responding to the interrupt request, the final in-
struction in the servicing routine can simply be the instruction
"JMP @ 0"; this will transfer control to the main program as in-
tended.
4_._4_ _ _ _ _ _ _ _P_r_i_o_r_i_t_y_ _I_n_t_e_r_r_u_p_t_s_ 4.4
If the Interrupt On flag remains 0 throughout the interrupt ser-
vice routine - as assumed above - all further interrupts will be
ignored and there is thus only one level of device priority. This
level of priority - i.e. which devices will be able to secure an
interrupt - will be determined either by the order in which I/O
SKIP instructions are issued or - if the INTERRUPT ACKNOWLEDGE
instruction is used - by the relative physical locations on the
I/O bus of the various devices.
If the complete computer installation embodies I/O devices of
widely differing speeds of operation - such as for example a
teletypewriter versus a fixed head disc - it can be convenient
for the programmer to set up a multi-level interrupt schedule;
this is accomplished by the use of the priority mask coupled
with the appropriate instructions.
\f
The priority mask is one 16-bit word to which the individual I/O
devices are connected in such a way, that each I/O device is as-
signed to one specific bit of the mask. The standard mask bit
assignment are arranged in such a manner, that devices having
roughly the same speed of operation will correspond to the same
bit in the mask and will therefore be on the same priority level.
(Appendix A of this manual contains - in addition to the device
codes - the standard RC mask bit assignments). Although this
standard is relevant for most purposes it is not necessary to
comply with it, and the programmer is completely free to define
his own levels of priority for the individual devices by using
the MASK OUT instruction (cf. section 4.7.5). Whenever a bit in
the priority mask is set to 1 all devices in the priority level
corresponding to that particular bit will be prevented from re-
questing an interrupt. In addition all pending interrupt requests
from devices in that priority level will be ignored.
When multi-level priority handling is implemented, the interrupt
service routine must be written in such a way that it may itself
be interrupted without damage. This is done by arranging for the
main interrupt routine to save the state of the machine, - the
contents of the four accumulators, the carry bit, and the return
address - whenever it takes over control.
The information concerned must be stored in separate locations
for each time the interrupt handler is entered, so that a higher
level of interrupt will not overlay the return information cor-
responding to a lower priority level. Having thus saved the
necessary return information the main interrupt routine must
determine which device has requested service and then transfer
control to the correct interrupt handling routine. The actual
transfer is effected in the same way as for the previously de-
scribed single-level interrupt handler.
When the correct service routine has received control it will
save the current priority mask, establish the new priority mask
and activate the interrupt system. When it has finished servi-
cing the I/O device, the routine will de-activate the interrupt
system, reset the priority mask to its original form, restore the
state of the machine, again activate the interrupt system, and
finally return control to the interrupted program.
\f
4_._5_ _ _ _ _ _ _ _D_i_r_e_c_t_ _M_e_m_o_r_y_ _A_c_c_e_s_s_ _D_a_t_a_ _C_h_a_n_n_e_l_ 4.5
The handling of data transfers under program control as described
above requires an interrupt plus the execution of several in-
structions for each word transferred and therefore occupies valu-
able time on the processor.
To avoid this and at the same time to obtain higher transfer ra-
tes the RC3803 CPU is equipped with a separate data channel
through which an I/O device - at its own request - can gain di-
rect access to main memory.
When an I/O device is ready to send or to receive data it re-
quests access to memory via the data channel. All such requests
are synchronized by the CPU at the beginning of each memory
cycle. The CPU will then pause at specified points during the
execution of an instruction; at each pause it will accept all
previously synchronized requests in which instance a word will
be transferred directly via the channel from the device to memory
or vice versa without interference with the program.
All requests are honoured in relation to the relative physical
positions on the I/O bus of the different requesting devices;
that is: the device being physically closest to the CPU is ser-
viced first, then the next closest device and so on until all
requests have been processed. As synchronization of new requests
occur continuously even while previous requests are being atten-
ded to, a device can in effect saturate the channel if it re-
quests transfer continually. All devices further out on the bus
cannot gain access to the channel until the transfers involving
the closer device have been processed, although of course devices
which are closer still on the bus will not be affected.
In addition to the pause intervals during the execution of an
instruction data channel request will be handled on completion
of an instruction. At this point furthermore, all outstanding
I/O interrupt requests will be accepted. When all such data
transfers have been accomplished the CPU will continue with nor-
mal sequential operation.
\f
4_._6_ _ _ _ _ _ _ _I_/_O_ _I_n_s_t_r_u_c_t_i_o_n_s_ 4.6
All I/O instructions use the format given below:
0 1 1 AC OP Con-
CODE trol DEVICE CODE
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
In this format bits 0, 1, and 2 are 011, bits 3 and 4 specify the
accumulator involved, bits 5 to 7 contain the operation code,
bits 8 and 9 control the Busy and Done flags in the device, and
bits 10 to 15 contain the device code. The six bits provided for
the device code will define 64dD10uU unique devices, but thetotal
number of separate devices which can be employed simultaneously
on any given installation will be slightly lower than this as
some of the available device codes are reserved for the CPU and
certain processor features. Of the remaining codes some have been
assigned to specific devices by Regnecentralen. A complete list-
ing of device codes appear in Appendix A.
The subset of I/O instructions has a number of options that can
be obtained by appending the appropriate optional mnemonic to
the standard mnemonic of the instruction. These optional mne-
monics are listed in the table below; the column headings corre-
spond to those given in section 3.6.
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
Class Optional Bit
A_b_b_r_e_v_i_a_t_i_o_n_ _ _ _M_n_e_m_o_n_i_c_ _ _ _S_e_t_t_i_n_g_s_ _ _ _ _ _ _ _ _ _O_p_e_r_a_t_i_o_n_ _ _ _ _ _ _ _ _ _ _ _ _
F 00 Does not affect the Busy
(Flags) and Done flags.
S 01 Start the device by set-
ting Busy = 1 and Done = 0.
C 10 Idle the device by setting
both Busy and Done to 0.
P 11 Pulse the special in-out
bus control line. The
effect - if any - depends
on the actual device.
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
\f
T BN 00 Tests for Busy = 1.
(Tests) BZ 01 Tests for Busy = 0.
DN 10 Tests for Done = 1.
DZ 11 Tests for Done = 0.
________________________________________________________________
The I/O instruction subset contains the following instructions:
DATA IN A, DATA IN B, DATA IN C, DATA OUT A, DATA OUT B, DATA
OUT C, I/O SKIP, and NO I/O TRANSFER.
4_._6_._1_ _ _ _ _ _D_A_T_A_ _I_N_ _A_ 4.6.1
DIA<f' ac,device
= == ======
0 1 1 AC 0 0 1 F DEVICE CODE
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
This instruction will place the contents of the A input buffer on
the specified device in the AC specified in the instruction.
After the data transfer has been completed the Busy and Done
flags are set as specified by "f".
The number of data bits moved depends on the size of the buffer
and the mode of operation of the device selected. Bits in the AC
not receiving any data are set to 0.
\f
4_._6_._2_ _ _ _ _ _D_A_T_A_ _I_N_ _B_ 4.6.2
DIB<f' ac,device
= == ======
0 1 1 AC 0 1 1 F DEVICE CODE
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
This instruction will have exactly the same effect as the one
previously described - except that it will utilize the B buffer
of the peripheral device.
4_._6_._3_ _ _ _ _ _D_A_T_A_ _I_N_ _C_ 4.6.3
DIC<f' ac,device
= == ======
0 1 1 AC 1 0 1 F DEVICE CODE
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
This instruction will have exactly the same effect as the two
previously described - except that it will utilize the C buffer
of the peripheral device.
\f
4_._6_._4_ _ _ _ _ _D_A_T_A_ _O_U_T_ _A_ 4.6.4
DOA<f' ac,device
= == ======
0 1 1 AC 0 1 0 F DEVICE CODE
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
This instruction will place the contents of the specified AC in
the A output buffer of the selected device. After the data
transfer has been completed, the Busy and Done flags are set as
specified by "f". The contents of the AC will remain unaltered.
The number of data bits moved will depend on the size of the
buffer and on the mode of operation of the device.
4_._6_._5_ _ _ _ _ _D_A_T_A_ _O_U_T_ _B_ 4.6.5
DOB<f' ac,device
= == ======
0 1 1 AC 1 0 0 F DEVICE CODE
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
This instruction will have exactly the same effect as the one
previously described - except that it will utilize the B buffer
of the peripheral device.
\f
4_._6_._6_ _ _ _ _ _D_A_T_A_ _O_U_T_ _C_ 4.6.6
DOC<f' ac,device
= == ======
0 1 1 AC 1 1 0 F DEVICE CODE
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
This instruction will have exactly the same effect as the two
previously described - except that it will utilize the C buffer
of the peripheral device.
4_._6_._7_ _ _ _ _ _I_/_O_ _S_K_I_P_ 4.6.7
SKP<t' device
= ======
0 1 1 0 0 1 1 1 T DEVICE CODE
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
This instruction will test the state of the Busy and Done flags
and will thus enable the programmer to decide on actions to be
taken in consequence of the values of these flags, i.e. whether
a device is in need of service from the interrupt system or not.
The test performed depends on the value of bits 8 and 9 of the
instruction and is selected by appending the appropriate op-
tional mnemonic to the instruction according to the table given
in section 4.6. If the test condition specified by "T" is true
the next sequential instruction will be skipped.
\f
4_._6_._8_ _ _ _ _ _N_O_ _I_/_O_ _T_R_A_N_S_F_E_R_ 4.6.8
NIO <f' device
= ======
0 1 1 0 0 0 0 0 F DEVICE CODE
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
This instruction will set the Busy and Done flags in the selec-
ted device according to the control code specified by "F".
4_._7_ _ _ _ _ _ _ _C_e_n_t_r_a_l_ _P_r_o_c_e_s_s_o_r_ _F_u_n_c_t_i_o_n_s_ 4.7
I/O instructions with a device code of 77Dd8uU will perform a number
of special functions rather than control a specific peripheral
device. With the exception of the I/O SKIP instruction all I/O in-
structions having a device code of 77dD8uU will use bits 8 and 9 of
the instruction format to control the state of the Interrupt On
flag. The I/O SKIP instruction - when used with a device code of
77dD8uU - will cause a test of the state of the Interrupt On flag.
(Alternatively it may be used to test the state of the Power Fail
flag; see section 5.2). The optional mnemonics for these special
instructions are the same as for normal I/O instructions. The
table below lists the resulting actions for these instructions
when used with the special device code 77dD8uU.
\f
_ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ _ _ __ __ ___
Class Optional Bit
A_b_b_r_e_v_i_a_t_i_o_n_ _ _ _M_n_e_m_o_n_i_c_ _ _ _S_e_t_t_i_n_g_s_ _ _ _ _ _ _ _ _ _O_p_e_r_a_t_i_o_n_ ____________
F 00 Does not affect the state
(Flags) of the Interrupt On flag.
S 01 Set the Interrupt On flag
to 1.
C 10 Set the Interrupt On flag
to 0.
P 11 Does not affect the state
of the Interrupt On flag.
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ ___________________________
T BN 00 Tests for Interrupt On = 1.
(Tests) BZ 01 Tests for Interrupt On = 0.
DN 10 Tests for Power Fail = 1.
DZ 11 Tests for Power Fail = 0.
________________________________________________________________
In addition to use of the ordinary I/O instructions with the spe-
cial device code 77dD8uU, there is a subset of special instructions
for processor functions which contains the following instruc-
tions: INTERRUPT ENABLE, INTERRUPT DISABLE, READ SWITCHES,
INTERRUPT ACKNOWLEDGE, MASK OUT, I/O RESET, HALT, and CPU SKIP.
\f
4_._7_._1_ _ _ _ _ _I_N_T_E_R_R_U_P_T_ _E_N_A_B_L_E_ 4.7.1
INTEN
NIOS CPU
0 1 1 0 0 0 0 0 0 1 1 1 1 1 1 1
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
This set of instructions will set the Interrupt On flag to 1. If
the state of the Interrupt On flag is hereby changed, the CPU
will allow one more instruction to be executed before the first
I/O interrupt can occur.
4.7.2
4_._7_._2_ _ _ _ _ _I_N_T_E_R_R_U_P_T_ _D_I_S_A_B_L_E_
INTDS
NIOC CPU
0 1 1 0 0 0 0 0 1 0 1 1 1 1 1 1
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
This set of instructions will set the Interrupt On flag to 0.
\f
4_._7_._3_ _ _ _ _ _R_E_A_D_ _S_W_I_T_C_H_E_S_ 4.7.3
READS ac (F = 00)
==
DIA <f' ac,CPU
= ==
0 1 1 AC 0 0 1 F 1 1 1 1 1 1
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
This set of instructions will place the current setting of the
data switches on either the Diagnostic Front Panel (if connected)
or the front frame of the CPU-board in the AC specified in the
instructions. After the transfer has been completed, the Interrupt
On flag is set according to the control code specified by "F".
4_._7_._4_ _ _ _ _ _I_N_T_E_R_R_U_P_T_ _A_C_K_N_O_W_L_E_D_G_E_ 4.7.4
INTA ac (F = 00)
==
DIB <f' ac,CPU
= ==
0 1 1 AC 0 1 1 F 1 1 1 1 1 1
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
This set of instructions will cause the six-bit device code of
that device, which is physically closest to the CPU on the I/O
bus, to be placed in bits 10 to 15 of the AC specified in the
instructions. Bits 0 to 9 of the AC involved will be set to 0.
After the transfer has been completed the Interrupt On flag is
set according to the control code specified by "F".
\f
4_._7_._5_ _ _ _ _ _M_A_S_K_ _O_U_T_ 4.7.5
MSKO ac (F = 00)
==
DOB <f' ac,CPU
= ==
0 1 1 AC 1 0 0 F 1 1 1 1 1 1
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
This set of instructions will place the contents of the AC speci-
fied in the priority mask. After the transfer has been completed,
the Interrupt On flag is set according to the control code speci-
fied by "F". The contents of the AC remain unaltered.
N_O_T_E_:
The digit 1 in any bit position disables interrupt re-
quests from any peripheral device in the corresponding
priority level.
4_._7_._6_ _ _ _ _ _I_/_O_ _R_E_S_E_T_ 4.7.6
IORST (F = 10)
DIC <f' ac,CPU
= ==
0 1 1 AC 1 0 1 F 1 1 1 1 1 1
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
This set of instructions will cause the Busy and Done flags in
all I/O devices to be set to 0; simultaneously all bits in the
16-bit priority mask are set to 0. The Interrupt On flag is set
according to the control code specified by "F".
\f
4_._7_._7_ _ _ _ _ _H_A_L_T_ 4.7.7
HALT (F = 00)
DOC <f' ac,CPU
= ==
0 1 1 AC 1 1 0 F 1 1 1 1 1 1
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
This set of instructions will set the Interrupt On flag accord-
ing to the control code specified by "F". Following this the pro-
cessor is stopped.
4_._7_._8_ _ _ _ _ _C_P_U_ _S_K_I_P_ 4.7.8
SKP <t', CPU
=
0 1 1 0 0 1 1 1 T 1 1 1 1 1 1
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
This instruction will cause the Interrupt On flag or the Power
Fail flag to be tested depending on the control code specified
by "T". If the test condition is true the next sequential in-
struction will be skipped.
\f
F_5_._ _ _ _ _ _ _ _ _P_R_O_C_E_S_S_O_R_ _F_E_A_T_U_R_E_S_ 5.
5_._1_ _ _ _ _ _ _ _I_n_t_r_o_d_u_c_t_i_o_n_ 5.1
Features included in the RC3803 computer are a power monitor
which will handle automatic shut-down and restart in the event of
a failure of the power supply, a special CPU function allowing
memory to be extended beyond the 32K words> capacity, and an ex-
tended instruction set containing the time consumption routines
in the RC3600 software.
The extended instruction set covers a set of micro-programmed
monitor-procedures.
Each procedure is described in details using a pseudo-language
notation as explained below.
A micro-programmed monitor-procedure is in fact one instruction
possibly interrupted by interrupt or DMA-request.
When finished request the procedure is restarted, that is the
instruction is executed once again. If then terminated the next
instruction is executed as usual. This formalisme is described
using the pseudo-functions fetchnext and serverequest:
Fetchnext: The actual value of the instruction counter PC is
incremented and the next instruction is fetched
from the memory word addressed in PC.
Serverequest: The actual value of the instruction counter PC is
decremented and the request sevice is entered. When
finished the serviceroutine includes a call of
fetchnext, hereby initiating execution of the ac-
tual instruction once again. Please refer to sec-
tion 4.3 for more details.
The notation used in describing the implemented procedures and
the examples given are related to those given in the system manu-
al >MUS SYSTEM, Programming Guide, Rev. 1.00>, with the follow-
ing notice:
CUR = Current process description address.
PC = Program Counter (instruction counter). \f
5_._2_ _ _ _ _ _ _ _P_o_w_e_r_ _F_a_i_l_ 5.2
Core memory in the RC3803 computer is of magnetic type and in-
formation stored in it is therefore independent of power supply
and will be retained unaltered for a very considerable time in
event of the power supply being cut off. The same does not, how-
ever, apply to the accumulators, program counter, various flags,
etc. in the CPU; all values in these components will be indeter-
minate following a break in the supply of power. The Power Fail
feature provides the capability to overcome this difficulty.
In the event of an unexpected power failure the voltage will
rapidly decrease from its normal value to the value where the
processor automatically shuts down completely. There will however
be an interval of time - roughly one or two milliseconds -
between the initial drop-off of voltage and the actual shut-down.
The Power Fail circuit will sense the beginning reduction of
voltage, set the Power Fail flag and request an interrupt. The
interrupt service routine will then be able to utilize the inter-
val before shut-down to store the contents of the accumulators,
the carry bit, and the current priority mask in memory. In addi-
tion to this it will save memory location 0, where it will store
a jump instruction to the desired restart location and finally it
will execute a HALT. As one or two milliseconds is sufficient
time to execute up to 1500 instructions there is ample time to
perform the power fail routine.
When the power supply is again restored, the CPU will execute a
"JMP 0" instruction after an interval of 100 milliseconds. This
will effect a restart of the interrupted program.
The power fail feature has no device code and no interrupt dis-
able bit in the priority mask. Neither does it respond to the
INTERRUPT ACKNOWLEDGE instruction. The Power Fail flag can be
tested by means of the CPU SKIP instruction as described in sec-
tion 4.7.8.
\f
5_._3_ _ _ _ _ _ _ _M_E_M_O_R_Y_ _E_X_T_E_N_S_I_O_N_ 5.3
Normal memory capacity of the RC3803 computer is 32K words (64K
bytes). The Memory Extension feature provides the capability to
increase this capacity to 64K words (128K bytes).
To switch from running in normal configuration to running in ex-
tended memory configuration the following instruction must be ap-
plied:
DICP ac, 1
==
0 1 1 XX 1 0 1 1 1 0 0 0 0 0 1
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
X = DON>T CARE
This instruction will allow the CPU to utilize the extra block
of core memory and it will furthermore set the Memory Extension
flag to 1. For the instruction to have the desired effect the
switch 64K/128K BYTES on the front frame of the CPU-board must
be in the 128K BYTES position; otherwise the instruction is dum-
my.
The state of the Memory Extension flag can be tested with the I/O
SKIP instruction using the device code (001) reserved for the
Extended Memory (see Appendix A). The testing of the flag thus
follows through the instruction:
SKPDN 1
0 1 1 0 0 1 1 1 1 0 0 0 0 0 0 1
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
As usual with this instruction the next sequential instruction
will be skipped if the test condition is true, i.e. if the Memory
Extension flag is 1.
\f
If the 64K/128K BYTES switch on the front panel is returned to
the 64K BYTES position the Memory Extension flag is n_o_t_ automati-
cally set back to 0 (although the CPU no longer will be able to
utilize the extended memory block). To return the Memory Extension
flag to 0 an I/O RESET instruction must be used. The flag will
also be set to 0 following a power up.
The CPU can execute programs placed in all 128K bytes, because
Multi-level indirect addressing is disabled, when Memory Extension
is selected.
The Disc Controller is capable of writing data into and reading
data from the extended area of memory.
N_O_T_E_: It is important to be aware of the fact, that when
Memory Extension is applied the program counter will
continue from 77777dD8uU to 100000dD8uU in the course of
normal sequential operation.
5_._4_ _ _ _ _ _ _ _C_P_U_ _I_D_E_N_T_I_F_Y_ 5.4
IDFY ac
==
0 1 1 AC 0 0 1 0 0 0 0 0 0 1 0
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
This instruction loads a microprogram revision number (2 for
RC3803) into the accumulator selected in the AC-field.
5_._5_ _ _ _ _ _ _ _B_y_t_e_ _M_a_n_i_p_u_l_a_t_i_o_n_ 5.5
In addition to performing operations on structured and unstruc-
tured 16-bit quantities, the instruction set of the RC3803 allows
loading and storing of 8-bit bytes.
\f
5_._5_._1_ _ _ _ _ _L_O_A_D_ _B_Y_T_E_ 5.5.1
LDB
0 1 1 0 0 1 0 1 1 0 0 0 0 0 0 1
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
CALL: RETURN:
; AC0 - AC0(0:7):=0; AC0(8:15):= BYTE
; AC1 FROM BYTEADDRESS UNCHANGED
; AC2 - UNCHANGED
; AC3 - UNCHANGED
The 8-bit byte addressed by the byte pointer contained in AC1 is
placed in bits 8-15 of the AC0. Bits 0-7 of the AC0 are set to 0.
The contents of AC2 and AC3 remain unchanged.
The byte address in AC1 is a word address left shifted one and
with a one added in bit 15 if the byte addressed within the word
is placed in bit 8:15.
\f
5_._5_._2_ _ _ _ _ _S_T_O_R_E_ _B_Y_T_E_ 5.5.2
STB
0 1 1 0 0 1 1 0 1 0 0 0 0 0 0 1
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
CALL: RETURN:
; AC0 AC0(8:15):= BYTE UNCHANGED
; AC1 TO BYTEADDRESS UNCHANGED
; AC2 - UNCHANGED
; AC3 - UNCHANGED
Bits 8-15 of AC0 are placed in the byte addressed by the pointer
contained in AC1. Bits 0-7 of AC0 are don>t care and not affect-
ed.
The contents of AC2 and AC3 remain unchanged. Note that the re-
maining part of the word addressed is untouched.
The byte address in AC1 is a word address left shifted one and
with a one added in bit 15 if the byte addressed with the word
placed in bit 8:15.
\f
5_._6_ _ _ _ _ _ _ _B_Y_T_E_ _M_O_V_E_ 5.6
BMOVE
0 1 1 XX 1 0 1 0 0 0 0 0 0 1 0
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
X = DON>T CARE
CALL: RETURN:
; AC0 CONVERT ADDR. CONVERT ADDR
; AC1 FROM ADDR. FROM ADDR + BYTE COUNT + 1
; AC2 TO ADDR. TO ADDR + BYTE COUNT + 1
; AC3 BYTE COUNT ZERO
This instruction moves a byte string from the byte address speci-
fied in AC1 to the byte address specified in AC2. The number of
bytes to be moved is specified in AC3. If AC0 <' 0 the moved byte
is converted via a table addressed by AC0.
The byte addresses in AC1, AC2, and AC0, are word addresses
shifted one and with a one added in bit 15 if a right byte is ad-
dressed. \f
The instruction may be interrupted by interrupt request and data
channel request following the algorithme:
START, ; BMOVE :
LOOP: If bytecount = 0 then goto EXIT else
begin
Q:= byte (fromaddr)
If convertaddr <' 0
then Q:= byte (Q + convertaddr) ;
byte (toaddr):= Q
fromaddr := fromaddr + 1 ; Update AC1
toaddr := toaddr + 1 ; Update AC2
bytecount := bytecount -1 ; Update AC3
end ;
TEST: If (INT REQ or DMA REQ) = 0
then goto LOOP
WAIT: Servereq (PC) ; Dcr. prog. counter and
serve req.
EXIT: Fetchnext (PC) ; Incr. prog. counter and
exec. instr.
5_._7_ _ _ _ _ _ _ _W_O_R_D_ _M_O_V_E_ 5.7
WMOVE
0 1 1 XX 1 0 1 0 1 0 0 0 0 1 0
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
X = DON>T CARE
CALL: RETURN:
; AC0 WORD COUNT ZERO
; AC1 FROM ADDR. FROM ADD + WORD COUNT + 1
; AC2 TO ADDR. TO ADDR + WORD COUNT + 1
; AC3 - UNCHANGED
\f
This instruction moves a word string from the address in AC1 to
the address in AC2. The number of words to be moved is specified
in AC0.
The instruction may be interrupted by interrupt and data channel
request following the algorithme:
START, ; WMOVE :
LOOP: If wordcount = 0 then goto EXIT else
begin
Q:= word (fromaddr)
word (toaddr):= Q
fromaddr := fromaddr + 1 ; Update AC1
toaddr := toaddr + 1 ; Update AC2
wordcount := wordcount -1 ; Update AC0
end ;
TEST: If (INT REQ or DMA REQ) = 0
then goto LOOP
WAIT: Servereq (PC) ; Decr. PC and serve req.
EXIT: Fetchnext (PC) ; Incr. PC and exec instr.
5_._8_ _ _ _ _ _ _ _S_E_A_R_C_H_ _I_T_E_M_ 5.8
SCHEL
0 1 1 XX 1 0 1 1 0 0 0 0 0 1 0
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
X = DON>T CARE
CALL: RETURN:
; AC0 - DESTROYED
; AC1 CHAINHEAD DESTROYED
; AC2 NAMEADDR ELEMENT
; AC3 - CUR \f
This instruction searches the chain for an element with a given
name and delivers the address of the element, if found, and a
zero if the name is not found in the chain. The chain-datastruc-
ture is illustrated in fig. 5.8.
N_A_M_E_A_D_D_R_ NAME(0)
NAME(1)
NAME(2)
RECORD CHAIN DESCRIPTOR
C_H_A_I_N_H_E_A_D_ + 0
+ 1
CHAINHEAD.CHAIN + 2
END;
1.ITEM 2.ITEM LAST ITEM
RECORD ITEMHEAD
ITEM + 0
+ 1
ITEM.CHAIN + 2
+ 3
ITEM.NAME(0) + 4
ITEM.NAME(1) + 5
ITEM.NAME(2) + 6
END;
E_L_E_M_E_N_T_ =ITEM
EXAMPLE: Search by name through the DOMUS - coreitemchain.
Figur 5.8
\f
The instruction may be interrupted by interrupt and data channel
request following the algorithme:
START: element:= CHAINHEAD ; SCHEL:
LOOP: element:= word (element.chain) ; AC3:= next element
If element = 0 then goto EXIT
Q:= word (nameaddr)
Q1:= word (element.name) ; Compare 1. word
If Q <' Q1 then goto TEST ; in name
Q:= word (nameaddr + 1)
Q1:= word (element.name + 1) ; Compare 2. word
If Q <' Q1 then goto TEST ; in name
Q:= word (nameaddr + 2)
Q1:= word (element.name + 2) ; Compare 3. word
If Q <' Q1 then goto TEST ; in name
Goto EXIT
TEST: CHAINHEAD:= element ; Saved work value for use
If (INT REQ or DMA REQ) = 0 ; when restarted after int.
then goto LOOP
WAIT Servereq (PC) ; Dcr. PC and servereq
Fetchnext (PC) ; Incr. PC and exec instr.
; *
EXIT: AC2:= element ; AC2:= AC3
AC3:= CUR ; AC3:= CUR,
Fetchnext (PC) ; Incr. PC and exec. instr.
* When served request a fetch results in executing the
current instruction (PC unchanged) once again with a
probably changed set of registers if so specified in the
microprogrammed instruction just interrupted.
\f
5_._9_ _ _ _ _ _ _ _S_E_A_R_C_H_ _F_R_E_E_ 5.9
SFREE
0 1 1 XX 1 0 1 1 1 0 0 0 0 1 0
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
X = DON>T CARE
CALL: RETURN:
; AC0 - UNCHANGED
; AC1 - UNCHANGED
; AC2 START ELEMENT FREE ELEMENT
; AC3 - UNCHANGED
This instruction searches a chain for a free element and delivers
it if present, and a zero if not found. The chain-datastructure
is illustrated in fig 5.9.
S_T_A_R_T_ _E_L_E_M_E_N_T_
C_H_A_I_N_H_E_A_D_.CHAIN
1.BUF- 2.BUF- 3.BUF-
RECORD BUFFERHEAD FER FER FER
B_U_F_F_E_R_ +0
+1
BUFFERCHAIN +2
+3 ..
+4
BUFFER.RECEIVER 0 +5 <' 0 0
END;
ELEMENT:= BUFFER
EXAMPLE: The MUS-buffer chain is searched for a free buffer
starting from the one addressed in >START ELEMENT>.
Figur 5.9
\f
The instruction may be interrupted by interrupt and data channel
request following the algorithme:
START: element:= start element ; SFREE:
LOOP: If element = 0 then goto EXIT
Q:= word (element. receiver)
If Q = 0 then goto EXIT ; AC2:=
element:= element.chain ; Next element;
TEST: If (INT REQ or DMA REQ) = 0
then goto LOOP
WAIT: Servereq (PC) ; Dcr. PC and serve req.
EXIT: Fetchnext (PC) ; Incr. PC and exec instr.
5_._1_0_ _ _ _ _ _ _P_R_O_C_E_S_S_ _L_I_N_K_ 5.10
LINK
0 1 1 XX 1 1 0 0 0 0 0 0 0 1 0
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
X = DON>T CARE
CALL:
; AC0 - DESTROYED
; AC1 QUEUEHEAD QUEUEHEAD
; AC2 NEW ELEMENT NEW ELEMENT
; AC3 - QUEUEHEAD \f
This instruction links an element to the end of a queue.
A queue consists of one or more queue elements. One of the
elements is the queue head as shown in fig 5.10.
a_ _I_n_i_t_:
N_E_W_ _E_L_E_M_E_N_T_
(neutral)
QUEUHEAD 1.EVENT 2.EVENT
RECORD EVENTHEAD
EVENT.NEXT
EVENT.PREV
END
b_ _I_n_s_e_r_t_e_d_: QUEUEHEAD 1.EVENT 2.EVENT 3.EVENT
(NEWELEMENT)
EXAMPLE: Bufferinsertion in the MUS-eventqueue of a process.
Figur 5.10: a+b \f
The instruction executes the following algorithme:
; LINK:
START: element:= new element ; Update
oldtail:= word (HEAD.prev) ; Link element
word (HEAD.prev):= element ;
word (element.next):= HEAD
word (element.prev):= oldtail
word (oldtail.next):= element
EXIT: Fetchnext (PC) ; Incr. PC and exec instr.
5_._1_1_ _ _ _ _ _ _P_R_O_C_E_S_S_ _R_E_M_O_V_E_ 5.11
REMEL
0 1 1 XX 1 1 0 0 1 0 0 0 0 1 0
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
X = DON>T CARE
CALL: RETURN:
; AC0 - PREDECESSOR
; AC1 - UNCHANGED
; AC2 OLD ELEMENT OLD ELEMENT
; AC3 - SUCCESSOR
\f
This instruction removes an element from a queue as shown in fig.
5.11.
QUEUEHEAD OLD ELEMENT
a_ _I_n_i_t_:
b_ _R_e_m_o_v_e_d_:
REMOVED
OLD ELEMENT
Figur 5.11: a + b
\f
The instruction executes the following algorithme:
START: element:= old element ; REMEL:
successor: word (element.next) ; Update gueue:
predecessor:= word (element.prev)
word (predecessor.next):= successor
word (successor.prev):= predecessor ; Remove element
word (element.next):= element
word (element.prev):= element
EXIT: Fetchnext (PC) ; Incr. PC and exec. instr.
5_._1_2_ _ _ _ _ _ _P_R_O_C_E_S_S_ _L_I_N_K_ _P_R_I_O_R_I_T_Y_ 5.12
PLINK
0 1 1 XX 1 1 0 1 0 0 0 0 0 1 0
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
X = DON>T CARE
CALL: RETURN:
; AC0 - DESTROYED
; AC1 - QUEUE HEAD
; AC2 PROCESS PROCESS
; AC3 - QUEUE HEAD
\f
This instruction links a process to the running queue as the last
process among processes of same priority.
QUEUEHEAD LAST
(prior)
54dD8uU
+ 15dD8uU
Inserted
LAST:= Last element in
the queue with P_R_O_C_E_S_S_
priority greather (neutral)
than or egual to
that of PROCESS
PROCESS.prior + 15Dd8uU
The QUEUEHEAD is itself an active element and points out first
process in the running queue, that is - current process. If
neutral - an empty queue - the first element (the head) points
out itself: the dummy process.
Figur 5.12
\f
The instruction may be interrupted by interrupt and data chan-
nel request following the algorithme:
; PLINK:
START: word (PROC.state):= 0 ; Proc state:= runnig
priority:= word (Proc.prior) ; ACO:= proc.priority
HEAD:= word (54dD8uU) ; HEAD:= running queue head
element:= HEAD ; AC3:= HEAD
LOOP: element:= word (element.next) ; AC3:= next element
Q:= word (element.prior) ; AC1:= priority of next
If Q < priority then goto EXIT
TEST: If (INT REQ or DMA REQ) = 0
then goto LOOP
WAIT: Servereq (PC) ; Dcr. PC and servereq
Fetchnext (PC) ; Incr. PC and exec instr.
EXIT: predecessor:= word (element.prev) ; Update queue
word (element.prev):= proc ;
word (proc.next):= element ; insert dement.
word (proc.prev):= predecessor ;
word (predecessor.next):= proc ;
Fetchnext (PC) ; Incr. PC and exec.instr.
\f
5_._1_3_ _ _ _ _ _ _I_N_S_T_R_U_C_T_I_O_N_ _F_E_T_C_H_ _(_M_U_S_I_L_)_ 5.13
FETCH
0 1 1 XX 1 1 0 1 1 0 0 0 0 1 0
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
X = DON>T CARE
CALL: RETURN:
;AC0 - DESTROVED
;AC1 - DESTROVED
;AC2 CUR CUR
;AC3 - UNCHANGED
This instruction decodes MUSIL-instructions and performs a vector
jump as shown in fig. 5.13. The MUSIL instruction-counter (deno-
M_M_m_ ted MPC) is found + 33 relative to current process description
P_p_p_ 8
P_P_p_ address CUR.
M_m_m_
Instruction address table.
Current instruction (PC) + 0
+ 1
+ 2
x + 3
+ 4
.
.
M_M_m_
MPC: MUSIL program counter, word (CUR.33 )
P_P_p_ 8
M_M_m_ DISP: (word(MPC) shift(-8)) and 377
P_P_p_ 8
EXAMPLE: DISP - vector jump to the MUSIL-instruction pointed out
by x above (DISP = 3)
Figur 5.13
\f
This instruction executes the following algorithme:
; FETCH:
M_M_m_ START: ; Fetch MPC:= word (CUR.33 )
P_P_p_ 8
Q:= word MPC ; Q = word (MPC) = next instruction;
Incr. MPC ; Increment MPC
M_M_m_ Result:= Q and 337 ; Decode instruction:
P_P_p_ 8
Q:= Q-result
DISP:= Q shift (-8) ; DISP:= word (MPC) (0:7)
EXIT: PC:= word (PC + DISP) ; Modify PC
Fetchnext (PC) ; Incr. PC and exec instr.
5_._1_4_ _ _ _ _ _ _T_A_K_E_ _A_D_D_R_E_S_S_ _(_M_U_S_I_L_)_ 5.14
TKADD
0 1 1 XX 1 1 1 0 0 0 0 0 0 1 0
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
X = DON>T CARE
CALL: RETURN:
;AC0 MODIFBITS MODIFBITS SHIFT (-2)
;AC1 - ADDRESS
;AC2 CUR CUR
;AC3 - DESTROYED \f
This instruction supplies the ADDR of an integer or string addressed
by the MUSIL PC (MPC) and increments MPC.
Integer, MODIF(14:15) = 00: Addr := Word (MPC) ;
String, - - - = 01: - - - - ;
File, - - - = 10: - - - - ;
Mfield,* - - - = 11: Addr := word (zone.zfirst) + Field (8:15),
zone = word (CUR.zn + Field (0:7))
*zonerecordfield
Field = word (MPC)
The instruction executes the following algorithme:
; TKADD:
START: ; Fetch MPC:= word (CUR.33Dd8Uu)
address:= word (MPC) ; Update AC1;
incr. MPC ; Increment MPC
If modif (14:15) = 3 then
begin
Q:= address and 377Dd8Uu ; Update AC1:
address:= (address -Q) shift (-8)
Q1:= address + cur ; Q1:= Cur + address (0:7)
Q1:= word (Q1.Zn) ; Zone:= word (Q1.Zn)
Q1:= word (Q1.zfirst) ; Q1:= word (zone.zfirst)
address:= Q1+Q ; Update AC1
end ; ADDRESS = Q1 + address (8:15)
EXIT: Modif:= modif shift (-2) ; Update AC0: modif shift (-2);
Fetchnext (PC) ; Incr. PC and exec. instr.
\f
5_._1_5_ _ _ _ _ _ _T_A_K_E_V_A_L_U_E_ _(_M_U_S_I_L_)_ 5.15
TKVAL
0 1 1 XX 1 1 1 0 1 0 0 0 0 1 0
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
X = DON>T CARE
CALL: RETURN:
;AC0 MODIFBITS MODIFBITS SHIFT (-2)
;AC1 - VAL
;AC2 CUR CUR
;AC3 - UNCHANGED
This instruction returns the value of an integer in MUSIL.
MODIF (14:15): 00 VAL = WORD (MPC)
- - : 01 VAL := R
- - : 10 VAL := WORD (WORD (MPC))
- - : 11 VAL := R
M_M_m_ R= word (CUR.32 ), the interpreter register
P_P_p_ 8 \f
This instruction is executed in following the algorithme:
; TKVAL:
START:If modif and (14:15) = 0 then
begin ; Case modif 0:
VAL:= word (MPC) ; AC1:= value
incr MPC
goto EXIT ; Increment MPC;
end
If modif (15) = 1 then ; Case modif 1 or 3:
begin
VAL:= R ; AC1:= value;
goto EXIT
end
; Case modif 2 :
Q:= word (MPC)
VAL:= word (Q) ; AC1:= value
incr MPC ; Increment MPC;
EXIT: Modif:= modif shift (-2) ; Update AC0;
Fetchnext (PC) ; Incr. PC and exec. instr.
\f
5_._1_6_ _ _ _ _ _ _C_O_M_P_A_R_E_ _B_y_t_e_ _S_t_r_i_n_g_s_ 5.16
COMP
0 1 1 XX 1 1 1 1 0 0 0 0 0 1 0
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
X = DON>T CARE
This instruction compares two byte strings and returns:
RESULT = byte (STR ADDR1 + x) - byte (STR ADDR2 + x),
if the strings differ in position x else zero.
CALL: RETURN:
;AC0 COUNT RESULT (R<0, R=0, R'0)
;AC1 STR ADDR1 UNDEFINED
;AC2 STR ADDR2 UNDEFINED
;AC3 - DESTROYED
\f
The instruction may be interrupted by interrupt and data channel
request following the algorithme:
START, ; COMP:
LOOP: If count = 0 then goto EXIT else
begin
Q1:= byte (str addr1)
Q2:= byte (str addr2)
If Q1 <' Q2 then
begin
count:= Q1-Q2 ; Update AC0;
goto EXIT
end
str addr1:= str addr1 + 1 ; Update: AC1
str addr2:= str addr2 + 1 ; - AC2
count:= count -1 ; - AC0;
end;
TEST: If (INT REQ or DMA REQ) = 0
then goto LOOP
WAIT: Servereq (PC) ; Decr. PC and servereq
Fetchnext (PC) ; Incr. PC and exec instr.
EXIT: RESULT:= count ; Update AC0,
Fetchnext (PC) ; Incr. PC and exec instr.
\f
6_._ _ _ _ _ _ _ _ _P_R_O_C_E_S_S_O_R_ _O_P_T_I_O_N_S_ 6.
The RC3803 CPU can be equipped with the following optional fea-
tures: a Real Time Clock and a Teletype Controller.
6_._1_ _ _ _ _ _ _ _R_e_a_l_ _T_i_m_e_ _C_l_o_c_k_ 6.1
The Real Time Clock generates a continuous sequence of pulses
independently of processor timing. The clock can be used prima-
rily for low resolution timing as compared to processor speed,
but it has a high long-term accuracy.
Following a power turn-on the various frequencies are only avail-
able after an interval of 5 seconds, because the crystal must be
given this amount of time to settle down after excitation in or-
der to emit a steady pulse train.
Selection of clock frequency is accomplished by means of the I/O
instruction DATA OUT A, Real Time Clock:
DOA <f' ac,RTC
= ==
0 1 1 AC 0 1 0 F 0 0 1 1 0 0
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
This instruction will select the clock frequency according to
the values of bits 14 and 15 in the specified AC as listed
below:
AC bits 14 & 15: 00 01 10 11
Frequency: 50 Hz 10 Hz 100 Hz 1000 Hz
In addition the instruction will cause the Busy and Done flags
to be set according to the control code specified by "F" (cf.
section 4.6). Setting the Busy flag by means of this instruction
will allow the next pulse from the clock to set Done thus re-
questing an interrupt if the Interrupt On flag is 1.
\f
The interrupt priority level of this device is associated with
bit 13 of the interrupt priority mask.
The DATA OUT A instruction applied to select the clock frequency
is needed only once. The first interrupt after this instruction
has set Busy = 1 can come at any time up to the clock frequency,
but once the first interrupt has appeared the following interrupts
will adhere to the selected frequency - provided that the program
sets Busy = 1 before the next interrupt is due. This is done by
the instruction:
NIOS 14.
The I/O RESET instruction will - whether it appears in the pro-
gram or is generated by using the Diagnostic Front Panel - reset
the clock to a frequency of 50 Hz.
6_._2_ _ _ _ _ _ _ _T_e_l_e_t_y_p_e_ _C_o_n_t_r_o_l_l_e_r_ 6.2
The Teletype Controller provides for two-way communication be-
tween the computer and the operator. The input device is the
Teletype keyboard and the output device is the Teletype printer.
All information exchanges between the computer and the keyboard/
printer use a subset of the 128 character alphanumeric ASCII code
as listed in Appendix B. In addition to a keyboard and a printer,
some models of the Teletype terminal can be equipped with a paper
tape reader/punch combination. Terminals so equipped are designated
Automatic Send/Receive (ASR) terminals, while those not so equipped
are designated Keyboard Send/Receive (KSR) terminals.
6_._2_._1_ _ _ _ _ _I_n_s_t_r_u_c_t_i_o_n_s_ 6.2.1
Since the terminal is in effect two peripheral devices coupled
together, the controller contains both an input buffer and an
output buffer. These buffers are independent of one another and
are both 8 bits in length.
Similarly two completely separate sets of Busy and Done flags
are available for input and output operations respectively.
\f
The Busy and Done flags are controlled by means of the two stan-
dard device flag commands in the instructions according to the
following list:
"F" = S Sets Busy = 1 and Done = 0 and either reads a charac-
ter into the input buffer or transfers a character in
the output buffer to the printer (or the punch).
"F" = C Sets Busy = 0 and Done = 0 thereby stopping all data
transfer operations. This command - if issued while a
transfer is in process - will result in partial
reception of the character code being transferred.
"F" = P No effect.
The instructions used to read the character buffer and to load
the character buffer are the standard I/O instructions with the
appropriate device codes. An extract of Appendix A containing
these codes appear below:
Octal
Code Mnemonic Maskbit Device
10 TTI 14 Teletype input, first controller
11 TT0 15 Teletype output, first controller
50 TTI1 14 Teletype input, second controller
51 TT01 15 Teletype output, second controller
\f
6_._2_._1_._1_ _ _ _R_E_A_D_ _C_H_A_R_A_C_T_E_R_ _B_U_F_F_E_R_ 6.2.1.1
DIA <f' ac,TTI
= ==
0 1 1 AC 0 0 1 F 0 0 1 0 0 0
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
This instruction will place the contents of the input buffer in
bits 8 to 15 of the AC specified in the instruction. Bit 8 is a
parity check bit while bits 9 to 15 contain the character code
proper. Bits 0 to 7 of the AC are all set to 0.
After the data transfer has been completed the controller>s Busy
and Done flags for input are set according to the control code
specified by "F".
6_._2_._1_._2_ _ _ _L_O_A_D_ _C_H_A_R_A_C_T_E_R_ _B_U_F_F_E_R_ 6.2.1.2
DOA <f' ac,TTO
= ==
0 1 1 AC 0 0 1 F 0 0 1 0 0 1
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
This instruction will place bits 9 to 15 of the specified AC in
the output buffer of the controller. After the transfer has been
completed the controller>s Busy and Done flags for output are set
according to the control code specified by "F". The contents of
the AC specified in the instruction will remain unaltered.
\f
6_._2_._2_ _ _ _ _ _P_r_o_g_r_a_m_m_i_n_g_ 6.2.2
On account of the two-sided nature of the Teletype terminal this
section will describe input and output procedures separately.
6_._2_._2_._1_ _ _ _I_n_p_u_t_ 6.2.2.1
Input operations - whether full- or half-duplex - do not have to
be initialized by the program because the striking of a key on
the keyboard automatically will transmit the corresponding char-
acter code to the controller. When the character has been assem-
bled the input Busy flag is set to 0, the input Done flag is set
to 1 and a program interrupt consequently requested - provided
that the priority mask bit is 0.
The character can then be read by issuing the READ CHARACTER
BUFFER instruction (DIA). The instruction should be issued with
either a C or an S command so that the input Done flag is set to
0; this will allow the controller to initiate a further program
interrupt request when the next character has been fully assembled.
6_._2_._2_._2_ _ _ _O_u_t_p_u_t_ 6.2.2.2
Output operations are initiated by the program using the LOAD
CHARACTER BUFFER instruction (DOA). The instruction should be
issued with an S command, which will set the Busy flag to 1 and
allow the transmitting of the character to the terminal. When the
transmission has been completed the output Busy flag is set to 0
and the output Done flag is set to 1 thus issuing a program in-
terrupt request.
The output buffer must be reloaded by means of the LOAD CHARACTER
BUFFER instruction every time a character is to be sent to the
terminal. Thus to transmit a multi-character message a sequence
of LOAD CHARACTER BUFFER instructions with S commands must be
issued. The program must make allowance for complete transmission
of every single character before transmission of the next char-
acter is initiated. \f
6_._2_._3_ _ _ _ _ _P_r_o_g_r_a_m_m_i_n_g_ _E_x_a_m_p_l_e_s_ 6.2.3
The following examples show sections of programs which will
handle character operations involving the Teletype keyboard,
printer, paper tape reader, and paper tape punch.
Example 1 reads a character from the Teletype keyboard, example
2 reads a character from Tape reader, and example 3 prints a
character on the Teletype printer and - if the tape punch on an
ASR terminal is turned on - simultaneously punches the character
on the tape.
6_._2_._3_._1_ _ _ _E_x_a_m_p_l_e_ _1_ 6.2.3.1
SKPDN TTI ;Character buffer loaded yet?
JMP .-1 ;No
DIAC 1,TTI ;Read character and clear Done
flag
6_._2_._3_._2_ _ _ _E_x_a_m_p_l_e_ _2_ 6.2.3.2
NIOS TTI ;Start reader
SKPDN TTI ;Frame buffer loaded yet?
JMP .-1 ;No
DIAC 1,TTI ;Read frame and clear Done flag
6_._2_._3_._3_ _ _ _E_x_a_m_p_l_e_ _3_ 6.2.3.3
SKPBZ TTO ;Printer free?
JMP .-1 ;No, try again
DOAS 1,TTO ;Print character
\f
6_._2_._3_._4_ _ _ _E_x_a_m_p_l_e_ _4_ 6.2.3.4
The subroutine shown in this example and called from the main
program by a JUMP TO SUBROUTINE instruction (JSR to TTYRD) illu-
strates reading and echoing characters on the Teletype with Tele-
type interrupts disabled. AC0 is used to store the character.
TTYRD: SKPDN TTI ;Has character been typed?
JMP .-1 ;No, then wait
DIAC 0,TTI ;Yes, then read character and
clear Done flag
SKPBZ TTO ;Is TT0 ready?
JMP .-1 ;No, then wait
DOAS 0,TTO ;Yes, then echo character
JMP 0,3 ;Return
6_._2_._3_._5_ _ _ _E_x_a_m_p_l_e_ _5_ 6.2.3.5
This example shows how Teletype may be programmed using the pro-
gram interrupt facility. To do so makes it possible to perform a
number of calculations in the intervals of time between Teletype
characters.
\f
This routine will read a line and echo it on the Teletype printer
using the interrupt priority system. The characters are read into
a buffer area beginning at location 1000dD8uU. The routine is termin-
ated by either a carriage return character or line overflow. Line
overflow is determined by the value of MAXLL (maximum line
length).
m_
.LOC O ;
0 ;Program counter stored here when
an interrupt occurs.
IHAND ;Address of interrupt handler
.LOC 400 ;
START: LDA 1,BUFFER ;Set up buffer pointer in
autoincrement location 23
STA 1,23 ;
LDA 1,MAXLL ;Get maximum line length
STA 1,CNTR ;Initialize line overflow counter
SUBZL 1,1 ;Set AC1 = 1
DOBS 1,CPU ;Mask out TTO and turn on
interrupts
.
.
.
HANG: LDA 0,CNTR ;When need full line to continue
hang up here until reading is all
done
MOV 0,0,SZR ;
JMP .-2 ;
.
.
.
.
BUFFR: 777 ;Buffer begins at location 1000
MAXLL: 110 ;Maximum of 72DD10UU
characters per line
CNTR: 0 ;Line overflow counter
.
.
.
IHAND: SKPDN TTI ;Make sure TTI caused the
p_interrupt \f
HALT ;Error - some other peripheral
interrupted
STA 0,SAV0 ;Save accumulators that will be
used
STA 1,SAV1 ;
DIAC 0,TTI ;Read character and clear Done
STA 0, 23 ;Store character in buffer
SKPBZ TTO ;Make sure TT0 not busy
JMP .-1 ;
DOAS 0,TTO ;Echo character
LDA 1,CR ;Is it a carriage return?
SUB 0,1,SZR ;
JMP .+4 ;No
SUBC 0,0 ;Yes, clear AC0 without changing
carry
STA 0,CNTR ;Zero out CNTR to indicate line
done
JMP .+3 ;
DSZ CNTR ;If not a carriage return,
decrement CNTR
JMP OUT ;Line not yet done, go dismiss
LDA 0,TTMSK ;Line is done
MSKO 0 ;Mask out TTI (and TT0) to inhibit
further input
OUT: LDA 0,SAV0 ;Restore accumulators
LDA 0,SAV1 ;
INTEN ;Turn interrupts back on
JMP 0 ;Return to interrupted program
SAV0: 0
SAV1: 0
CR: 215
TTMSK: 3
\f
F_7_._ _ _ _ _ _ _ _ _P_R_O_G_R_A_M_ _L_O_A_D_I_N_G_ 7.
7_._1_ _ _ _ _ _ _ _I_n_t_r_o_d_u_c_t_i_o_n_ 7.1
Whenever the computer is used for information processing of any
kind the program must - as previously mentioned - reside in main
memory. But to read a program into memory is in itself a kind of
information processing and therefore requires the existence in
memory of a program - called a loading program - to perform this
duty.
Although the loading program will normally be present, it may
from time to time be necessary to read it into memory. This is
done by a small, specialized loading program which is called a
"bootstrap loader" and whose only function is to read into memory
the more general-purpose loading program.
Two methods are available for entering the bootstrap loader into
memory. One is for the operator to enter it manually utilizing
the data switches and the deposit switch on the Diagnostic Front
Panel. The other is to use the Automatic Program Load option if
the computer in question is so equipped.
In this chapter only automatic program loading is described. For
details about manual loading the reader must consult the Reference
Manual for the Diagnostic Front Panel - RCSL: 52-AA542.
\f
7_._2_ _ _ _ _ _ _ _A_u_t_o_m_a_t_i_c_ _L_o_a_d_i_n_g_ 7.2
To use the Automatic Program Load option, the operator must first
select the input device and set up the loading program on this
device in preparation to be read. In addition the device code of
this unit must be set up in its binary form on the data switches
10 to 15 on the front frame of the CPU board (cf. the illustra-
tion appearing in the following chapter). The setting of data
switch 0 on the front panel depends on the type of input device
selected. If this is a data channel device - for instance magne-
tic tape - data switch 0 must be set to 1. If it is a low-speed
device - for instance a paper tape reader - data switch 0 must be
set to 0.
When this has been done, push the AUTOLOAD switch on the opera-
tor panel. This will cause the bootstrap loader to be read, de-
posited in memory locations 0 to 37Dd8uU and started location 0.The
bootstrap loader will then read the data switches (0 and 10 to
15), set up its own I/O instructions with the device code as read
and finally perform a program load procedure which depends on the
setting of data switch 0.
If data switch 0 has been set to 1, the bootstrap loader will
start the device for data channel transfer starting storage at
location 0 and will then loop at location 377dD8uUuntil adatachan-
nel transfer places a word in this location. When this happens,
the word placed in this location is executed as an instruction;
typically this will be a JUMP into the data which have been
placed in locations 0 to 376dD8uU.
N_O_T_E_: For proper program loading via the data channel the de-
vice in use must be initialized for the reading opera-
tion by an I/O RESET instruction followed by a NIOS
instruction. Furthermore the device must stop reading
when 256dD10uU words has been read; otherwise the avail-
able memory locations will overflow.
\f
If data switch 0 has been set to 0, the bootstrap loader will
read the loading program via programmed I/O. The device must
supply data as 8-bit bytes; each pair of bytes read will be me-
mory stored in as a single word wherein the first and second byte
will become respectively the left and right halves of the word.
To simplify the positioning of the input medium - for instance
paper tape - the bootstrap loader will ignore leading null char-
acters, i.e. it will not store any word until it has read a non-
zero synchronization byte.
The first word following this synchronization byte must be the
negative of the total number of words to be read including this
first word. The number of words to be read - including the first
- cannot exceed 192dD10uU. The bootstrap loader will storethe words
read in memory starting in location 100dD8uU. When the lastword has
been read the bootstrap loader will transfer control to that lo-
cation.
The Automatic Loading hardware in RC3803 is capable of contain-
ing up to 16 times 32 word programs, one of this programs is
listed on the following pages, a bootstrap loader capable of
loading in either of the manners described above.
A list of the available bootstrap loaders in the Automatic Pro-
gram Load option, F10A is too shown.
For details about the RC3803 program load refer to:
GENERAL INFORMATION
Hardware Testprograms and Program Load to RC3803
RCSL - 52AA894
\f
B_O_O_T_S_T_R_A_P_ _L_O_A_D_E_R_ _F_O_R_
A_U_T_O_M_A_T_I_C_ _P_R_O_G_R_A_M_ _L_O_A_D_
00000 060477 BEG: READS 0 ;READ SWITCHES INTO AC0
00001 105120 MOVZL 0,1 ;ISOLATE DEVICE CODE
00002 124240 COMOR 1,1 ;-DEVICE CODE -1
00003 010011 LOOP: ISZ OP1 ;COUNT DEVICE CONTROL INTO
ALL
00004 010031 ISZ OP2 ;I0 INSTRUCTIONS
00005 010033 ISZ OP3 ;
00006 010014 ISZ OP4 ;
00007 125404 INC 1,1,SZR ;DONE?
00010 000003 JMP LOOP ;NO INCREMENT AGAIN
00011 060077 OP1: 060077 ;START DEVICE;(NIOS 0) -1
00012 030017 LDA 2,C377 ;YES,PUTJMP 377INTO
LOCATION 377
00013 050377 STA 2,377 ;
00014 063377 OP4: 063377 ;BUSY ? :( SKPBN 0 ) -1
00015 000011 JMP OP1 ;NO, GO TO OP1
00016 101102 MOVL 0,0,SZC ;LOW SPEED DEVICE?(TEST
SWITCH 0)
00017 000377 C377: JMP 377 ;NO, GO TO 377 AND WAIT
FOR CHAN.
00020 004031 LOOP2:JSR GET+1 ;GET A FRAME
00021 101065 MOVC 0,0.SNR ;IS IT NONZERO?
00022 000020 JMP LOOP2 ;NO, IGNORE AND GET ANOTHER
00023 004030 LOOP4:JSR GET ;YES, GET A FULL WORD
00024 046027 STA 1,@C77 ;STORE STARTING AT 100
00025 010100 ISZ 100 ;COUNT WORD - DONE?
00026 000023 JMP LOOP4 ;NO, GET ANOTHER
00027 000077 C77: JMP 77 ;YES - LOCATION COUNTER AND
JUMP TO LAST WORD
00030 126420 GET: SUBZ 1,1 ;CLEAR AC1, SET CARRY
OP2:
Figur 7.1 \f
\f
«eof»