|
DataMuseum.dkPresents historical artifacts from the history of: CP/M |
This is an automatic "excavation" of a thematic subset of
See our Wiki for more about CP/M Excavated with: AutoArchaeologist - Free & Open Source Software. |
top - metrics - download
Length: 67456 (0x10780) Types: TextFile Names: »D174«
└─⟦4b76feb82⟧ Bits:30008865 Diskette med tekster der formodes at være 31-D-163…174 └─⟦this⟧ »D174«
G_e_n_e_r_a_l_ _R_u_l_e_s_ Operations can be initiated by an internal process that has i_n_- i_t_i_a_l_i_z_e_d_ or r_e_s_e_r_v_e_d_ the device. When the device is local input operations will be terminated im- mediately with the intervention bit set. The device is set local, after a timer error, when the input tray is full or when the out- put tray is full. S_e_n_s_e_ _O_p_e_r_a_t_i_o_n_ The device is sensed and the status word is delivered as an answer. S_e_n_s_e_ _R_e_a_d_y_ _O_p_e_r_a_t_i_o_n_ The operation is delayed until the device is either set to the remote state or disconnected. The device is then sensed and the status word is delivered as an answer. The operation is only de- layed one minute of which a timeout will occur. It is possible to regret a sense ready message sent to the card reader process by means of the monitor procedure regret message. I_n_p_u_t_ _O_p_e_r_a_t_i_o_n_ A number of punched cards of 80 columns each are input to a stor- age area within the sending process. \f Input is terminated, 1) where there is no room for an entire card, or 2) when the sending process is stopped, or 3) when any status bit is set whichever occurs first. In all cases input is terminated by an answer defining the actual number of characters transferred to the storage area. I_n_p_u_t_ _M_o_d_e_ The following modes can be used: 0: Punched binary 10: Punched decimal with conversion 64: Mark sense binary 74: Mark sense decimal with conversion 256: Basic cards Depending on the mode a character is inserted following each punched card: M_o_d_e_ A_d_d_i_t_i_o_n_ 0 : none 10 : NL 64 : none 74 : CR, NL 256 : none \f The blocksize depends on the mode: M_o_d_e_ B_y_t_e_s_ 0 : 120 10 : 81 64 : 60 74 : 42 256 : variable Status bits b_i_t_ _n_o_ 0 intervention 1 parity error 2 timer 3 data overrun 5 end document 7 bit 7 alone file separation card read 8 bit 7 and 8 job separation card read 10 read error 11 card reject M_e_s_s_a_g_e_s_ _a_n_d_ _A_n_s_w_e_r_s_ operation: message: answer: sense 0 status word 0 0 \f operation: message: answer: sense 0 < 12 + 4 status word ready 0 0 input 3 < 12 + mode status word first storage address number of halfwords last storage address number of characters number of error-free characters \f G_e_n_e_r_a_l_ _R_u_l_e_s_ Operation can only be initiated by an internal process that has i_n_i_t_i_a_l_i_z_e_d_ or r_e_s_e_r_v_e_d_ the device. S_e_n_s_e_ _O_p_e_r_a_t_i_o_n_ The device does not permit a sense operation, so a status zero is always delivered. S_e_n_s_e_ _R_e_a_d_y_ _O_p_e_r_a_t_i_o_n_ The operation specifies the mode in which the tape must be read. The operation is delayed until a paper tape is loaded in the reader and the reset-button is pressed, if not already done. When a tape is loaded, 3 characters are read and converted according to the mode specified. The characters are kept until an input op- eration arrives. Note that if mode = 6, the process should not be initialized be- tween sense ready and the next input, as that may disturb the case situation. I_n_p_u_t_ _O_p_e_r_a_t_i_o_n_ Characters are input to a storage area within the sending pro- cess. Three 8-bit characters are packed in each word. Unused character positions in the last input word are filled with NUL characters. \f Input is terminated, 1) when the area is full, or 2) after a parity error, or 3) at the end of the paper tape, 4) after 3 characters, if first message after sense ready, whichever occurs first. In all cases input is terminated by an answer defining the actual number of characters transferred to the storage area. I_n_p_u_t_ _M_o_d_e_ Characters can be input after removal of an odd or even parity bit, or directly as 8 bits without parity checking. Finally they can be input and converted from the F_l_e_x_o_w_r_i_t_e_r_ _c_o_d_e_ to the ISO 7-bit code. The case situation is set to lower case when the reader is initialized or reserved. The input is part of the message: mode: 0 odd parity 2 even parity 4 no parity 6 Flexowriter to ISO conversion In mode 0, 2, and 6 input is terminated after a p_a_r_i_t_y_ _e_r_r_o_r_. The erroneous character is replaced by a SUBSTITUTE character (ISO 26). In mode 6 however ALL HOLES characters are skipped. S_t_a_t_u_s_ _B_i_t_s_ 1 parity 2 timer (after sense ready) 5 end of paper It should be noted that the input block can have a length greater than zero when the status word indicates an e_n_d_ _o_f_ _p_a_p_e_r_. \f M_e_s_s_a_g_e_s_ _a_n_d_ _A_n_s_w_e_r_s_ operation: message: answer: sense 0 0 0 0 sense ready 0 < 12 + 4 status word 0 0 input 3 < 12 + mode status word first storage address number of halfwords last storage address number of characters \f T_a_b_l_e_ _o_f_ _D_e_c_i_m_a_l_ _V_a_l_u_e_s_ _o_f_ _I_S_O_-_C_h_a_r_a_c_t_e_r_s_ 0 NUL 32 SP 64 96 1 SOH 33 ! 65 A 97 a 2 STX 34 " 66 B 98 b 3 EXT 35 67 C 99 c 4 EOT 36 S 68 D 100 d 5 ENQ 37 % 69 E 101 e 6 ACK 38 & 70 F 102 f 7 BEL 39 71 G 103 g 8 BS 40 ( 72 H 104 h 9 HT 41 ) 73 I 105 i 10 NL 42 * 74 J 106 j 11 VT 43 + 75 K 107 k 12 FF 44 , 76 L 108 l 12 CR 45 - 77 M 109 m 14 SO 46 . 78 N 110 n 15 SI 47 / 79 O 111 o 16 DLE 48 0 80 P 112 p 17 DC1 49 1 81 Q 113 q 18 DC2 50 2 82 R 114 r 19 DC3 51 3 83 S 115 s 20 DC4 52 4 84 T 116 t 21 NAK 53 5 85 U 117 u 22 SYN 54 6 86 V 118 v 23 ETB 55 7 87 W 119 w 24 CAN 56 8 88 X 120 x 25 EM 57 9 89 Y 121 y 26 SUB 58 : 90 Z 122 z 27 ESC 59 ; 91 Æ 123 æ 28 FS 60 < 92 Ø 124 ø 29 GS 61 = 93 Å 125 å 30 RS 62 > 94 126 31 US 63 ? 95 _ 127 DEL \f S_t_a_n_d_a_r_d_ _C_o_n_v_e_r_s_i_o_n_ _T_a_b_l_e_ _f_o_r_ _D_i_s_c_e_t_t_e_s_ This character conversion table is used as a standard in con- nection with discettes written (or to be written) in EBCDIC. The table is valid for conversion from ISO to EBCDIC as well as from EBCDIC to ISO. Besides what is mentioned in the table, the following is valid for EBCDIC to ISO conversion: - EBCDIC 79 (') is converted to ISO 33 (!) - EBCDIC 250 () is converted to ISO 94 ( ). - EBCDIC characters, which do not correspond to ISO characters are converted to ISO 26 (SUB). \f S_t_a_n_d_a_r_d_ _C_o_n_v_e_r_s_i_o_n_ _T_a_b_l_e_ _f_o_r_ _D_i_s_c_e_t_t_e_s_ ISO EBCDIC ISO EBCDIC -------------------- -------------------- 0 NUL 0 NUL 32 SP 64 SP 1 SOH 1 SOH 33 ! 90 ! 2 STX 2 STX 34 " 127 " 3 ETX 3 ETX 35 123 # 4 EOT 55 EOT 36 S 91 S 5 ENQ 45 ENQ 37 % 108 % 6 ACK 46 ACK 38 & 80 & 7 BEL 47 BEL 39 ' 125 ' 8 BS 22 BS 40 ( 77 ( 9 HT 5 HT 41 ) 93 ) 10 NL 37 LF 42 * 92 * 11 VT 11 VT 43 + 78 + 12 FF 12 FF 44 , 107 , 13 CR 13 CR 45 - 96 - 14 SO 14 SO 46 . 75 . 15 SI 15 SI 47 / 97 / 16 DLE 16 DLE 48 0 240 0 17 DC1 17 DC1 49 1 241 1 18 DC2 18 DC2 50 2 242 2 19 DC3 19 DC3 51 3 243 3 20 DC4 60 DC4 52 4 244 4 21 NAK 61 NAK 53 5 245 5 22 SYN 50 SYN 54 6 246 6 23 ETB 38 ETB 55 7 247 7 24 CAN 24 CAN 56 8 248 8 25 EM 25 EM 57 9 249 9 26 SUB 63 SUB 58 : 122 : 27 ESC 39 ESC 59 ; 94 ; 28 FS 28 IFS 60 < 76 < 29 GS 29 IGS 61 = 126 = 30 RS 30 IRS 62 > 110 > 31 US 31 IUS 63 ? 111 ? \f S_t_a_n_d_a_r_d_ _C_o_n_v_e_r_s_i_o_n_ _T_a_b_l_e_ _f_o_r_ _D_i_s_c_e_t_t_e_s_ ISO EBCDIC ISO EBCDIC ------------------- ------------------- 64 124 96 121 65 A 193 A 97 a 129 a 66 B 194 B 98 b 130 b 67 C 195 C 99 c 131 c 68 D 196 D 100 d 132 d 69 E 197 E 101 e 133 e 70 F 198 F 102 f 134 f 71 G 199 G 103 g 135 g 72 H 200 H 104 h 136 h 73 I 201 I 105 i 137 i 74 J 209 J 106 j 145 j 75 K 210 K 107 k 146 k 76 L 211 L 108 l 147 l 77 M 212 M 109 m 148 m 78 N 213 N 110 n 149 n 79 O 214 O 111 o 150 o 80 P 215 P 112 p 151 p 81 Q 216 Q 113 q 152 q 82 R 217 R 114 r 153 r 83 S 226 S 115 s 162 s 84 T 227 T 116 t 163 t 85 U 228 U 117 u 164 u 86 V 229 V 118 v 165 v 87 W 230 W 119 w 166 w 88 X 231 X 120 x 167 x 89 Y 232 Y 121 y 168 y 90 Z 233 Z 122 z 169 z 91 Æ 173 123 æ 192 92 Ø 224 / 124 ø 106 93 Å 189 125 å 208 94 95 126 161 95 _ 109 _ 127 DEL 7 DEL \f S_t_a_n_d_a_r_d_ _C_o_n_v_e_r_s_i_o_n_ _f_o_r_ _C_a_r_d_r_e_a_d_e_r_s_ The standard conversion is EBCDIC to ISO, as described in the following: Unassigned codes are converted to the SUB character. A NL character is inserted after each card during input. \f F_l_e_x_o_w_r_i_t_e_r_ _t_o_ _I_S_O_ _C_o_n_v_e_r_s_i_o_n_ In the table below, each element corresponds to a Flexowriter character in lower or upper case with a decimal value equal to the sum of the column and row numbers. To the left in the element is shown the Flexowriter character, while the corresponding ISO character is shown to the right. As an example, the Flexowriter character is an upper case char- acter with the decimal value 16 + 0 = 16; it is converted to the ISO character &. An underline _ or a bar followed by a space are converted to the special characters _ and ! respectively. Multiple inderlines or bars, case shifts, and unassigned codes are skipped between the first underline or bar and the space. An underline or bar followed by a graphic character are converted to the SUB char- acter. Unassigned codes and codes 65-127 are skipped during input. \f I_S_O_ _t_o_ _F_l_e_x_o_w_r_i_t_e_r_ _C_o_n_v_e_r_s_i_o_n_ In the table below, each element corresponds to an ISO character with a decimal value equal to the sum of the column and row num- bers. To the left in the element is shown the ISO character, while the corresponding Flexowriter character is shown to the right. As an example, the ISO character & has the decimal value 32 + 6 = 38, and is converted to the upper case Flexowriter character . An exclamation mark ! and an underline _ are converted to the special character and _ followed by a space. Unassigned codes and codes > 127 are skipped during output. \f G_e_n_e_r_a_l_ _R_u_l_e_s_ Operations can be initiated by any internal process that is a u_s_e_r_ of the device. I_n_i_t_i_a_l_i_z_a_t_i_o_n_ has no effect. A terminal process accepts messages simultaneously from more than one in- ternal process provided no internal process has r_e_s_e_r_v_e_d_ it. Setting the terminal in the l_o_c_a_l_ state has no effect other than delaying input/output until the device is set r_e_m_o_t_e_ again, while it works as disconnected and connected for the other devices served by this process. All input operations are started by out- putting a bell character (value 7) on the device. A_t_t_e_n_t_i_o_n_ _M_e_s_s_a_g_e_ The operator depresses the ESC button. This will cause the mon- itor to write 'att' on the device and the operator can now iden- tify the internal process he wants to communicate with by writing its process name. In normal cases the monitor sends an attention message to the in- ternal process identifying the device by its process description address (sender(buf)). However, if the name does not identify an existing internal process the monitor answers 'unknown'. If the terminal process is reserved, no 'att' is written, but an attention message is sent to the reserving internal process. Attention Message: 0 0 0 0 S_e_n_s_e_ _O_p_e_r_a_t_i_o_n_ The operation is dummy and is answered with statusword = 0 \f I_n_p_u_t_ _O_p_e_r_a_t_i_o_n_ User Name If the name of the sender differs from the name of the last in- ternal process that has communicated with the terminal process, the name of the sender is output in the following format: <new line> to <name of sender> <new line> Input A BELL-character is output, to signal the operator that input may take place. Now the operator can input characters to a storage area within the sending process. Characters are stored with three 8-bit char- acters per word. Unused character positions in the last input word are filled with NUL characters. Conversion To serve the teletype terminal a facility for converting capital letters to small letters is included. Conversion takes place for input in mode 0 and 2 provided the conversion state is true. This state is set to true when one of the following conditions are satisfied: 1) EM is read (mode 0) 2) the device becomes disconnected (modes 0, 2, or 4) 3) at operator key interrupt (mode 0) The conversion state is set to false when the first small letter is encountered. Timer interrupt. If the operator waits more than approx. 60 seconds (in mode 2 or 4 only 5 seconds) between input of two characters the input oper- ation is terminated. Input Termination Input termination depends on the input mode \f Input Mode The mode which is part of the message defines how the read char- acters are interpreted by the monitor. Mode = 0 The mode is intended for conversational operation by means of the keyboard. In this mode answers are returned to the sending pro- cess in the following situations: 1) when the area is full, or 2) at operator key interrupt, or 3) when timeout occurs, or 4) when the device is disconnected, or 5) when a NL character is read, or 6) when a EM character is read, whichever occurs first. The characters are interpreted as ISO characters in even parity. All odd parity characters are replaced by a SUBSTITUTE character (ISO 26). Four characters have a special action in this mode; they are called: ENQ (ENQUIRY) key CTRL + E EM (END MEDIUM) key CTRL + Y BS (BACKSPACE) key BACKSPACE RUBOUT (RUBOUT) key RUBOUT The ENQ character will cause all previously read characters (since last line termination or timeout) to be deleted, while the BS character and the RUBOUT character will delete the last read character (if any character was read since last line termination or timeout). EM will terminate input. \f RC STANDARD: ISO value Echoed as ENQ 5 94 ( ) EM 25 13 10 (CR LF) BS 8 8 32 8 (BS SP BS) RUBOUT 127 95 ( ) Mode = 2 and Mode = 4 These two intput modes are intended for paper input from tele- terminals. The problem using the paper reader connected to the terminals arises from the fact that this reader cannot be program controlled. Once started the reader will continue to transmit characters either until manually stopped or until the end of the paper tape. This again means that the only way a program can de- termine whether the transmission of a paper tape is terminated, is through the timer interrupt generated when no characters have been input for a certain period. In these two modes answers are returned to the sending process in the following situations: 1) when the area is full, or 2) when one timer interrupt is received, or 3) when the device is disconnected, whichever occurs first. In mode 2 the characters read are interpreted as ISO characters in even parity. All odd parity characters are replaced by a SUB- STITUTE character (ISO 26). In mode 4 the characters read are interpreted in no parity mode i.e. as 8-bit characters without parity. All 8-bit patterns are accepted and stored in the input area. This mode enables the user to have 8-bit paper tapes of any coding and in any parity trans- mitted from the terminal to RC8000. \f O_u_t_p_u_t_ _O_p_e_r_a_t_i_o_n_ User Name If the name of the sender differs from the name of the last in- ternal process that has communicated with the terminal process, the name of the sender is output in the following format: <new line> from <name of sender> <new line> Output A textstring consisting of one or more lines is output from a storage area within the sending process. Characters must be stored with three characters per word. Output Termination Output is terminated, 1) when the area is empty, or 2) at operator key interrupt, or 3) after timer interrupt, or 4) when the device is disconnected, whichever occurs first. Output is terminated by an answer defining the actual number of characters output. In case of abnormal termination (2, 3, and 4) the number of characters may be wrong using output in mode 0. O_u_t_p_u_t_ _M_o_d_e_ Output can be performed in 3 modes: 0, 2, and 4. In all modes the char. 128 will cause the multiplexer to stop output. \f Mode 0: Normal text mode: The characters are interpreted as 7-bit ISO characters with or without parity. The characters with value >_ 32 and <_ 255 will be written without conversion. The character with value 10 (NL) will be converted to the following sequence: <13><10><127><127><127><127> The character with value 7 (BELL) will be output as <7>, all other characters with value <32 will be skipped. Mode 2: Transparent text mode: The characters are interpreted as ISO- characters in even parity. All characters will be written as (char and 127). Mode 4: Transparent output mode: The characters are interpreted in no parity mode i.e. as 8-bit characters without parity. All 8-bit patterns (256) excl. 128 are accepted and written. S_t_a_t_u_s_ _B_i_t_s_ 2 timer 7 operator key M_e_s_s_a_g_e_s_ _a_n_d_ _A_n_s_w_e_r_s_ Operation: message: answer: sense 0 0 0 0 input 3 < 12 + mode status word first storage address number of halfwords last storage address number of characters \f Operation: message: answer: output 5 < 12 + mode status word first storage address number of halfwords last storage address number of characters \f G_e_n_e_r_a_l_ _R_u_l_e_s_ Operations can be initiated by an internal process that has i_n_- i_t_i_a_l_i_z_e_d_ or r_e_s_e_r_v_e_d_ the device. S_e_n_s_e_ _O_p_e_r_a_t_i_o_n_ The device does not permit a sense operation, so status zero will always be delivered. O_u_t_p_u_t_ _O_p_e_r_a_t_i_o_n_ A storage area within the sending process is output as one block. Each storage word is output as three 8-bit characters. Output is terminated, 1) when the block has been output, or 2) after a timer error, whichever occurs first. Output is terminated by an answer defining the actual number of characters output. O_u_t_p_u_t_ _M_o_d_e_ Characters can be output after the addition of an odd or even parity bit, or directly as 8 bits without a parity bit. Further- more it is possible in even parity to have the character <10> converted to <13><10><127>. Finally they can be converted from the ISO 7-bit code to the F_l_e_x_o_w_r_i_t_e_r_ _c_o_d_e_ and output as defined RCSL 31-D60. The c_a_s_e_ situation is set to lower case when the punch is initialized or reserved. \f The output mode is part of the message: mode: 0 odd parity 2 even parity 4 no parity 6 ISO to Flexowriter conversion 8 even parity (<10> implies <13><10><127>) S_t_a_t_u_s_ _B_i_t_s_ 0 intervention 2 timer M_e_s_s_a_g_e_s_ _a_n_d_ _A_n_s_w_e_r_s_ operation: message: answer: sense 0 0 0 0 output 5 < 12 + mode status word first storage address number of halfwords last storage address number of characters \f i T_A_B_L_E_ _O_F_ _C_O_N_T_E_N_T_S_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _P_A_G_E_ 1. GENERAL ................................................ 1 2. FUNCTIONAL DESCRIPTION ................................. 2 2.1 Addressing ........................................ 2 2.2 Interrupt Sense ................................... 3 2.3 Master Selection Logic ............................ 4 2.4 Special Controls .................................. 4 2.4.1 Generate INTA .............................. 5 2.4.2 Set or Clear Interrupt Masks ............... 5 2.4.3 Set Interrupt Bit .......................... 5 2.4.4 Generate INIT .............................. 6 2.4.5 Reserve Bus ................................ 6 2.5 Slave Addressing .................................. 6 2.6 Reset and Connection Survey ....................... 6 3. MBA LINK DEFINITION .................................... 8 3.1 Data and Address Lines ............................ 8 3.2 Controls .......................................... 9 3.3 Sense Interrupt ................................... 9 3.4 Connected ......................................... 10 4. BOARD LAYOUT ........................................... 13 5. LOGIC DIAGRAMS ......................................... 14 6. PARTLIST ............................................... 40 \f ii \f F_ 1_._ _ _ _ _ _ _ _ _G_E_N_E_R_A_L_ 1. The MBA 603 plugs into the Intel Multibus and acts as a master controlled by the remote MBA (MBA 201). The MBA 603 is able to execute memory accesses on the Multibus both byte- and word-wide in all addresses up to EFFFF, and I/O accesses in all addresses from F000 to FFFEF. The remaining 16 addresses are used by the remote MBA for control purposes. The MBA 603 has the ability to sense the interrupt lines INTR, and to receive interrupts both as BVI (Bus Vectored Interrupts) and NBVI (Non Bus Vectored Interrupt). The MBA 603 may also send interrupt signals but only as NBVI. The interface towards the remote MBA is defined in chapter 3 (MBA Link Definition). \f F_ 2_._ _ _ _ _ _ _ _ _F_U_N_C_T_I_O_N_A_L_ _D_E_S_C_R_I_P_T_I_O_N_ 2. When the remote MBA activates MBA 603, it first applies an address to the buslines then rises one of the taglines, indicating hereby whether a read- or write-sequence is to take place. If the A tag is activated at this time, a write sequence is in- dicated. If the B tag is activated at this time, a read sequence is in- dicated. MBA 603 now latches the address in the bus address transmitter latches with the decoded detail information (memory access, I/O access or control function). If the address does not indicate control function or the control function is an INTA-function, mastership of the Multibus is requested. When the second tagsignal arrives and mastership is obtained, the transfer sequence is started. The transfer is synchronized to the on board 20 MHz clock in order to space the single events sufficiently. When acknowledge arrives from the addressed slave on the Multibus or the 9,6 sec. timer runs out (which ever happens first), an acknowledge is generated and sent to the remote MBA, causing this to drop the two tags, which in turn reset the transfer sequence logic terminating the operation. 2_._1_ _ _ _ _ _ _ _A_d_d_r_e_s_s_i_n_g_ 2.1 If the area 00000 to EFFFF is addressed, MRDC or MWTC (Memory Read Command or Memory Write Command) is generated. If the area F0000 to FFFEF is addressed, IORC or IOWC (I/O Read Command or I/O Write Command) is generated. If the area FFFF0 to FFFFF is addressed, special functions (not\f necessarily involving the Multibus) are activated: FFFF0 : INTA read/write FFFF1 : ITRIE M_m_m_ FFFF2 : ITROE write P_p_p_ FFFF3 : INTR FFFF4 : INIT FFFF5 : Reservation 2_._2_ _ _ _ _ _ _ _I_n_t_e_r_r_u_p_t_ _S_e_n_s_e_ 2.2 When the interrupt sense signal is activated by the remote MBA, the MBA 603 presents the masked interrupt situation on the buslines towards the other MBA while activating the acknowledge signal. The masked interrupt situation is a result of the state on the Multibus interrupt lines masked with the ITRIE mask plus the out- going flip-flops ITRO having been cleared since last interrupt sense which are not masked out by means of ITROE. The principle of masking of interrupts is shown for a single interrupt bit in fig. 1. Figure 1: Interrupt generation, one bit. \f 2_._3_ _ _ _ _ _ _ _M_a_s_t_e_r_ _S_e_l_e_c_t_i_o_n_ _L_o_g_i_c_ 2.3 The master selection or arbitor-circuit consists of a synchronous sequence network operating on the 10 MHz BCLK (Busclock) common to all devices on the Multibus. Only one preselected master de- vice on the bus generates BCLK. MBA 603 becomes the BCLK (and CCLK (Common Clock)) generator when the straps ST2 and ST3 are installed. The arbitration among masters on the Multibus may be serial or parallel. In the first case, the buspriority is rippled through each master from one end of the bus to the other. In the parallel arbitration case, a single arbitration unit located at the bus motherboard directly sends buspriority to the highest priority unit requesting mastership. In this case the strap ST4 should be removed. Serial priority is not recommended when more than 3 masters are installed on the same Multibus. When an access on the Multibus is completed, MBA 603 may release the bus immediately or keep the mastership until the next access is performed saving arbitration time, or until someone else requests the bus. If strap ST1 is installed, the first situation is selected. 2_._4_ _ _ _ _ _ _ _S_p_e_c_i_a_l_ _C_o_n_t_r_o_l_s_ 2.4 The following special functions can be controlled from the remote MBA: 1. Generate INTA FFFF0 write 2. Generate INTA and sense vector FFFF0 read 3. Set or clear interrupt mask bit (ITRIE) FFFF1 write 4. Set or clear interrupt mask bit (ITROE) FFFF2 write 5. Set interrupt bit (INTR) FFFF3 write 6. Generate INIT-pulse FFFF4 write 7. Set or clear bus reservation FFFF5 write \f 2_._4_._1_ _ _ _ _ _G_e_n_e_r_a_t_e_ _I_N_T_A_ 2.4.1 This function is used by the remote MBA to service a busvectored interrupt. The sequence is that the other MBA (or the CPU controlling it) issues a generate INTA with an integer in the range 0-7 as param- eter, indicating which interrupt line is to be serviced. This command catches the bus, locks the mastership and generates an INTA pulse of a certain duration (250 nS) on the Multibus not carrying any information nor awaiting XACK. Following this, the remote MBA issues a generate INTA read command, with the effect that the interrupting device sends its interrupt vector to the remote MBA. This transfer is acknowledged in the normal way on the Multibus by means of a XACK. Finally the remote MBA has to issue a clear bus reservation to unlock the mastership allowing other masters to use the Multibus. 2_._4_._2_ _ _ _ _ _S_e_t_ _o_r_ _C_l_e_a_r_ _I_n_t_e_r_r_u_p_t_ _M_a_s_k_s_ 2.4.2 The two interrupt masks ITRIE and ITROE, the functions of which are discussed in section 2.2 are manipulated by these controls. The data sent along with the write commands carry the parameters bit number select and new bit value: bit number + 128*new value. Only the selected bit is affected. 2_._4_._3_ _ _ _ _ _S_e_t_ _I_n_t_e_r_r_u_p_t_ _B_i_t_ 2.4.3 This operation sets the selected interrupt, pulling down the voltage on the corresponding interrupt line. The flip-flop can be reset only by addressing the corresponding slaveaddress from the Multibus or by INIT. \f 2_._4_._4_ _ _ _ _ _G_e_n_e_r_a_t_e_ _I_N_I_T_ 2.4.4 This command generates an INIT pulse with a duration of approxi- mately 10 mS. Before the pulse is started, the INIT input to the connected line is gated off, assuring that this INIT does not cause an autoload in the system controlling the remote MBA. 2_._4_._5_ _ _ _ _ _R_e_s_e_r_v_e_ _B_u_s_ 2.4.5 When this bit is set, the bus will not be released after the next busaccess regardless of CBREQ. This bit is set and cleared by the Reserve Bus command corresponding with the value of the most significant bit in the write data byte. The bit is also set and cleared by the Reserve Bus command corresponding with the value of the most significant bit in the write data byte. The bit is also set when a Generate INTA is issued. 2_._5_ _ _ _ _ _ _ _S_l_a_v_e_ _A_d_d_r_e_s_s_i_n_g_ 2.5 The MBA 603 may be addressed as a slave by other masters on the Multibus (or by itself), with the only purpose to clear the interrupt flip-flops. When one of the eight contiguous addresses preselected on the switches on MBA 603 is addressed with an IOWRT pulse, the corresponding interrupt flip-flop (if set) is cleared, and an interrupt (if enabled) sent to the remote MBA. The address switches are divided into two groups, the most sig- nificant of which may be disregarded if the system supports only eight address lines for I/O. 2_._6_ _ _ _ _ _ _ _R_e_s_e_t_ _a_n_d_ _C_o_n_n_e_c_t_i_o_n_ _S_u_r_v_e_y_ 2.6 As described above, the system is reset by means of a generate INIT command. The "connected" line is checked for a low indicating\f that the other MBA either has no power or is not connected. This condition is used to assure that the Multibus is released in break down situations. An INIT on the Multibus is signalled to the other MBA by pulling down the voltage on the "connected" line. \f F_ 3_._ _ _ _ _ _ _ _ _M_B_A_ _L_I_N_K_ _D_E_F_I_N_I_T_I_O_N_ 3. The inter MBA connection is implemented as a 50 lead ribbon cable carrying 24 balanced signals, one ground line and one unbalanced signal: the "connected" signal. 20 signals carry address from the master MBA to the slave MBA. 16 of these are then used for data transfer in one or the other direction. 3 handshake signals control the data transfer: Atag, Btag and Ack. 1 signal reads the interrupt situation from slave to master: SNSI. 3_._1_ _ _ _ _ _ _ _D_a_t_a_ _a_n_d_ _A_d_d_r_e_s_s_ _L_i_n_e_s_ 3.1 The twenty balanced signals called IBUS(0:15) and ADR(10:13) are used both for addressing and data transfer. During the address phase all twenty carry an address, IBUS(0:15) carrying the least significant 16 bits. During the data phase, IBUS(0:15) carry data. In the case of a Read, data is transferred from the slave MBA to the master MBA, and on a write in the opposite direction. IBUS 0 is the least significant bit. If single bytes are transferred, IBUS(0:7) is used. ADR(13) indicates byte or word to the slave during the data phase. \f 3_._2_ _ _ _ _ _ _ _C_o_n_t_r_o_l_s_ 3.2 The Atag and Btag signals are used by the master MBA to control the transfer. The master MBA rises the Atag or the Btag indicating an address phase for a transfer. If the Atag is rised, a read operation is initiated. If the Btag is rised, a write operation is initiated. After a certain time, the master MBA enters the data phase rising the other tag. If the operation is a read, the transmitters are turned off, if the operation is a write, the address is replaced with the data to be written. The slave rises Ack to indicate that data has been latched or data is available on IBUS(0:15). The master then drops both tags causing the slave to drop Ack terminating the operation. 3_._3_ _ _ _ _ _ _ _S_e_n_s_e_ _I_n_t_e_r_r_u_p_t_ 3.3 The SNSI is set by the master MBA when no transfer is in progress, and the master wishes to sense the interrupt situation on the Multibus. SNSI is handshaked with Ack and differs from a data transfer operation in that no address is involved. The interrupt pattern is transferred on IBUS(8:15), IBUS 8 corresponding to ITR and IBUS15 to ITR7 on the Multibus. \f 3_._4_ _ _ _ _ _ _ _C_o_n_n_e_c_t_e_d_ 3.4 The "connected" signal is used to indicate that connection is established between the MBAs and to reset one MBA (the master) from the other. The signal is unbalanced. In the master it is connected through a 100 Ohm resistor to plus 5 V, and in the slave through a 100 Ohm resistor to a low TTL output. The criterion for a good connection with power on each MBA is that a voltage of approximately 2,5 V (+_ 0,5) exists on the "connected" line. The slave MBA signals a Reset by pulling the "connected" voltage to ground, and that power on condition is not ok by opening the TTL output. \f Timing requirements for MBA 603 Symbol Parameter min max unit tASU address to tag set up time 30 nS tAH address to tag hold time 30 nS tAB tag to tag delay 30 nS tWDSU write data set up time 20 nS tR response time 200 nS tAABH tag hold time from ack 0 nS tACKH ack hold time from tag 0 100 nS tfloat time from busfloat to read tag 0 nS tRDSU time from read data to ack 100 nS tRDH read data hold after ack -20 30 nS tRINTA response from INTA 90 170 nS tIDSU time from INTR data to ack 50 nS tAIH INTA hold time from ack 0 nS tIDH INTR data held after ack -20 30 nS Table 1. \f F_ \f F_ 4_._ _ _ _ _ _ _ _ _B_O_A_R_D_ _L_A_Y_O_U_T_ 4. Location of Components on MBA 603. \f F_ 5_._ _ _ _ _ _ _ _ _L_O_G_I_C_ _D_I_A_G_R_A_M_S_ 5. \f F_ \f F_ S_i_g_n_a_l_ _ _ _ _ _ _ _ _ _D_e_s_t_i_n_a_t_i_o_n_ _ _D_e_s_c_r_i_p_t_i_o_n_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ ADR13/BYTEEN 1,7 Four most significant address bits ADR 10-12 recieved from MBA cable. MEM R/W* 1 Decoding of four most significant address bits saying: not highest 64K. SPECIAL AREA* 1 Decoding of address saying: highest 16 bytes. LATCH ADDRESS 1,7 A tag or B tag active. MEM R/W 2 Latched versions of the decodings SPECIAL AREA 1,2 marked with asterix. ADR 0-3 AREA 1,7,10 Four least significant address bits after latching. -,CATCH BUS 4 Indicates, the Multibus is going to be needed during this operation. INTA OP 2 Partial decoding of function. -,SPEC INTA or 2 \f F_ \f F_ S_i_g_n_a_l_ _ _ _ _ _ _ _ _ _D_e_s_t_i_n_a_t_i_o_n_ _ _D_e_s_c_r_i_p_t_i_o_n_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ WRITE OP 2,8 High if A tag is activated before B tag. -,READ 5,6 Low when A tag and B tag are active A B 2 and B tag came first. The addressphase is finished, and the data phase entered. DELAY1 2 The start of a Multibus operation is synchornized to 20 MHz. COMMAND 2,7,8 Write or Read command is generated. XACKSYNC 2 XACK * syncronized DELAY2 2 XACKSYNC delayed 50 nS. ACK 3 Responce on A and B tags. -,I/O READ 8 These commands are sent to the -,I/O WRITE 8 multibus. -,MEM READ 8 -,MEM WRITE 8 -,SPEC WRITE 10 Low indicates write commands to the MBA. SPEC WRITE 2 -,DELAY 1 2 COMMAND* 2 XACK* 2 True when timeout, xack recieved from multibus, and of spec. op or when XACK is set. T128 2 true after 6,4 S T64 2 true after 3,2 S T8 2 true after 0,4 S \f F_ \f F_ S_i_g_n_a_l_ _ _ _ _ _ _ _ _ _D_e_s_t_i_n_a_t_i_o_n_ _ _D_e_s_c_r_i_p_t_i_o_n_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ -,Atag 1,2 Received Tags. -,Btag 1,2 -,INTAR 5,9,10,11 SNSI received. INTAR 3 -,CLEAR MASTER 4 Clears bus arbitration logic if the remote MBA is not corrected or has no power on. -,CLEAR 4,10,12 Clears registers when INIT is CLEAR 3 received from the Multibus. INIT/ 3 CONNECTED 3 OV if the remote MBA is not connected or has no power on or if INIT is received from the Multibus while no INIT is generated on this MBA. INIT 3 INIT pulse 10 msec generated by means of an INIT command. INTADEL 3 Generates CK as responce to SNS Interrupt. \f F_ \f F_ S_i_g_n_a_l_ _ _ _ _ _ _ _ _ _D_e_s_t_i_n_a_t_i_o_n_ _ _D_e_s_c_r_i_p_t_i_o_n_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ BPRO/ J1-16 Serial Buspriority out. BUSPRIORITY 4 Priority received. CBREQ/ 4,J1-18 Common busrequest. BUSY/ 4,J1-17 The bus is occupied. MASTER* 4 See MASTER BUSREQPRESYNC 4 BUSREQUEST 4 MASTER 4,7 When true, this MBA controls the -,MASTER 2,7 Multibs. LOCK 4 Keeps the mastership between accesses. BCLK/ 4,J1-13 BUS Clock. CCLK/ 4,J1-31 Common Clock NB: One and only one controller on the Multibus must generate BCLK and CCLK. Lock* 4 Controls LOCK controlled by a special write. 10 MHz 4 Clockgenerator outputs. 20 MHz 2 \f F_ \f F_ S_i_g_n_a_l_ _ _ _ _ _ _ _ _ _D_e_s_t_i_n_a_t_i_o_n_ _ _D_e_s_c_r_i_p_t_i_o_n_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ IBUS 8-F 5 Balanced buslines to the remote MBA -,IBUS 8F 5 DI 8-F 1,7,8 Received bussignals. \f F_ \f F_ S_i_g_n_a_l_ _ _ _ _ _ _ _ _ _D_e_s_t_i_n_a_t_i_o_n_ _ _D_e_s_c_r_i_p_t_i_o_n_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ IBUS 0-7 6 Balanced buslines to the remote MBA. -,IBUS 0-7 6 DI 0 1,4,7,8,10 Received bus signals. DI 1-2 1,7,8,10 DI 3 1,8 DI 4-6 1,7,8 DI 7 1,7,8,10 \f F_ \f F_ S_i_g_n_a_l_ _ _ _ _ _ _ _ _ _D_e_s_t_i_n_a_t_i_o_n_ _ _D_e_s_c_r_i_p_t_i_o_n_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ ADR0/-ADDRF/ 9 Multibus address lines. INTA/ J1-33 Multibus Interrupt ack. BHEN/ J1-27 Byte high enable. \f F_ \f F_ S_i_g_n_a_l_ _ _ _ _ _ _ _ _ _D_e_s_t_i_n_a_t_i_o_n_ _ _D_e_s_c_r_i_p_t_i_o_n_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ DO 0-DOF 5,6 Received Multibus Databits. 10WC/ 9 Multibus 10 Write command. \f F_ \f F_ S_i_g_n_a_l_ _ _ _ _ _ _ _ _ _D_e_s_t_i_n_a_t_i_o_n_ _ _D_e_s_c_r_i_p_t_i_o_n_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ -,CLEAR INTR 9,10 Interrupt clear command received from multibus. SLAVE ACK 9 SLAVE ACK 9 Responce to clear interrupt. XACK/ 2 Multibus xfer acknowledge. \f F_ \f F_ S_i_g_n_a_l_ _ _ _ _ _ _ _ _ _D_e_s_t_i_n_a_t_i_o_n_ _ _D_e_s_c_r_i_p_t_i_o_n_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ ITROE 0-7 11 Mask for interrupt when outgoin interrupt is cleared. ITRIE 0-7 11 Mask for ingoing interrupts. -,SINT 0-7 12 Set outgoing interrupts. INTROC 0-7 11 Interrupt when outgoing interrupt is cleared. -,CINT 0-7 12 Clear outgoing interrupt. -,INTA WRITE 4 -,SET ITRIE 10 Special writecommands to the MBA. -,SET ITROE 10 -,SET INTR 10 -,SET RESERVATION 4 INITC 3 \f F_ \f F_ S_i_g_n_a_l_ _ _ _ _ _ _ _ _ _D_e_s_t_i_n_a_t_i_o_n_ _ _D_e_s_c_r_i_p_t_i_o_n_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ IT 0-7 5 Interrupts to the remote MBA. \f F_ \f F_ S_i_g_n_a_l_ _ _ _ _ _ _ _ _ _D_e_s_t_i_n_a_t_i_o_n_ _ _D_e_s_c_r_i_p_t_i_o_n_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ INT 0-7 11 Interrupts received from multibus. \f F_ \f F_ 6_._ _ _ _ _ _ _ _ _P_A_R_T_L_I_S_T_ 6. The following spareparts are applicable for MBA 603. Q_T_Y_ D_E_S_C_R_I_P_T_I_O_N_ _ _ _ _ 2 IC SN 7417 1 IC SN 74425 2 IC SN 74S00 2 IC SN 74S02 2 IC SN 74S04 1 IC SN 74S10 1 IC SN 74S20 1 IC SN 74S37 1 IC SN 74S38 1 IC SN 74S133 1 IC SN 74S138 1 IC SN 74S174 1 IC SN 74S175 1 IC SN 74LS08 4 IC SN 74LS51 1 IC SN 74LS74 3 IC SN 74LS138 1 IC SN 74S64 2 IC SN 74LS175 4 IC SN 74LS240 1 IC SN 74LS244 3 IC SN 74LS259 3 IC SN 74LS279 1 IC SN 74LS374 1 IC SN 74LS393 3 IC SN 74LS533 2 IC SN 74LS534 2 IC AM 25LS2521 5 IC AM 26LS31 6 IC AM 26LS32 1 IC LM 555 \f Q_T_Y_ D_E_S_C_R_I_P_T_I_O_N_ _ _ _ _ 3 Resistor 5% 1/8W 100E 3 Resistor 5% 1/8W 1K 1 Resistor 5% 1/8W 100K 2 Resistor 5% 1/8W 330E 1 Condensator 10% 01F 1 Condensator 5% 63V 220pF 35 Condensator Ceramics 47nF/12V 3 Condensator TANTAL 22F/15V 1 Condensator 5% 63V 100 pF 6 Bourns 4308R-102-151 4*150E 1 IC Oscillator - CC08 20 MHz 7 DIP Switch Interdil 09.16401 1 Resistor 3K 5% 1/8W 1 Condensator 0,1 F \f F_ \f \f F_ S_i_g_n_a_l_ _ _ _ _ _ _ _ _ _D_e_s_t_i_n_a_t_i_o_n_ _ _D_e_s_c_r_i_p_t_i_o_n_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ \f «eof»