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Types: RcTekst
Names: »99109944.WP«
└─⟦670c8f5a6⟧ Bits:30005866/disk2.imd Dokumenter i RcTekst format (RCSL 99-1-*)
└─⟦this⟧ »99109944.WP«
╱04002d4e0c00060000000003014831600000000000000000000000000000000000000000000000002d37414b555f69737d8791ffffffffff04╱
↲
╞ __________________________↲
╞ Edition:╞ 1984.11.20↲
╞ Author: ╞ Peter Lundbo↲
╞ RCSL No.:╞ 99 - 1 - 09944↲
↲
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INTERNAL DOCUMENT↲
↲
↲
↲
↲
↲
↲
________________________________________________________________________↲
↲
Title:↲
↲
ETC 601 Hardware Selftest↲
User's Manual↲
Version 1.0↲
↲
↲
↲
________________________________________________________________________↲
════════════════════════════════════════════════════════════════════════
↓
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-----------------------------------------------------------------------↲
KEYWORDS :↲
↲
ETC 601, RC 3900, Intel, Multibus, Hardware Selftest.↲
↲
↲
↲
↲
↲
↲
----------------------------------------------------------------------↲
ABSTRACT :↲
↲
┆84┆This manual covers the ETC 601 (Ethernet Controller) Hardware ↓
┆19┆┆8a┆┄┄Selftest program installed in on-board PROM's together with ↓
┆19┆┆8a┆┄┄the bootloader.↲
↲
↲
↲
↲
↲
(56 printed pages)↲
════════════════════════════════════════════════════════════════════════
↓
┆06┆i↲
↲
┆b0┆┆a1┆TABLE OF CONTENTS┆05┆PAGE↲
↲
╱04002d4e0c0006000000000301483160000000000000000000000000000000000000000000000000050a0f17464b555f69737dffffffffff04╱
╱04002d4e0c00060000000003014831600000000000000000000000000000000000000000000000002d37414b555f69737d8791ffffffffff04╱
↓
↲
↲
1.╞ INTRODUCTION ................................................... 1↲
1.1 The Object of the Tests ................................... 2↲
1.2 Automatic Configuration ................................... 2↲
1.3 Selftest Equipment ........................................ 3↲
1.4 List of Included Tests .................................... 3↲
↲
2.╞ Testadministraor ............................................... 5↲
2.1 Operator Stimuli of the Selftest .......................... 5↲
2.2 Parameters ................................................ 9↲
2.3 Test Numbers .............................................. 11↲
2.4 Output from a Test ........................................ 12↲
2.5 Default Interrupt Handling ................................ 12↲
2.5.1 Instruction Exception .............................. 12↲
2.5.2 Illegal Interrupt .................................. 13↲
↲
3. I/O Procedure and Table Indexing ............................... 15↲
3.1 Input ..................................................... 15↲
3.2 Output .................................................... 15↲
3.3 Test Selection ............................................ 15↲
↲
4. Selftest Switch Settings ....................................... 17↲
↲
5. Initialization ................................................. 18↲
5.1 Wait States ............................................... 18↲
5.2 iAPX186 Interrupt Controller .............................. 18↲
5.3 Programmable Interrupt Controller 8259 .................... 19↲
5.4 iAPX186 Timer 1 ........................................... 19↲
5.5 MPSC 8274 Ch. B (Console Interface) ....................... 20↲
5.6 Bustest, Chip Select ...................................... 20↲
↲
6. Automatic Baud Rate Determination .............................. 22↲
↲
7.╞ The Selftest Snooper ...........................................╞ 23↲
7.1 Press <R> ................................................. 24↲
7.2 Press <S> ................................................. 24↲
↲
════════════════════════════════════════════════════════════════════════
↓
┆06┆ ii↲
↲
┆a1┆┆b0┆TABLE OF CONTENTS PAGE╞ ↲
↲
7.3 Press <I> ................................................. 25↲
7.4 Press <O> ................................................. 25↲
↲
┆a1┆┆e1┆8┆e1┆. Test 0 = Memory Test ........................................... 27↲
8.1 PROM Checksum Test ........................................ 27↲
8.2 RAM Memory Test ........................................... 28↲
8.2.2 Memory Test Pattern ................................ 28↲
↲
9. Test 1 = RAM Refresh Test ...................................... 30↲
↲
10. Test 2 = iAPX186 DMA Test ...................................... 31↲
↲
11. Test 3 = PIC (8259) Interrupt Test ............................. 34↲
↲
12. Test 4 = iAPX186 Interrupt Test ................................ 35↲
↲
13. Test 5 = Ethernet Test 2 ....................................... 36↲
↲
14. Test 6 = 8274 ChA Test ......................................... 38↲
↲
15. Test 7 = Floppy Test ........................................... 42↲
╞ 15.1 Test Results .............................................. 42↲
15.2 The Test Disk ............................................. 44↲
↲
16. Multibus Configuration and Test Monitor ........................ 45↲
╞ 16.1 Automatic Configuration ................................... 45↲
16.2 "Test Slave" Management ................................... 46↲
16.3 Bootload .................................................. 47↲
↲
17. ETC601 as a "Test-Slave" ....................................... 48↲
↲
↲
┆b0┆┆a1┆APPENDIX↲
↲
A. LAYOUT OF THE MASTER TO SLAVE COMMUNICATION BUFFER ............ 49↲
↲
════════════════════════════════════════════════════════════════════════
↓
┆14┆┆b3┆┆06┆┆0b┆↲
┆b0┆┆a1┆1. Introduction.↲
↲
↲
RC3900 is a family based on the Intel Multibus card format. ↓
An actual configuration may consists of one or more CPU-boards, ↓
one or more communication controllers (COM601) and a number of ↓
other controllers. The ETC601 which is covered by this manual may ↓
in some system be the main CPU board, whereas in others it may be ↓
a communication controller only.↲
↲
These Single Board Computers (SBC) may each be considered as ↓
intelligent units. Some with the role as potentional Multibus ↓
masters (ETC601), and some as potentional slaves (COM601).↲
↲
Every RC-manufactured intelligent Multibus SBC will contain a ↓
built-in PROM-based selftest program which can be considered as ↓
an integrated part of the SBC bootload-facility. In other words ↓
the power up of a system could be devided into three phases. The ↓
first would be an initialization of the onboard controller chips. ↓
Second would be a selftest of each SBC, terminated by a ↓
centrallization of informations in one of the boards connected to ↓
the Multibus, namely the "test-master". The third phase is a ↓
common bootload of all boards connected to the Multibus.↲
↲
In the test-phase, an RC3900 system, must be considered as ↓
consisting of one and only one "test-master" card and a number of ↓
"test-slave" cards. After power on the "test-master" and "test-↓
slaves" execute their selftest programs concurrently. When the ↓
"test-master" has finished it's own selftest, it will be able to ↓
monitor messages from the "test-slaves", and to influence these ↓
to i.e. loop in a specific test several times. This means, that ↓
the "test-master" may act as an intelligent monitor for a ↓
debugging session on the "test-slaves".↲
↲
↲
════════════════════════════════════════════════════════════════════════
↓
┆81┆┆b0┆┆a1┆┆f0┆1.1 The Object of the Tests.↲
↲
↲
It is the intention of this system of SBC-selftests to cover ↓
three in the nature different needs.↲
↲
↲
a) ┆84┆The RC3900 is equipped with a power up selftest, consisting of ↓
┆19┆┆83┆┄┄a sequence of different test programs. These tests are ↓
┆19┆┆83┆┄┄organized with rising complexity, so that as far as possible ↓
┆19┆┆83┆┄┄no part of the hardware is used, before it is tested. It ↓
┆19┆┆83┆┄┄should establish a basic level of confidence to the hardware ↓
┆19┆┆83┆┄┄included in the RC3900 system. It requires no interaction from ↓
┆19┆┆83┆┄┄the operator.↲
↲
b) ┆84┆It gives the production department the possibility of using ↓
┆19┆┆83┆┄┄the same test programs as a burn-in facility. This is uptained ↓
┆19┆┆83┆┄┄by the fact that the test programs may be controlled from a ↓
┆19┆┆83┆┄┄connected console. The tests in the ETC601 may each either run ↓
┆19┆┆83┆┄┄in loop-mode, or in a big sequencial loop including all tests. ↓
┆19┆┆83┆┄┄Furthermore there is a possibility of having several SBC's ↓
┆19┆┆83┆┄┄running their tests in parallel, and make them repeat it in ↓
┆19┆┆83┆┄┄the infinite, under the controle of a "test-master".↲
↲
c) ┆84┆It supplies the Technical Service Department with a diagnostic ↓
┆19┆┆83┆┄┄tool, that will assist them during their debugging sessions.↲
↲
↲
┆b0┆┆a1┆┆f0┆1.2 Automatic Configuration.↲
↲
↲
The selftest of the ETC601 consists of a set of different ↓
testprograms which is run in sequence. When the selftest runs in ↓
the default mode with no operator interference, then the selftest ↓
terminates by performing a configuration of the Multibus address-↓
space. It will act as a "test-master" and collect test results ↓
from all connected RC-manufactured SBC's. If none of the ↓
connected SBC's has exhibited an error during the selftest, then ↓
the complete system will enter its bootload phase.↲
↲
┆8c┆┆83┆┆e0┆↓
It is possible by operator intervention to prevent the system ↓
from entering the bootload phase, and instead enter an ↓
interactive test mode. This gives the possibility of monitoring ↓
tests executed cuncurrently on several "test-slaves".↲
↲
↲
┆b0┆┆a1┆┆f0┆1.3 Selftest Equipment.↲
↲
↲
One of the extended tests, the 8274 ChA test (not run by default) ↓
requires a loopback cable either CBL 788 (rear cabinet) or CBL ↓
789 (card edge) to be installed.↲
↲
Another extended test the floppy test requires an iSBX board ↓
named FDC601 to be installed and connected to a 5 1/4" floppy ↓
disk drive.↲
↲
↲
┆b0┆┆a1┆┆f0┆1.4 List of Included Tests.↲
↲
↲
Besides the test programs, the RC3900, SBC Selftests includes a ↓
test administrator and a library of some simple input and output ↓
routines.↲
↲
The simple test administrator administers the mode in which a ↓
particular test is run. Different modes is determined by ↓
parameter settings. See chapter 2.↲
↲
The test programs are as follows:↲
↲
Simple Bustest - ┆84┆a part of the initialization. This test ↓
┆19┆┆9a┆┄┄may be selected by the 8255 switch PA3 ↓
┆19┆┆9a┆┄┄and is intended to be used for complex ↓
┆19┆┆9a┆┄┄fault finding of bus errors.↲
↲
PROM checksum test - ┆84┆a simple PROM checkseum is calculated. ↓
┆19┆┆9a┆┄┄It is only executed once after each ↓
┆19┆┆9a┆┄┄power up unitialization.↲
↲
┆8c┆┆83┆┆e0┆↓
RAM memory test - ┆84┆a modulus 3 pattern test of the board ↓
┆19┆┆9a┆┄┄resident RAM memory.↲
↲
RAM refresh test - ┆84┆a test of the automatic refreshing of ↓
┆19┆┆9a┆┄┄the RAM-memory.↲
↲
iAPX186 DMA test - ┆84┆a test of the iAPX186 on-chip DMA ↓
┆19┆┆9a┆┄┄controller.↲
↲
iAPX186 interrupt test - ┆84┆a test of the on-chip interrupt ↓
┆19┆┆9a┆┄┄controller and its ability to receive ↓
┆19┆┆9a┆┄┄interrupts from the on-chip timer.↲
↲
8259 interrupt test - ┆84┆a test of the 8259 interrupt controller ↓
┆19┆┆9a┆┄┄and its ability to receive a flagbyte ↓
┆19┆┆9a┆┄┄interrupt.↲
↲
Ethernet test 2╞ - ┆84┆a test that makes an external loop back ↓
┆19┆┆9a┆┄┄data transport with the Ethernet ↓
┆19┆┆9a┆┄┄Controller.↲
↲
8274 CHA test╞ ╞ - ┆84┆a test that makes an external loop back ↓
┆19┆┆9a┆┄┄data transport on the 8274 MPSC ↓
┆19┆┆9a┆┄┄controller channel A.↲
↲
Floppy test╞ ╞ - ┆84┆a test that verifies the iSBX interface ↓
┆19┆┆9a┆┄┄where a FDC601 Floppy Disc Controller ↓
┆19┆┆9a┆┄┄should be attached.↲
↲
Multibus Test Monitor - ┆84┆a Monitor that supplies the operator ↓
┆19┆┆9a┆┄┄with remote control the execution of ↓
┆19┆┆9a┆┄┄other SBC selftests.↲
↲
Messages from the test programs are explained along with the ↓
description of the individual test loops. The message "OK" is ↓
used by all test programs, and indicates that no error has been ↓
detected.↲
════════════════════════════════════════════════════════════════════════
↓
┆b0┆┆a1┆2. Testadministrator.↲
↲
↲
The ETC601 SBC Selftest is equipped with a simple test ↓
administrator, that administers the mode in which a particular ↓
test is executed.↲
↲
The selftest consists of a set of test programs and a Multibus ↓
configuration module. By default all the tests are run sequential ↓
and terminated by entering the bootloader. The main purpose of ↓
the testadministrator is to compute the address of the next test ↓
in sequence and to generate error messages to the console.↲
↲
The mode and sequence in which the tests are executed may be ↓
controlled from a connected console.↲
↲
Note that the ETC601 SBC Selftest is equipped with two versions ↓
of the testadministrator, one when configurated as a "test-↓
master" and another when configurated as a "test-slave". Which of ↓
the two that is active is determined by the 8255, PA2 strap ↓
(S23), see chapter 4.↲
↲
The description of the differences in the testadministrator, when ↓
in "test-slave" mode is in chapter 17.↲
↲
Fig. 1 gives a simple overview of the Selftest program flow.↲
↲
↲
┆b0┆┆a1┆┆f0┆2.1 Operator Stimuli of the Selftest.↲
↲
↲
The ETC601 SBC Selftest recognizes receive interrupts from the ↓
8274 USART and reads the corrosponding character, which enables ↓
operator manipulation of the Selftest flow. It is a fact, that ↓
the ETC601 SBC Selftest is designed to ensure "no stop" in the ↓
default power up bootload. Therefore be aware, that if any ↓
manipulation of the test flow is wanted, that be looping in the ↓
ETC601 Selftest or monitoring of "test-slaves", the decision must ↓
┆8c┆┆83┆┆c8┆↓
be taken before the bootloading is started, else the control is ↓
lost.↲
════════════════════════════════════════════════════════════════════════
↓
↲
════════════════════════════════════════════════════════════════════════
↓
The ETC601 SBC Selftest is sensitive to several kinds of inputs, ↓
which has different meanings:↲
↲
Press <esc> : ┆84┆enables interactive change of program flow ↓
┆19┆┆93┆┄┄parameters. See section 2.2.↲
↲
Press <cntrl><@> : ┆84┆starts the test snooper facility. See chapter ↓
┆19┆┆93┆┄┄7.↲
↲
Press <cntrl><Q> : ┆84┆quit present state. This could be an error-↓
┆19┆┆93┆┄┄halt condition or the Multibus test monitoring ↓
┆19┆┆93┆┄┄of "test-slaves".↲
↲
Press <cntrl><S> : ┆84┆request Multibus test monitoring of "test-↓
┆19┆┆93┆┄┄slaves" at the end of the ETC601 selftest.↲
↲
If any other character is typed the ETC601 SBC Selftest will ↓
respond with the following menu and wait for yet another ↓
character to continue.↲
↲
┆f0┆----MENU----↲
<esc> : change parameters↲
<cntrl><@> : enter snooper↲
<cntrl><Q> : quit present state↲
<cntrl><S> : request debug of test slaves↲
test no.:↲
00007: Floppy test↲
00006: 8274 CHA test↲
00005: Ethernet test 2↲
00004: iAPX186 slave interrupt test↲
00003: PIC test↲
00002: iAPX186 DMA test↲
00001: RAM refresh test↲
00000: memory test↲
----MENU----↲
↲
Figure 2: Selftest menu.↲
↲
┆8c┆┆83┆┆c8┆↓
┆a1┆2.2 Parameters.↲
↲
↲
The flow of the ETC601 SBC Selftest is based upon the fact that ↓
each test program receives a set of parameters as input and ↓
deliveres a buffer of error informations as output.↲
↲
The parameters are contained in a 16 bit word variable, a ↓
socalled switch variable, which survives the memory test in an ↓
internal iAPX186 CPU register. This variable contains the ↓
information necessary for the test administrator to manage the ↓
flow of the test program.↲
┆8c┆┆81┆┆90┆↓
┆0e┆↓
↲
┆a1┆name initial value ┆06┆comment┆05┆↲
halt bit 1 1: ┆84┆halts execution when an error is ↓
┆19┆┆a0┆┄┄discovered.↲
0: bypasses errors.↲
↲
loop bit 0 1: ┆84┆repeats the selection of the test ↓
┆19┆┆a0┆┄┄specified.↲
0: sequential flow.↲
↲
wait bit 0 1: ┆84┆used in the configuration phase ↓
┆19┆┆a0┆┄┄by the "test slaves".↲
0: ┆84┆release "test-slaves" (only ↓
┆19┆┆a0┆┄┄internal).↲
↲
boot bit 1 1: ┆84┆configurate and bootload after ↓
┆19┆┆a0┆┄┄end of selftest.↲
0: repeat own selftest.↲
↲
status bit 0 1: ┆84┆suppress status check.↲
0: perform status check.↲
↲
data bit 0 1: suppress data check.↲
0: perform data check.↲
↲
not used 0↲
↲
┆a1┆not used 0 ┆05┆↲
┆a1┆test.no. 00 identification of test program┆05┆↲
↲
Figure 3: Test parameter variable.↲
┆0f┆↓
↲
It is possible for the operator to manipulate these parameters by ↓
typing <esc>. this will cause the following questions, which must ↓
be answered one by one, to appear on the screen.↲
↲
============== Onboard memory size (k bytes): 00256↲
halt on error ? <Y/N>, Y/↲
┆8c┆┆83┆┆c8┆↓
loop ? <Y/N>, N/↲
boot after test ? <Y/N>, Y/↲
suppress status check ? <Y/N>, N/↲
suppress data check ? <Y/N>, N/↲
test no.: 00000/↲
↲
Figure 4: parameter setting.↲
↲
The answers to the "<Y/N>" questions are "Y", "N" or carriage ↓
return.↲
↲
The answer to the "test no.:" question is a legal test number ↓
and/or carriage return.↲
↲
↲
┆b0┆┆a1┆┆f0┆2.3 Test Numbers.↲
↲
↲
The relationship between test numbers and actual test programs ↓
are as follows:↲
┆0e┆↓
↲
┆a2┆┆e2┆┆a1┆Test No Test name ↲
0 memory test↲
1 RAM refresh test↲
2 iAPX186 DMA test power up↲
3 PIC test╞ ╞ tests↲
┆a1┆ 4 iAPX186 slave interrupt test↲
┆a1┆┆e1┆ 5 Ethernet test 2↲
6 8274 CHA test╞ ╞ extended↲
┆a1┆ 7╞ Floppy test┆e1┆╞ ╞ tests↲
┆0f┆↓
↲
The tests numbered 5-7 are not run in the default power up ↓
sequence. They are included as extended tests and must be ↓
requested explicit by operator intervention.↲
↲
↲
════════════════════════════════════════════════════════════════════════
↓
┆b0┆┆a1┆┆f0┆2.4 Output From a Test.↲
↲
↲
At the end of every test program, the selftest will inform about ↓
its state, ok or error, to the operator via the connected ↓
console. The format will normally look as follows:↲
╱04002d4e0a0006000000000201413100000000000000000000000000000000000000000000000000050f19232d37414b555f69737d8791ff04╱
╱04002d4e0c0006000000000301483160000000000000000000000000000000000000000000000000050a0f17464b555f69737dffffffffff04╱
↓
↲
<OK>↲
<test name:> , N↲
<error type> , <text><error data> ↲
0↲
╱04002d4e0a0006000000000301413100000000000000000000000000000000000000000000000000050f19232d37414b555f69737d8791ff04╱
╱04002d4e0a0006000000000201413100000000000000000000000000000000000000000000000000050f19232d37414b555f69737d8791ff04╱
↓
↲
<error type> is a primary errortext informing about the specific ↓
error. <text> is of the kind "addr:", "exp:" and the like.↲
↲
↲
┆b0┆┆a1┆┆f0┆2.5 Default Interrupt Handling.↲
↲
↲
When the ETC601 SBC Selftest has finished the memory test, a set ↓
of default interrupt vectors are placed in the interrupt vector ↓
table. These vectors are primarily used to handle unexpected ↓
interrupts. There are two kinds of unexpected interrupts. The ↓
first is handled by the interrupt procedure for internal iAPX186 ↓
instruction interrupts and the second is handled by the interrupt ↓
procedure for illegal device interrupts.↲
↲
↲
┆b0┆┆a1┆┆f0┆2.5.1 Instruction Exception.↲
↲
↲
If an Instruction Exception interrupt occurs, it is likely to ↓
believe that this was caused by a malfunction of the iAPX186, ↓
because this interrupt is related to some CPU instructions.↲
↲
If this error should occur it will produce the following ↓
errortext:↲
↲
┆b0┆╞ ╞ ">> instruction exception"↲
↲
The corrosponding error number is 8.↲
↲
↲
┆8c┆┆83┆┆f0┆↓
┆b0┆┆a1┆┆f0┆2.5.2 Illegal Interrupt.↲
↲
↲
At the end of every test loop the reception of interrupts are ↓
enabled. Only two of the interrupt request lines will be used in ↓
the Selftest. This is the MPSC 8274 receive interrupt which is ↓
connected to the 80186 interrupt request INT1 and the parity ↓
interrupt which is connected to the 8259 interrupt request IR3.↲
↲
↲
All other interrupt requests will be decoded as illegal ↓
interrupts and will produce the following errortext:↲
↲
┆b0┆╞ ╞ "illegal interrupt"↲
↲
followed by the information about, which level was issuing the ↓
interrupt.↲
↲
The corresponding error number is 5.↲
↲
↲
In the PIC interrupt test and the Multibus interrupt test an ↓
"illegal interrupt" error is produced if it is impossible to ↓
clear the interrupt following the test. This may happen if a ↓
jumper in the interrupt strap area S6 is missing.↲
┆8c┆┆82┆┆ac┆↓
┆0e┆↓
↲
┆a1┆Interrupt name Vector type Related instructions┆05┆↲
Divide Error 0 DIV, IDIV↲
Single step 1 ALL↲
NMI 2 ALL↲
Breakpoint 3 INT↲
INT0 Detected 4 INT0↲
overflow↲
Array Bounds 5 BOUND↲
Unused Opcode 6 Undefined Opcodes↲
┆a1┆ESC Opcode 7 ESC Opcodes┆05┆↲
┆a1┆Interrupt name Vector type Related interrupt level┆05┆↲
Timer 0 Interrupt 8 8↲
Reserved 9 -↲
DMA 0 Interrupt 10 10↲
DMA 1 Interrupt 11 11↲
INT0 Interrupt 12* 12↲
INT1 Interrupt 13** 13↲
INT2 Interrupt 14* 14↲
INT3 Interrupt 15** 15↲
Timer 1 Interrupt 18 8↲
┆a1┆Timer 2 Interrupt 19 8┆05┆↲
8259 IR0 20 20↲
8259 IR1 21 21↲
8259 IR2 22 22↲
Par-int 23 23↲
8259 IR4 24 24↲
8259 IR5 25 25↲
8259 IR6 26 26↲
8259 IR7 27 27↲
↲
Figure 5: Interrupt Level Table.↲
↲
* INT0 and INT2 are used as INT0 and INTA0 for the 8259.↲
** INT1 and INT3 are used as INT1 and INTA2 for the 8274 MPSC.↲
┆0f┆↓
════════════════════════════════════════════════════════════════════════
↓
┆b0┆┆a1┆┆b0┆3. I/O Procedures and Table Indexing.↓
↲
↲
Included in the ETC601 SBC Selftest is a rather simple handling ↓
of console input and output. Furthermore it uses array tables to ↓
decide which test is to be started and which errortext is to be ↓
written.↲
↲
↲
┆b0┆┆a1┆┆f0┆3.1 Input.↲
↲
↲
Input is handled in the most simple way possible. It works ↓
operator interactive using the one character buffer in the USART ↓
itself.↲
↲
USART receive interrupts is only used to give different ↓
attentions to the selftest. These are <esc>, <cntrl><@>, ↓
<cntrl><Q>, and <cntrl><S>. See section 2.1.↲
↲
↲
┆b0┆┆a1┆┆f0┆3.2 Output.↲
↲
↲
The testoutput from the selftest is a character by character ↓
output without any interrupt generation. The condition for ↓
sending a character to the MPSC 8274 is the status, transmitter ↓
buffer empty.↲
↲
┆b0┆┆a1┆┆f0┆3.3 Test Selection.↲
↲
↲
The test number field of the test parameter switch (see fig. 3) ↓
is used to select the next test to be run. This number is an ↓
index in an array, which for every test contains the offset to ↓
the introduction text and the starting address.↲
↲
┆8c┆┆83┆┆bc┆↓
The ETC601 SBC Selftest will always write the test introduction ↓
text before the test is started.↲
════════════════════════════════════════════════════════════════════════
↓
┆b0┆┆a1┆4┆a1┆. Selftest Switch Settings.↲
↲
↲
The ETC601 is equipped with a Selftest configuration switch ↓
(S23), which is connected to the 8255, PA port.↲
↲
PA, bit 0-1 : ┆84┆These bits are used by the memory test to determine ↓
┆19┆┆8e┆┄┄the onboard memory size.↲
↲
PA, bit 2 : ┆84┆this bit is used to configurate the CPU as a "test-↓
┆19┆┆8e┆┄┄host" or "test-slave".↲
↲
PA, bit 3 : ┆84┆This bit, if "1", will cause the Selftest to ↓
┆19┆┆8e┆┄┄continously run in a loop that is testing the CPU ↓
┆19┆┆8e┆┄┄to memory bus and generate chip select on all ↓
┆19┆┆8e┆┄┄onboard controller chips. See chapter 7. This is ↓
┆19┆┆8e┆┄┄intended for complex fault finding.↲
↲
PA, bit 4 : ┆84┆this bit, if "1" makes the testprogram to assume an ↓
┆19┆┆8e┆┄┄8 MHz CPU installed. This information is used to ↓
┆19┆┆8e┆┄┄control the on-chip timer used as baudrate ↓
┆19┆┆8e┆┄┄generator.↲
↲
╞ ╞ ╞ ╞ ╞ 00 : 128 Kbytes RAM↲
. . . . .╞ ╞ ╞ ╞ 01 : 256 Kbytes RAM↲
1┆b0┆.┆f0┆ . . . .╞ ╞ ╞ ╞ 10 : 512 Kbytes RAM↲
! ! ! ┆a1┆! ! 11 : 1 Mbytes RAM ╞ ↲
! ! !↲
! ! !╞ ╞ ╞ ╞ 0 : Master ETC601↲
! ! !┆a2┆┆a1┆┆e2┆ ╞ ╞ ╞ ╞ 1 : Slave ETC601 ↲
! !↲
! !╞ ╞ ╞ ╞ 0 : Normal mode↲
! !┆a1┆╞ ╞ ╞ ╞ 1 : Chip select mode ↲
!↲
!╞ ╞ ╞ ╞ 0 : 6 MHz iAPX186 ↲
!┆a1┆ ╞ ╞ ╞ ╞ 1 : 8 MHz iAPX186 ↲
↲
┆a1┆┆e1┆┆e1┆┆e1┆↲
┆a1┆Figure 8 : The S23 jumper area.↲
════════════════════════════════════════════════════════════════════════
↓
┆b0┆┆a1┆5. Initialization.↲
↲
↲
After power up/reset the ETC601 SBC Selftest will perform some ↓
initializations of the onboard controllers.↲
↲
The initializations are common for the Selftest and the ↓
bootloader.↲
↲
↲
┆b0┆┆a1┆┆f0┆5.1 Wait States.↲
↲
↲
The PROM and RAM memory will have 0 wait states.↲
↲
Pheripherals on PCS 0-3 will have 1 wait state↲
Pheripherals on PCS 4-6 will have 2 wait states.↲
↲
↲
┆b0┆┆a1┆┆f0┆5.2 iAPX186 Interrupt Controller.↲
↲
↲
The interrupt vector for the iAPX186 controllers is tied to ↓
specific memory locations, equal to the location 20H for the ↓
first vector in the table. See section 2.5.↲
↲
╞ ┆1f┆┆a1┆INT0/INT2:↲
Port : FF38H↲
Value : 37H↲
↲
These two pins of the iAPX186 is used for cascading to the extern ↓
interrupt controller 8259.↲
↲
╞ ┆a1┆INT1/INT3:↲
Port : FF3AH↲
Value : 37H↲
↲
┆8c┆┆83┆┆bc┆↓
These two pins of the iAPX80186 is used for cascading to the MPSC ↓
8274.↲
↲
╞ ┆a1┆Mask Register:↲
Port : FF28H↲
Value : FDH↲
↲
Which will mask the following:↲
↲
╞ I3 : 1╞ ; INT3↲
╞ I2 : 1╞ ; INT2↲
╞ I1 : 1╞ ; INT1↲
╞ I0 : 0╞ ; INT0↲
╞ D1 : 1╞ ; DMA1↲
╞ D0 : 1╞ ; DMA0↲
╞ TRM : 1╞ ; Timers↲
↲
↲
┆b0┆┆a1┆┆f0┆5.3 Programable Interrupt Controller 8259.↲
↲
↲
The ETC601 SBC Selftest is configurated with USART parity ↓
interrupt connected to IR3.↲
↲
╞ ┆a1┆8259 setup:↲
ICW 1 : 1BH ; level triggered input, single mode↲
ICW 2 : 20H ; the interrupt vector table starts in 80H↲
ICW 4 : 1DH ┆84┆; non buffer mode, normal EOI and not fully ↓
┆19┆┆95┆┄┄; nested.↲
MASK : F7H ; enable parity interrupt on IR3.↲
↲
↲
┆b0┆┆a1┆┆f0┆5.4 iAPX186 Timer 1.↲
↲
↲
Timer 1 is initialized as a baudrate generator in alternating ↓
mode with even duty cycle. If no console is connected the ↓
baudrate is set to 9600 baud, otherwise the Baud Rate ↓
Determination procedure is entered see chapter 6.↲
↲
↲
┆8c┆┆83┆┆ec┆↓
┆b0┆┆a1┆┆f0┆5.5 MPSC 8274 Ch. B (Console Interface).↲
↲
↲
Baudrate factor : X16↲
Character length : 8 bits↲
Parity : none↲
Stop bits : 2↲
Mode : asynchronous.↲
↲
↲
┆b0┆┆a1┆┆f0┆5.6 Bustest, Chip Select.↲
↲
↲
To ease complex debugging, a CPU to memory bustest and a chip ↓
select loop are supplied as a function of the 8255 PA3 bit.↲
↲
If the 8255 PA3 bit is set to "1" both the bustest and the chip ↓
select loop are executed. First there will be performed input ↓
instructions on all relevant I/O-devices. These are:↲
↲
Port 0, 80H, 100H, 180H, 182H, 184H, 186H, 190H, 1C0H, 1C2H, ↓
200H, 280H and 300H.↲
↲
This might be used for measurements.↲
↲
Secondly a CPU to memory bustest is performed. This loop will use ↓
one word in the RAM-memory. This word is initialized with a zero, ↓
whereafter a one-bit is shifted from the LSB towards the MSB. For ↓
every shift, the pattern is read and checked. Should it occur, ↓
that the pattern was not written, the program will loop ↓
continously trying to read the correct pattern. This means, that ↓
if the bus signals are checked by an oscilloscope and the word ↓
read is found to have the bits 0 and 1 to the one level and the ↓
rest to the zero level, it must be bit 2, that contains the ↓
error.↲
↲
When the one-bit has been shifted through the entire word, this ↓
word is reinitialized to all ones and a zero-bit is shifted ↓
through it.↲
↲
┆8c┆┆83┆┆e0┆↓
If the 8255 PA3 bit is strapped to "0", these measurement loops ↓
are bypassed when powering up.↲
════════════════════════════════════════════════════════════════════════
↓
┆a1┆┆b0┆6. Automatic Baud Rate Determination.↲
↲
↲
After power on or external reset the selftest determines whether ↓
a console is present or not by sampling the DSR signal.↲
↲
If a console is present then the selftest enters the Automatic ↓
Baud Rate determination phase, otherwise the baud rate is set to ↓
9600 Baud and the selftest proceeds.↲
↲
In the Automatic Baud Rate Determination phase the test program ↓
initializes the console to 9600 Baud, and starts to write * ↓
(stars) to the console. Note that the appearance on the operator ↓
console may not be stars, worst case nothing is seen at all. The ↓
selftest waits for the operator to type one or two upper case U, ↓
this will allow the selftest to determine the baud rate of the ↓
attached console. After the determination of the baud rate the ↓
test proceeds. Baud rate recognized are 300, 600, 1200, 2400, ↓
4800 and 9600 Baud.↲
════════════════════════════════════════════════════════════════════════
↓
┆b0┆┆a1┆7. The Selftest Snooper.↲
↲
↲
The ETC601 SBC Selftest is equipped with a socalled Snooper ↓
facility, which enables the user to manipulate with RAM data and ↓
input, output ports. It is envoked by entering af <cntrl><@> on ↓
the connected console.↲
↲
The Snooper can be entered at the termination of any of the test ↓
programs.↲
↲
When the Snooper is entered, it will respond with the following ↓
menu:↲
↲
>> Snooper↲
↲
<R> : display memory↲
<S> : substitute word↲
<I> : input from port↲
<O> : output to port↲
<,> : continue selected↲
<X> : exit from snooper↲
↲
*** Note: ┆84┆that canging the content of RAM memory words or ↓
┆19┆┆8a┆┄┄performing output to devices may have som drastic ↓
┆19┆┆8a┆┄┄effect to the Selftest system.↲
↲
When entering the character "X" on the connected console, the ↓
Snooper will return control to the Selftest, which will proceed ↓
its operation.↲
↲
The Snooper works in an interrupt disabled mode.↲
↲
↲
════════════════════════════════════════════════════════════════════════
↓
┆b0┆┆a1┆┆f0┆7.1 Press <R>.↲
↲
↲
When the character "R" has been selected, the following two ↓
questions concerning the address will be asked:↲
↲
Segm.: _ _ _ _ Addr.: _ _ _ _↲
↲
These questions must be answered with the address of the first ↓
memory word to be displayed.↲
↲
When the address has been selected, 100 - 16 bit words will be ↓
shown on the display of the connected console. The format of the ↓
output is 20 lines each with the content of 5 words. It is shown ↓
in hexadecimal and in ascii.↲
↲
The following 100 words will be displayed if a "," is entered.↲
↲
A new first address can be selected by reentering the character ↓
"R".↲
↲
↲
┆b0┆┆a1┆┆f0┆7.2 Press <S>.↲
↲
↲
When the character "S" has been selected, the following two ↓
questions concerning the address will be asked:↲
↲
Segm.: _ _ _ _ Addr.: _ _ _ _↲
↲
These questions must be answered with the address of the first ↓
word to be changed.↲
↲
When the address has been selected, the first word is displayed.↓
Now there are two possibilities, either to fill in a new value or↓
to press ",".↲
↲
A new value may consist of from one up to four digits. If less↓
than four digits is input, the number will be entered by pressing↓
"return".↲
↲
┆8c┆┆83┆┆ec┆↓
When a new value has been entered, the value of the next word is ↓
shown.↲
┆b0┆┆a1┆↲
If the character "," is entered, the memory word displayed is ↓
left unchanged, and the next word is displayed.↲
↲
The way to escape the substitute session, is to select a new ↓
function or to exit the snooper.↲
↲
It is possible to fill an amount of i.e. the DMA-transmit buffer ↓
with a certain data pattern by pressing repeat and the data (e.g. ↓
0-F). This is due to the fact that entering 4 digits, will ↓
automatically enter these data into the word and continue with ↓
the next word.↲
↲
↲
┆b0┆┆a1┆┆f0┆7.3 Press <I>.↲
↲
↲
When the character "I" has been selected the Snooper will respond ↓
with the question:↲
↲
port: _ _ _ _↲
↲
When a port number has been entered, the 16 bit word contained in ↓
this port is shown. If the port is an 8 bit type, it is the 8 ↓
LSB, that is significant.↲
↲
↲
┆b0┆┆a1┆┆b0┆┆f0┆7.4 Press <O>.↲
↲
↲
When the character "O" has been selected the Snooper will respond ↓
with the question:↲
↲
port: _ _ _ _↲
↲
════════════════════════════════════════════════════════════════════════
↓
When a port number has been entered, the 16 bit word to be send, ↓
must be entered. If the port is an 8 bit type, it is the 8 LSB, ↓
that is significant.↲
════════════════════════════════════════════════════════════════════════
↓
┆b0┆┆a1┆8. Test 0 = Memory Test.↲
↲
↲
The memory test of the ETC601 SBC Selftest consists of two ↓
parts, a PROM checksum test and a RAM memory test. The PROM ↓
checksum test is only run once at power up, whereas the RAM ↓
memory test may be run several times, if requested by the ↓
operator.↲
↲
↲
┆b0┆┆a1┆┆f0┆8.1 PROM Checksum Test.↲
↲
↲
The content of the two PROM's, located in U34 and U35, are ↓
summarixed independently of each other. The summation for each ↓
PROM must result in a zero. For that reason each of the PROM's ↓
contains a compensation byte.↲
↲
U34 contains all the even bytes and U35 all the odd bytes.↲
↲
If the summation is different from zero the following error-↓
message will be output to the console:↲
↲
┆b0┆checksum: <00><EE> error↲
↲
where <00> is the 8 bit sum of U35, and <EE> is the 8 bit sum of ↓
U34.↲
↲
This error means that the content of the program PROM's has been ↓
damaged and that the PROM's must be changed.↲
↲
The corresponding error number is 1.↲
↲
↲
════════════════════════════════════════════════════════════════════════
↓
┆b0┆┆a1┆┆f0┆8.2 RAM Memory Test.↲
↲
The RAM memory test of the ETC601 SBC Selftest verifies the ↓
onboard memory.↲
↲
The RAM memory test is able to test onboard memory of four ↓
different sizes. These are 128 k-, 256 k-, 512 k-bytes, or 1 ↓
Mbytes.↲
↲
The size of the memory is configurated in the S23 strap, PA bit 0 ↓
and 1, see chapter 4 fig. 8.↲
↲
The memory test is a register based test not using memory ↓
variables at all, neither for values nor stack. It is testing ↓
every single byte of the onboard memory.↲
↲
This fact leaves only two registers for variables that can ↓
survive the memory test, a pass-counter and the parameter word. ↓
It gives some of the explanation for the simple structure of the ↓
selftest testadministrator.↲
↲
↲
┆b0┆┆a1┆┆f0┆8.2.2 Memory Test Pattern.↲
↲
↲
The onboard Dual Port RAM memory consists of memory chips of 1 ↓
bit x 64 k. the memory test executes 4 passes through the entire ↓
memory, two times writing and two times reading.↲
↲
The test starts in the highest address, derived from the S23 ↓
strap, and inserts the pattern towards lower addresses.↲
↲
When all memory words have been written and tested, they are ↓
tested again with the inversed pattern, this means, all bits are ↓
tested for "zero" and "one" insertion.↲
↲
If an error occurs, a message will be written as follows:↲
↲
╱04002d4e0a0006000000000301453100000000000000000000000000000000000000000000000000050f19232d37414b555f69737d8791ff04╱
╱04002d4e0a0006000000000301413100000000000000000000000000000000000000000000000000050f19232d37414b555f69737d8791ff04╱
↓
┆b0┆memory test: error, addr.: <ssss>:<aaaa>, exp.: <eeee>,rec.: <rrrr>↲
╱04002d4e0a0006000000000301413100000000000000000000000000000000000000000000000000050f19232d37414b555f69737d8791ff04╱
╱04002d4e0a0006000000000301453100000000000000000000000000000000000000000000000000050f19232d37414b555f69737d8791ff04╱
↓
↲
┆8c┆┆83┆┆e0┆↓
Where ↲
╞ <ssss> is the segment address↲
╞ <aaaa> is the offset address↲
╞ <eeee> is the expected pattern↲
╞ <rrrr> is the received pattern.↲
↲
In case of an error the testadministrator pass-counter will be ↓
destroyed.↲
↲
↲
════════════════════════════════════════════════════════════════════════
↓
┆b0┆┆a1┆9. Test 1 = RAM Refresh Test.↲
↲
↲
The RAM refresh test of the ETC601 SBC Selftest assist in the ↓
verification of the memory control logic functionality. The main ↓
purpose is to discover the decay of data caused by a malfunction ↓
of the RAM refresh circuitry.↲
↲
The test pattern written is a counting pattern and the size of ↓
the test buffer is 4 K, 16 bit words.↲
↲
When the pattern has been written the test program enters a ↓
waiting loop for approximate 5 sec., in which the CPU will not ↓
access the RAM memory. After the delay, the buffer will be ↓
checked to discover any decay.↲
↲
If decay is found, a message is written like this:↲
↲
╱04002d4e0a0006000000000301453100000000000000000000000000000000000000000000000000050f19232d37414b555f69737d8791ff04╱
╱04002d4e0a0006000000000301413100000000000000000000000000000000000000000000000000050f19232d37414b555f69737d8791ff04╱
↓
┆b0┆RAM refresh test: error, addr.: <aaaa>, exp.: <eeee>, rec.: <rrrr>↲
╱04002d4e0a0006000000000301413100000000000000000000000000000000000000000000000000050f19232d37414b555f69737d8791ff04╱
╱04002d4e0a0006000000000301453100000000000000000000000000000000000000000000000000050f19232d37414b555f69737d8791ff04╱
↓
↲
Where↲
╞ <aaaa> ┆84┆is the offset address relative to the start of the ↓
┆19┆┆8b┆┄┄test buffer.↲
<eeee> is the pattern written in this word.↲
╞ <rrrr> is the pattern read from this word.↲
↲
The corresponding error number is 9.↲
════════════════════════════════════════════════════════════════════════
↓
┆b0┆┆a1┆10. Test 2 = iAPX186 DMA Test.↲
↲
↲
The iAPX186 DMA Test of ETC601 SBC Selftest applies to the ↓
verification of the functionality of the two on-chip iAPX186 DMA ↓
channels.↲
↲
Both DMA channels are initialized to memory to memory transports. ↓
Channel 0 will transfer to the lowest address of its receive ↓
buffer first, and channel 1 will transfer to the highest address ↓
of its receive buffer first.↲
↲
Both channels are started and will transfer bytes simultaneously. ↓
The procedure of the test is to check that the transfer count ↓
reaches zero before a programmed time-interval elapses. The ↓
timeout is approximate 200mS.↲
↲
If both channels have transferred the test buffer of 8 k bytes ↓
each without timeout, a datacheck of both receive buffers is ↓
performed. The data compare routine is based upon a string ↓
compare instruction. If a difference between the transmit and ↓
receive buffer is discovered, the 16 bit word in question is ↓
fetched from memory and shown as an errormessage. In other words, ↓
the errorneous word is fetches in both the string compare ↓
instruction and for the errormessage. This could mean, that if ↓
the discovered error was due to a sporadic memory error, the ↓
shown expected and received values could turn out to be equal.↲
↲
the control word of channel 0 is initialized to B606H and the ↓
control word of channel 1 is initialized to DA06H.↲
┆8c┆┆82┆┆e8┆↓
┆0e┆↓
↲
< ┆a1┆ Register Address ↲
┆a1┆ Register name Ch. 0 Ch.1 ↲
Control Word FFCAH FFDAH↲
Transfer Count FFC8H FFD8H↲
Destination Pointer FFC6H FFD6H↲
(upper 4 bits)↲
Destination Pointer FFC4H FFD4H↲
Source Pointer FFC2H FFD2H↲
(upper 4 bits)↲
┆a1┆ Source Pointer FFC0H FFC0H ↲
↲
Figure 13: DMA Control Block Format.↲
┆0f┆↓
↲
If the Transfer Count of one of the channels does not reach zero ↓
before timeout, a message as follows will be written:↲
↲
┆b0┆iAPX186 DMA test: transfer count error, reg.:<aaaa>, exp.:<eeee>↲
╞ ╞ ╞ ┆b0┆rec.:<rrrr>↲
↲
The corresponding error number is 4.↲
↲
where↲
╞ <aaaa> is the related Transfer Count Register.↲
╞ <eeee> is the expected value, always zero.↲
╞ <rrrr> is the content of the Transfer Count Register.↲
↲
If a data error is discovered, a message as follows will be ↓
written.↲
↲
┆b0┆iAPX186 DMA test: data error, addr.:<aaaa>, exp.:<eeee>,↲
┆b0┆ rec.: <rrrr>↲
↲
The corresponding error number is 3.↲
↲
where↲
╞ <aaaa> is the offset address in the receive buffer.↲
╞ <eeee> is the 16 bit word in the transmit buffer.↲
┆8c┆┆83┆┆c8┆↓
╞ <rrrr> is the 16 bit word in the received buffer.↲
↲
Both errors might be internal to the iAPX186 chip. ↓
════════════════════════════════════════════════════════════════════════
↓
┆b0┆┆a1┆11. Test 3 = PIC (8259) Interrupt Test.↲
↲
↲
The PIC (8259) Interrupt Test of the ETC601 SBC Selftest applies ↓
to the verification of the functionality of the 8259 interrupt ↓
controller.↲
↲
The procedure of the test is that the CPU writes the flagbyte. ↓
This will cause an interrupt request on the PIC level IR4. It is ↓
verified that the interrupt is generated within a programmed time ↓
interval, and that the interrupt arrived on the expected level. ↲
If no interrupt has arrived within the 4 mSec. a message is ↓
written like this:↲
↲
┆b0┆PIC test: interrupt timeout.↲
↲
The corresponding error number is 6.↲
If an interrupt has arrived, but on an unexpected level, a ↓
message is written like this:↲
↲
┆b0┆PIC test: illegal interrupt serviced, lev.: <aaaa>↲
↲
The corresponding error number is 11.↲
↲
where↲
╞ <aaaa> is the interrupt request level.↲
↲
Note that the default jumper settings in S6 giving flagbyte ↓
interrupt on IR4 is necessary to perform this test. (Consult ↓
hardware reference manual for strapping instructions).↲
↲
Failure to install this jumper will cause an error 5: "illegal ↓
interrupt".↲
════════════════════════════════════════════════════════════════════════
↓
┆b0┆┆a1┆12. Test 4 = iAPX186 Interrupt Test.↲
↲
↲
The iAPX186 Interrupt Test of the ETC601 SBC Selftest applies to ↓
the verification of the functionality of the on-chip interrupt ↓
controller.↲
↲
The procedure of the test is to start the internal timer 2 with a ↓
count value equal 1. It is tested that an interrupt is generated ↓
within a programmed time interval, and that the interrupt arrived ↓
on the expected level.↲
↲
If no interrupt has arrived within 4 mSec, a message is written ↓
like this:↲
↲
┆b0┆iAPX186 slave interrupt test: timeout↲
↲
The corresponding error number is 13.↲
↲
If an interrupt has arrived, but on an unexpected level, a ↓
message is written like this:↲
↲
┆b0┆iAPX186 slave interrupt test: illegal level serviced,↲
┆b0┆ lev.: <aaaa>↲
↲
The corresponding error number is 12.↲
↲
where↲
╞ <aaaa> is the actual level that interrupted.↲
↲
Both errors should be localized internal to the iAPX186 chip.↲
════════════════════════════════════════════════════════════════════════
↓
┆b0┆┆a1┆13. Test 5 = Ethernet Test 2.↲
↲
↲
The ethernet test 2 applies to the verification of the 82586 co-↓
processor and its interface circuitry. The test makes an external ↓
data loopback test on the ethernet chip.↲
↲
First a software reset of the ethernet chip is made. This reset ↓
causes the ethernet controller to issue an interrupt when the ↓
reset is complete. If no interrupt is received an error message ↓
is generated like this:↲
↲
┆b0┆Ethernet test 2 : missing reset interrupt↲
↲
Corresponding error number is 61.↲
↲
Second a configure command is executed to the ethernet controller ↓
in order to select the external loopback mode. Again the sleftest ↓
awaits a configure complete interrupt, and if none is received an ↓
error message is generated like this:↲
↲
┆b0┆Ethernet test 2 : configuration command not accepted↲
↲
Corresponding error number is 58.↲
↲
Third a transmit frame command is executed. The ethernet address ↓
is the broadcast address and the message length is 14 bytes. If ↓
the transmit frame command is not accepted by the ethernet ↓
controller an error message is generated like this:↲
↲
┆b0┆Ethernet test 2 : transmit command not accepted↲
↲
corresponding error number is 59.↲
↲
Fourth, when the transmit frame command is completed the data ↓
sent is copared with the data received and if not the same an ↓
error message is generated otherwise the ethernet interface is ↓
said to be OK.↲
↲
┆8c┆┆83┆┆d4┆↓
┆b0┆Ethernet test 2 : data error add.:<aaaa>, exp.:<eeee>,↲
┆b0┆╞ ╞ ╞ ╞ rec.:<rrrr>↲
┆81┆↲
Corresponding error number is 60.↲
↲
where↲
add.:<aaaa> is offset address in the receive buffer↲
exp.:<eeee> is the expected value from the transmit buffer↲
rec.:<rrrr> is the received value in the receive buffer↲
↲
Another error message is written if the ethernet controller ↓
generates an interrupt without having reset the command just ↓
executed.↲
↲
┆b0┆Ethernet test 2 : interrupt but command word not cleared↲
↲
Corresponding error number is 48.↲
════════════════════════════════════════════════════════════════════════
↓
┆b0┆┆a1┆14. Test 6 = 8274 ChA Test.↲
↲
↲
The 8274 test applies to the verification of the X.21 and V.24 ↓
interface build around the MPSC 8274 Channel A. This test is not ↓
part of the default power up test. It must be specially requsted ↓
by operator intervention. Before execution of the test it is ↓
necessary to install a loopback cable CBL 788(rear cabinet) or ↓
CBL 789 (card edge).↲
↲
The test examines the status signals for both the X.21 and the ↓
V.24 interface. A datatest in interrupt driven mode is made on ↓
both the X.21 and the V.24 interface. The capability of ↓
datatransport in DMA driven mode is tested on the V.24 interface.↲
↲
If no loopback cable is installed the test responds with this ↓
message:↲
↲
┆b0┆8274 CHA test : No testplug installed.↲
↲
Corresponding error number is 55.↲
↲
Note that this test rises the /RTS from the MPSC 8274 to test if ↓
the testplug is present. Therefore this error may be caused by a ↓
hardware error instead of missing testplug.↲
↲
If an error is detected during the status signal test an error ↓
message is written.↲
↲
┆b0┆8274 CHA test : V.24 status error exp.:<000e>, rec.:<000r>↲
↲
Corresponding error number is 53.↲
↲
OR↲
↲
┆b0┆8274 CHA test : X.21 status error exp.:<000e>, rec.:<000r>↲
┆82┆↲
Corresponding error number is 54.↲
↲
┆8c┆┆83┆┆d4┆↓
The received value holds the received CTS, DCD, CI ans DSR ↓
signals. In the V.24 status test the difference between expected ↓
and received must be interpreted like this:↲
↲
╞ expected bit 0 not equal received bit 0 = DCD error↲
╞ expected bit 2 not equal received bit 2 = CTS error↲
╞ expected bit 3 not equal received bit 3 = CI error↲
╞ expected bit 4 not equal received bit 4 = DSR error↲
↲
In the X.21 status test the difference between expected and ↓
received value must be intepreted like this:↲
↲
╞ expected bit 0 not equal received bit 0 = ┆84┆Clearing State ↓
┆19┆┆ae┆┄┄error (DCD)↲
╞ expected bit 2 not equal received bit 2 = ┆84┆Indication error ↓
┆19┆┆ae┆┄┄(CTS)↲
╞ expected bit 3 not equal received bit 3 = ┆84┆Clearing state ↓
┆19┆┆ae┆┄┄error (DCD)↲
╞ expected bit 4 not equal received bit 4 = ┆84┆Indication error ↓
┆19┆┆ae┆┄┄(CTS)↲
↲
↲
If an error is detected during the data test one of the following ↓
errormessages are produced:↲
↲
┆b0┆8274 CHA test : V.24 data error addr.:<aaaa>, exp.:<eeee>,↲
┆19┆┄┆81┆┆82┆╞ ╞ ╞ ╞ rec.:<rrrr>↲
┆81┆↲
Corresponding error number is 49.↲
↲
↲
┆b0┆8274 CHA test : X.21 data error addr.:<aaaa>, exp.:<eeee>,↲
┆b0┆╞ ╞ ╞ ╞ ╞ rec.:<rrrr>↲
┆81┆↲
Corresponding error number is 51.↲
↲
┆b0┆8274 CHA test : DMA data error addr.:<aaaa>, exp.:<eeee>,↲
┆b0┆╞ ╞ ╞ ╞ ╞ rec.:<rrrr>↲
┆8c┆┆83┆┆c8┆↓
┆81┆↲
Corresponding error number is 57.↲
↲
where↲
add.:<aaaa> is offset address in the receive buffer↲
exp.:<eeee> is the expected value from the transmit buffer↲
rec.:<rrrr> is the received value in the receive buffer↲
↲
The data test of the 8274 is executed with 8274 interrupts ↓
enabeled. If a exception interrupts is received during the ↓
data transfer an error message is produced.↲
↲
If the interrupt occur in the interrupt driven mode a message is ↓
generated like this:↲
↲
┆b0┆┆b0┆8274 CHA test : Interrupterror in interruptmode rec.:<rrrr>↲
↲
Corresponding error number is 52.↲
↲
If the interrupt occur in the DMA mode a message is generated ↓
like this:↲
↲
┆b0┆8274 CHA test : Interrupterror in DMA mode rec.:<rrrr>↲
↲
Corresponding error number is 56.↲
↲
Where↲
┆84┆rec.:<rrrr> holds the vectorcode related to the exception ↓
┆19┆┆85┆┄┄interrupt.↲
↲
If the data transfer is not completed within 250 ms. a timeout ↓
message is generated.↲
↲
┆b0┆8274 CHA test : Timeout↲
↲
Corresponding error number is 50.↲
↲
┆8c┆┆83┆┆bc┆↓
This message shoulæd indicate that the 8274 interrupt system ↓
failed.↲
════════════════════════════════════════════════════════════════════════
↓
┆b0┆┆a1┆15. Test 7 = Floppy Test.↲
↲
↲
The floppy test applies to the verification of the functionality ↓
of the FDC601 controller and attached hardware. The FDC601 is a ↓
iSBX (Single Board eXtention) controller. The test should not be ↓
executed if no FDC601 is present.↲
↲
The test is an Extended test which is not executed by default ↓
after power on, but only when requested explicitely by an ↓
operator selecting loop in test no. 7, or setting the "boot after ↓
test" to "N".↲
↲
The procedure of the test is to write, read and compare a set of ↓
test pattern over a set of tracks on the floppy disk. The test ↓
use only sector one on the tracks, but both sides of the floppy ↓
disc are tested.↲
↲
↲
┆a1┆15.1 Test Results.↲
↲
↲
The floppy test will respond with one of the following texts to ↓
inform the operator about the outcome of the test.↲
↲
┆b0┆┆b0┆Floppy test : OK↲
↲
The result "OK" indicates a well succeded writing/reading and ↓
comparing for all sectors tested as well as proper functioning ↓
hardware, e.g. interrupt system and DMA transferring.↲
↲
┆b0┆Floppy test : FDC601 not installed↲
┆b0┆↲
Corresponding error number is 39.↲
↲
The result "FDC601 not installed" is evident, e.g. the SBX board ↓
FDC601 is not installed on top of the ETC601 board.↲
↲
┆8c┆┆83┆┆c8┆↓
┆b0┆Floppy test : drive not ready↲
↲
Corresponding error number is 31.↲
↲
The result "drive not ready" normally indicates that no disc is ↓
installed in the drive or the door is not closed. If these ↓
precautions are satisfied, a hard error exist, e.g. bad drive, ↓
bad FDC601 board, missing cables ti the drive, etc.↲
↲
┆b0┆Floppy test : write protect↲
┆b0┆↲
Corrosponding error number is 32.↲
↲
The result "write protect" is evident, e.g. the inserted floppy ↓
disk is write protected. Remove the disk protection for proper ↓
function.↲
↲
┆b0┆Floppy test : seek error↲
┆b0┆↲
Corresponding error number is 33.↲
↲
┆b0┆Floppy test : CRC error↲
┆b0┆↲
Corresponding error number is 34.↲
↲
┆b0┆Floppy test : record not found↲
┆b0┆↲
Corresponding error number is 35.↲
↲
The result "seek error", "CRC error" and "record not found" ↓
normally indicates a hard error on the inserted disk or that the ↓
disc is not formatted correct.↲
↲
┆b0┆Floppy test : lost data↲
┆b0┆↲
Corresponding error number is 36.↲
↲
┆8c┆┆83┆┆bc┆↓
The result "lost data" might indicate lack of data acknowledge ↓
from the FD1797 to the iAPX186 CPU within the DMA transfers, e.g. ↓
a strap on the ETC601 board.↲
↲
┆b0┆Floppy test : write fault↲
↲
Corresponding error number is 37.↲
↲
The result "write fault" might indicate hard errors on the ↓
inserted disk, but might also indicate hard errors within the ↓
hardware system.↲
↲
┆b0┆Floppy test : receive data error, reg:<aa>, exp: <ee>, rec: <rr>↲
↲
┆b0┆┆f0┆Corresponding error number is 38.↲
↲
The result "receive data error" indicates an inconsistence with ↓
┆19┆┄┆81┆┄respect to the data pattern read from the floppy disk. <aa> gives ↓
┆19┆┄┆81┆┄the local offset address in the received data block where the ↓
┆19┆┄┆81┆┄inconsistence was found, <ee> gives the expected value and <rr> ↓
┆19┆┄┆81┆┄gives the received value. This result could indicate a transfer ↓
┆19┆┄┆81┆┄error, due to speed variations.↲
↲
↲
┆a1┆15.2 The Test Disk.↲
↲
↲
Before the floppy test initiated, a formatted disk must be ↓
inserted in the floppy drive. The disk inserted must be double ↓
sided, double density, soft sectoring with track density of 96 ↓
TPI. The format of the disk corresponds with a CP/M format, e.g ↓
have 77 tracks where each track has 10 sectors of each 512 bytes ↓
length.↲
════════════════════════════════════════════════════════════════════════
↓
┆b0┆┆a1┆16. Multibus Configuration and Test Monitor.↲
↲
↲
The socalled Multibus Test Monitor is deviced into two phases, an↓
automatic configuration with decoding of errors produced by the ↓
"test-slaves" and an interactive test phase, which must be ↓
requested by the operator.↲
↲
In the configuration phase the "test host" will produce a ↓
complete configuration table of the total RC3900 Multibus System.↲
↲
Example of the Multibus configuration:↲
┆0e┆↓
↲
╱04002d4e0a00060000000003014c3100000000000000000000000000000000000000000000000000050f19232d37414b555f69737d8791ff04╱
╱04002d4e0a0006000000000301413100000000000000000000000000000000000000000000000000050f19232d37414b555f69737d8791ff04╱
↓
┆a2┆┆05┆↲
Entry no. ,MB block ,state ,name ,RAM size * 64k, flag offset * 16k,err no.↲
┆a2┆┆05┆↲
00004 4000↲
00007 7000 ready COM601 00003 00004┆05┆00000 ↲
00010 A000 ready COM601 00001 00002 00002↲
╱04002d4e0a0006000000000301413100000000000000000000000000000000000000000000000000050f19232d37414b555f69737d8791ff04╱
╱04002d4e0a00060000000003014c3100000000000000000000000000000000000000000000000000050f19232d37414b555f69737d8791ff04╱
↓
┆0f┆↓
↲
The interactive testphase, where it is possible to control the ↓
execution of tests on different "test-slaves", will only be ↓
entered, when requested by the operator (press <cntrl><S>) during ↓
the "test-master" selftest).↲
↲
↲
┆b0┆┆a1┆┆f0┆16.1 Automatic Configuration.↲
↲
↲
When a "test-master" has terminated its selftest, it will always ↓
perform an automatic Multibus configuration, in order to locate ↓
active "test-slaves" and eventually inactive memory areas.↲
↲
It is a convention that every "test-slave", when terminating its ↓
selftest will communicate with "test-master" by means of a ↓
predefined protocol.↲
↲
┆8c┆┆83┆┆bc┆↓
The configuration table will be shown on the console, and it is ↓
possible for the operator to decide, if it corresponds with the ↓
actual configuration. The entries, which has passed a handshake ↓
with the "test-master" will have the state "READY" and an ↓
identification name set in the configuration table.↲
↲
If one or more of the "test-slaves" have produced an error, the ↓
communication buffer for the related "test-slave" will contain ↓
some data and text, which will identify the error. The text in ↓
the buffer will be shown on the console as an errortext. About ↓
"test slave" errortexts, please consult the related manual.↲
↲
If the "test-master" has halted on one of these errors, it is ↓
possible to continue by typing <cntrl><Q>.↲
↲
↲
┆b0┆┆a1┆┆f0┆16.2 "Test Slave" Management.↲
↲
↲
The default action of the ETC601 SBC Selftest is to enter the ↓
bootloader when the configuration phase has been terminated. This ↓
can be overwritten by the operator typing <cntrl><S> during the ↓
"test-master" selftest.↲
↲
When the interactive test phase has been selected the following ↓
text will be written, when the automatic configuration has been ↓
terminated:↲
↲
┆b0┆>> Multibus monitoring↲
↲
Each of the connected "test slaves" has its own seperate set of ↓
parameters, which has the same format as those used by the CPU. ↓
↲
In the interative phase it is possible to start one or several ↓
"test-slaves" looping in the complete selftest or in a specific ↓
testprogram.↲
↲
┆8c┆┆83┆┆bc┆↓
Until a "test-slave" has received its first set of parameters, it ↓
will stay in an inactive mode.↲
↲
Every time "test-slave" recognizes an error, the related message ↓
will be written on the console.↲
↲
By typing <cntrl><S>, the configuration will be shown. When the ↓
interactive phase is selected new parameters for a "test-slave" ↓
may be entered after the configuration table has been written.↲
↲
An errormessage will be retyped on the console, when a change of ↓
parameters has been made.↲
↲
↲
┆b0┆┆a1┆┆f0┆16.3 Bootload.↲
↲
↲
Default action of the ETC601 SBC selftest is to enter the ↓
bootloader immediately after the configuration.↲
↲
When testing in the interactive phase the character <cntrl><Q> ↓
has two purposes.↲
↲
a) ┆84┆When the "test-master" has halted due to a "test slave" error, ↓
┆19┆┆83┆┄┄this "halt" can be quit by typing <entrl><Q>.↲
↲
b) ┆84┆When running in the interactive phase and typing <cntrl><Q>, ↓
┆19┆┆83┆┄┄this will force all the "test-slaves" and finally the "test- ↓
┆19┆┆83┆┄┄master" to enter the bootloader.↲
════════════════════════════════════════════════════════════════════════
↓
┆b0┆┆a1┆17. ETC601 as a "Test-slave".↲
↲
↲
It is possible to configurate a ETC601 as a "test-slave" by the ↓
switch shown in fig. 9. This means that several ETC601 boards can ↓
be managed by one "test-master".↲
↲
Specialities:↲
↲
a) ┆84┆When looping in the memory test, the "test-slave" will ┆a1┆not┆e1┆ ↓
┆19┆┆83┆┄┄communicate with the "test-master".↲
↲
b) ┆84┆When both the parameters "suppress status check" and "suppress ↓
┆19┆┆83┆┄┄data check" is set to "Y", it will only communicate in case of ↓
┆19┆┆83┆┄┄errors.↲
════════════════════════════════════════════════════════════════════════
↓
┆b0┆┆a1┆A. LAYOUT OF THE MASTER TO SLAVE COMMUNICATION BUFFER↲
╱04002d4e0a0006000000000201413100000000000000000000000000000000000000000000000000050f19232d37414b555f69737d8791ff04╱
╱04002d4e0a0006000000000301413100000000000000000000000000000000000000000000000000050f19232d37414b555f69737d8791ff04╱
↓
↲
↲
┆a1┆┆05┆↲
!xxxx:FFFF ! id field ! !┆05┆!↲
┆a1┆! FFFE ! state ! !┆05┆!↲
! FFFD ! 'C' ! ! ┆05┆!↲
! FFFC ! 'O' ! ! !↲
! FFFB ! name 'M' ! ! !↲
! FFFA ! '6' ! ! ┆05┆!↲
! FFF9 ! '0' ! !┆05┆!↲
┆a1┆! FFF8 ! '1' ! ! !↲
! FFF7 ! ramsize ! !┆05┆!↲
! FFF6 ! flag_offset ! !┆05┆!↲
┆a1┆! FFF5 ! data pat ! !┆05┆!↲
! FFF4 ! switch ! ! ┆05┆!↲
┆a1┆! FFF3 ! test no ! !┆05┆!↲
┆a1┆! FFF2 ! param flag ! !┆05┆!↲
! FFF1 ! ! ! ┆05┆!↲
! FFF0 ! ! !┆05┆!↲
! **** ! slave error ! !┆05┆!↲
! **** ! text string ! !┆05┆!↲
! **** ! max 80 chars ! !┆05┆!↲
! FFA3 ! ! !┆05┆!↲
┆a1┆! FFA2 ! ! !┆05┆!↲
! FFA1 ! text length ! ! ┆05┆!↲
┆a1┆! FFA0 ! ! ! !↲
! FF9F ! aux3_data ! !┆05┆!↲
┆a1┆! FF9E ! ! !┆05┆!↲
! FF9D ! aux2_data ! !┆05┆!↲
┆a1┆! FF9C ! ! !┆05┆!↲
! FF9B ! aux1_data ! !┆05┆!↲
┆a1┆! FF9A ! ! !┆05┆!↲
! FF99 ! rec_data ! !┆05┆!↲
┆a1┆! FF98 ! ! !┆05┆!↲
! FF97 ! exp_data ! !┆05┆!↲
┆a1┆! FF96 ! ! !┆05┆!↲
! FF95 ! adr_data ! !┆05┆!↲
┆a1┆! FF94 ! ! !┆05┆!↲
! FF93 ! err_no ! !┆05┆!↲
┆a1┆! FF92 ! error flag ! !┆05┆!↲
┆1a┆┆1a┆onding error number i.↲
↲
┆b0┆Floppy test : drive not reagurat↓
┆b0┆ot found↲
┆b0┆↲
Corresponding error number i