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Length: 4096 (0x1000)
Types: RcTekst
Names: »99110066.WP«
└─⟦7fab0c8ae⟧ Bits:30005866/disk3.imd Dokumenter i RcTekst format (RCSL 99-1-*)
└─⟦this⟧ »99110066.WP«
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┆b0┆ _______________________↲
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┆b0┆ RCSL No: ┆f0┆ 99-1 10066↲
┆b0┆Edition:┆f0┆ March 1985↲
┆b0┆Author: ┆f0┆ Henning Pedersen↲
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┆b0┆__________________________________________________________________↲
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┆b0┆Title:↲
BPL606 BACKPLANE↲
Technical Manual↲
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┆b0┆__________________________________________________________________↲
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┆b0┆ RC A/S Regnecentralen↲
┆b0┆↲
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┆b0┆__________________________________________________________________↲
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┆b0┆Keywords:↲
System RC39↲
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┆b0┆__________________________________________________________________↲
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┆b0┆Abstract:↲
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┆84┆┆84┆This manual contains a timing diagram, a logic diagram, ↓
┆19┆┆89┆┄┄a functional description and an assembly drawings for ↓
┆19┆┆89┆┄┄the Backplane┆b0┆ BPL606┆f0┆. The Backplane includes a ┆b0┆MULTIBUS┆f0┆ ↓
┆19┆┆89┆┆82┆┄with sixteen slots and two independt ┆b0┆iLBX┆f0┆ busses. (The ↓
┆19┆┆89┆┆83┆┄┆b0┆iLBX ┆f0┆busses contains four and five slots each. (┆b0┆MULTIBUS┆f0┆ ↓
┆19┆┆89┆┆85┆┄and ┆b0┆iLBX┆f0┆ bus are trade marks of INTEL). ↲
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┆b0┆__________________________________________________________________↲
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┆a1┆┆b0┆CONTENTS PAGE↲
┆19┆┄┆82┆┆82┆↲
┆f0┆1. INTRODUCTION ........................... 1↲
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2. BLOCK DIAGRAM .......................... 2↲
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3. TIMING DIAGRAM ......................... 3↲
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4. FUNCTIONAL DESCRIPTION ................. 4↲
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5. LOGIC DIAGRAM .......................... 5↲
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6. ASSEMBLY DRAWINGS ...................... 10↲
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7. MULTIBUS SIGNALS ...................... 11↲
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8. iLBX BUS SIGNALS ...................... 12↲
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9. REFERENCES ............................. 13↲
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┆b0┆ ______________________________________________________↲
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┆14┆┆b3┆ ┆0b┆↲
┆a1┆┆b0┆↲
┆b0┆┆a1┆1. INTRODUCTION.↲
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┆84┆The Backplane BPL606 is placed in the computer unit ↓
┆19┆┆89┆┄┄RC3902. It connects up to sixteen MULTIBUS cards. It ↓
┆19┆┆89┆┄┄includes two iLBX busses, one with four slots and one ↓
┆19┆┆89┆┄┄with five slots. The Backplane distributes power ↓
┆19┆┆89┆┄┄(5v,12v,-12v) to the MULTIBUS cards. Further it ↓
┆19┆┆89┆┄┄includes a Reset circuit and multibus arbitration logic ↓
┆19┆┆89┆┄┄with parallel priority.↲
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┆a1┆┆b0┆↲
┆b0┆┆a1┆2. BLOCK DIAGRAM.↲
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┆a1┆┆b0┆↲
┆b0┆┆a1┆3. TIMING DIAGRAM.↲
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┆b0┆┆a1┆4. FUNCTIONAL DESCRIPTION.↲
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┆84┆The main purpose of the Backplane ┆b0┆BPL606┆f0┆ is to connect ↓
┆19┆┆89┆┆81┆┄and terminate up to sixteen ┆b0┆MULTIBUS┆f0┆ compatible Cards. The ↓
┆19┆┆89┆┆82┆┄secondary purpose is to Transmit a system ┆b0┆RESET┆f0┆ to the ↓
┆19┆┆89┆┆83┆┄Cards. The third purpose of the Backplane is the control ↓
┆19┆┆89┆┆83┆┄of the master Cards on the ┆b0┆MULTIBUS┆f0┆. It controls that by ↓
┆19┆┆89┆┆84┆┄parallel priority. Only one ┆b0┆MULTIBUS┆f0┆ card is able to ↓
┆19┆┆89┆┆85┆┄gain control of the ┆b0┆MULTIBUS┆f0┆ at a given time. The Bus ↓
┆19┆┆89┆┆86┆┄priority circuit is functions as follows:↲
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┆84┆A unit which wants to become bus master sends a bus ↓
┆19┆┆89┆┄┄request on the bus reqest line ┆b0┆BREQ/┆f0┆. The bus ↓
┆19┆┆89┆┆81┆┄arbitration logic on the backplane BPL606 then answers ↓
┆19┆┆89┆┆81┆┄on the bus priority in line ┆b0┆BPRN/┆f0┆ if no higher priority ↓
┆19┆┆89┆┆82┆┄units sends a bus request. The priority on the Backplane ↓
┆19┆┆89┆┆82┆┄is from J1 to J16. J1 has the highest priority.↲
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┆a1┆┆b0┆↲
┆b0┆┆a1┆5. LOGIC DIAGRAM.↲
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┆a1┆┆b0┆↲
┆b0┆┆a1┆┆a1┆┆b0┆↲
┆b0┆┆a1┆6. ASSEMBLY DRAWINGS.↓
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┆a1┆┆b0┆↲
┆b0┆┆a1┆7. MULTIBUS SIGNALS.↲
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┆a1┆┆b0┆↲
┆b0┆┆a1┆8. iLBX BUS SIGNALS.↲
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┆b0┆┆a1┆┆a1┆↲
┆a1┆┆b0┆┆a1┆9. REFERENCES.↲
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1. INTEL MULTIBUS SPECIFICATION 9800683-04↲
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2. INTEL iLBX BUS SPECIFICATION 145695-REV A↲
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┆1a┆┆1a┆ INTEL MUL