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Length: 16384 (0x4000)
Types: RcTekst
Names: »99110231.WP«
└─⟦82b75ed7a⟧ Bits:30005866/disk4.imd Dokumenter i RcTekst format (RCSL 99-1-*)
└─⟦this⟧ »99110231.WP«
╱04002d4c0a00050000000002013c3140000000000000000000000000000000000000000000000000050a0f19232d37414b555f69737d87ff04╱
┆06┆i↲
↲
┆b0┆┆a1┆TABLE OF CONTENTS┆05┆PAGE↲
↲
1. INTRODUCTION ....................................... 1↲
↲
2. FUNCTIONAL DESCRIPTION ............................. 2↲
2.1 Block Diagram .................................. 2↲
2.2 Pin Out ........................................ 3↲
2.3 Pin Designation ................................ 4↲
2.4 Register Addressing ............................ 7↲
2.5 Register Definitions ........................... 7↲
2.5.1 Control Register a ....................... 7↲
2.5.2 Control Register b ....................... 8↲
2.5.3 Transmit Register ........................ 8↲
2.5.4 Receive Register ......................... 8↲
2.5.5 Status Register .......................... 9↲
↲
3. SLAVE MODE CONFIGURATION ........................... 10↲
3.1 Initializing ................................... 10↲
3.2 Running ........................................ 10↲
3.3 Broadcast Options .............................. 10↲
↲
4. SELFTEST MODE CONFIGURATION ........................ 11↲
4.1 Initializing ................................... 11↲
4.2 Running ........................................ 11↲
↲
5. GENERAL CHARACTERISTICS ............................ 12↲
↲
6. DC CHARACTERISTICS ................................. 13↲
↲
7. AC CHARACTERISTICS ................................. 14↲
════════════════════════════════════════════════════════════════════════
↓
┆06┆ii↲
↲
┆a1┆┆b0┆REFERENCES╞ ╞ ╞ ╞ ╞ ↲
↲
CIRCUIT II Reference Manual RCSL No.: 44-RT2157, May 1984↲
↲
Philips CMOS Gate array design Manual, autumn 1984↲
╞ PCF/PCC0330; 0450; 0700; 1100 gate array family↲
Philips doc. no.?↲
↲
Philips HCMOS Gate array Development sample data, june 1984↲
PCF/PCC0335; 0455; 0705; 1105 gate array family↲
╞ Philips doc. no. 9397 022 60142.↲
════════════════════════════════════════════════════════════════════════
↓
┆14┆┆b3┆┆06┆┆0b┆↲
↲
┆b0┆┆a1┆1. INTRODUCTION↲
↲
The Circuit II Protocol Communications Controller (CPCC) is ↓
made as a peripheral device to interface be┄tween a CPU and ↓
the CIRCUIT II protocol developed by RC. This character ↓
oriented protocol is based on a polling mas┄ter and up to 32 ↓
slaves with the data transfer only between the Mas┄ter and ↓
one Slave device at a time. In the CPCC how┄ever a Broadcast ↓
option is implemented to make it possible for the Master to ↓
transfer data to several Slaves simultan┄ously.↲
↲
A selftest option is implemented to make it possible to test ↓
the entire interface circuit by echoing transmitted data via ↓
the driving transformer into the receiver.↲
↲
The CPCC is implemented in an 1116 gate Shrinked High Speed ↓
CMOS Array from Philips and is in- and output compatible to ↓
HC/HCT logic.↲
↲
↲
════════════════════════════════════════════════════════════════════════
↓
↲
┆b0┆┆a1┆2. FUNCTIONAL DESCRIPTION↲
↲
┆b0┆┆a1┆2.1 Block Diagram↲
↲
════════════════════════════════════════════════════════════════════════
↓
┆b0┆┆a1┆2.2 Pin Out↲
↲
════════════════════════════════════════════════════════════════════════
↓
┆b0┆┆a1┆2.3 Pin Designation↲
↲
┆a1┆Mnemonic Pin no Type Name and Function┆05┆↲
↲
┆b0┆D0..D7┆f0┆ 1-8 I/O ┆84┆This 3-state bidirectional 8 bit ↓
┆19┆┆9b┆┆81┆┄buffer is used to interface to ↓
┆19┆┆9b┆┆81┆┄the Control-, Data- and Statusre┄┄↓
┆19┆┆9b┆┆81┆┄gister.↲
↲
┆b0┆-,RD┆f0┆ 9 I ┆84┆A "low" on this input informs the ↓
┆19┆┆9b┆┆81┆┄CPCC that the CPU is reading data ↓
┆19┆┆9b┆┆81┆┄or status informations from the ↓
┆19┆┆9b┆┆81┆┄CPCC.↲
↲
┆b0┆-,WR┆f0┆ 10 I ┆84┆A "low" on this input informs the ↓
┆19┆┆9b┆┆81┆┄CPCC that the CPU is writing Con┄↓
┆19┆┆9b┆┆81┆┄trol or Data informations to the ↓
┆19┆┆9b┆┆81┆┄CPCC.↲
↲
┆b0┆-,CS┆f0┆ 11 I ┆84┆A "low" on this input selects the ↓
┆19┆┆9b┆┆81┆┄CPCC. No reading or writing will ↓
┆19┆┆9b┆┆81┆┄occur unless the device is selec┄↓
┆19┆┆9b┆┆81┆┄ted. When -,CS is high, the Data ↓
┆19┆┆9b┆┆81┆┄bus condition will have no effect ↓
┆19┆┆9b┆┆81┆┄on the chip.↲
↲
┆b0┆A0..A1┆f0┆ 12,13 I ┆84┆These inputs in conjunction with ↓
┆19┆┆9b┆┆81┆┄the -,RD and -,WR inputs, informs ↓
┆19┆┆9b┆┆81┆┄the CPCC that the word on the da┄↓
┆19┆┆9b┆┆81┆┄ta bus is either control data or ↓
┆19┆┆9b┆┆81┆┄Status information.↲
↲
┆b0┆Gnd ┆f0┆ 14 ┆84┆Ground: 0V reference↲
↲
┆b0┆XTAL1,┆f0┆ 15,16 XTAL1 and XTAL2 are the output ↲
┆19┆┄┆81┆┄┆b0┆XTAL2┆f0┆ ┆84┆and input respectively of an in┄↓
┆19┆┆9b┆┆82┆┄verting amplifier which is inten┄↓
┆19┆┆9b┆┆82┆┄ded for use as a crystal oscilla┄↓
┆19┆┆9b┆┆82┆┄tor. To drive the CPCC with an ↓
┆19┆┆9b┆┆82┆┄external oscillator XTAL1 must be ↓
┆19┆┆9b┆┆82┆┄used as input while XTAL2 must be ↓
┆19┆┆9b┆┆82┆┄left open.↲
↲
┆b0┆TxRDY ┆f0┆ 17 0 ┆84┆Transmitter Ready.↲
┆84┆In Slave mode this output signals ↓
┆19┆┆9b┆┄┄the CPU that the transmitter is ↓
┆19┆┆9b┆┄┄ready to ac┄┄cept a data character. ↲
════════════════════════════════════════════════════════════════════════
↓
┆a1┆Mnemonic Pin no Type Name and Function┆05┆↲
↲
┆84┆The TxRDY output pin can be used ↓
┆19┆┆9b┆┄┄as an in-terrupt to the system ↓
┆19┆┆9b┆┄┄or, for Polled operation, the CPU ↓
┆19┆┆9b┆┄┄can check TxRDY using a Status ↓
┆19┆┆9b┆┄┄Read operation. TxRDY is automa┄↓
┆19┆┆9b┆┄┄tically reset by the leading edge ↓
┆19┆┆9b┆┄┄of WR when a data character is ↓
┆19┆┆9b┆┄┄loaded from the CPU. The TxRDY ↓
┆19┆┆9b┆┄┄output pin is masked by the TxEN ↓
┆19┆┆9b┆┄┄control bit. ↲
↲
┆84┆In Master mode if this pin is ↓
┆19┆┆9b┆┄┄asserted together with the TxRDY ↓
┆19┆┆9b┆┄┄pin it indicates that a proper ↓
┆19┆┆9b┆┄┄answer with no data has been ↓
┆19┆┆9b┆┄┄received.↲
↲
┆b0┆RxRDY ┆f0┆ 18 0 Receiver Ready.↲
┆84┆This output indicates that the ↓
┆19┆┆9b┆┄┄CPCC contains a character that is ↓
┆19┆┆9b┆┄┄ready to be input to the CPU. ↓
┆19┆┆9b┆┄┄RxRDY can be connected to the in┄↓
┆19┆┆9b┆┄┄terrupt structure of the CPU or, ↓
┆19┆┆9b┆┄┄for Polled operation, the CPU can ↓
┆19┆┆9b┆┄┄check the condition of RxRDY ↓
┆19┆┆9b┆┄┄using a Status Read operation. ↓
┆19┆┆9b┆┄┄RxRDY is automatically reset by ↓
┆19┆┆9b┆┄┄the leading edge of RD. The RxRDY ↓
┆19┆┆9b┆┄┄output pin is masked by the RxEN ↓
┆19┆┆9b┆┄┄control bit.↲
↲
┆84┆Failure to read the received ↓
┆19┆┆9b┆┄┄character from the Rx Data Output ↓
┆19┆┆9b┆┄┄Register prior to the assembly of ↓
┆19┆┆9b┆┄┄the next Rx Data character will ↓
┆19┆┆9b┆┄┄set overrun condition error and ↓
┆19┆┆9b┆┄┄the previous character will be ↓
┆19┆┆9b┆┄┄written over and lost. If the Rx ↓
┆19┆┆9b┆┄┄Data is being read by the CPU ↓
┆19┆┆9b┆┄┄when the internal transfer is oc┄↓
┆19┆┆9b┆┄┄curing, overrun error will be set ↓
┆19┆┆9b┆┄┄and the old character will be ↓
┆19┆┆9b┆┄┄lost.↲
↲
┆b0┆X0, X1┆f0┆ 19,20 0 ┆84┆these outputs contains the values ↓
┆19┆┆9b┆┆81┆┄of the don't care bits in the Ad┄↓
┆19┆┆9b┆┆81┆┄dress Header of the protocol, and ↓
┆19┆┆9b┆┆81┆┄changes value just prior to RxRDY ↓
┆19┆┆9b┆┆81┆┄dependent of the received frame.↲
↲
┆b0┆↓
════════════════════════════════════════════════════════════════════════
↓
┆a1┆┆e1┆↲
┆a1┆Mnemonic Pin no Type Name and Function┆05┆↲
↲
┆b0┆BRC ┆f0┆ 21 0 ┆84┆If Broadcast option is chosen, ↓
┆19┆┆9b┆┆81┆┄this output indicates whether the ↓
┆19┆┆9b┆┆81┆┄received data is normally addres┄↓
┆19┆┆9b┆┆81┆┄sed to the CPCC or is of Broad┄┄┄↓
┆19┆┆9b┆┆81┆┄cast type (BRC = "high"); other┄↓
┆19┆┆9b┆┆81┆┄wise it remains low.↲
↲
┆b0┆-,RESET ┆f0┆ 22 I ┆84┆A "low" on this input forces the ↓
┆19┆┆9b┆┆81┆┄CPCC into an "Idle" mode. The de┄↓
┆19┆┆9b┆┆81┆┄vice will remain at "Idle" until ↓
┆19┆┆9b┆┆81┆┄a new set of control words is ↓
┆19┆┆9b┆┆81┆┄written into the CPCC to program ↓
┆19┆┆9b┆┆81┆┄its functional defintion. Minimum ↓
┆19┆┆9b┆┆81┆┄RESET pulse width is XtCY (clock ↓
┆19┆┆9b┆┆81┆┄must be running).↲
↲
┆b0┆ ┆f0┆ 23 ┆84┆No connection (used during facto┄↓
┆19┆┆9b┆┆81┆┄ry test).↲
↲
┆b0┆FMDIN ┆f0┆ 24 I ┆84┆Frequence MoDulated INput.↲
┆84┆The Biphase-S encoded incomming ↓
┆19┆┆9b┆┄┄data from the CIRCUIT II line ↓
┆19┆┆9b┆┄┄must be fed to this input.↲
↲
25 ┆84┆No connection (used during facto┄↓
┆19┆┆9b┆┄┄ry test).↲
↲
┆b0┆NFMDO┆f0┆ 26 0 ┆84┆Negated Frequence MoDulated Out┄↓
┆19┆┆9b┆┆81┆┄put.↲
┆84┆This output contains the negative ↓
┆19┆┆9b┆┄┄part of the Biphase-S encoded ↓
┆19┆┆9b┆┄┄data to be transmitted on the ↓
┆19┆┆9b┆┄┄CIRCUIT II line.↲
↲
┆b0┆FMDO┆f0┆ 27 0 Frequence MoDulated Output.↲
┆84┆This output contains the positive ↓
┆19┆┆9b┆┄┄part of the Biphase-S encoded ↓
┆19┆┆9b┆┄┄data to be transmitted on the ↓
┆19┆┆9b┆┄┄CIRCUIT II line.↲
↲
↲
════════════════════════════════════════════════════════════════════════
↓
┆b0┆┆a1┆2.4 Register Addressing↲
↲
┆a1┆┆e1┆ -,CS -,WR -,RD A┆82┆1 ┆81┆A┆82┆0┆81┆ ↲
┆a1┆┆81┆┆05┆↲
0 0 1 1 0 CPU->Control register a↲
↲
0 0 1 1 1 CPU->Control register b↲
↲
0 0 1 0 0 CPU->Tx data register↲
↲
0 1 0 0 0 Rx data register->CPU↲
┆a1┆↲
┆a1┆┆a1┆┆e1┆ 0 1 0 0 1 Status register->CPU┆05┆↲
┆a1┆╞ ╞ ╞ ╞ ╞ ╞ ╞ ╞ ╞ ╞ ╞ ╞ ╞ ↲
↲
↲
┆b0┆┆a1┆2.5 Register Definitions↲
↲
Upon power up the CPCC must be initialized before it is al┄↓
lowed to initiate any communication on the serial bus. This ↓
is done to prohibit the CPCC to answer an unspecified Ad┄┄┄↓
dress and thus violate communication on the bus. ↲
↲
↲
┆b0┆┆a1┆2.5.1 Control Register a↲
↲
┆a1┆ msb lsb ↲
┆a1┆┆e1┆! ! ! ! ! ! ! ! !↲
! CCEN ! TXEN ! RXEN ! Device Address !↲
┆a1┆! ! ! ! ! ! ! ! !↲
↲
This register contains the recognition address of which the ↓
CPCC is to answer.↲
↲
┆b0┆CCEN ┆f0┆ ┆84┆The Communication ENable is the overall enable of the ↓
┆19┆┆87┆┆81┆┄CPCC. When all other registers have been initiated ↓
┆19┆┆87┆┆81┆┄this bit must be set high to enable the CPCC recep┄┄↓
┆19┆┆87┆┆81┆┄tion/transmission on the bus. Upon Reset CCEN is set ↓
┆19┆┆87┆┆81┆┄to 0 (disable).↲
↲
┆b0┆RXEN┆f0┆ ┆84┆Receive is enable/-,disable of the RxRDY output pin ↓
┆19┆┆87┆┆81┆┄to give the ability to chose either polled or inter┄↓
┆19┆┆87┆┆81┆┄rupt mode.↲
↲
┆b0┆TXEN┆f0┆ ┆84┆Transmit ENable is similar to RxEN concerning TXRDY. ↓
┆19┆┆87┆┆81┆┄Since the CIRCUIT II protocol allways requires an an┄↓
┆19┆┆87┆┆81┆┄swer to a poll, the TXEN only concerns the TXEN out┄↓
┆19┆┆87┆┆81┆┄put and not the required "no data" answer provided by ↓
┆19┆┆87┆┆81┆┄the Tx-part.↲
↲
↲
════════════════════════════════════════════════════════════════════════
↓
┆b0┆┆a1┆2.5.2 Control Register b↲
┆a1┆ msb lsb ↲
┆a1┆┆e1┆! ! ! ! ! ! ! ! !↲
! BREN ! ER ! STST ! Broadcast Address !↲
┆a1┆! ! ! ! ! ! ! ! !↲
↲
The b register contains the recognition address at which the ↓
CPCC is not to answer. This Broadcast address can be used by ↓
the master of the bus to transmit messages to several slaves ↓
at a time. ↲
↲
┆b0┆BREN ┆f0┆ ┆84┆is used to determine whether the CPCC is to use this ↓
┆19┆┆87┆┆81┆┄second address recognition or not. ↲
↲
┆b0┆ER ┆f0┆ ┆84┆is a reset bit which resets the content of status re┄↓
┆19┆┆87┆┆81┆┄gister bits FE OE and PE (error codes). When ER is ↓
┆19┆┆87┆┆81┆┄set to "1" the error code bits are reset and the ↓
┆19┆┆87┆┆81┆┄error detection circuit is disabled. When ER is set ↓
┆19┆┆87┆┆81┆┄to "0" the error detection circuit is enabled.↲
↲
┆b0┆STST ┆f0┆┆84┆Self TeST mode if choosen, must be set upon Reset to ↓
┆19┆┆87┆┆81┆┄select this mode. The mode requires no Address since ↓
┆19┆┆87┆┆81┆┄the Re┄ceiver receives the echo of the transmitted da┄↓
┆19┆┆87┆┆81┆┄ta of the CPCC. To use this mode the CPCC with its ↓
┆19┆┆87┆┆81┆┄peripheral drivers must not be attached to any active ↓
┆19┆┆87┆┆81┆┄CIRCUIT II bus.↲
↲
↲
┆b0┆┆a1┆2.5.3 Transmit register↲
┆a1┆ msb lsb ↲
┆a1┆┆e1┆! ! ! ! ! ! ! ! !↲
! Tx-data !↲
┆a1┆! ! ! ! ! ! ! ! !↲
↲
To this register the CPU must write the data to be transmit┄↓
ted on CIRCUIT II.↲
↲
↲
┆b0┆┆a1┆2.5.4 Receive Register↲
┆a1┆ msb lsb ↲
┆a1┆┆e1┆! ! ! ! ! ! ! ! ! ↲
! Rx-Data !↲
┆a1┆! ! ! ! ! ! ! ! !↲
↲
From this register the CPU can read the data received from ↓
CIRCUIT II.↲
↲
↲
════════════════════════════════════════════════════════════════════════
↓
┆b0┆┆a1┆2.5.5 Status Register↲
↲
┆a1┆ msb lsb ↲
┆a1┆┆e1┆! ! ! ! ! ! ! ! ! ↲
! X┆82┆1┆81┆ ! X┆82┆0┆81┆ ! FE ! OE ! PE ! BRC !RxRDY !TxRDY !↲
┆a1┆! ! ! ! ! ! ! ! !↲
↲
┆e1┆┆e1┆┆b0┆RxRDY┆e1┆ ┆f0┆ ┆84┆This bit indicates that the CPCC contains a character ↓
┆19┆┆87┆┆81┆┄that is ready to be input to the CPU.↲
↲
┆a1┆┆e1┆┆b0┆TxRDY┆e1┆┆f0┆ ┆84┆This bit indicates that the CPCC is ready to accept a ↓
┆19┆┆87┆┆81┆┄data character from the CPU.↲
↲
┆84┆Note that when using the Polled operation, the TxRDY ↓
┆19┆┆87┆┄┄status bit is not masked by Tx Enabled, but will only ↓
┆19┆┆87┆┄┄indicate the Empty/Full Status of the Tx Data input ↓
┆19┆┆87┆┄┄Register.↲
↲
┆a1┆┆e1┆┆b0┆BRC┆e1┆ ┆f0┆ ┆84┆If BRoadCast bit is high it indicates that the broad┄↓
┆19┆┆87┆┆81┆┄cast option has been chosen and that the character in ↓
┆19┆┆87┆┆81┆┄the Receive register is received via the broadcast ↓
┆19┆┆87┆┆81┆┄ad┄dress. The BRC bit is identical to the BRC output ↓
┆19┆┆87┆┆81┆┄pin.↲
↲
┆b0┆┆e1┆PE┆e1┆ ┆b0┆┆f0┆┆84┆The Parity Error flag is set when a parity error is ↓
┆19┆┆87┆┆82┆┄detected. It is reset by the ER bit of the Command ↓
┆19┆┆87┆┆82┆┄Instruction. PE does not inhibit operation of the ↓
┆19┆┆87┆┆82┆┄CPCC but the frame containing the Parity error is ↓
┆19┆┆87┆┆82┆┄lost.↲
↲
┆a1┆┆e1┆┆b0┆OE┆e1┆ ┆f0┆ ┆84┆The Overrun Error flag is set when the CPU does not ↓
┆19┆┆87┆┆81┆┄read a char┄acter before the next one becomes avail┄┄↓
┆19┆┆87┆┆81┆┄able. It is re┄set by the ER bit of the Command In┄┄↓
┆19┆┆87┆┆81┆┄struction. OE does not inhibit operation of the CPCC ↓
┆19┆┆87┆┆81┆┄however, the pre┄viously overrun character is lost.↲
↲
┆b0┆FE┆f0┆ ┆84┆The Framing Error flag is set when a valid Stop or ↓
┆19┆┆87┆┆81┆┄start bit is not detec┄ted at the end of every charac┄↓
┆19┆┆87┆┆81┆┄ter. It is reset by the ER bit of the Command Inst┄↓
┆19┆┆87┆┆81┆┄ruction. FE does not inhibit the operation of the ↓
┆19┆┆87┆┆81┆┄CPCC, but the frame containing the framing error is ↓
┆19┆┆87┆┆81┆┄lost. Note that if FE flag is set PE flag may also be ↓
┆19┆┆87┆┆81┆┄set since the parity checker also checks start and ↓
┆19┆┆87┆┆81┆┄stop bits in the middle of a frame containing data.↲
↲
┆b0┆X ,X ┆f0┆These bit contains the values of the don't care bits ↲
┆81┆┆b0┆ 0 1 ┆f0┆ ┆82┆in the Address Header of the protocol, and changes ↲
┆84┆value just prior to RxRDY dependent of the received ↓
┆19┆┆87┆┄┄frame. These bits is identical to the output pins.↲
════════════════════════════════════════════════════════════════════════
↓
┆b0┆┆a1┆┆b0┆┆a1┆┆b0┆┆a1┆3. SLAVE MODE CONFIGURATION↲
↲
When the Slave Mode has been Selected (M/-,S pin is low) the ↓
CPCC typically runs in a system with many peripherals to be ↓
serviced by the same CPU. Therefore the RxRDY and TxRDY pins ↓
has been implemented to give the ability of making a clean ↓
interrupt interface.↲
↲
↲
┆b0┆┆a1┆3.1 Initializing↲
↲
Prior to operation the Control registers must be initiali┄↓
zed. The STST bit of Control register B must be low and the ↓
BREN must be low unless Broadcast option is chosen (explai┄↓
ned below). If the Control register A is loaded after the B ↓
register, the CCEN may be made high together with the wri┄↓
ting of the device address, RxEN and TxEN, the reception ↓
will be initiated upon CCEN high.↲
↲
↲
┆b0┆┆a1┆3.2 Running↲
↲
When the CPCC is initiated and CCEN is high the Reception is ↓
enabled and upon reception of a frame for the device, the ↓
transmission is initiated either with the previously loaded ↓
data byte or with the "no data" answer. Upon reception of a ↓
valid frame with a data byte the RxRDY is asserted and upon ↓
load of a byte to be transmitted TxRDY is asserted. Both ↓
RxRDY and TxRDY are cleared by the leading edge of read from ↓
the Rx-register and write to the Tx-register respectively.↲
↲
↲
┆b0┆┆a1┆3.3 Broadcast Options↲
↲
If BREN is set to high level during Initialization the ↓
Broadcast Recognition Address too has to be loaded to the ↓
Control register B. If this Broadcast address is recognized ↓
and followed by a data byte during the communication on the ↓
line, RxRDY is asserted together with BRC to indicate that ↓
the data byte has been received via the Broadcast Address. ↓
No Transmission are initiated upon reception of a broadcast ↓
frame.↲
↲
↲
════════════════════════════════════════════════════════════════════════
↓
┆b0┆┆a1┆4. SELFTEST MODE CONFIGURATION↲
↲
This Mode have been implemented to gain the ability to have ↓
the CPCC and surrounded circuitry to test it self. To do ↓
this the CPCC must not be attached to any active Circuit II ↓
line since the format of the selftest frames transmitted by ↓
the device under test to the line would violate all other ↓
communication on the line. The selftest function is merely ↓
an echoing of transmitted data via the line transformer to ↓
the Receive buffer of the CPCC. All status informationis ac┄↓
tive during this mode as well as the interrupt generation.↲
↲
↲
┆b0┆┆a1┆4.1 Initializing↲
↲
Since no Address header is necessary, Control register A and ↓
B are only to be initialized in the matter of RxEN, TxEN, ↓
STST (STST="1") and CCEN. M/-,S must be held low.↲
↲
↲
┆b0┆┆a1┆4.2 Running↲
↲
To initiate Communication data must be written to the Tx-re┄↓
gister. The meaning of TxRDY and RxRDY differs sligthly from ↓
the slave mode. Opposite the slave mode it is not allowed to ↓
write the next data byte to the transmit register earlier ↓
than 32 tcy (8 us at 4MHz) after the assertion of RxRDY from ↓
the previous transception. This is due to the way transmis┄↓
sion is initiated in the selftest mode.↲
↲
════════════════════════════════════════════════════════════════════════
↓
┆b0┆┆a1┆5. GENERAL CHARACTERISTICS↲
↲
════════════════════════════════════════════════════════════════════════
↓
┆b0┆┆a1┆6. DC CHARACTERISTICS↲
↲
↲
════════════════════════════════════════════════════════════════════════
↓
┆b0┆┆a1┆7. AC CHARACTERISTICS↲
↲
↲
┆1a┆┆1a┆received ↓
┆19┆┆87┆┄┄frame. These bits is
0x0000…0020 (0,) 00 00 00 00 00 00 00 00 3a 03 06 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 0c 4e 00 00 00 ┆ : N ┆
0x0020…0040 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ┆ ┆
0x0040…0047 00 00 00 00 00 00 00 ┆ ┆
0x0047…0080 Params {
0x0047…0080 04 00 2d 4c 0a 00 05 00 00 00 00 02 01 3c 31 40 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ┆ -L <1@ ┆
0x0047…0080 00 00 00 00 00 00 00 00 05 0a 0f 19 23 2d 37 41 4b 55 5f 69 73 7d 87 ff 04 ┆ #-7AKU_iså ┆
0x0047…0080 }
0x0080…00a0 06 69 0d 0a 0d 0a b0 a1 54 41 42 4c 45 20 4f 46 20 43 4f 4e 54 45 4e 54 53 05 50 41 47 45 0d 0a ┆ i TABLE OF CONTENTS PAGE ┆
0x00a0…00c0 0d 0a 31 2e 20 49 4e 54 52 4f 44 55 43 54 49 4f 4e 20 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e ┆ 1. INTRODUCTION ..............┆
0x00c0…00e0 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 20 20 20 20 31 0d 0a ┆......................... 1 ┆
0x00e0…0100 0d 0a 32 2e 20 46 55 4e 43 54 49 4f 4e 41 4c 20 44 45 53 43 52 49 50 54 49 4f 4e 20 2e 2e 2e 2e ┆ 2. FUNCTIONAL DESCRIPTION ....┆
0x0100…0120 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 20 20 20 20 32 0d 0a ┆......................... 2 ┆
0x0120…0140 20 20 20 32 2e 31 20 42 6c 6f 63 6b 20 44 69 61 67 72 61 6d 20 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e ┆ 2.1 Block Diagram ...........┆
0x0140…0160 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 20 20 20 20 32 0d 0a 20 20 ┆....................... 2 ┆
0x0160…0180 20 32 2e 32 20 50 69 6e 20 4f 75 74 20 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e ┆ 2.2 Pin Out ...................┆
0x0180…01a0 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 20 20 20 20 33 0d 0a 20 20 20 32 ┆..................... 3 2┆
0x01a0…01c0 2e 33 20 50 69 6e 20 44 65 73 69 67 6e 61 74 69 6f 6e 20 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e ┆.3 Pin Designation .............┆
0x01c0…01e0 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 20 20 20 20 34 0d 0a 20 20 20 32 2e 34 ┆................... 4 2.4┆
0x01e0…0200 20 52 65 67 69 73 74 65 72 20 41 64 64 72 65 73 73 69 6e 67 20 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e ┆ Register Addressing ...........┆
0x0200…0220 (1,) 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 20 20 20 20 37 0d 0a 20 20 20 32 2e 35 20 52 ┆................. 7 2.5 R┆
0x0220…0240 65 67 69 73 74 65 72 20 44 65 66 69 6e 69 74 69 6f 6e 73 20 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e ┆egister Definitions ............┆
0x0240…0260 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 20 20 20 20 37 0d 0a 20 20 20 20 20 20 20 32 2e 35 ┆............... 7 2.5┆
0x0260…0280 2e 31 20 43 6f 6e 74 72 6f 6c 20 52 65 67 69 73 74 65 72 20 61 20 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e ┆.1 Control Register a ..........┆
0x0280…02a0 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 20 20 20 20 37 0d 0a 20 20 20 20 20 20 20 32 2e 35 2e 32 ┆............. 7 2.5.2┆
0x02a0…02c0 20 43 6f 6e 74 72 6f 6c 20 52 65 67 69 73 74 65 72 20 62 20 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e ┆ Control Register b ............┆
0x02c0…02e0 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 20 20 20 20 38 0d 0a 20 20 20 20 20 20 20 32 2e 35 2e 33 20 54 ┆........... 8 2.5.3 T┆
0x02e0…0300 72 61 6e 73 6d 69 74 20 52 65 67 69 73 74 65 72 20 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e ┆ransmit Register ...............┆
0x0300…0320 2e 2e 2e 2e 2e 2e 2e 2e 2e 20 20 20 20 38 0d 0a 20 20 20 20 20 20 20 32 2e 35 2e 34 20 52 65 63 ┆......... 8 2.5.4 Rec┆
0x0320…0340 65 69 76 65 20 52 65 67 69 73 74 65 72 20 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e ┆eive Register ..................┆
0x0340…0360 2e 2e 2e 2e 2e 2e 2e 20 20 20 20 38 0d 0a 20 20 20 20 20 20 20 32 2e 35 2e 35 20 53 74 61 74 75 ┆....... 8 2.5.5 Statu┆
0x0360…0380 73 20 52 65 67 69 73 74 65 72 20 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e ┆s Register .....................┆
0x0380…03a0 2e 2e 2e 2e 2e 20 20 20 20 39 0d 0a 0d 0a 33 2e 20 53 4c 41 56 45 20 4d 4f 44 45 20 43 4f 4e 46 ┆..... 9 3. SLAVE MODE CONF┆
0x03a0…03c0 49 47 55 52 41 54 49 4f 4e 20 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e ┆IGURATION ......................┆
0x03c0…03e0 2e 2e 2e 2e 2e 20 20 20 31 30 0d 0a 20 20 20 33 2e 31 20 49 6e 69 74 69 61 6c 69 7a 69 6e 67 20 ┆..... 10 3.1 Initializing ┆
0x03e0…0400 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e ┆................................┆
0x0400…0420 (2,) 2e 2e 2e 20 20 20 31 30 0d 0a 20 20 20 33 2e 32 20 52 75 6e 6e 69 6e 67 20 2e 2e 2e 2e 2e 2e 2e ┆... 10 3.2 Running .......┆
0x0420…0440 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e ┆................................┆
0x0440…0460 2e 20 20 20 31 30 0d 0a 20 20 20 33 2e 33 20 42 72 6f 61 64 63 61 73 74 20 4f 70 74 69 6f 6e 73 ┆. 10 3.3 Broadcast Options┆
0x0460…0480 20 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 20 ┆ .............................. ┆
0x0480…04a0 20 20 31 30 0d 0a 0d 0a 34 2e 20 53 45 4c 46 54 45 53 54 20 4d 4f 44 45 20 43 4f 4e 46 49 47 55 ┆ 10 4. SELFTEST MODE CONFIGU┆
0x04a0…04c0 52 41 54 49 4f 4e 20 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 20 ┆RATION ........................ ┆
0x04c0…04e0 20 20 31 31 0d 0a 20 20 20 34 2e 31 20 49 6e 69 74 69 61 6c 69 7a 69 6e 67 20 2e 2e 2e 2e 2e 2e ┆ 11 4.1 Initializing ......┆
0x04e0…0500 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 20 20 20 ┆............................. ┆
0x0500…0520 31 31 0d 0a 20 20 20 34 2e 32 20 52 75 6e 6e 69 6e 67 20 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e ┆11 4.2 Running .............┆
0x0520…0540 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 20 20 20 31 31 ┆........................... 11┆
0x0540…0560 0d 0a 0d 0a 35 2e 20 47 45 4e 45 52 41 4c 20 43 48 41 52 41 43 54 45 52 49 53 54 49 43 53 20 2e ┆ 5. GENERAL CHARACTERISTICS .┆
0x0560…0580 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 20 20 20 31 32 ┆........................... 12┆
0x0580…05a0 0d 0a 0d 0a 36 2e 20 44 43 20 43 48 41 52 41 43 54 45 52 49 53 54 49 43 53 20 2e 2e 2e 2e 2e 2e ┆ 6. DC CHARACTERISTICS ......┆
0x05a0…05c0 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 20 20 20 31 33 ┆........................... 13┆
0x05c0…05e0 0d 0a 0d 0a 37 2e 20 41 43 20 43 48 41 52 41 43 54 45 52 49 53 54 49 43 53 20 2e 2e 2e 2e 2e 2e ┆ 7. AC CHARACTERISTICS ......┆
0x05e0…0600 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 20 20 20 31 34 ┆........................... 14┆
0x0600…0602 (3,) 0d 0a ┆ ┆
0x0602…0605 FormFeed {
0x0602…0605 0c 82 a0 ┆ ┆
0x0602…0605 }
0x0605…0620 0a 06 69 69 0d 0a 0d 0a a1 b0 52 45 46 45 52 45 4e 43 45 53 09 09 09 09 09 20 20 ┆ ii REFERENCES ┆
0x0620…0640 20 20 20 0d 0a 0d 0a 43 49 52 43 55 49 54 20 49 49 20 52 65 66 65 72 65 6e 63 65 20 4d 61 6e 75 ┆ CIRCUIT II Reference Manu┆
0x0640…0660 61 6c 20 20 20 52 43 53 4c 20 4e 6f 2e 3a 20 34 34 2d 52 54 32 31 35 37 2c 20 4d 61 79 20 31 39 ┆al RCSL No.: 44-RT2157, May 19┆
0x0660…0680 38 34 0d 0a 0d 0a 50 68 69 6c 69 70 73 20 43 4d 4f 53 20 47 61 74 65 20 61 72 72 61 79 20 64 65 ┆84 Philips CMOS Gate array de┆
0x0680…06a0 73 69 67 6e 20 4d 61 6e 75 61 6c 2c 20 61 75 74 75 6d 6e 20 31 39 38 34 0d 0a 09 20 20 20 20 50 ┆sign Manual, autumn 1984 P┆
0x06a0…06c0 43 46 2f 50 43 43 30 33 33 30 3b 20 30 34 35 30 3b 20 30 37 30 30 3b 20 31 31 30 30 20 67 61 74 ┆CF/PCC0330; 0450; 0700; 1100 gat┆
0x06c0…06e0 65 20 61 72 72 61 79 20 66 61 6d 69 6c 79 0d 0a 20 20 20 20 20 20 20 20 50 68 69 6c 69 70 73 20 ┆e array family Philips ┆
0x06e0…0700 64 6f 63 2e 20 6e 6f 2e 3f 0d 0a 0d 0a 50 68 69 6c 69 70 73 20 48 43 4d 4f 53 20 47 61 74 65 20 ┆doc. no.? Philips HCMOS Gate ┆
0x0700…0720 61 72 72 61 79 20 44 65 76 65 6c 6f 70 6d 65 6e 74 20 73 61 6d 70 6c 65 20 64 61 74 61 2c 20 6a ┆array Development sample data, j┆
0x0720…0740 75 6e 65 20 31 39 38 34 0d 0a 20 20 20 20 20 20 20 20 50 43 46 2f 50 43 43 30 33 33 35 3b 20 30 ┆une 1984 PCF/PCC0335; 0┆
0x0740…0760 34 35 35 3b 20 30 37 30 35 3b 20 31 31 30 35 20 67 61 74 65 20 61 72 72 61 79 20 66 61 6d 69 6c ┆455; 0705; 1105 gate array famil┆
0x0760…0780 79 0d 0a 09 20 20 20 20 50 68 69 6c 69 70 73 20 64 6f 63 2e 20 6e 6f 2e 20 39 33 39 37 20 30 32 ┆y Philips doc. no. 9397 02┆
0x0780…078a 32 20 36 30 31 34 32 2e 0d 0a ┆2 60142. ┆
0x078a…078d FormFeed {
0x078a…078d 0c 80 f5 ┆ ┆
0x078a…078d }
0x078d…07a0 0a 14 b3 06 0b 0d 0a 0d 0a b0 a1 31 2e 20 49 4e 54 52 4f ┆ 1. INTRO┆
0x07a0…07c0 44 55 43 54 49 4f 4e 0d 0a 0d 0a 54 68 65 20 43 69 72 63 75 69 74 20 49 49 20 50 72 6f 74 6f 63 ┆DUCTION The Circuit II Protoc┆
0x07c0…07e0 6f 6c 20 43 6f 6d 6d 75 6e 69 63 61 74 69 6f 6e 73 20 43 6f 6e 74 72 6f 6c 6c 65 72 20 28 43 50 ┆ol Communications Controller (CP┆
0x07e0…0800 43 43 29 20 69 73 20 0a 6d 61 64 65 20 61 73 20 61 20 70 65 72 69 70 68 65 72 61 6c 20 64 65 76 ┆CC) is made as a peripheral dev┆
0x0800…0820 (4,) 69 63 65 20 74 6f 20 69 6e 74 65 72 66 61 63 65 20 62 65 80 74 77 65 65 6e 20 61 20 43 50 55 20 ┆ice to interface be tween a CPU ┆
0x0820…0840 61 6e 64 20 0a 74 68 65 20 43 49 52 43 55 49 54 20 49 49 20 70 72 6f 74 6f 63 6f 6c 20 64 65 76 ┆and the CIRCUIT II protocol dev┆
0x0840…0860 65 6c 6f 70 65 64 20 62 79 20 52 43 2e 20 54 68 69 73 20 63 68 61 72 61 63 74 65 72 20 0a 6f 72 ┆eloped by RC. This character or┆
0x0860…0880 69 65 6e 74 65 64 20 70 72 6f 74 6f 63 6f 6c 20 69 73 20 62 61 73 65 64 20 6f 6e 20 61 20 70 6f ┆iented protocol is based on a po┆
0x0880…08a0 6c 6c 69 6e 67 20 6d 61 73 80 74 65 72 20 61 6e 64 20 75 70 20 74 6f 20 33 32 20 0a 73 6c 61 76 ┆lling mas ter and up to 32 slav┆
0x08a0…08c0 65 73 20 77 69 74 68 20 74 68 65 20 64 61 74 61 20 74 72 61 6e 73 66 65 72 20 6f 6e 6c 79 20 62 ┆es with the data transfer only b┆
0x08c0…08e0 65 74 77 65 65 6e 20 74 68 65 20 4d 61 73 80 74 65 72 20 61 6e 64 20 0a 6f 6e 65 20 53 6c 61 76 ┆etween the Mas ter and one Slav┆
0x08e0…0900 65 20 64 65 76 69 63 65 20 61 74 20 61 20 74 69 6d 65 2e 20 49 6e 20 74 68 65 20 43 50 43 43 20 ┆e device at a time. In the CPCC ┆
0x0900…0920 68 6f 77 80 65 76 65 72 20 61 20 42 72 6f 61 64 63 61 73 74 20 0a 6f 70 74 69 6f 6e 20 69 73 20 ┆how ever a Broadcast option is ┆
0x0920…0940 69 6d 70 6c 65 6d 65 6e 74 65 64 20 74 6f 20 6d 61 6b 65 20 69 74 20 70 6f 73 73 69 62 6c 65 20 ┆implemented to make it possible ┆
0x0940…0960 66 6f 72 20 74 68 65 20 4d 61 73 74 65 72 20 74 6f 20 0a 74 72 61 6e 73 66 65 72 20 64 61 74 61 ┆for the Master to transfer data┆
0x0960…0980 20 74 6f 20 73 65 76 65 72 61 6c 20 53 6c 61 76 65 73 20 73 69 6d 75 6c 74 61 6e 80 6f 75 73 6c ┆ to several Slaves simultan ousl┆
0x0980…09a0 79 2e 0d 0a 0d 0a 41 20 73 65 6c 66 74 65 73 74 20 6f 70 74 69 6f 6e 20 69 73 20 69 6d 70 6c 65 ┆y. A selftest option is imple┆
0x09a0…09c0 6d 65 6e 74 65 64 20 74 6f 20 6d 61 6b 65 20 69 74 20 70 6f 73 73 69 62 6c 65 20 74 6f 20 74 65 ┆mented to make it possible to te┆
0x09c0…09e0 73 74 20 0a 74 68 65 20 65 6e 74 69 72 65 20 69 6e 74 65 72 66 61 63 65 20 63 69 72 63 75 69 74 ┆st the entire interface circuit┆
0x09e0…0a00 20 62 79 20 65 63 68 6f 69 6e 67 20 74 72 61 6e 73 6d 69 74 74 65 64 20 64 61 74 61 20 76 69 61 ┆ by echoing transmitted data via┆
0x0a00…0a20 (5,) 20 0a 74 68 65 20 64 72 69 76 69 6e 67 20 74 72 61 6e 73 66 6f 72 6d 65 72 20 69 6e 74 6f 20 74 ┆ the driving transformer into t┆
0x0a20…0a40 68 65 20 72 65 63 65 69 76 65 72 2e 0d 0a 0d 0a 54 68 65 20 43 50 43 43 20 69 73 20 69 6d 70 6c ┆he receiver. The CPCC is impl┆
0x0a40…0a60 65 6d 65 6e 74 65 64 20 69 6e 20 61 6e 20 31 31 31 36 20 67 61 74 65 20 53 68 72 69 6e 6b 65 64 ┆emented in an 1116 gate Shrinked┆
0x0a60…0a80 20 48 69 67 68 20 53 70 65 65 64 20 0a 43 4d 4f 53 20 41 72 72 61 79 20 66 72 6f 6d 20 50 68 69 ┆ High Speed CMOS Array from Phi┆
0x0a80…0aa0 6c 69 70 73 20 61 6e 64 20 69 73 20 69 6e 2d 20 61 6e 64 20 6f 75 74 70 75 74 20 63 6f 6d 70 61 ┆lips and is in- and output compa┆
0x0aa0…0abd 74 69 62 6c 65 20 74 6f 20 0a 48 43 2f 48 43 54 20 6c 6f 67 69 63 2e 0d 0a 0d 0a 0d 0a ┆tible to HC/HCT logic. ┆
0x0abd…0ac0 FormFeed {
0x0abd…0ac0 0c 81 bd ┆ ┆
0x0abd…0ac0 }
0x0ac0…0ae0 0a 0d 0a b0 a1 32 2e 20 46 55 4e 43 54 49 4f 4e 41 4c 20 44 45 53 43 52 49 50 54 49 4f 4e 0d 0a ┆ 2. FUNCTIONAL DESCRIPTION ┆
0x0ae0…0af9 0d 0a b0 a1 32 2e 31 20 42 6c 6f 63 6b 20 44 69 61 67 72 61 6d 0d 0a 0d 0a ┆ 2.1 Block Diagram ┆
0x0af9…0afc FormFeed {
0x0af9…0afc 0c 80 ad ┆ ┆
0x0af9…0afc }
0x0afc…0b00 0a b0 a1 32 ┆ 2┆
0x0b00…0b0e 2e 32 20 50 69 6e 20 4f 75 74 0d 0a 0d 0a ┆.2 Pin Out ┆
0x0b0e…0b11 FormFeed {
0x0b0e…0b11 0c 80 92 ┆ ┆
0x0b0e…0b11 }
0x0b11…0b20 0a b0 a1 32 2e 33 20 50 69 6e 20 44 65 73 69 ┆ 2.3 Pin Desi┆
0x0b20…0b40 67 6e 61 74 69 6f 6e 0d 0a 0d 0a a1 4d 6e 65 6d 6f 6e 69 63 20 20 20 50 69 6e 20 6e 6f 20 20 20 ┆gnation Mnemonic Pin no ┆
0x0b40…0b60 54 79 70 65 20 20 20 4e 61 6d 65 20 61 6e 64 20 46 75 6e 63 74 69 6f 6e 05 0d 0a 0d 0a b0 44 30 ┆Type Name and Function D0┆
0x0b60…0b80 2e 2e 44 37 f0 20 20 20 20 20 31 2d 38 20 20 20 20 20 20 49 2f 4f 20 20 20 20 84 54 68 69 73 20 ┆..D7 1-8 I/O This ┆
0x0b80…0ba0 33 2d 73 74 61 74 65 20 62 69 64 69 72 65 63 74 69 6f 6e 61 6c 20 38 20 62 69 74 20 0a 19 9b 81 ┆3-state bidirectional 8 bit ┆
0x0ba0…0bc0 80 62 75 66 66 65 72 20 69 73 20 75 73 65 64 20 74 6f 20 69 6e 74 65 72 66 61 63 65 20 74 6f 20 ┆ buffer is used to interface to ┆
0x0bc0…0be0 0a 19 9b 81 80 74 68 65 20 43 6f 6e 74 72 6f 6c 2d 2c 20 44 61 74 61 2d 20 61 6e 64 20 53 74 61 ┆ the Control-, Data- and Sta┆
0x0be0…0c00 74 75 73 72 65 80 80 0a 19 9b 81 80 67 69 73 74 65 72 2e 0d 0a 0d 0a b0 2d 2c 52 44 f0 20 20 20 ┆tusre gister. -,RD ┆
0x0c00…0c20 (6,) 20 20 20 20 39 20 20 20 20 20 20 20 20 49 20 20 20 20 20 20 84 41 20 22 6c 6f 77 22 20 6f 6e 20 ┆ 9 I A "low" on ┆
0x0c20…0c40 74 68 69 73 20 69 6e 70 75 74 20 69 6e 66 6f 72 6d 73 20 74 68 65 20 0a 19 9b 81 80 43 50 43 43 ┆this input informs the CPCC┆
0x0c40…0c60 20 74 68 61 74 20 74 68 65 20 43 50 55 20 69 73 20 72 65 61 64 69 6e 67 20 64 61 74 61 20 0a 19 ┆ that the CPU is reading data ┆
0x0c60…0c80 9b 81 80 6f 72 20 73 74 61 74 75 73 20 69 6e 66 6f 72 6d 61 74 69 6f 6e 73 20 66 72 6f 6d 20 74 ┆ or status informations from t┆
0x0c80…0ca0 68 65 20 0a 19 9b 81 80 43 50 43 43 2e 0d 0a 0d 0a b0 2d 2c 57 52 f0 20 20 20 20 20 20 20 31 30 ┆he CPCC. -,WR 10┆
0x0ca0…0cc0 20 20 20 20 20 20 20 49 20 20 20 20 20 20 84 41 20 22 6c 6f 77 22 20 6f 6e 20 74 68 69 73 20 69 ┆ I A "low" on this i┆
0x0cc0…0ce0 6e 70 75 74 20 69 6e 66 6f 72 6d 73 20 74 68 65 20 0a 19 9b 81 80 43 50 43 43 20 74 68 61 74 20 ┆nput informs the CPCC that ┆
0x0ce0…0d00 74 68 65 20 43 50 55 20 69 73 20 77 72 69 74 69 6e 67 20 43 6f 6e 80 0a 19 9b 81 80 74 72 6f 6c ┆the CPU is writing Con trol┆
0x0d00…0d20 20 6f 72 20 44 61 74 61 20 69 6e 66 6f 72 6d 61 74 69 6f 6e 73 20 74 6f 20 74 68 65 20 0a 19 9b ┆ or Data informations to the ┆
0x0d20…0d40 81 80 43 50 43 43 2e 0d 0a 0d 0a b0 2d 2c 43 53 f0 20 20 20 20 20 20 20 31 31 20 20 20 20 20 20 ┆ CPCC. -,CS 11 ┆
0x0d40…0d60 20 49 20 20 20 20 20 20 84 41 20 22 6c 6f 77 22 20 6f 6e 20 74 68 69 73 20 69 6e 70 75 74 20 73 ┆ I A "low" on this input s┆
0x0d60…0d80 65 6c 65 63 74 73 20 74 68 65 20 0a 19 9b 81 80 43 50 43 43 2e 20 4e 6f 20 72 65 61 64 69 6e 67 ┆elects the CPCC. No reading┆
0x0d80…0da0 20 6f 72 20 77 72 69 74 69 6e 67 20 77 69 6c 6c 20 0a 19 9b 81 80 6f 63 63 75 72 20 75 6e 6c 65 ┆ or writing will occur unle┆
0x0da0…0dc0 73 73 20 74 68 65 20 64 65 76 69 63 65 20 69 73 20 73 65 6c 65 63 80 0a 19 9b 81 80 74 65 64 2e ┆ss the device is selec ted.┆
0x0dc0…0de0 20 57 68 65 6e 20 2d 2c 43 53 20 69 73 20 68 69 67 68 2c 20 74 68 65 20 44 61 74 61 20 0a 19 9b ┆ When -,CS is high, the Data ┆
0x0de0…0e00 81 80 62 75 73 20 63 6f 6e 64 69 74 69 6f 6e 20 77 69 6c 6c 20 68 61 76 65 20 6e 6f 20 65 66 66 ┆ bus condition will have no eff┆
0x0e00…0e20 (7,) 65 63 74 20 0a 19 9b 81 80 6f 6e 20 74 68 65 20 63 68 69 70 2e 0d 0a 0d 0a b0 41 30 2e 2e 41 31 ┆ect on the chip. A0..A1┆
0x0e20…0e40 f0 20 20 20 20 20 31 32 2c 31 33 20 20 20 20 49 20 20 20 20 20 20 84 54 68 65 73 65 20 69 6e 70 ┆ 12,13 I These inp┆
0x0e40…0e60 75 74 73 20 69 6e 20 63 6f 6e 6a 75 6e 63 74 69 6f 6e 20 77 69 74 68 20 0a 19 9b 81 80 74 68 65 ┆uts in conjunction with the┆
0x0e60…0e80 20 2d 2c 52 44 20 61 6e 64 20 2d 2c 57 52 20 69 6e 70 75 74 73 2c 20 69 6e 66 6f 72 6d 73 20 0a ┆ -,RD and -,WR inputs, informs ┆
0x0e80…0ea0 19 9b 81 80 74 68 65 20 43 50 43 43 20 74 68 61 74 20 74 68 65 20 77 6f 72 64 20 6f 6e 20 74 68 ┆ the CPCC that the word on th┆
0x0ea0…0ec0 65 20 64 61 80 0a 19 9b 81 80 74 61 20 62 75 73 20 69 73 20 65 69 74 68 65 72 20 63 6f 6e 74 72 ┆e da ta bus is either contr┆
0x0ec0…0ee0 6f 6c 20 64 61 74 61 20 6f 72 20 0a 19 9b 81 80 53 74 61 74 75 73 20 69 6e 66 6f 72 6d 61 74 69 ┆ol data or Status informati┆
0x0ee0…0f00 6f 6e 2e 0d 0a 0d 0a b0 47 6e 64 20 f0 20 20 20 20 20 20 20 31 34 20 20 20 20 20 20 20 20 20 20 ┆on. Gnd 14 ┆
0x0f00…0f20 20 20 20 20 84 47 72 6f 75 6e 64 3a 20 30 56 20 72 65 66 65 72 65 6e 63 65 0d 0a 0d 0a b0 58 54 ┆ Ground: 0V reference XT┆
0x0f20…0f40 41 4c 31 2c f0 20 20 20 20 20 31 35 2c 31 36 20 20 20 20 20 20 20 20 20 20 20 58 54 41 4c 31 20 ┆AL1, 15,16 XTAL1 ┆
0x0f40…0f60 61 6e 64 20 58 54 41 4c 32 20 61 72 65 20 74 68 65 20 6f 75 74 70 75 74 20 0d 0a 19 80 81 80 b0 ┆and XTAL2 are the output ┆
0x0f60…0f80 58 54 41 4c 32 f0 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 84 61 6e 64 ┆XTAL2 and┆
0x0f80…0fa0 20 69 6e 70 75 74 20 72 65 73 70 65 63 74 69 76 65 6c 79 20 6f 66 20 61 6e 20 69 6e 80 0a 19 9b ┆ input respectively of an in ┆
0x0fa0…0fc0 82 80 76 65 72 74 69 6e 67 20 61 6d 70 6c 69 66 69 65 72 20 77 68 69 63 68 20 69 73 20 69 6e 74 ┆ verting amplifier which is int┆
0x0fc0…0fe0 65 6e 80 0a 19 9b 82 80 64 65 64 20 66 6f 72 20 75 73 65 20 61 73 20 61 20 63 72 79 73 74 61 6c ┆en ded for use as a crystal┆
0x0fe0…1000 20 6f 73 63 69 6c 6c 61 80 0a 19 9b 82 80 74 6f 72 2e 20 54 6f 20 64 72 69 76 65 20 74 68 65 20 ┆ oscilla tor. To drive the ┆
0x1000…1020 (8,) 43 50 43 43 20 77 69 74 68 20 61 6e 20 0a 19 9b 82 80 65 78 74 65 72 6e 61 6c 20 6f 73 63 69 6c ┆CPCC with an external oscil┆
0x1020…1040 6c 61 74 6f 72 20 58 54 41 4c 31 20 6d 75 73 74 20 62 65 20 0a 19 9b 82 80 75 73 65 64 20 61 73 ┆lator XTAL1 must be used as┆
0x1040…1060 20 69 6e 70 75 74 20 77 68 69 6c 65 20 58 54 41 4c 32 20 6d 75 73 74 20 62 65 20 0a 19 9b 82 80 ┆ input while XTAL2 must be ┆
0x1060…1080 6c 65 66 74 20 6f 70 65 6e 2e 0d 0a 0d 0a b0 54 78 52 44 59 20 f0 20 20 20 20 20 31 37 20 20 20 ┆left open. TxRDY 17 ┆
0x1080…10a0 20 20 20 20 30 20 20 20 20 20 20 84 54 72 61 6e 73 6d 69 74 74 65 72 20 52 65 61 64 79 2e 0d 0a ┆ 0 Transmitter Ready. ┆
0x10a0…10c0 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 84 49 6e 20 53 ┆ In S┆
0x10c0…10e0 6c 61 76 65 20 6d 6f 64 65 20 74 68 69 73 20 6f 75 74 70 75 74 20 73 69 67 6e 61 6c 73 20 0a 19 ┆lave mode this output signals ┆
0x10e0…1100 9b 80 80 74 68 65 20 43 50 55 20 74 68 61 74 20 74 68 65 20 74 72 61 6e 73 6d 69 74 74 65 72 20 ┆ the CPU that the transmitter ┆
0x1100…1120 69 73 20 0a 19 9b 80 80 72 65 61 64 79 20 74 6f 20 61 63 80 80 63 65 70 74 20 61 20 64 61 74 61 ┆is ready to ac cept a data┆
0x1120…112e 20 63 68 61 72 61 63 74 65 72 2e 20 0d 0a ┆ character. ┆
0x112e…1131 FormFeed {
0x112e…1131 0c 83 a7 ┆ ┆
0x112e…1131 }
0x1131…1140 0a a1 4d 6e 65 6d 6f 6e 69 63 20 20 20 50 69 ┆ Mnemonic Pi┆
0x1140…1160 6e 20 6e 6f 20 20 20 54 79 70 65 20 20 20 4e 61 6d 65 20 61 6e 64 20 46 75 6e 63 74 69 6f 6e 05 ┆n no Type Name and Function ┆
0x1160…1180 0d 0a 0d 0a 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 84 ┆ ┆
0x1180…11a0 54 68 65 20 54 78 52 44 59 20 6f 75 74 70 75 74 20 70 69 6e 20 63 61 6e 20 62 65 20 75 73 65 64 ┆The TxRDY output pin can be used┆
0x11a0…11c0 20 0a 19 9b 80 80 61 73 20 61 6e 20 69 6e 2d 74 65 72 72 75 70 74 20 74 6f 20 74 68 65 20 73 79 ┆ as an in-terrupt to the sy┆
0x11c0…11e0 73 74 65 6d 20 0a 19 9b 80 80 6f 72 2c 20 66 6f 72 20 50 6f 6c 6c 65 64 20 6f 70 65 72 61 74 69 ┆stem or, for Polled operati┆
0x11e0…1200 6f 6e 2c 20 74 68 65 20 43 50 55 20 0a 19 9b 80 80 63 61 6e 20 63 68 65 63 6b 20 54 78 52 44 59 ┆on, the CPU can check TxRDY┆
0x1200…1220 (9,) 20 75 73 69 6e 67 20 61 20 53 74 61 74 75 73 20 0a 19 9b 80 80 52 65 61 64 20 6f 70 65 72 61 74 ┆ using a Status Read operat┆
0x1220…1240 69 6f 6e 2e 20 54 78 52 44 59 20 69 73 20 61 75 74 6f 6d 61 80 0a 19 9b 80 80 74 69 63 61 6c 6c ┆ion. TxRDY is automa ticall┆
0x1240…1260 79 20 72 65 73 65 74 20 62 79 20 74 68 65 20 6c 65 61 64 69 6e 67 20 65 64 67 65 20 0a 19 9b 80 ┆y reset by the leading edge ┆
0x1260…1280 80 6f 66 20 57 52 20 77 68 65 6e 20 61 20 64 61 74 61 20 63 68 61 72 61 63 74 65 72 20 69 73 20 ┆ of WR when a data character is ┆
0x1280…12a0 0a 19 9b 80 80 6c 6f 61 64 65 64 20 66 72 6f 6d 20 74 68 65 20 43 50 55 2e 20 54 68 65 20 54 78 ┆ loaded from the CPU. The Tx┆
0x12a0…12c0 52 44 59 20 0a 19 9b 80 80 6f 75 74 70 75 74 20 70 69 6e 20 69 73 20 6d 61 73 6b 65 64 20 62 79 ┆RDY output pin is masked by┆
0x12c0…12e0 20 74 68 65 20 54 78 45 4e 20 0a 19 9b 80 80 63 6f 6e 74 72 6f 6c 20 62 69 74 2e 20 0d 0a 0d 0a ┆ the TxEN control bit. ┆
0x12e0…1300 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 84 49 6e 20 4d ┆ In M┆
0x1300…1320 61 73 74 65 72 20 6d 6f 64 65 20 69 66 20 74 68 69 73 20 70 69 6e 20 69 73 20 0a 19 9b 80 80 61 ┆aster mode if this pin is a┆
0x1320…1340 73 73 65 72 74 65 64 20 74 6f 67 65 74 68 65 72 20 77 69 74 68 20 74 68 65 20 54 78 52 44 59 20 ┆sserted together with the TxRDY ┆
0x1340…1360 0a 19 9b 80 80 70 69 6e 20 69 74 20 69 6e 64 69 63 61 74 65 73 20 74 68 61 74 20 61 20 70 72 6f ┆ pin it indicates that a pro┆
0x1360…1380 70 65 72 20 0a 19 9b 80 80 61 6e 73 77 65 72 20 77 69 74 68 20 6e 6f 20 64 61 74 61 20 68 61 73 ┆per answer with no data has┆
0x1380…13a0 20 62 65 65 6e 20 0a 19 9b 80 80 72 65 63 65 69 76 65 64 2e 0d 0a 0d 0a b0 52 78 52 44 59 20 f0 ┆ been received. RxRDY ┆
0x13a0…13c0 20 20 20 20 20 31 38 20 20 20 20 20 20 20 30 20 20 20 20 20 20 52 65 63 65 69 76 65 72 20 52 65 ┆ 18 0 Receiver Re┆
0x13c0…13e0 61 64 79 2e 0d 0a 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 ┆ady. ┆
0x13e0…1400 20 84 54 68 69 73 20 6f 75 74 70 75 74 20 69 6e 64 69 63 61 74 65 73 20 74 68 61 74 20 74 68 65 ┆ This output indicates that the┆
0x1400…1420 (10,) 20 0a 19 9b 80 80 43 50 43 43 20 63 6f 6e 74 61 69 6e 73 20 61 20 63 68 61 72 61 63 74 65 72 20 ┆ CPCC contains a character ┆
0x1420…1440 74 68 61 74 20 69 73 20 0a 19 9b 80 80 72 65 61 64 79 20 74 6f 20 62 65 20 69 6e 70 75 74 20 74 ┆that is ready to be input t┆
0x1440…1460 6f 20 74 68 65 20 43 50 55 2e 20 0a 19 9b 80 80 52 78 52 44 59 20 63 61 6e 20 62 65 20 63 6f 6e ┆o the CPU. RxRDY can be con┆
0x1460…1480 6e 65 63 74 65 64 20 74 6f 20 74 68 65 20 69 6e 80 0a 19 9b 80 80 74 65 72 72 75 70 74 20 73 74 ┆nected to the in terrupt st┆
0x1480…14a0 72 75 63 74 75 72 65 20 6f 66 20 74 68 65 20 43 50 55 20 6f 72 2c 20 0a 19 9b 80 80 66 6f 72 20 ┆ructure of the CPU or, for ┆
0x14a0…14c0 50 6f 6c 6c 65 64 20 6f 70 65 72 61 74 69 6f 6e 2c 20 74 68 65 20 43 50 55 20 63 61 6e 20 0a 19 ┆Polled operation, the CPU can ┆
0x14c0…14e0 9b 80 80 63 68 65 63 6b 20 74 68 65 20 63 6f 6e 64 69 74 69 6f 6e 20 6f 66 20 52 78 52 44 59 20 ┆ check the condition of RxRDY ┆
0x14e0…1500 0a 19 9b 80 80 75 73 69 6e 67 20 61 20 53 74 61 74 75 73 20 52 65 61 64 20 6f 70 65 72 61 74 69 ┆ using a Status Read operati┆
0x1500…1520 6f 6e 2e 20 0a 19 9b 80 80 52 78 52 44 59 20 69 73 20 61 75 74 6f 6d 61 74 69 63 61 6c 6c 79 20 ┆on. RxRDY is automatically ┆
0x1520…1540 72 65 73 65 74 20 62 79 20 0a 19 9b 80 80 74 68 65 20 6c 65 61 64 69 6e 67 20 65 64 67 65 20 6f ┆reset by the leading edge o┆
0x1540…1560 66 20 52 44 2e 20 54 68 65 20 52 78 52 44 59 20 0a 19 9b 80 80 6f 75 74 70 75 74 20 70 69 6e 20 ┆f RD. The RxRDY output pin ┆
0x1560…1580 69 73 20 6d 61 73 6b 65 64 20 62 79 20 74 68 65 20 52 78 45 4e 20 0a 19 9b 80 80 63 6f 6e 74 72 ┆is masked by the RxEN contr┆
0x1580…15a0 6f 6c 20 62 69 74 2e 0d 0a 0d 0a 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 ┆ol bit. ┆
0x15a0…15c0 20 20 20 20 20 20 84 46 61 69 6c 75 72 65 20 74 6f 20 72 65 61 64 20 74 68 65 20 72 65 63 65 69 ┆ Failure to read the recei┆
0x15c0…15e0 76 65 64 20 0a 19 9b 80 80 63 68 61 72 61 63 74 65 72 20 66 72 6f 6d 20 74 68 65 20 52 78 20 44 ┆ved character from the Rx D┆
0x15e0…1600 61 74 61 20 4f 75 74 70 75 74 20 0a 19 9b 80 80 52 65 67 69 73 74 65 72 20 70 72 69 6f 72 20 74 ┆ata Output Register prior t┆
0x1600…1620 (11,) 6f 20 74 68 65 20 61 73 73 65 6d 62 6c 79 20 6f 66 20 0a 19 9b 80 80 74 68 65 20 6e 65 78 74 20 ┆o the assembly of the next ┆
0x1620…1640 52 78 20 44 61 74 61 20 63 68 61 72 61 63 74 65 72 20 77 69 6c 6c 20 0a 19 9b 80 80 73 65 74 20 ┆Rx Data character will set ┆
0x1640…1660 6f 76 65 72 72 75 6e 20 63 6f 6e 64 69 74 69 6f 6e 20 65 72 72 6f 72 20 61 6e 64 20 0a 19 9b 80 ┆overrun condition error and ┆
0x1660…1680 80 74 68 65 20 70 72 65 76 69 6f 75 73 20 63 68 61 72 61 63 74 65 72 20 77 69 6c 6c 20 62 65 20 ┆ the previous character will be ┆
0x1680…16a0 0a 19 9b 80 80 77 72 69 74 74 65 6e 20 6f 76 65 72 20 61 6e 64 20 6c 6f 73 74 2e 20 49 66 20 74 ┆ written over and lost. If t┆
0x16a0…16c0 68 65 20 52 78 20 0a 19 9b 80 80 44 61 74 61 20 69 73 20 62 65 69 6e 67 20 72 65 61 64 20 62 79 ┆he Rx Data is being read by┆
0x16c0…16e0 20 74 68 65 20 43 50 55 20 0a 19 9b 80 80 77 68 65 6e 20 74 68 65 20 69 6e 74 65 72 6e 61 6c 20 ┆ the CPU when the internal ┆
0x16e0…1700 74 72 61 6e 73 66 65 72 20 69 73 20 6f 63 80 0a 19 9b 80 80 63 75 72 69 6e 67 2c 20 6f 76 65 72 ┆transfer is oc curing, over┆
0x1700…1720 72 75 6e 20 65 72 72 6f 72 20 77 69 6c 6c 20 62 65 20 73 65 74 20 0a 19 9b 80 80 61 6e 64 20 74 ┆run error will be set and t┆
0x1720…1740 68 65 20 6f 6c 64 20 63 68 61 72 61 63 74 65 72 20 77 69 6c 6c 20 62 65 20 0a 19 9b 80 80 6c 6f ┆he old character will be lo┆
0x1740…1760 73 74 2e 0d 0a 0d 0a b0 58 30 2c 20 58 31 f0 20 20 20 20 20 31 39 2c 32 30 20 20 20 20 30 20 20 ┆st. X0, X1 19,20 0 ┆
0x1760…1780 20 20 20 20 84 74 68 65 73 65 20 6f 75 74 70 75 74 73 20 63 6f 6e 74 61 69 6e 73 20 74 68 65 20 ┆ these outputs contains the ┆
0x1780…17a0 76 61 6c 75 65 73 20 0a 19 9b 81 80 6f 66 20 74 68 65 20 64 6f 6e 27 74 20 63 61 72 65 20 62 69 ┆values of the don't care bi┆
0x17a0…17c0 74 73 20 69 6e 20 74 68 65 20 41 64 80 0a 19 9b 81 80 64 72 65 73 73 20 48 65 61 64 65 72 20 6f ┆ts in the Ad dress Header o┆
0x17c0…17e0 66 20 74 68 65 20 70 72 6f 74 6f 63 6f 6c 2c 20 61 6e 64 20 0a 19 9b 81 80 63 68 61 6e 67 65 73 ┆f the protocol, and changes┆
0x17e0…1800 20 76 61 6c 75 65 20 6a 75 73 74 20 70 72 69 6f 72 20 74 6f 20 52 78 52 44 59 20 0a 19 9b 81 80 ┆ value just prior to RxRDY ┆
0x1800…1820 (12,) 64 65 70 65 6e 64 65 6e 74 20 6f 66 20 74 68 65 20 72 65 63 65 69 76 65 64 20 66 72 61 6d 65 2e ┆dependent of the received frame.┆
0x1820…1826 0d 0a 0d 0a b0 0a ┆ ┆
0x1826…1829 FormFeed {
0x1826…1829 0c 83 dd ┆ ┆
0x1826…1829 }
0x1829…1840 0a a1 e1 0d 0a a1 4d 6e 65 6d 6f 6e 69 63 20 20 20 50 69 6e 20 6e 6f ┆ Mnemonic Pin no┆
0x1840…1860 20 20 20 54 79 70 65 20 20 20 4e 61 6d 65 20 61 6e 64 20 46 75 6e 63 74 69 6f 6e 05 0d 0a 0d 0a ┆ Type Name and Function ┆
0x1860…1880 b0 42 52 43 20 f0 20 20 20 20 20 20 20 32 31 20 20 20 20 20 20 20 30 20 20 20 20 20 20 84 49 66 ┆ BRC 21 0 If┆
0x1880…18a0 20 42 72 6f 61 64 63 61 73 74 20 6f 70 74 69 6f 6e 20 69 73 20 63 68 6f 73 65 6e 2c 20 0a 19 9b ┆ Broadcast option is chosen, ┆
0x18a0…18c0 81 80 74 68 69 73 20 6f 75 74 70 75 74 20 69 6e 64 69 63 61 74 65 73 20 77 68 65 74 68 65 72 20 ┆ this output indicates whether ┆
0x18c0…18e0 74 68 65 20 0a 19 9b 81 80 72 65 63 65 69 76 65 64 20 64 61 74 61 20 69 73 20 6e 6f 72 6d 61 6c ┆the received data is normal┆
0x18e0…1900 6c 79 20 61 64 64 72 65 73 80 0a 19 9b 81 80 73 65 64 20 74 6f 20 74 68 65 20 43 50 43 43 20 6f ┆ly addres sed to the CPCC o┆
0x1900…1920 72 20 69 73 20 6f 66 20 42 72 6f 61 64 80 80 80 0a 19 9b 81 80 63 61 73 74 20 74 79 70 65 20 28 ┆r is of Broad cast type (┆
0x1920…1940 42 52 43 20 3d 20 22 68 69 67 68 22 29 3b 20 6f 74 68 65 72 80 0a 19 9b 81 80 77 69 73 65 20 69 ┆BRC = "high"); other wise i┆
0x1940…1960 74 20 72 65 6d 61 69 6e 73 20 6c 6f 77 2e 0d 0a 0d 0a b0 2d 2c 52 45 53 45 54 20 f0 20 20 20 32 ┆t remains low. -,RESET 2┆
0x1960…1980 32 20 20 20 20 20 20 20 49 20 20 20 20 20 20 84 41 20 22 6c 6f 77 22 20 6f 6e 20 74 68 69 73 20 ┆2 I A "low" on this ┆
0x1980…19a0 69 6e 70 75 74 20 66 6f 72 63 65 73 20 74 68 65 20 0a 19 9b 81 80 43 50 43 43 20 69 6e 74 6f 20 ┆input forces the CPCC into ┆
0x19a0…19c0 61 6e 20 22 49 64 6c 65 22 20 6d 6f 64 65 2e 20 54 68 65 20 64 65 80 0a 19 9b 81 80 76 69 63 65 ┆an "Idle" mode. The de vice┆
0x19c0…19e0 20 77 69 6c 6c 20 72 65 6d 61 69 6e 20 61 74 20 22 49 64 6c 65 22 20 75 6e 74 69 6c 20 0a 19 9b ┆ will remain at "Idle" until ┆
0x19e0…1a00 81 80 61 20 6e 65 77 20 73 65 74 20 6f 66 20 63 6f 6e 74 72 6f 6c 20 77 6f 72 64 73 20 69 73 20 ┆ a new set of control words is ┆
0x1a00…1a20 (13,) 0a 19 9b 81 80 77 72 69 74 74 65 6e 20 69 6e 74 6f 20 74 68 65 20 43 50 43 43 20 74 6f 20 70 72 ┆ written into the CPCC to pr┆
0x1a20…1a40 6f 67 72 61 6d 20 0a 19 9b 81 80 69 74 73 20 66 75 6e 63 74 69 6f 6e 61 6c 20 64 65 66 69 6e 74 ┆ogram its functional defint┆
0x1a40…1a60 69 6f 6e 2e 20 4d 69 6e 69 6d 75 6d 20 0a 19 9b 81 80 52 45 53 45 54 20 70 75 6c 73 65 20 77 69 ┆ion. Minimum RESET pulse wi┆
0x1a60…1a80 64 74 68 20 69 73 20 58 74 43 59 20 28 63 6c 6f 63 6b 20 0a 19 9b 81 80 6d 75 73 74 20 62 65 20 ┆dth is XtCY (clock must be ┆
0x1a80…1aa0 72 75 6e 6e 69 6e 67 29 2e 0d 0a 0d 0a b0 20 20 20 20 20 f0 20 20 20 20 20 20 32 33 20 20 20 20 ┆running). 23 ┆
0x1aa0…1ac0 20 20 20 20 20 20 20 20 20 20 84 4e 6f 20 63 6f 6e 6e 65 63 74 69 6f 6e 20 28 75 73 65 64 20 64 ┆ No connection (used d┆
0x1ac0…1ae0 75 72 69 6e 67 20 66 61 63 74 6f 80 0a 19 9b 81 80 72 79 20 74 65 73 74 29 2e 0d 0a 0d 0a b0 46 ┆uring facto ry test). F┆
0x1ae0…1b00 4d 44 49 4e 20 f0 20 20 20 20 20 32 34 20 20 20 20 20 20 20 49 20 20 20 20 20 20 84 46 72 65 71 ┆MDIN 24 I Freq┆
0x1b00…1b20 75 65 6e 63 65 20 4d 6f 44 75 6c 61 74 65 64 20 49 4e 70 75 74 2e 0d 0a 20 20 20 20 20 20 20 20 ┆uence MoDulated INput. ┆
0x1b20…1b40 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 84 54 68 65 20 42 69 70 68 61 73 65 2d ┆ The Biphase-┆
0x1b40…1b60 53 20 65 6e 63 6f 64 65 64 20 69 6e 63 6f 6d 6d 69 6e 67 20 0a 19 9b 80 80 64 61 74 61 20 66 72 ┆S encoded incomming data fr┆
0x1b60…1b80 6f 6d 20 74 68 65 20 43 49 52 43 55 49 54 20 49 49 20 6c 69 6e 65 20 0a 19 9b 80 80 6d 75 73 74 ┆om the CIRCUIT II line must┆
0x1b80…1ba0 20 62 65 20 66 65 64 20 74 6f 20 74 68 69 73 20 69 6e 70 75 74 2e 0d 0a 0d 0a 20 20 20 20 20 20 ┆ be fed to this input. ┆
0x1ba0…1bc0 20 20 20 20 20 32 35 20 20 20 20 20 20 20 20 20 20 20 20 20 20 84 4e 6f 20 63 6f 6e 6e 65 63 74 ┆ 25 No connect┆
0x1bc0…1be0 69 6f 6e 20 28 75 73 65 64 20 64 75 72 69 6e 67 20 66 61 63 74 6f 80 0a 19 9b 80 80 72 79 20 74 ┆ion (used during facto ry t┆
0x1be0…1c00 65 73 74 29 2e 0d 0a 0d 0a b0 4e 46 4d 44 4f f0 20 20 20 20 20 20 32 36 20 20 20 20 20 20 20 30 ┆est). NFMDO 26 0┆
0x1c00…1c20 (14,) 20 20 20 20 20 20 84 4e 65 67 61 74 65 64 20 46 72 65 71 75 65 6e 63 65 20 4d 6f 44 75 6c 61 74 ┆ Negated Frequence MoDulat┆
0x1c20…1c40 65 64 20 4f 75 74 80 0a 19 9b 81 80 70 75 74 2e 0d 0a 20 20 20 20 20 20 20 20 20 20 20 20 20 20 ┆ed Out put. ┆
0x1c40…1c60 20 20 20 20 20 20 20 20 20 20 20 20 20 84 54 68 69 73 20 6f 75 74 70 75 74 20 63 6f 6e 74 61 69 ┆ This output contai┆
0x1c60…1c80 6e 73 20 74 68 65 20 6e 65 67 61 74 69 76 65 20 0a 19 9b 80 80 70 61 72 74 20 6f 66 20 74 68 65 ┆ns the negative part of the┆
0x1c80…1ca0 20 42 69 70 68 61 73 65 2d 53 20 65 6e 63 6f 64 65 64 20 0a 19 9b 80 80 64 61 74 61 20 74 6f 20 ┆ Biphase-S encoded data to ┆
0x1ca0…1cc0 62 65 20 74 72 61 6e 73 6d 69 74 74 65 64 20 6f 6e 20 74 68 65 20 0a 19 9b 80 80 43 49 52 43 55 ┆be transmitted on the CIRCU┆
0x1cc0…1ce0 49 54 20 49 49 20 6c 69 6e 65 2e 0d 0a 0d 0a b0 46 4d 44 4f f0 20 20 20 20 20 20 20 32 37 20 20 ┆IT II line. FMDO 27 ┆
0x1ce0…1d00 20 20 20 20 20 30 20 20 20 20 20 20 46 72 65 71 75 65 6e 63 65 20 4d 6f 44 75 6c 61 74 65 64 20 ┆ 0 Frequence MoDulated ┆
0x1d00…1d20 4f 75 74 70 75 74 2e 0d 0a 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 ┆Output. ┆
0x1d20…1d40 20 20 20 20 84 54 68 69 73 20 6f 75 74 70 75 74 20 63 6f 6e 74 61 69 6e 73 20 74 68 65 20 70 6f ┆ This output contains the po┆
0x1d40…1d60 73 69 74 69 76 65 20 0a 19 9b 80 80 70 61 72 74 20 6f 66 20 74 68 65 20 42 69 70 68 61 73 65 2d ┆sitive part of the Biphase-┆
0x1d60…1d80 53 20 65 6e 63 6f 64 65 64 20 0a 19 9b 80 80 64 61 74 61 20 74 6f 20 62 65 20 74 72 61 6e 73 6d ┆S encoded data to be transm┆
0x1d80…1da0 69 74 74 65 64 20 6f 6e 20 74 68 65 20 0a 19 9b 80 80 43 49 52 43 55 49 54 20 49 49 20 6c 69 6e ┆itted on the CIRCUIT II lin┆
0x1da0…1da8 65 2e 0d 0a 0d 0a 0d 0a ┆e. ┆
0x1da8…1dab FormFeed {
0x1da8…1dab 0c 83 8c ┆ ┆
0x1da8…1dab }
0x1dab…1dc0 0a b0 a1 32 2e 34 20 52 65 67 69 73 74 65 72 20 41 64 64 72 65 ┆ 2.4 Register Addre┆
0x1dc0…1de0 73 73 69 6e 67 0d 0a 0d 0a a1 e1 20 2d 2c 43 53 20 20 20 2d 2c 57 52 20 20 20 2d 2c 52 44 20 20 ┆ssing -,CS -,WR -,RD ┆
0x1de0…1e00 20 41 82 31 20 20 20 81 41 82 30 81 20 0d 0a a1 81 05 0d 0a 20 20 30 20 20 20 20 20 20 30 20 20 ┆ A 1 A 0 0 0 ┆
0x1e00…1e20 (15,) 20 20 20 20 31 20 20 20 20 20 31 20 20 20 20 30 20 20 20 43 50 55 2d 3e 43 6f 6e 74 72 6f 6c 20 ┆ 1 1 0 CPU->Control ┆
0x1e20…1e40 72 65 67 69 73 74 65 72 20 61 0d 0a 0d 0a 20 20 30 20 20 20 20 20 20 30 20 20 20 20 20 20 31 20 ┆register a 0 0 1 ┆
0x1e40…1e60 20 20 20 20 31 20 20 20 20 31 20 20 20 43 50 55 2d 3e 43 6f 6e 74 72 6f 6c 20 72 65 67 69 73 74 ┆ 1 1 CPU->Control regist┆
0x1e60…1e80 65 72 20 62 0d 0a 0d 0a 20 20 30 20 20 20 20 20 20 30 20 20 20 20 20 20 31 20 20 20 20 20 30 20 ┆er b 0 0 1 0 ┆
0x1e80…1ea0 20 20 20 30 20 20 20 43 50 55 2d 3e 54 78 20 64 61 74 61 20 72 65 67 69 73 74 65 72 0d 0a 0d 0a ┆ 0 CPU->Tx data register ┆
0x1ea0…1ec0 20 20 30 20 20 20 20 20 20 31 20 20 20 20 20 20 30 20 20 20 20 20 30 20 20 20 20 30 20 20 20 20 ┆ 0 1 0 0 0 ┆
0x1ec0…1ee0 20 20 20 20 52 78 20 64 61 74 61 20 72 65 67 69 73 74 65 72 2d 3e 43 50 55 0d 0a a1 0d 0a a1 a1 ┆ Rx data register->CPU ┆
0x1ee0…1f00 e1 20 20 30 20 20 20 20 20 20 31 20 20 20 20 20 20 30 20 20 20 20 20 30 20 20 20 20 31 20 20 20 ┆ 0 1 0 0 1 ┆
0x1f00…1f20 20 20 20 20 20 53 74 61 74 75 73 20 72 65 67 69 73 74 65 72 2d 3e 43 50 55 05 0d 0a a1 09 09 09 ┆ Status register->CPU ┆
0x1f20…1f40 09 09 09 09 09 09 09 09 09 09 0d 0a 0d 0a 0d 0a b0 a1 32 2e 35 20 52 65 67 69 73 74 65 72 20 44 ┆ 2.5 Register D┆
0x1f40…1f60 65 66 69 6e 69 74 69 6f 6e 73 0d 0a 0d 0a 55 70 6f 6e 20 70 6f 77 65 72 20 75 70 20 74 68 65 20 ┆efinitions Upon power up the ┆
0x1f60…1f80 43 50 43 43 20 6d 75 73 74 20 62 65 20 69 6e 69 74 69 61 6c 69 7a 65 64 20 62 65 66 6f 72 65 20 ┆CPCC must be initialized before ┆
0x1f80…1fa0 69 74 20 69 73 20 61 6c 80 0a 6c 6f 77 65 64 20 74 6f 20 69 6e 69 74 69 61 74 65 20 61 6e 79 20 ┆it is al lowed to initiate any ┆
0x1fa0…1fc0 63 6f 6d 6d 75 6e 69 63 61 74 69 6f 6e 20 6f 6e 20 74 68 65 20 73 65 72 69 61 6c 20 62 75 73 2e ┆communication on the serial bus.┆
0x1fc0…1fe0 20 54 68 69 73 20 0a 69 73 20 64 6f 6e 65 20 74 6f 20 70 72 6f 68 69 62 69 74 20 74 68 65 20 43 ┆ This is done to prohibit the C┆
0x1fe0…2000 50 43 43 20 74 6f 20 61 6e 73 77 65 72 20 61 6e 20 75 6e 73 70 65 63 69 66 69 65 64 20 41 64 80 ┆PCC to answer an unspecified Ad ┆
0x2000…2020 (16,) 80 80 0a 64 72 65 73 73 20 61 6e 64 20 74 68 75 73 20 76 69 6f 6c 61 74 65 20 63 6f 6d 6d 75 6e ┆ dress and thus violate commun┆
0x2020…2040 69 63 61 74 69 6f 6e 20 6f 6e 20 74 68 65 20 62 75 73 2e 20 0d 0a 0d 0a 0d 0a b0 a1 32 2e 35 2e ┆ication on the bus. 2.5.┆
0x2040…2060 31 20 43 6f 6e 74 72 6f 6c 20 52 65 67 69 73 74 65 72 20 61 0d 0a 0d 0a a1 20 20 6d 73 62 20 20 ┆1 Control Register a msb ┆
0x2060…2080 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 ┆ ┆
0x2080…20a0 20 20 20 20 20 20 20 20 20 20 20 20 20 6c 73 62 20 20 0d 0a a1 e1 21 20 20 20 20 20 20 21 20 20 ┆ lsb ! ! ┆
0x20a0…20c0 20 20 20 20 21 20 20 20 20 20 20 21 20 20 20 20 20 20 21 20 20 20 20 20 20 21 20 20 20 20 20 20 ┆ ! ! ! ! ┆
0x20c0…20e0 21 20 20 20 20 20 20 21 20 20 20 20 20 20 21 0d 0a 21 20 43 43 45 4e 20 21 20 54 58 45 4e 20 21 ┆! ! ! ! CCEN ! TXEN !┆
0x20e0…2100 20 52 58 45 4e 20 21 20 20 20 20 20 20 20 20 20 20 44 65 76 69 63 65 20 41 64 64 72 65 73 73 20 ┆ RXEN ! Device Address ┆
0x2100…2120 20 20 20 20 20 20 20 20 20 21 0d 0a a1 21 20 20 20 20 20 20 21 20 20 20 20 20 20 21 20 20 20 20 ┆ ! ! ! ! ┆
0x2120…2140 20 20 21 20 20 20 20 20 20 21 20 20 20 20 20 20 21 20 20 20 20 20 20 21 20 20 20 20 20 20 21 20 ┆ ! ! ! ! ! ┆
0x2140…2160 20 20 20 20 20 21 0d 0a 0d 0a 54 68 69 73 20 72 65 67 69 73 74 65 72 20 63 6f 6e 74 61 69 6e 73 ┆ ! This register contains┆
0x2160…2180 20 74 68 65 20 72 65 63 6f 67 6e 69 74 69 6f 6e 20 61 64 64 72 65 73 73 20 6f 66 20 77 68 69 63 ┆ the recognition address of whic┆
0x2180…21a0 68 20 74 68 65 20 0a 43 50 43 43 20 69 73 20 74 6f 20 61 6e 73 77 65 72 2e 0d 0a 0d 0a b0 43 43 ┆h the CPCC is to answer. CC┆
0x21a0…21c0 45 4e 20 f0 20 20 84 54 68 65 20 43 6f 6d 6d 75 6e 69 63 61 74 69 6f 6e 20 45 4e 61 62 6c 65 20 ┆EN The Communication ENable ┆
0x21c0…21e0 69 73 20 74 68 65 20 6f 76 65 72 61 6c 6c 20 65 6e 61 62 6c 65 20 6f 66 20 74 68 65 20 0a 19 87 ┆is the overall enable of the ┆
0x21e0…2200 81 80 43 50 43 43 2e 20 57 68 65 6e 20 61 6c 6c 20 6f 74 68 65 72 20 72 65 67 69 73 74 65 72 73 ┆ CPCC. When all other registers┆
0x2200…2220 (17,) 20 68 61 76 65 20 62 65 65 6e 20 69 6e 69 74 69 61 74 65 64 20 0a 19 87 81 80 74 68 69 73 20 62 ┆ have been initiated this b┆
0x2220…2240 69 74 20 6d 75 73 74 20 62 65 20 73 65 74 20 68 69 67 68 20 74 6f 20 65 6e 61 62 6c 65 20 74 68 ┆it must be set high to enable th┆
0x2240…2260 65 20 43 50 43 43 20 72 65 63 65 70 80 80 0a 19 87 81 80 74 69 6f 6e 2f 74 72 61 6e 73 6d 69 73 ┆e CPCC recep tion/transmis┆
0x2260…2280 73 69 6f 6e 20 6f 6e 20 74 68 65 20 62 75 73 2e 20 55 70 6f 6e 20 52 65 73 65 74 20 43 43 45 4e ┆sion on the bus. Upon Reset CCEN┆
0x2280…22a0 20 69 73 20 73 65 74 20 0a 19 87 81 80 74 6f 20 30 20 28 64 69 73 61 62 6c 65 29 2e 0d 0a 0d 0a ┆ is set to 0 (disable). ┆
0x22a0…22c0 b0 52 58 45 4e f0 20 20 20 84 52 65 63 65 69 76 65 20 69 73 20 65 6e 61 62 6c 65 2f 2d 2c 64 69 ┆ RXEN Receive is enable/-,di┆
0x22c0…22e0 73 61 62 6c 65 20 6f 66 20 74 68 65 20 52 78 52 44 59 20 6f 75 74 70 75 74 20 70 69 6e 20 0a 19 ┆sable of the RxRDY output pin ┆
0x22e0…2300 87 81 80 74 6f 20 67 69 76 65 20 74 68 65 20 61 62 69 6c 69 74 79 20 74 6f 20 63 68 6f 73 65 20 ┆ to give the ability to chose ┆
0x2300…2320 65 69 74 68 65 72 20 70 6f 6c 6c 65 64 20 6f 72 20 69 6e 74 65 72 80 0a 19 87 81 80 72 75 70 74 ┆either polled or inter rupt┆
0x2320…2340 20 6d 6f 64 65 2e 0d 0a 0d 0a b0 54 58 45 4e f0 20 20 20 84 54 72 61 6e 73 6d 69 74 20 45 4e 61 ┆ mode. TXEN Transmit ENa┆
0x2340…2360 62 6c 65 20 69 73 20 73 69 6d 69 6c 61 72 20 74 6f 20 52 78 45 4e 20 63 6f 6e 63 65 72 6e 69 6e ┆ble is similar to RxEN concernin┆
0x2360…2380 67 20 54 58 52 44 59 2e 20 0a 19 87 81 80 53 69 6e 63 65 20 74 68 65 20 43 49 52 43 55 49 54 20 ┆g TXRDY. Since the CIRCUIT ┆
0x2380…23a0 49 49 20 70 72 6f 74 6f 63 6f 6c 20 61 6c 6c 77 61 79 73 20 72 65 71 75 69 72 65 73 20 61 6e 20 ┆II protocol allways requires an ┆
0x23a0…23c0 61 6e 80 0a 19 87 81 80 73 77 65 72 20 74 6f 20 61 20 70 6f 6c 6c 2c 20 74 68 65 20 54 58 45 4e ┆an swer to a poll, the TXEN┆
0x23c0…23e0 20 6f 6e 6c 79 20 63 6f 6e 63 65 72 6e 73 20 74 68 65 20 54 58 45 4e 20 6f 75 74 80 0a 19 87 81 ┆ only concerns the TXEN out ┆
0x23e0…2400 80 70 75 74 20 61 6e 64 20 6e 6f 74 20 74 68 65 20 72 65 71 75 69 72 65 64 20 22 6e 6f 20 64 61 ┆ put and not the required "no da┆
0x2400…2420 (18,) 74 61 22 20 61 6e 73 77 65 72 20 70 72 6f 76 69 64 65 64 20 62 79 20 0a 19 87 81 80 74 68 65 20 ┆ta" answer provided by the ┆
0x2420…242e 54 78 2d 70 61 72 74 2e 0d 0a 0d 0a 0d 0a ┆Tx-part. ┆
0x242e…2431 FormFeed {
0x242e…2431 0c 83 cb ┆ ┆
0x242e…2431 }
0x2431…2440 0a b0 a1 32 2e 35 2e 32 20 43 6f 6e 74 72 6f ┆ 2.5.2 Contro┆
0x2440…2460 6c 20 52 65 67 69 73 74 65 72 20 62 0d 0a a1 20 20 6d 73 62 20 20 20 20 20 20 20 20 20 20 20 20 ┆l Register b msb ┆
0x2460…2480 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 ┆ ┆
0x2480…24a0 20 20 6c 73 62 20 20 20 0d 0a a1 e1 21 20 20 20 20 20 20 21 20 20 20 20 20 20 21 20 20 20 20 20 ┆ lsb ! ! ! ┆
0x24a0…24c0 20 21 20 20 20 20 20 20 21 20 20 20 20 20 20 21 20 20 20 20 20 20 21 20 20 20 20 20 20 21 20 20 ┆ ! ! ! ! ! ┆
0x24c0…24e0 20 20 20 20 21 0d 0a 21 20 42 52 45 4e 20 21 20 20 45 52 20 20 21 20 53 54 53 54 20 21 20 20 20 ┆ ! ! BREN ! ER ! STST ! ┆
0x24e0…2500 20 20 20 20 42 72 6f 61 64 63 61 73 74 20 41 64 64 72 65 73 73 20 20 20 20 20 20 20 20 20 20 21 ┆ Broadcast Address !┆
0x2500…2520 0d 0a a1 21 20 20 20 20 20 20 21 20 20 20 20 20 20 21 20 20 20 20 20 20 21 20 20 20 20 20 20 21 ┆ ! ! ! ! !┆
0x2520…2540 20 20 20 20 20 20 21 20 20 20 20 20 20 21 20 20 20 20 20 20 21 20 20 20 20 20 20 21 0d 0a 0d 0a ┆ ! ! ! ! ┆
0x2540…2560 54 68 65 20 62 20 72 65 67 69 73 74 65 72 20 63 6f 6e 74 61 69 6e 73 20 74 68 65 20 72 65 63 6f ┆The b register contains the reco┆
0x2560…2580 67 6e 69 74 69 6f 6e 20 61 64 64 72 65 73 73 20 61 74 20 77 68 69 63 68 20 74 68 65 20 0a 43 50 ┆gnition address at which the CP┆
0x2580…25a0 43 43 20 69 73 20 6e 6f 74 20 74 6f 20 61 6e 73 77 65 72 2e 20 54 68 69 73 20 42 72 6f 61 64 63 ┆CC is not to answer. This Broadc┆
0x25a0…25c0 61 73 74 20 61 64 64 72 65 73 73 20 63 61 6e 20 62 65 20 75 73 65 64 20 62 79 20 0a 74 68 65 20 ┆ast address can be used by the ┆
0x25c0…25e0 6d 61 73 74 65 72 20 6f 66 20 74 68 65 20 62 75 73 20 74 6f 20 74 72 61 6e 73 6d 69 74 20 6d 65 ┆master of the bus to transmit me┆
0x25e0…2600 73 73 61 67 65 73 20 74 6f 20 73 65 76 65 72 61 6c 20 73 6c 61 76 65 73 20 0a 61 74 20 61 20 74 ┆ssages to several slaves at a t┆
0x2600…2620 (19,) 69 6d 65 2e 20 0d 0a 0d 0a b0 42 52 45 4e 20 f0 20 20 84 69 73 20 75 73 65 64 20 74 6f 20 64 65 ┆ime. BREN is used to de┆
0x2620…2640 74 65 72 6d 69 6e 65 20 77 68 65 74 68 65 72 20 74 68 65 20 43 50 43 43 20 69 73 20 74 6f 20 75 ┆termine whether the CPCC is to u┆
0x2640…2660 73 65 20 74 68 69 73 20 0a 19 87 81 80 73 65 63 6f 6e 64 20 61 64 64 72 65 73 73 20 72 65 63 6f ┆se this second address reco┆
0x2660…2680 67 6e 69 74 69 6f 6e 20 6f 72 20 6e 6f 74 2e 20 0d 0a 0d 0a b0 45 52 20 f0 20 20 20 20 84 69 73 ┆gnition or not. ER is┆
0x2680…26a0 20 61 20 72 65 73 65 74 20 62 69 74 20 77 68 69 63 68 20 72 65 73 65 74 73 20 74 68 65 20 63 6f ┆ a reset bit which resets the co┆
0x26a0…26c0 6e 74 65 6e 74 20 6f 66 20 73 74 61 74 75 73 20 72 65 80 0a 19 87 81 80 67 69 73 74 65 72 20 62 ┆ntent of status re gister b┆
0x26c0…26e0 69 74 73 20 46 45 20 4f 45 20 61 6e 64 20 50 45 20 28 65 72 72 6f 72 20 63 6f 64 65 73 29 2e 20 ┆its FE OE and PE (error codes). ┆
0x26e0…2700 57 68 65 6e 20 45 52 20 69 73 20 0a 19 87 81 80 73 65 74 20 74 6f 20 22 31 22 20 74 68 65 20 65 ┆When ER is set to "1" the e┆
0x2700…2720 72 72 6f 72 20 63 6f 64 65 20 62 69 74 73 20 61 72 65 20 72 65 73 65 74 20 61 6e 64 20 74 68 65 ┆rror code bits are reset and the┆
0x2720…2740 20 0a 19 87 81 80 65 72 72 6f 72 20 64 65 74 65 63 74 69 6f 6e 20 63 69 72 63 75 69 74 20 69 73 ┆ error detection circuit is┆
0x2740…2760 20 64 69 73 61 62 6c 65 64 2e 20 57 68 65 6e 20 45 52 20 69 73 20 73 65 74 20 0a 19 87 81 80 74 ┆ disabled. When ER is set t┆
0x2760…2780 6f 20 22 30 22 20 74 68 65 20 65 72 72 6f 72 20 64 65 74 65 63 74 69 6f 6e 20 63 69 72 63 75 69 ┆o "0" the error detection circui┆
0x2780…27a0 74 20 69 73 20 65 6e 61 62 6c 65 64 2e 0d 0a 0d 0a b0 53 54 53 54 20 20 20 f0 84 53 65 6c 66 20 ┆t is enabled. STST Self ┆
0x27a0…27c0 54 65 53 54 20 6d 6f 64 65 20 69 66 20 63 68 6f 6f 73 65 6e 2c 20 6d 75 73 74 20 62 65 20 73 65 ┆TeST mode if choosen, must be se┆
0x27c0…27e0 74 20 75 70 6f 6e 20 52 65 73 65 74 20 74 6f 20 0a 19 87 81 80 73 65 6c 65 63 74 20 74 68 69 73 ┆t upon Reset to select this┆
0x27e0…2800 20 6d 6f 64 65 2e 20 54 68 65 20 6d 6f 64 65 20 72 65 71 75 69 72 65 73 20 6e 6f 20 41 64 64 72 ┆ mode. The mode requires no Addr┆
0x2800…2820 (20,) 65 73 73 20 73 69 6e 63 65 20 0a 19 87 81 80 74 68 65 20 52 65 80 63 65 69 76 65 72 20 72 65 63 ┆ess since the Re ceiver rec┆
0x2820…2840 65 69 76 65 73 20 74 68 65 20 65 63 68 6f 20 6f 66 20 74 68 65 20 74 72 61 6e 73 6d 69 74 74 65 ┆eives the echo of the transmitte┆
0x2840…2860 64 20 64 61 80 0a 19 87 81 80 74 61 20 6f 66 20 74 68 65 20 43 50 43 43 2e 20 54 6f 20 75 73 65 ┆d da ta of the CPCC. To use┆
0x2860…2880 20 74 68 69 73 20 6d 6f 64 65 20 74 68 65 20 43 50 43 43 20 77 69 74 68 20 69 74 73 20 0a 19 87 ┆ this mode the CPCC with its ┆
0x2880…28a0 81 80 70 65 72 69 70 68 65 72 61 6c 20 64 72 69 76 65 72 73 20 6d 75 73 74 20 6e 6f 74 20 62 65 ┆ peripheral drivers must not be┆
0x28a0…28c0 20 61 74 74 61 63 68 65 64 20 74 6f 20 61 6e 79 20 61 63 74 69 76 65 20 0a 19 87 81 80 43 49 52 ┆ attached to any active CIR┆
0x28c0…28e0 43 55 49 54 20 49 49 20 62 75 73 2e 0d 0a 0d 0a 0d 0a b0 a1 32 2e 35 2e 33 20 54 72 61 6e 73 6d ┆CUIT II bus. 2.5.3 Transm┆
0x28e0…2900 69 74 20 72 65 67 69 73 74 65 72 0d 0a a1 20 20 6d 73 62 20 20 20 20 20 20 20 20 20 20 20 20 20 ┆it register msb ┆
0x2900…2920 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 ┆ ┆
0x2920…2940 20 6c 73 62 20 20 20 0d 0a a1 e1 21 20 20 20 20 20 20 21 20 20 20 20 20 20 21 20 20 20 20 20 20 ┆ lsb ! ! ! ┆
0x2940…2960 21 20 20 20 20 20 20 21 20 20 20 20 20 20 21 20 20 20 20 20 20 21 20 20 20 20 20 20 21 20 20 20 ┆! ! ! ! ! ┆
0x2960…2980 20 20 20 21 0d 0a 21 20 54 78 2d 64 61 74 61 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 ┆ ! ! Tx-data ┆
0x2980…29a0 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 21 0d ┆ ! ┆
0x29a0…29c0 0a a1 21 20 20 20 20 20 20 21 20 20 20 20 20 20 21 20 20 20 20 20 20 21 20 20 20 20 20 20 21 20 ┆ ! ! ! ! ! ┆
0x29c0…29e0 20 20 20 20 20 21 20 20 20 20 20 20 21 20 20 20 20 20 20 21 20 20 20 20 20 20 21 0d 0a 0d 0a 54 ┆ ! ! ! ! T┆
0x29e0…2a00 6f 20 74 68 69 73 20 72 65 67 69 73 74 65 72 20 74 68 65 20 43 50 55 20 6d 75 73 74 20 77 72 69 ┆o this register the CPU must wri┆
0x2a00…2a20 (21,) 74 65 20 74 68 65 20 64 61 74 61 20 74 6f 20 62 65 20 74 72 61 6e 73 6d 69 74 80 0a 74 65 64 20 ┆te the data to be transmit ted ┆
0x2a20…2a40 6f 6e 20 43 49 52 43 55 49 54 20 49 49 2e 0d 0a 0d 0a 0d 0a b0 a1 32 2e 35 2e 34 20 52 65 63 65 ┆on CIRCUIT II. 2.5.4 Rece┆
0x2a40…2a60 69 76 65 20 52 65 67 69 73 74 65 72 0d 0a a1 20 20 6d 73 62 20 20 20 20 20 20 20 20 20 20 20 20 ┆ive Register msb ┆
0x2a60…2a80 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 ┆ ┆
0x2a80…2aa0 20 20 6c 73 62 20 20 20 0d 0a a1 e1 21 20 20 20 20 20 20 21 20 20 20 20 20 20 21 20 20 20 20 20 ┆ lsb ! ! ! ┆
0x2aa0…2ac0 20 21 20 20 20 20 20 20 21 20 20 20 20 20 20 21 20 20 20 20 20 20 21 20 20 20 20 20 20 21 20 20 ┆ ! ! ! ! ! ┆
0x2ac0…2ae0 20 20 20 20 21 20 0d 0a 21 20 52 78 2d 44 61 74 61 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 ┆ ! ! Rx-Data ┆
0x2ae0…2b00 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 ┆ ┆
0x2b00…2b20 21 0d 0a a1 21 20 20 20 20 20 20 21 20 20 20 20 20 20 21 20 20 20 20 20 20 21 20 20 20 20 20 20 ┆! ! ! ! ! ┆
0x2b20…2b40 21 20 20 20 20 20 20 21 20 20 20 20 20 20 21 20 20 20 20 20 20 21 20 20 20 20 20 20 21 0d 0a 0d ┆! ! ! ! ! ┆
0x2b40…2b60 0a 46 72 6f 6d 20 74 68 69 73 20 72 65 67 69 73 74 65 72 20 74 68 65 20 43 50 55 20 63 61 6e 20 ┆ From this register the CPU can ┆
0x2b60…2b80 72 65 61 64 20 74 68 65 20 64 61 74 61 20 72 65 63 65 69 76 65 64 20 66 72 6f 6d 20 0a 43 49 52 ┆read the data received from CIR┆
0x2b80…2b8e 43 55 49 54 20 49 49 2e 0d 0a 0d 0a 0d 0a ┆CUIT II. ┆
0x2b8e…2b91 FormFeed {
0x2b8e…2b91 0c 83 b0 ┆ ┆
0x2b8e…2b91 }
0x2b91…2ba0 0a b0 a1 32 2e 35 2e 35 20 53 74 61 74 75 73 ┆ 2.5.5 Status┆
0x2ba0…2bc0 20 52 65 67 69 73 74 65 72 0d 0a 0d 0a a1 20 20 6d 73 62 20 20 20 20 20 20 20 20 20 20 20 20 20 ┆ Register msb ┆
0x2bc0…2be0 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 ┆ ┆
0x2be0…2c00 20 6c 73 62 20 20 20 0d 0a a1 e1 21 20 20 20 20 20 20 21 20 20 20 20 20 20 21 20 20 20 20 20 20 ┆ lsb ! ! ! ┆
0x2c00…2c20 (22,) 21 20 20 20 20 20 20 21 20 20 20 20 20 20 21 20 20 20 20 20 20 21 20 20 20 20 20 20 21 20 20 20 ┆! ! ! ! ! ┆
0x2c20…2c40 20 20 20 21 20 0d 0a 21 20 20 58 82 31 81 20 20 21 20 20 58 82 30 81 20 20 21 20 20 46 45 20 20 ┆ ! ! X 1 ! X 0 ! FE ┆
0x2c40…2c60 21 20 20 4f 45 20 20 21 20 20 50 45 20 20 21 20 20 42 52 43 20 21 52 78 52 44 59 20 21 54 78 52 ┆! OE ! PE ! BRC !RxRDY !TxR┆
0x2c60…2c80 44 59 20 21 0d 0a a1 21 20 20 20 20 20 20 21 20 20 20 20 20 20 21 20 20 20 20 20 20 21 20 20 20 ┆DY ! ! ! ! ! ┆
0x2c80…2ca0 20 20 20 21 20 20 20 20 20 20 21 20 20 20 20 20 20 21 20 20 20 20 20 20 21 20 20 20 20 20 20 21 ┆ ! ! ! ! !┆
0x2ca0…2cc0 0d 0a 0d 0a e1 e1 b0 52 78 52 44 59 e1 20 f0 20 84 54 68 69 73 20 62 69 74 20 69 6e 64 69 63 61 ┆ RxRDY This bit indica┆
0x2cc0…2ce0 74 65 73 20 74 68 61 74 20 74 68 65 20 43 50 43 43 20 63 6f 6e 74 61 69 6e 73 20 61 20 63 68 61 ┆tes that the CPCC contains a cha┆
0x2ce0…2d00 72 61 63 74 65 72 20 0a 19 87 81 80 74 68 61 74 20 69 73 20 72 65 61 64 79 20 74 6f 20 62 65 20 ┆racter that is ready to be ┆
0x2d00…2d20 69 6e 70 75 74 20 74 6f 20 74 68 65 20 43 50 55 2e 0d 0a 0d 0a a1 e1 b0 54 78 52 44 59 e1 f0 20 ┆input to the CPU. TxRDY ┆
0x2d20…2d40 20 84 54 68 69 73 20 62 69 74 20 69 6e 64 69 63 61 74 65 73 20 74 68 61 74 20 74 68 65 20 43 50 ┆ This bit indicates that the CP┆
0x2d40…2d60 43 43 20 69 73 20 72 65 61 64 79 20 74 6f 20 61 63 63 65 70 74 20 61 20 0a 19 87 81 80 64 61 74 ┆CC is ready to accept a dat┆
0x2d60…2d80 61 20 63 68 61 72 61 63 74 65 72 20 66 72 6f 6d 20 74 68 65 20 43 50 55 2e 0d 0a 0d 0a 20 20 20 ┆a character from the CPU. ┆
0x2d80…2da0 20 20 20 20 84 4e 6f 74 65 20 74 68 61 74 20 77 68 65 6e 20 75 73 69 6e 67 20 74 68 65 20 50 6f ┆ Note that when using the Po┆
0x2da0…2dc0 6c 6c 65 64 20 6f 70 65 72 61 74 69 6f 6e 2c 20 74 68 65 20 54 78 52 44 59 20 0a 19 87 80 80 73 ┆lled operation, the TxRDY s┆
0x2dc0…2de0 74 61 74 75 73 20 62 69 74 20 69 73 20 6e 6f 74 20 6d 61 73 6b 65 64 20 62 79 20 54 78 20 45 6e ┆tatus bit is not masked by Tx En┆
0x2de0…2e00 61 62 6c 65 64 2c 20 62 75 74 20 77 69 6c 6c 20 6f 6e 6c 79 20 0a 19 87 80 80 69 6e 64 69 63 61 ┆abled, but will only indica┆
0x2e00…2e20 (23,) 74 65 20 74 68 65 20 45 6d 70 74 79 2f 46 75 6c 6c 20 53 74 61 74 75 73 20 6f 66 20 74 68 65 20 ┆te the Empty/Full Status of the ┆
0x2e20…2e40 54 78 20 44 61 74 61 20 69 6e 70 75 74 20 0a 19 87 80 80 52 65 67 69 73 74 65 72 2e 0d 0a 0d 0a ┆Tx Data input Register. ┆
0x2e40…2e60 a1 e1 b0 42 52 43 e1 20 f0 20 20 20 84 49 66 20 42 52 6f 61 64 43 61 73 74 20 62 69 74 20 69 73 ┆ BRC If BRoadCast bit is┆
0x2e60…2e80 20 68 69 67 68 20 69 74 20 69 6e 64 69 63 61 74 65 73 20 74 68 61 74 20 74 68 65 20 62 72 6f 61 ┆ high it indicates that the broa┆
0x2e80…2ea0 64 80 0a 19 87 81 80 63 61 73 74 20 6f 70 74 69 6f 6e 20 68 61 73 20 62 65 65 6e 20 63 68 6f 73 ┆d cast option has been chos┆
0x2ea0…2ec0 65 6e 20 61 6e 64 20 74 68 61 74 20 74 68 65 20 63 68 61 72 61 63 74 65 72 20 69 6e 20 0a 19 87 ┆en and that the character in ┆
0x2ec0…2ee0 81 80 74 68 65 20 52 65 63 65 69 76 65 20 72 65 67 69 73 74 65 72 20 69 73 20 72 65 63 65 69 76 ┆ the Receive register is receiv┆
0x2ee0…2f00 65 64 20 76 69 61 20 74 68 65 20 62 72 6f 61 64 63 61 73 74 20 0a 19 87 81 80 61 64 80 64 72 65 ┆ed via the broadcast ad dre┆
0x2f00…2f20 73 73 2e 20 54 68 65 20 42 52 43 20 62 69 74 20 69 73 20 69 64 65 6e 74 69 63 61 6c 20 74 6f 20 ┆ss. The BRC bit is identical to ┆
0x2f20…2f40 74 68 65 20 42 52 43 20 6f 75 74 70 75 74 20 0a 19 87 81 80 70 69 6e 2e 0d 0a 0d 0a b0 e1 50 45 ┆the BRC output pin. PE┆
0x2f40…2f60 e1 20 20 20 20 20 b0 f0 84 54 68 65 20 50 61 72 69 74 79 20 45 72 72 6f 72 20 66 6c 61 67 20 69 ┆ The Parity Error flag i┆
0x2f60…2f80 73 20 73 65 74 20 77 68 65 6e 20 61 20 70 61 72 69 74 79 20 65 72 72 6f 72 20 69 73 20 0a 19 87 ┆s set when a parity error is ┆
0x2f80…2fa0 82 80 64 65 74 65 63 74 65 64 2e 20 49 74 20 69 73 20 72 65 73 65 74 20 62 79 20 74 68 65 20 45 ┆ detected. It is reset by the E┆
0x2fa0…2fc0 52 20 62 69 74 20 6f 66 20 74 68 65 20 43 6f 6d 6d 61 6e 64 20 0a 19 87 82 80 49 6e 73 74 72 75 ┆R bit of the Command Instru┆
0x2fc0…2fe0 63 74 69 6f 6e 2e 20 50 45 20 64 6f 65 73 20 6e 6f 74 20 69 6e 68 69 62 69 74 20 6f 70 65 72 61 ┆ction. PE does not inhibit opera┆
0x2fe0…3000 74 69 6f 6e 20 6f 66 20 74 68 65 20 0a 19 87 82 80 43 50 43 43 20 62 75 74 20 74 68 65 20 66 72 ┆tion of the CPCC but the fr┆
0x3000…3020 (24,) 61 6d 65 20 63 6f 6e 74 61 69 6e 69 6e 67 20 74 68 65 20 50 61 72 69 74 79 20 65 72 72 6f 72 20 ┆ame containing the Parity error ┆
0x3020…3040 69 73 20 0a 19 87 82 80 6c 6f 73 74 2e 0d 0a 0d 0a a1 e1 b0 4f 45 e1 20 f0 20 20 20 20 84 54 68 ┆is lost. OE Th┆
0x3040…3060 65 20 4f 76 65 72 72 75 6e 20 45 72 72 6f 72 20 66 6c 61 67 20 69 73 20 73 65 74 20 77 68 65 6e ┆e Overrun Error flag is set when┆
0x3060…3080 20 74 68 65 20 43 50 55 20 64 6f 65 73 20 6e 6f 74 20 0a 19 87 81 80 72 65 61 64 20 61 20 63 68 ┆ the CPU does not read a ch┆
0x3080…30a0 61 72 80 61 63 74 65 72 20 62 65 66 6f 72 65 20 74 68 65 20 6e 65 78 74 20 6f 6e 65 20 62 65 63 ┆ar acter before the next one bec┆
0x30a0…30c0 6f 6d 65 73 20 61 76 61 69 6c 80 80 0a 19 87 81 80 61 62 6c 65 2e 20 49 74 20 69 73 20 72 65 80 ┆omes avail able. It is re ┆
0x30c0…30e0 73 65 74 20 62 79 20 74 68 65 20 45 52 20 62 69 74 20 6f 66 20 74 68 65 20 43 6f 6d 6d 61 6e 64 ┆set by the ER bit of the Command┆
0x30e0…3100 20 49 6e 80 80 0a 19 87 81 80 73 74 72 75 63 74 69 6f 6e 2e 20 4f 45 20 64 6f 65 73 20 6e 6f 74 ┆ In struction. OE does not┆
0x3100…3120 20 69 6e 68 69 62 69 74 20 6f 70 65 72 61 74 69 6f 6e 20 6f 66 20 74 68 65 20 43 50 43 43 20 0a ┆ inhibit operation of the CPCC ┆
0x3120…3140 19 87 81 80 68 6f 77 65 76 65 72 2c 20 74 68 65 20 70 72 65 80 76 69 6f 75 73 6c 79 20 6f 76 65 ┆ however, the pre viously ove┆
0x3140…3160 72 72 75 6e 20 63 68 61 72 61 63 74 65 72 20 69 73 20 6c 6f 73 74 2e 0d 0a 0d 0a b0 46 45 f0 20 ┆rrun character is lost. FE ┆
0x3160…3180 20 20 20 20 84 54 68 65 20 46 72 61 6d 69 6e 67 20 45 72 72 6f 72 20 66 6c 61 67 20 69 73 20 73 ┆ The Framing Error flag is s┆
0x3180…31a0 65 74 20 77 68 65 6e 20 61 20 76 61 6c 69 64 20 53 74 6f 70 20 6f 72 20 0a 19 87 81 80 73 74 61 ┆et when a valid Stop or sta┆
0x31a0…31c0 72 74 20 62 69 74 20 69 73 20 6e 6f 74 20 64 65 74 65 63 80 74 65 64 20 61 74 20 74 68 65 20 65 ┆rt bit is not detec ted at the e┆
0x31c0…31e0 6e 64 20 6f 66 20 65 76 65 72 79 20 63 68 61 72 61 63 80 0a 19 87 81 80 74 65 72 2e 20 49 74 20 ┆nd of every charac ter. It ┆
0x31e0…3200 69 73 20 72 65 73 65 74 20 62 79 20 74 68 65 20 45 52 20 62 69 74 20 6f 66 20 74 68 65 20 43 6f ┆is reset by the ER bit of the Co┆
0x3200…3220 (25,) 6d 6d 61 6e 64 20 49 6e 73 74 80 0a 19 87 81 80 72 75 63 74 69 6f 6e 2e 20 46 45 20 64 6f 65 73 ┆mmand Inst ruction. FE does┆
0x3220…3240 20 6e 6f 74 20 69 6e 68 69 62 69 74 20 74 68 65 20 6f 70 65 72 61 74 69 6f 6e 20 6f 66 20 74 68 ┆ not inhibit the operation of th┆
0x3240…3260 65 20 0a 19 87 81 80 43 50 43 43 2c 20 62 75 74 20 74 68 65 20 66 72 61 6d 65 20 63 6f 6e 74 61 ┆e CPCC, but the frame conta┆
0x3260…3280 69 6e 69 6e 67 20 74 68 65 20 66 72 61 6d 69 6e 67 20 65 72 72 6f 72 20 69 73 20 0a 19 87 81 80 ┆ining the framing error is ┆
0x3280…32a0 6c 6f 73 74 2e 20 4e 6f 74 65 20 74 68 61 74 20 69 66 20 46 45 20 66 6c 61 67 20 69 73 20 73 65 ┆lost. Note that if FE flag is se┆
0x32a0…32c0 74 20 50 45 20 66 6c 61 67 20 6d 61 79 20 61 6c 73 6f 20 62 65 20 0a 19 87 81 80 73 65 74 20 73 ┆t PE flag may also be set s┆
0x32c0…32e0 69 6e 63 65 20 74 68 65 20 70 61 72 69 74 79 20 63 68 65 63 6b 65 72 20 61 6c 73 6f 20 63 68 65 ┆ince the parity checker also che┆
0x32e0…3300 63 6b 73 20 73 74 61 72 74 20 61 6e 64 20 0a 19 87 81 80 73 74 6f 70 20 62 69 74 73 20 69 6e 20 ┆cks start and stop bits in ┆
0x3300…3320 74 68 65 20 6d 69 64 64 6c 65 20 6f 66 20 61 20 66 72 61 6d 65 20 63 6f 6e 74 61 69 6e 69 6e 67 ┆the middle of a frame containing┆
0x3320…3340 20 64 61 74 61 2e 0d 0a 0d 0a b0 58 20 2c 58 20 20 20 f0 54 68 65 73 65 20 62 69 74 20 63 6f 6e ┆ data. X ,X These bit con┆
0x3340…3360 74 61 69 6e 73 20 74 68 65 20 76 61 6c 75 65 73 20 6f 66 20 74 68 65 20 64 6f 6e 27 74 20 63 61 ┆tains the values of the don't ca┆
0x3360…3380 72 65 20 62 69 74 73 20 0d 0a 81 b0 20 30 20 20 31 20 f0 20 82 69 6e 20 74 68 65 20 41 64 64 72 ┆re bits 0 1 in the Addr┆
0x3380…33a0 65 73 73 20 48 65 61 64 65 72 20 6f 66 20 74 68 65 20 70 72 6f 74 6f 63 6f 6c 2c 20 61 6e 64 20 ┆ess Header of the protocol, and ┆
0x33a0…33c0 63 68 61 6e 67 65 73 20 0d 0a 20 20 20 20 20 20 20 84 76 61 6c 75 65 20 6a 75 73 74 20 70 72 69 ┆changes value just pri┆
0x33c0…33e0 6f 72 20 74 6f 20 52 78 52 44 59 20 64 65 70 65 6e 64 65 6e 74 20 6f 66 20 74 68 65 20 72 65 63 ┆or to RxRDY dependent of the rec┆
0x33e0…3400 65 69 76 65 64 20 0a 19 87 80 80 66 72 61 6d 65 2e 20 54 68 65 73 65 20 62 69 74 73 20 69 73 20 ┆eived frame. These bits is ┆
0x3400…341f (26,) 69 64 65 6e 74 69 63 61 6c 20 74 6f 20 74 68 65 20 6f 75 74 70 75 74 20 70 69 6e 73 2e 0d 0a ┆identical to the output pins. ┆
0x341f…3422 FormFeed {
0x341f…3422 0c 83 b9 ┆ ┆
0x341f…3422 }
0x3422…3440 0a b0 a1 b0 a1 b0 a1 33 2e 20 53 4c 41 56 45 20 4d 4f 44 45 20 43 4f 4e 46 49 47 55 52 41 ┆ 3. SLAVE MODE CONFIGURA┆
0x3440…3460 54 49 4f 4e 0d 0a 0d 0a 57 68 65 6e 20 74 68 65 20 53 6c 61 76 65 20 4d 6f 64 65 20 68 61 73 20 ┆TION When the Slave Mode has ┆
0x3460…3480 62 65 65 6e 20 53 65 6c 65 63 74 65 64 20 28 4d 2f 2d 2c 53 20 70 69 6e 20 69 73 20 6c 6f 77 29 ┆been Selected (M/-,S pin is low)┆
0x3480…34a0 20 74 68 65 20 0a 43 50 43 43 20 74 79 70 69 63 61 6c 6c 79 20 72 75 6e 73 20 69 6e 20 61 20 73 ┆ the CPCC typically runs in a s┆
0x34a0…34c0 79 73 74 65 6d 20 77 69 74 68 20 6d 61 6e 79 20 70 65 72 69 70 68 65 72 61 6c 73 20 74 6f 20 62 ┆ystem with many peripherals to b┆
0x34c0…34e0 65 20 0a 73 65 72 76 69 63 65 64 20 62 79 20 74 68 65 20 73 61 6d 65 20 43 50 55 2e 20 54 68 65 ┆e serviced by the same CPU. The┆
0x34e0…3500 72 65 66 6f 72 65 20 74 68 65 20 52 78 52 44 59 20 61 6e 64 20 54 78 52 44 59 20 70 69 6e 73 20 ┆refore the RxRDY and TxRDY pins ┆
0x3500…3520 0a 68 61 73 20 62 65 65 6e 20 69 6d 70 6c 65 6d 65 6e 74 65 64 20 74 6f 20 67 69 76 65 20 74 68 ┆ has been implemented to give th┆
0x3520…3540 65 20 61 62 69 6c 69 74 79 20 6f 66 20 6d 61 6b 69 6e 67 20 61 20 63 6c 65 61 6e 20 0a 69 6e 74 ┆e ability of making a clean int┆
0x3540…3560 65 72 72 75 70 74 20 69 6e 74 65 72 66 61 63 65 2e 0d 0a 0d 0a 0d 0a b0 a1 33 2e 31 20 49 6e 69 ┆errupt interface. 3.1 Ini┆
0x3560…3580 74 69 61 6c 69 7a 69 6e 67 0d 0a 0d 0a 50 72 69 6f 72 20 74 6f 20 6f 70 65 72 61 74 69 6f 6e 20 ┆tializing Prior to operation ┆
0x3580…35a0 74 68 65 20 43 6f 6e 74 72 6f 6c 20 72 65 67 69 73 74 65 72 73 20 6d 75 73 74 20 62 65 20 69 6e ┆the Control registers must be in┆
0x35a0…35c0 69 74 69 61 6c 69 80 0a 7a 65 64 2e 20 54 68 65 20 53 54 53 54 20 62 69 74 20 6f 66 20 43 6f 6e ┆itiali zed. The STST bit of Con┆
0x35c0…35e0 74 72 6f 6c 20 72 65 67 69 73 74 65 72 20 42 20 6d 75 73 74 20 62 65 20 6c 6f 77 20 61 6e 64 20 ┆trol register B must be low and ┆
0x35e0…3600 74 68 65 20 0a 42 52 45 4e 20 6d 75 73 74 20 62 65 20 6c 6f 77 20 75 6e 6c 65 73 73 20 42 72 6f ┆the BREN must be low unless Bro┆
0x3600…3620 (27,) 61 64 63 61 73 74 20 6f 70 74 69 6f 6e 20 69 73 20 63 68 6f 73 65 6e 20 28 65 78 70 6c 61 69 80 ┆adcast option is chosen (explai ┆
0x3620…3640 0a 6e 65 64 20 62 65 6c 6f 77 29 2e 20 49 66 20 74 68 65 20 43 6f 6e 74 72 6f 6c 20 72 65 67 69 ┆ ned below). If the Control regi┆
0x3640…3660 73 74 65 72 20 41 20 69 73 20 6c 6f 61 64 65 64 20 61 66 74 65 72 20 74 68 65 20 42 20 0a 72 65 ┆ster A is loaded after the B re┆
0x3660…3680 67 69 73 74 65 72 2c 20 74 68 65 20 43 43 45 4e 20 6d 61 79 20 62 65 20 6d 61 64 65 20 68 69 67 ┆gister, the CCEN may be made hig┆
0x3680…36a0 68 20 74 6f 67 65 74 68 65 72 20 77 69 74 68 20 74 68 65 20 77 72 69 80 0a 74 69 6e 67 20 6f 66 ┆h together with the wri ting of┆
0x36a0…36c0 20 74 68 65 20 64 65 76 69 63 65 20 61 64 64 72 65 73 73 2c 20 52 78 45 4e 20 61 6e 64 20 54 78 ┆ the device address, RxEN and Tx┆
0x36c0…36e0 45 4e 2c 20 74 68 65 20 72 65 63 65 70 74 69 6f 6e 20 0a 77 69 6c 6c 20 62 65 20 69 6e 69 74 69 ┆EN, the reception will be initi┆
0x36e0…3700 61 74 65 64 20 75 70 6f 6e 20 43 43 45 4e 20 68 69 67 68 2e 0d 0a 0d 0a 0d 0a b0 a1 33 2e 32 20 ┆ated upon CCEN high. 3.2 ┆
0x3700…3720 52 75 6e 6e 69 6e 67 0d 0a 0d 0a 57 68 65 6e 20 74 68 65 20 43 50 43 43 20 69 73 20 69 6e 69 74 ┆Running When the CPCC is init┆
0x3720…3740 69 61 74 65 64 20 61 6e 64 20 43 43 45 4e 20 69 73 20 68 69 67 68 20 74 68 65 20 52 65 63 65 70 ┆iated and CCEN is high the Recep┆
0x3740…3760 74 69 6f 6e 20 69 73 20 0a 65 6e 61 62 6c 65 64 20 61 6e 64 20 75 70 6f 6e 20 72 65 63 65 70 74 ┆tion is enabled and upon recept┆
0x3760…3780 69 6f 6e 20 6f 66 20 61 20 66 72 61 6d 65 20 66 6f 72 20 74 68 65 20 64 65 76 69 63 65 2c 20 74 ┆ion of a frame for the device, t┆
0x3780…37a0 68 65 20 0a 74 72 61 6e 73 6d 69 73 73 69 6f 6e 20 69 73 20 69 6e 69 74 69 61 74 65 64 20 65 69 ┆he transmission is initiated ei┆
0x37a0…37c0 74 68 65 72 20 77 69 74 68 20 74 68 65 20 70 72 65 76 69 6f 75 73 6c 79 20 6c 6f 61 64 65 64 20 ┆ther with the previously loaded ┆
0x37c0…37e0 0a 64 61 74 61 20 62 79 74 65 20 6f 72 20 77 69 74 68 20 74 68 65 20 22 6e 6f 20 64 61 74 61 22 ┆ data byte or with the "no data"┆
0x37e0…3800 20 61 6e 73 77 65 72 2e 20 55 70 6f 6e 20 72 65 63 65 70 74 69 6f 6e 20 6f 66 20 61 20 0a 76 61 ┆ answer. Upon reception of a va┆
0x3800…3820 (28,) 6c 69 64 20 66 72 61 6d 65 20 77 69 74 68 20 61 20 64 61 74 61 20 62 79 74 65 20 74 68 65 20 52 ┆lid frame with a data byte the R┆
0x3820…3840 78 52 44 59 20 69 73 20 61 73 73 65 72 74 65 64 20 61 6e 64 20 75 70 6f 6e 20 0a 6c 6f 61 64 20 ┆xRDY is asserted and upon load ┆
0x3840…3860 6f 66 20 61 20 62 79 74 65 20 74 6f 20 62 65 20 74 72 61 6e 73 6d 69 74 74 65 64 20 54 78 52 44 ┆of a byte to be transmitted TxRD┆
0x3860…3880 59 20 69 73 20 61 73 73 65 72 74 65 64 2e 20 42 6f 74 68 20 0a 52 78 52 44 59 20 61 6e 64 20 54 ┆Y is asserted. Both RxRDY and T┆
0x3880…38a0 78 52 44 59 20 61 72 65 20 63 6c 65 61 72 65 64 20 62 79 20 74 68 65 20 6c 65 61 64 69 6e 67 20 ┆xRDY are cleared by the leading ┆
0x38a0…38c0 65 64 67 65 20 6f 66 20 72 65 61 64 20 66 72 6f 6d 20 0a 74 68 65 20 52 78 2d 72 65 67 69 73 74 ┆edge of read from the Rx-regist┆
0x38c0…38e0 65 72 20 61 6e 64 20 77 72 69 74 65 20 74 6f 20 74 68 65 20 54 78 2d 72 65 67 69 73 74 65 72 20 ┆er and write to the Tx-register ┆
0x38e0…3900 72 65 73 70 65 63 74 69 76 65 6c 79 2e 0d 0a 0d 0a 0d 0a b0 a1 33 2e 33 20 42 72 6f 61 64 63 61 ┆respectively. 3.3 Broadca┆
0x3900…3920 73 74 20 4f 70 74 69 6f 6e 73 0d 0a 0d 0a 49 66 20 42 52 45 4e 20 69 73 20 73 65 74 20 74 6f 20 ┆st Options If BREN is set to ┆
0x3920…3940 68 69 67 68 20 6c 65 76 65 6c 20 64 75 72 69 6e 67 20 49 6e 69 74 69 61 6c 69 7a 61 74 69 6f 6e ┆high level during Initialization┆
0x3940…3960 20 74 68 65 20 0a 42 72 6f 61 64 63 61 73 74 20 52 65 63 6f 67 6e 69 74 69 6f 6e 20 41 64 64 72 ┆ the Broadcast Recognition Addr┆
0x3960…3980 65 73 73 20 74 6f 6f 20 68 61 73 20 74 6f 20 62 65 20 6c 6f 61 64 65 64 20 74 6f 20 74 68 65 20 ┆ess too has to be loaded to the ┆
0x3980…39a0 0a 43 6f 6e 74 72 6f 6c 20 72 65 67 69 73 74 65 72 20 42 2e 20 49 66 20 74 68 69 73 20 42 72 6f ┆ Control register B. If this Bro┆
0x39a0…39c0 61 64 63 61 73 74 20 61 64 64 72 65 73 73 20 69 73 20 72 65 63 6f 67 6e 69 7a 65 64 20 0a 61 6e ┆adcast address is recognized an┆
0x39c0…39e0 64 20 66 6f 6c 6c 6f 77 65 64 20 62 79 20 61 20 64 61 74 61 20 62 79 74 65 20 64 75 72 69 6e 67 ┆d followed by a data byte during┆
0x39e0…3a00 20 74 68 65 20 63 6f 6d 6d 75 6e 69 63 61 74 69 6f 6e 20 6f 6e 20 74 68 65 20 0a 6c 69 6e 65 2c ┆ the communication on the line,┆
0x3a00…3a20 (29,) 20 52 78 52 44 59 20 69 73 20 61 73 73 65 72 74 65 64 20 74 6f 67 65 74 68 65 72 20 77 69 74 68 ┆ RxRDY is asserted together with┆
0x3a20…3a40 20 42 52 43 20 74 6f 20 69 6e 64 69 63 61 74 65 20 74 68 61 74 20 0a 74 68 65 20 64 61 74 61 20 ┆ BRC to indicate that the data ┆
0x3a40…3a60 62 79 74 65 20 68 61 73 20 62 65 65 6e 20 72 65 63 65 69 76 65 64 20 76 69 61 20 74 68 65 20 42 ┆byte has been received via the B┆
0x3a60…3a80 72 6f 61 64 63 61 73 74 20 41 64 64 72 65 73 73 2e 20 0a 4e 6f 20 54 72 61 6e 73 6d 69 73 73 69 ┆roadcast Address. No Transmissi┆
0x3a80…3aa0 6f 6e 20 61 72 65 20 69 6e 69 74 69 61 74 65 64 20 75 70 6f 6e 20 72 65 63 65 70 74 69 6f 6e 20 ┆on are initiated upon reception ┆
0x3aa0…3abc 6f 66 20 61 20 62 72 6f 61 64 63 61 73 74 20 0a 66 72 61 6d 65 2e 0d 0a 0d 0a 0d 0a ┆of a broadcast frame. ┆
0x3abc…3abf FormFeed {
0x3abc…3abf 0c 83 8c ┆ ┆
0x3abc…3abf }
0x3abf…3ac0 0a ┆ ┆
0x3ac0…3ae0 b0 a1 34 2e 20 53 45 4c 46 54 45 53 54 20 4d 4f 44 45 20 43 4f 4e 46 49 47 55 52 41 54 49 4f 4e ┆ 4. SELFTEST MODE CONFIGURATION┆
0x3ae0…3b00 0d 0a 0d 0a 54 68 69 73 20 4d 6f 64 65 20 68 61 76 65 20 62 65 65 6e 20 69 6d 70 6c 65 6d 65 6e ┆ This Mode have been implemen┆
0x3b00…3b20 74 65 64 20 74 6f 20 67 61 69 6e 20 74 68 65 20 61 62 69 6c 69 74 79 20 74 6f 20 68 61 76 65 20 ┆ted to gain the ability to have ┆
0x3b20…3b40 0a 74 68 65 20 43 50 43 43 20 61 6e 64 20 73 75 72 72 6f 75 6e 64 65 64 20 63 69 72 63 75 69 74 ┆ the CPCC and surrounded circuit┆
0x3b40…3b60 72 79 20 74 6f 20 74 65 73 74 20 69 74 20 73 65 6c 66 2e 20 54 6f 20 64 6f 20 0a 74 68 69 73 20 ┆ry to test it self. To do this ┆
0x3b60…3b80 74 68 65 20 43 50 43 43 20 6d 75 73 74 20 6e 6f 74 20 62 65 20 61 74 74 61 63 68 65 64 20 74 6f ┆the CPCC must not be attached to┆
0x3b80…3ba0 20 61 6e 79 20 61 63 74 69 76 65 20 43 69 72 63 75 69 74 20 49 49 20 0a 6c 69 6e 65 20 73 69 6e ┆ any active Circuit II line sin┆
0x3ba0…3bc0 63 65 20 74 68 65 20 66 6f 72 6d 61 74 20 6f 66 20 74 68 65 20 73 65 6c 66 74 65 73 74 20 66 72 ┆ce the format of the selftest fr┆
0x3bc0…3be0 61 6d 65 73 20 74 72 61 6e 73 6d 69 74 74 65 64 20 62 79 20 0a 74 68 65 20 64 65 76 69 63 65 20 ┆ames transmitted by the device ┆
0x3be0…3c00 75 6e 64 65 72 20 74 65 73 74 20 74 6f 20 74 68 65 20 6c 69 6e 65 20 77 6f 75 6c 64 20 76 69 6f ┆under test to the line would vio┆
0x3c00…3c20 (30,) 6c 61 74 65 20 61 6c 6c 20 6f 74 68 65 72 20 0a 63 6f 6d 6d 75 6e 69 63 61 74 69 6f 6e 20 6f 6e ┆late all other communication on┆
0x3c20…3c40 20 74 68 65 20 6c 69 6e 65 2e 20 54 68 65 20 73 65 6c 66 74 65 73 74 20 66 75 6e 63 74 69 6f 6e ┆ the line. The selftest function┆
0x3c40…3c60 20 69 73 20 6d 65 72 65 6c 79 20 0a 61 6e 20 65 63 68 6f 69 6e 67 20 6f 66 20 74 72 61 6e 73 6d ┆ is merely an echoing of transm┆
0x3c60…3c80 69 74 74 65 64 20 64 61 74 61 20 76 69 61 20 74 68 65 20 6c 69 6e 65 20 74 72 61 6e 73 66 6f 72 ┆itted data via the line transfor┆
0x3c80…3ca0 6d 65 72 20 74 6f 20 0a 74 68 65 20 52 65 63 65 69 76 65 20 62 75 66 66 65 72 20 6f 66 20 74 68 ┆mer to the Receive buffer of th┆
0x3ca0…3cc0 65 20 43 50 43 43 2e 20 41 6c 6c 20 73 74 61 74 75 73 20 69 6e 66 6f 72 6d 61 74 69 6f 6e 69 73 ┆e CPCC. All status informationis┆
0x3cc0…3ce0 20 61 63 80 0a 74 69 76 65 20 64 75 72 69 6e 67 20 74 68 69 73 20 6d 6f 64 65 20 61 73 20 77 65 ┆ ac tive during this mode as we┆
0x3ce0…3d00 6c 6c 20 61 73 20 74 68 65 20 69 6e 74 65 72 72 75 70 74 20 67 65 6e 65 72 61 74 69 6f 6e 2e 0d ┆ll as the interrupt generation. ┆
0x3d00…3d20 0a 0d 0a 0d 0a b0 a1 34 2e 31 20 49 6e 69 74 69 61 6c 69 7a 69 6e 67 0d 0a 0d 0a 53 69 6e 63 65 ┆ 4.1 Initializing Since┆
0x3d20…3d40 20 6e 6f 20 41 64 64 72 65 73 73 20 68 65 61 64 65 72 20 69 73 20 6e 65 63 65 73 73 61 72 79 2c ┆ no Address header is necessary,┆
0x3d40…3d60 20 43 6f 6e 74 72 6f 6c 20 72 65 67 69 73 74 65 72 20 41 20 61 6e 64 20 0a 42 20 61 72 65 20 6f ┆ Control register A and B are o┆
0x3d60…3d80 6e 6c 79 20 74 6f 20 62 65 20 69 6e 69 74 69 61 6c 69 7a 65 64 20 69 6e 20 74 68 65 20 6d 61 74 ┆nly to be initialized in the mat┆
0x3d80…3da0 74 65 72 20 6f 66 20 52 78 45 4e 2c 20 54 78 45 4e 2c 20 0a 53 54 53 54 20 28 53 54 53 54 3d 22 ┆ter of RxEN, TxEN, STST (STST="┆
0x3da0…3dc0 31 22 29 20 61 6e 64 20 43 43 45 4e 2e 20 4d 2f 2d 2c 53 20 6d 75 73 74 20 62 65 20 68 65 6c 64 ┆1") and CCEN. M/-,S must be held┆
0x3dc0…3de0 20 6c 6f 77 2e 0d 0a 0d 0a 0d 0a b0 a1 34 2e 32 20 52 75 6e 6e 69 6e 67 0d 0a 0d 0a 54 6f 20 69 ┆ low. 4.2 Running To i┆
0x3de0…3e00 6e 69 74 69 61 74 65 20 43 6f 6d 6d 75 6e 69 63 61 74 69 6f 6e 20 64 61 74 61 20 6d 75 73 74 20 ┆nitiate Communication data must ┆
0x3e00…3e20 (31,) 62 65 20 77 72 69 74 74 65 6e 20 74 6f 20 74 68 65 20 54 78 2d 72 65 80 0a 67 69 73 74 65 72 2e ┆be written to the Tx-re gister.┆
0x3e20…3e40 20 54 68 65 20 6d 65 61 6e 69 6e 67 20 6f 66 20 54 78 52 44 59 20 61 6e 64 20 52 78 52 44 59 20 ┆ The meaning of TxRDY and RxRDY ┆
0x3e40…3e60 64 69 66 66 65 72 73 20 73 6c 69 67 74 68 6c 79 20 66 72 6f 6d 20 0a 74 68 65 20 73 6c 61 76 65 ┆differs sligthly from the slave┆
0x3e60…3e80 20 6d 6f 64 65 2e 20 4f 70 70 6f 73 69 74 65 20 74 68 65 20 73 6c 61 76 65 20 6d 6f 64 65 20 69 ┆ mode. Opposite the slave mode i┆
0x3e80…3ea0 74 20 69 73 20 6e 6f 74 20 61 6c 6c 6f 77 65 64 20 74 6f 20 0a 77 72 69 74 65 20 74 68 65 20 6e ┆t is not allowed to write the n┆
0x3ea0…3ec0 65 78 74 20 64 61 74 61 20 62 79 74 65 20 74 6f 20 74 68 65 20 74 72 61 6e 73 6d 69 74 20 72 65 ┆ext data byte to the transmit re┆
0x3ec0…3ee0 67 69 73 74 65 72 20 65 61 72 6c 69 65 72 20 0a 74 68 61 6e 20 33 32 20 74 63 79 20 28 38 20 75 ┆gister earlier than 32 tcy (8 u┆
0x3ee0…3f00 73 20 61 74 20 34 4d 48 7a 29 20 61 66 74 65 72 20 74 68 65 20 61 73 73 65 72 74 69 6f 6e 20 6f ┆s at 4MHz) after the assertion o┆
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