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Names: »D43«
└─⟦2294a1cd1⟧ Bits:30005867/disk06.imd Dokumenter (RCSL m.m.)
└─⟦this⟧ »D43«
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T_A_B_L_E_ _O_F_ _C_O_N_T_E_N_T_S_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _P_A_G_E_
1. DESCRIPTION ............................................ 1
2. BLOCKDIAGRAM ........................................... 2
3. TIMING DIAGRAMS ........................................ 3
4. LOGIC DIAGRAMS AND FUNCTIONAL DESCRIPTION .............. 6
4.1 COM203 Drawings ................................... 6
4.2 COM201 Replacement Drawings ....................... 40
4.3 SLA201 Drawings ................................... 46
5. MICROPROGRAM ........................................... 86
5.1 Functional Description ............................ 86
5.2 Microprogram Format ............................... 86
5.3 Interrupt ......................................... 89
5.4 Micro Assembler Listing ........................... 91
6. ASSEMBLY DRAWINGS ...................................... 107
7. PLUG LIST .............................................. 109
8. COMPONENT LIST ......................................... 113
8.1 COM203 ............................................ 113
8.2 SLA201 ............................................ 114
9. PROM LISTINGS .......................................... 115
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F_ 1_._ _ _ _ _ _ _ _ _D_E_S_C_R_I_P_T_I_O_N_ 1.
RC3541 is a 1 channel HDLC consisting of the COM203 (or COM201)
controller board. It is able to control 1 V24 line in both direc-
tions.
The RC3543 is a 4 channel HDLC consisting of the COM203 (or
COM201) combined with the SLA201 board. These two boards in con-
nection can control 4 V24 lines or 4 V35 lines in any combina-
tion.
The main circuit of each of the communication controllers is a
USRT (Universal Synchronous Receiver/Transmitter) LSI integrated
circuit, which executes a lot of the time-consuming functions in
connection with bit oriented protocols. To enable possibility to
receive blocks with small gabs in between, the controller uses a
FiFo of store addresses and bytecounts, implemented with 3 256x4
RAMs. This gives the controller the possibility of reading and
writing in the store with chained DMA. The data of a block can be
placed in different places in store, without involving the soft-
ware driver in the shifts.
To be able to increment addresses and bytecount, and to check and
set flags the controller has a 2901 sequencer which is used as an
accumulator with an incrementer.
The controller has a very small microprogram which controls the
FiFo and the transfer of data during I/O instruction and DMA
transfers. The microprogram is 256 words by 16 bits.
The COM203 diagrams consist of 17 pages. The COM201 consists of
the same diagrams, except for diagrams 4, 14 and 15. These dia-
grams are changed and added after the COM203 diagrams.
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F_ 2_._ _ _ _ _ _ _ _ _B_L_O_C_K_D_I_A_G_R_A_M_ 2.
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F_ 3_._ _ _ _ _ _ _ _ _T_I_M_I_N_G_ _D_I_A_G_R_A_M_ 3.
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F_
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F_ 4_._ _ _ _ _ _ _ _ _L_O_G_I_C_ _D_I_A_G_R_A_M_S_ _A_N_D_ _F_U_N_C_T_I_O_N_A_L_ _D_E_S_C_R_I_P_T_I_O_N_ 4.
4_._1_ _ _ _ _ _ _ _C_O_M_2_0_3_ _D_r_a_w_i_n_g_s_ 4.1
S_i_g_n_a_l_ _ _ _ _ _ _ _ _ _ _ _ _D_e_s_t_i_n_a_t_i_o_n_ _ _ _ _ _D_e_s_c_r_i_p_t_i_o_n_
-,BUS 0-15 J1 Backplane bus.
BUS IN 0-15 2 Internal bus.
MSEL 0-7 J1 Module select.
Used to select memory module or
I/O.
MSEL IN 0-7 4 Controller and channel address.
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F_ S_i_g_n_a_l_ _ _ _ _ _ _ _ _ _ _ _ _D_e_s_t_i_n_a_t_i_o_n_ _ _ _ _ _D_e_s_c_r_i_p_t_i_o_n____________________
BUS OUT 0-15 1 Output to backplane bus.
DATA IN 0-7 16 Input to internal bus.
-,PARITY 3 Parity output to backplane bus.
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F_ S_i_g_n_a_l_ _ _ _ _ _ _ _ _ _ _ _ _D_e_s_t_i_n_a_t_i_o_n_ _ _ _ _ _D_e_s_c_r_i_p_t_i_o_n____________________
TRANSFER GATE 5 I/O command initiation.
The signal is used to start up
the microprogram.
-,COMMAND GATE 6 Header of I/O command.
The signal is used to decode a
map address to the
microprogram, and to update the
current channel no.
-,INT GATE 4 Set or clear of interrupt.
-,EXTEND CYCLE J1 All I/O command are extended
until the microprogram sets
XFER ACK.
-,I/O COMMAND 3 Operation requiring EXTEND
CYCLE.
-,WRITE REC 3 Backplane bus write pulse.
-,EN MSEL 1 Enable module select during DMA
transfer.
-,PROM ADD J1 Prom addressing.
-,BUS LP J1 Parity bit bus (0:7).
-,BUS RP J1 Parity bit bus (8:15).
-,RESET BIT 6 9 These signals keep bit 6 or bit
-,RESET BIT 7 9 7 or both low before entering
the accumulator/incrementer.
-,EN SEL 5 Select current channel no.
during I/O command.
EN BUS REQUEST 5 Enable possibility for DMA
request.
-,EN INTERRUPT 1 Enable MSel-drivers for setting
interrupt.
-,EN MSEL* 1 Enable MSel-drivers for memory
module addressing.
-,EN BYTE 3 Enable byte addressing of the
memory.
-,EN BUS 3 Enable busdrivers during DMA
access.
-,XFER ACK J1C17 Xfer acknowledge. Bus control
signal that ends a bus cycle
with "extend cycle".
-,(READ v WRITE) 3 Read or write pulse from the
bus.
-,EN BUS* 1 Enable busdrivers.
-,EN XFER ACK 3 Enable "xfer ack" bus control
signal.
-,READ 3, J1A14 Bus control signals used during
-,WRITE 3, J1A15 memory addressing and data
-,FOREWARD READ J1C16 transfer.
-,IORS 1 3 Bus control signal.
This signal must be active when
the controller wants to set its
own interrupt.
-,BYTE EN J1A17 Bus control signal used to
address the memory bytewise.
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F_ S_i_g_n_a_l_ _ _ _ _ _ _ _ _ _ _ _ _D_e_s_t_i_n_a_t_i_o_n_ _ _ _ _ _D_e_s_c_r_i_p_t_i_o_n____________________
-,MODSEL 3 Device selection.
LEVEL (9:12) 1 Device code. This code is put
on the bus when the CPU uses
"INTA" and the controller has
an interrupt set.
DMA SYNC 5 Synchronization of busrequests.
-,S1 7 Control signal for the micro-
program sequencer.
After a MAP or a return from
subroutine the microprogram
address is not counted up.
I/O COMMAND During a MAP operation in the
microprogram, the map address
depends on whether an I/O
instruction or a bus acknowl-
edge causes the mapping.
EN SEL Select current channel no.
during I/O command.
-,EN LEVEL 1 Enable level number to the bus
when the CPU uses an "INTA" and
the controller has an interrupt
set.
-,INTERRUPT (0:7) 4 The controller has 8 levels of
interrupt.
-,EN LEVEL* 4 The controller has at least one
interrupt level set, when this
signal is active.
LEVEL (13:15) 1 Interrupt level priority.
-,INTERRUPT J1C18 Interrupt priority chain.
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F_ S_i_g_n_a_l_ _ _ _ _ _ _ _ _ _ _ _ _D_e_s_t_i_n_a_t_i_o_n_ _ _ _ _ _D_e_s_c_r_i_p_t_i_o_n____________________
-,DMA OUT J1C31 DMA priority chain.
-,DMA REQ J1C14 DMA request.
BUS ACK 3, 5, 9 Bus acknowledge. This signal is
used to start up the micropro-
gram.
START 6 Start of microprogram.
-,START n/c (jump condition).
COMMAND BIT (8:9) 6 These control signals are used
when decoding an I/O instruc-
tion in the map prom.
-,INTERRUPT 6 This control signal indicates
REQUEST to the map prom that a bus
acknowledge is issued by an
interrupt request.
CURRENT 1, 10, 17 Current channel number is
CHANNEL (0:1) specified either by the channel
CURRENT 6, 10, 14, 17 that has requested a bus access
CHANNEL 2 or by the device number
addressed by a I/O command.
BUS REQUEST 5 Bus access request, generated
by an interrupt request or a
USRT data request.
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F_ S_i_g_n_a_l_ _ _ _ _ _ _ _ _ _ _ _ _D_e_s_t_i_n_a_t_i_o_n_ _ _ _ _ _D_e_s_c_r_i_p_t_i_o_n____________________
MAP (0:7) 7 Next microprogram address
during mapping.
MODE 6 Jump condition (not used).
CP CARRY OUT 6 Carry jump condition.
CONDITION (4:7) 6 COM Bus 4-7 jump condition.
-,JUMP n/c Jump condition fulfilled.
S0, S1 7 Selection of microprogram
sequence.
(0,0) = Continue.
(0,1) = Return from subroutine.
(1,0) = Jump.
(1,1) = Jump map.
-,FE File enable. This signal is
active when a jump also is a
subroutine call.
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F_ S_i_g_n_a_l_ _ _ _ _ _ _ _ _ _ _ _ _D_e_s_t_i_n_a_t_i_o_n_ _ _ _ _ _D_e_s_c_r_i_p_t_i_o_n____________________
NEXT MP ADDRESS 7 Next microprogram address.
(0:7)
MP (0:15) 8 Microprogram control word.
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F_ S_i_g_n_a_l_ _ _ _ _ _ _ _ _ _ _ _ _D_e_s_t_i_n_a_t_i_o_n_ _ _ _ _ _D_e_s_c_r_i_p_t_i_o_n____________________
MPREG (0:15) 1, 3, 6, 7, 8, Microprogram control register.
9, 10, 11, 12 See microprogram format de-
17 scription.
-,JUMP 6 Decoding of the 4 different
INSTRUCTION formats in the microprogram.
-,IMID 8, 9
INSTRUCTION
-,FiFo n/c
INSTRUCTION
-,USRT n/c
INSTRUCTION
CP RT 14 Clock pulses to different
CP FiFo registers (destinations).
CP MODEM 14
CP INC 9
CP CHANNEL 5
CP MSEL 1
CP POINTER 10
CP BUS 3
-,EN INO 1 Enable signals to different
-,EN INI 1 registers (sources).
-,EN INC 9
-,EN FiFo 10
-,EN STATUS 13
-,CLEAR MODEM 15
-,EN FLAGS 10
MP2 8 MP2 is modified in case the
previous instruction was a map
or a return subroutine.
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F_ S_i_g_n_a_l_ _ _ _ _ _ _ _ _ _ _ _ _D_e_s_t_i_n_a_t_i_o_n_ _ _ _ _ _D_e_s_c_r_i_p_t_i_o_n____________________
CARRY OUT 6 Carry from incrementer.
(Jump condition).
INC (0:7) 17 Output form incrementer.
IMID (0:7) 17 Output from immediate instruc-
tion.
-,RXA 17 Receiver and transmitter
-,TXA 17 active. These signals are used
to drive front panel lamps.
COMMAND GATE 5, 6 Indicates that a start was
caused by an I/O header from
the CPU. This is used during
mapping.
-,BUSACK 3 Bus acknowledge.
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F_ S_i_g_n_a_l_ _ _ _ _ _ _ _ _ _ _ _ _D_e_s_t_i_n_a_t_i_o_n_ _ _ _ _ _D_e_s_c_r_i_p_t_i_o_n____________________
FiFo (0:7) 17 Output from FiFo-Ram.
USRT ADDR (0:2) 12 The pointer register is used
both as pointer for the FiFo
Ram and for the USRT registers.
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F_ S_i_g_n_a_l_ _ _ _ _ _ _ _ _ _ _ _ _D_e_s_t_i_n_a_t_i_o_n_ _ _ _ _ _D_e_s_c_r_i_p_t_i_o_n____________________
CLOCK 11 6,4 MHz clock.
CP480 n/c This clock system generates a
CP320 n/c 160 nS microprogram clock
CP160 n/c unless the microprogram format
CP ENABLE 11
CP 5, 6, 7, 8, 15 case a 480 nS clock is
-,CP 17 generated.
SET USRT TIME 11 The USRT TIME is generated only
USRT TIME 14 in an USRT instruction and is
used as enable and gate signal
to the USRT.
64 KHz 17 64 KHz clock used for test pur-
pose.
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F_ S_i_g_n_a_l_ _ _ _ _ _ _ _ _ _ _ _ _D_e_s_t_i_n_a_t_i_o_n_ _ _ _ _ _D_e_s_c_r_i_p_t_i_o_n____________________
MPCC (0:7) 17 Output from USRT.
RXA 9 Receiver and transmitter
active, used for front panel
lamps.
RXDA 13, 14 Receiver data available and
TXBE 14 transmitter buffer empty, used
to generate a dma access.
RXSA 13 Receiver status available and
TXU 13 transmitter underrun, used to
generate a bus request to set
interrupt.
TXSO 15 Transmitter serial output
(transmitted data).
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F_ S_i_g_n_a_l_ _ _ _ _ _ _ _ _ _ _ _ _D_e_s_t_i_n_a_t_i_o_n_ _ _ _ _ _D_e_s_c_r_i_p_t_i_o_n____________________
STATUS (0:7) 17 Status drivers.
-,INT R0 5 Receiver and transmitter
interrupt requests. These
signals generate bus request to
set interrupt.
REQUEST TO SEND J3-4 RTS modem signal.
DATA TERMINAL J3-10 DTR modem signal.
READY
RATE SELECT J3-23 Rate modem signal.
-,CTS 13 Clear to send modem signal.
-,DSR 15 Data set ready modem signal.
-,DCD 15 Data carrier detect modem
signal.
-,SQD 15 Signal quality detect modem
signal.
-,CI 13, 15 Calling indicator modem signal.
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F_ S_i_g_n_a_l_ _ _ _ _ _ _ _ _ _ _ _ _D_e_s_t_i_n_a_t_i_o_n_ _ _ _ _ _D_e_s_c_r_i_p_t_i_o_n____________________
-,RTS 13 Request to send, modem signal.
-,DTR 13 Data terminal ready, modem
signal.
ENABLE CI 15 Enable calling indicator
interrupt. When active the
raise of CI will generate an
interrupt.
-,RATE 13 Rate select, modem signal.
TXE 12 Transmitter and receiver
RXE 12 enable.
ENABLE T INT 13 Enable interrupt request from
ENABLE R INT 13 transmitter or receiver.
OVERRUN 13 Receiver overrun, status
signal.
TRANSM INT 13 Set transmitter or receiver
RECEIVE INT 13 interrupt request if enabled.
COM INT 13 Transmitter or receiver inter-
rupt, status signal.
-,TXBE* 0 5 DMA request from transmitter.
DBEN 12 Enable or gate signal to user.
-,EN STATUS 0 13 Enable status drivers.
-,CLEAR MODEM 0 15 Clear modem status latches.
-,RXDA 0 5 DMA request from receiver.
RXC 12 Receiver clock.
RESET 11, 12 System Reset.
-,RESET 7, 14
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F_ S_i_g_n_a_l_ _ _ _ _ _ _ _ _ _ _ _ _D_e_s_t_i_n_a_t_i_o_n_ _ _ _ _ _D_e_s_c_r_i_p_t_i_o_n____________________
RCD V24 15 Receiver data from the modem.
-,TCL V24 15 Transmitter clock from the
modem.
-,RCL V24 15 Receiver clock from the modem.
TRM CLOCK V24 OUT J3-9 Internal generated clock for
REC CLOCK V24 OUT test purposes.
TRM DATA V24 OUT J3-2 Transmitter data to the modem.
RXSI 12 Receiver data from the modem.
-,RXC 14 Receiver clock from the modem.
TXC 12 Transmitter clock from the
modem.
SELECT V35 n/c Select between V24 I/O or V35
I/O (from SLA).
SQD OFF LATCH 13 Signal quality detect has been
off, status signal.
CI ON LATCH 13 Calling indicator has raised
while enabled.
DSR OFF LATCH 13 Latching off fall of modem
DCD OFF LATCH n/c signals.
-,DSR LATCH 13 The modem is or has been off.
-,DCD LATCH Status signal.
DSR 15 Modem signals.
DCD 15
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F_ S_i_g_n_a_l_ _ _ _ _ _ _ _ _ _ _ _ _D_e_s_t_i_n_a_t_i_o_n_ _ _ _ _ _D_e_s_c_r_i_p_t_i_o_n____________________
COM BUS (0:7) 2 Internal tri-state bus.
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F_ S_i_g_n_a_l_ _ _ _ _ _ _ _ _ _ _ _ _D_e_s_t_i_n_a_t_i_o_n_ _ _ _ _ _D_e_s_c_r_i_p_t_i_o_n____________________
COM BUS (0:7) J2 Control signals are transfered
CURRENT CHANNEL J2 to the SLA via J2.
(0:2)
MPREG (10:11) J2
USRT TIME J2
-,EN STATUS J2
-,CLEAR MODEM J2
-,CP* J2
CPRT J2
CPPOINTER J2
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F_ 4_._2_ _ _ _ _ _ _ _C_O_M_2_0_1_ _R_e_p_l_a_c_e_m_e_n_t_ _D_r_a_w_i_n_g_s_ 4.2
S_i_g_n_a_l_ _ _ _ _ _ _ _ _ _ _ _ _D_e_s_t_i_n_a_t_i_o_n_ _ _ _ _ _D_e_s_c_r_i_p_t_i_o_n_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
-,MODSEL 3 Device selection.
LEVEL (9:12) 1 Device code. This code is put
on the bus when the CPU uses
"INTA" and the controller has
an interrupt set.
DMA SYNC 5 Synchronization of busrequests.
-,S1 7 Control signal for the micro-
program sequencer.
After a MAP or a return from
subroutine the microprogram
address is not counted up.
I/O COMMAND During a MAP operation in the
microprogram, the map address
depends on whether an I/O
instruction or a bus acknowl-
edge causes the mapping.
EN SEL Select current channel no.
during I/O command.
-,EN LEVEL 1 Enable level number to the bus
when the CPU uses an "INTA" and
the controller has an interrupt
set.
-,INTERRUPT (0:7) 4 The controller has 8 levels of
interrupt.
-,EN LEVEL* 4 The controller has at least one
interrupt level set, when this
signal is active.
LEVEL (13:15) 1 Interrupt level priority.
-,INTERRUPT J1C18 Interrupt priority chain.
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F_ S_i_g_n_a_l_ _ _ _ _ _ _ _ _ _ _ _ _D_e_s_t_i_n_a_t_i_o_n_ _ _ _ _ _D_e_s_c_r_i_p_t_i_o_n____________________
-,RTS 13 Request to send, modem signal.
-,DTR 13 Data terminal ready, modem
signal.
ENABLE CI 15 Enable calling indicator
interrupt. When active the
raise of CI will generate an
interrupt.
-,RATE 13 Rate select, modem signal.
TXE 12 Transmitter and receiver
RXE 12 enable.
ENABLE T INT 13 Enable interrupt request from
ENABLE R INT 13 transmitter or receiver.
OVERRUN 13 Receiver overrun, status
signal.
TRANSM INT 13 Set transmitter or receiver
RECEIVE INT 13 interrupt request if enabled.
COM INT 13 Transmitter or receiver inter-
rupt, status signal.
-,TXBE* 0 5 DMA request from transmitter.
DBEN 12 Enable or gate signal to user.
-,EN STATUS 0 13 Enable status drivers.
-,CLEAR MODEM 0 15 Clear modem status latches.
-,RXDA 0 5 DMA request from receiver.
RXC 12 Receiver clock.
RESET 11, 12 System Reset.
-,RESET 7, 14
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F_ S_i_g_n_a_l_ _ _ _ _ _ _ _ _ _ _ _ _D_e_s_t_i_n_a_t_i_o_n_ _ _ _ _ _D_e_s_c_r_i_p_t_i_o_n____________________
RCD V24 15 Receiver data from the modem.
-,TCL V24 15 Transmitter clock from the
modem.
-,RCL V24 15 Receiver clock from the modem.
TRM CLOCK V24 OUT J3-9 Internal generated clock for
REC CLOCK V24 OUT test purposes.
TRM DATA V24 OUT J3-2 Transmitter data to the modem.
RXSI 12 Receiver data from the modem.
-,RXC 14 Receiver clock from the modem.
TXC 12 Transmitter clock from the
modem.
SELECT V35 n/c Select between V24 I/O or V35
I/O (from SLA).
SQD OFF LATCH 13 Signal quality detect has been
off, status signal.
CI ON LATCH 13 Calling indicator has raised
while enabled.
DSR OFF LATCH 13 Latching off fall of modem
DCD OFF LATCH n/c signals.
-,DSR LATCH 13 The modem is or has been off.
-,DCD LATCH Status signal.
DSR 15 Modem signals.
DCD 15
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F_ 4_._3_ _ _ _ _ _ _ _S_L_A_2_0_1_ _D_r_a_w_i_n_g_s_ 4.3
S_i_g_n_a_l_ _ _ _ _ _ _ _ _ _ _ _ _D_e_s_t_i_n_a_t_i_o_n_ _ _ _ _ _D_e_s_c_r_i_p_t_i_o_n_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
COM BUS (0:7) J2 Direct connection to COM
internal bus.
SLA IN (0:7) 19 Input to internal SLA bus.
-,EN STATUS 2 Enable status register
(source).
USRT TIME 2 Enabling and gating of USRT.
MPREG 11 2 Microprogram register 11.
Indicates active USRT instruc-
tion.
-,READ/WRITE 6, 7, 8 Read or write into USRT.
-,EN SLA OUT 1 Control of connection between
-,EN SLA IN 1 SLA bus and COM bus. Normally
the input is active. When an
USRT read or a status read is
active the input is disabled,
and if also current channel is
2-7, the output is active.
CURRENT CHANNEL 2, 3, 4 Current channel no.
(0:2)
-,CLEAR MODEM* 2 Clear modem status latches.
-,CP* 5, 9, 11, 13 Microprogram clock.
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F_ S_i_g_n_a_l_ _ _ _ _ _ _ _ _ _ _ _ _D_e_s_t_i_n_a_t_i_o_n_ _ _ _ _ _D_e_s_c_r_i_p_t_i_o_n_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
CP MODEM (0:3) 3, 4 Distribution of destination and
CP RT (0:3) 3, 4 source on the 4 channels.
-,EN STATUS (0:3) 10, 12, 14 Channel 0 is used on the COM.
-,CLEAR MODEM 9, 11, 13
(0:3)
DBEN (0:3) 6, 7, 8
LOGIC 1 A 1, 2, 5 Pull ups.
LOGIC 1 B 9, 10, 15
LOGIC 1 C 11, 12, 16
LOGIC 1 D 13, 14, 16
USRT ADDR (0:2) 6, 7, 8 Pointer for USRT.
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F_ S_i_g_n_a_l_ _ _ _ _ _ _ _ _ _ _ _ _D_e_s_t_i_n_a_t_i_o_n_ _ _ _ _ _D_e_s_c_r_i_p_t_i_o_n_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
RTS (0:1) J2, 10 Request to send.
DTR (0:1) J2, 10 Data terminal ready.
ENABLE CI (0:1) J1, 9 Enable calling indicator
interrupt.
-,TRATE (0:1) J2, 10 Rate select.
TXE (0:1) J2, 6 Transmitter enable. USRT
control signal.
RXE (0:1) J2, 6 Receiver enable. USRT control
signal.
ENABLE T INT J2, 10 Enable transmitter interrupt.
(0:1)
ENABLE R INT J2, 10 Enable receiver interrupt.
(0:1)
OVERRUN (0:1) J2, 10 Receiver overrun.
TRANSM INT (0:1) J2, 10 Set transmitter interrupt
request.
RECEIVE INT (0:1) J2, 10 Set receiver interrupt request.
ENABLE TXBE (0:1) J2, 5 Enable transmitter DMA request.
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F_ S_i_g_n_a_l_ _ _ _ _ _ _ _ _ _ _ _ _D_e_s_t_i_n_a_t_i_o_n_ _ _ _ _ _D_e_s_c_r_i_p_t_i_o_n_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
RTS (2:3) 12, 14 Request to send.
DTR (2:3) 12, 14 Data terminal ready.
ENABLE CI (2:3) 11, 13 Enable calling indicator
interrupt.
-,RATE 12, 14 Rate select.
TXE (2:3) 7, 8 Transmitter enable. USRT
control signal.
RXE (2:3) 7, 8 Receiver enable. USRT control
signal.
ENABLE T INT 12, 14 Enable transmitter interrupt.
(2:3)
ENABLE R INT 12, 14 Enable receiver interrupt.
(2:3)
OVERRUN (2:3) 12, 14 Receiver overrun.
TRANSM INT (2:3) 12, 14 Set transmitter interrupt
request.
RECEIVE INT (2:3) 12, 14 Set receiver interrupt request.
ENABLE TXBE (2:3) 5 Enable transmitter DMA request.
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F_ S_i_g_n_a_l_ _ _ _ _ _ _ _ _ _ _ _ _D_e_s_t_i_n_a_t_i_o_n_ _ _ _ _ _D_e_s_c_r_i_p_t_i_o_n_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
-,RXA (1:3) J2 Receiver and transmitter
-,TXA (1:3) active. These signals drive the
COM front panel lamps.
RESET 5, 6, 7, 8 Main reset signal.
-,RESET* 3, 4
-,RXDA (1:3) J2 Receiver DMA request.
-,TXBE* (1:3) J2 Transmitter DMA request.
RXC (1:3) 6, 7, 8 Receiver clock. Input clock to
USRT.
\f
F_
\f
F_ S_i_g_n_a_l_ _ _ _ _ _ _ _ _ _ _ _ _D_e_s_t_i_n_a_t_i_o_n_ _ _ _ _ _D_e_s_c_r_i_p_t_i_o_n_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
1 MPCC (0:7) 19 Output from USRT.
RXA 1 5 Receiver and transmitter
TXA 1 5 active, used for front panel
lamps.
RXDA 1 5 Receiver data available and
TABE 1 5 transmitter buffer empty, used
to generate a dma access.
RXSA 1 10 Receiver status available and
TXU 1 10 transmitter underrun, used to
generate a bus request to set
interrupt.
TXSO 1 9, 17 Transmitter serial output
(transmitted data).
\f
F_
\f
F_ S_i_g_n_a_l_ _ _ _ _ _ _ _ _ _ _ _ _D_e_s_t_i_n_a_t_i_o_n_ _ _ _ _ _D_e_s_c_r_i_p_t_i_o_n_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
2 MPCC (0:7) 19 Output from USRT.
RXA 2 5 Receiver and transmitter
TXA 2 5 active, used for front panel
lamps.
RXDA 2 5 Receiver data available and
TABE 2 5 transmitter buffer empty, used
to generate a dma access.
RXSA 2 12 Receiver status available and
TXU 2 12 transmitter underrun, used to
generate a bus request to set
interrupt.
TXSO 2 11, 18 Transmitter serial output
(transmitted data).
\f
F_
\f
F_ S_i_g_n_a_l_ _ _ _ _ _ _ _ _ _ _ _ _D_e_s_t_i_n_a_t_i_o_n_ _ _ _ _ _D_e_s_c_r_i_p_t_i_o_n_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
3 MPCC (0:7) 19 Output from USRT.
RXA 3 5 Receiver and transmitter
TXA 3 5 active, used for front panel
lamps.
RXDA 3 5 Receiver data available and
TABE 3 5 transmitter buffer empty, used
to generate a dma access.
RXSA 3 14 Receiver status available and
TXU 3 14 transmitter underrun, used to
generate a bus request to set
interrupt.
TXSO 3 13, 18 Transmitter serial output
(transmitted data).
\f
F_
\f
F_ S_i_g_n_a_l_ _ _ _ _ _ _ _ _ _ _ _ _D_e_s_t_i_n_a_t_i_o_n_ _ _ _ _ _D_e_s_c_r_i_p_t_i_o_n_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
RCD V24 1 9 Receiver data from the modem.
-,TCL V24 1 9 Transmitter clock from the
modem.
-,RCL V24 1 9 Receiver clock from the modem.
TRM CLOCK V24 J3-9 Internal generated clock for
OUT 1 test purpose.
REC CLOCK V24 J3-10
OUT 1
TRM DATA V24 J3-1 Transmitter data to the modem.
OUT 1
RXSI 1 6 Receiver data from the modem.
-,RXC 1 6 Receiver clock from the modem.
TXC 1 6 Transmitter clock from the
modem.
SQD OFF LACTH 1 10 Signal quality detect has been
off, status signal.
CI ON LATCH 1 10 Calling indicator has raised
while enabled.
DSR OFF LATCH 1 n/c Latching of fall of modem
DCD OFF LATCH 1 n/c signals.
-,DSR LATCH 1 10 The modem is or has been off.
-,DCD LATCH 1 10 Status signal.
DSR 1 9 Modem signals.
DCD 1 9
\f
F_
\f
F_ S_i_g_n_a_l_ _ _ _ _ _ _ _ _ _ _ _ _D_e_s_t_i_n_a_t_i_o_n_ _ _ _ _ _D_e_s_c_r_i_p_t_i_o_n_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
1 STATUS (0:7) 19 Status drivers.
-,INT R 1 J2A12 Receiver and transmitter inter-
-,INT T 1 J2C12 rupt request. These signals
generate bus request to set
interrupt.
REQUEST TO SEND 1 J3-3 RTS modem signal.
DATA TERMINAL J3-13 DTR modem signal.
READY 1
RATE SELECT 1 J3-16 Rate modem signal.
-,CTS 1 10 Clear to send modem signal.
-,DSR 1 9 Data set ready modem signal.
-,DCD 1 9 Data carrier detect modem
signal.
-,SQD 1 9 Signal quality detect modem
signal.
-,CI 1 9, 10 Calling Indicator modem signal.
\f
F_
\f
F_ S_i_g_n_a_l_ _ _ _ _ _ _ _ _ _ _ _ _D_e_s_t_i_n_a_t_i_o_n_ _ _ _ _ _D_e_s_c_r_i_p_t_i_o_n_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
RCD V24 2 11 Receiver data from the modem.
-,TCL V24 2 11 Transmitter clock from the
modem.
-,RCL V24 2 11 Receiver clock from the modem.
TRM CLOCK V24 J3-27 Internal generated clock for
OUT 2 test purpose.
REC CLOCK V24 J3-28
OUT 2
TRM DATA V24 J3-19 Transmitter data to the modem.
OUT 2
RXSI 2 7 Receive data from the modem.
-,RXC 2 7 Receiver clock from the modem.
TXC 2 7 Transmitter clock from the
modem.
SQD OFF LATCH 2 12 Signal quality detect has been
off, status signal.
CI ON LATCH 2 12 Calling indicator has raised
while enabled.
DSR OFF LATCH n/c Latching of fall of modem
DCD OFF LATCH n/c signals.
-,DSR LATCH 12 The modem is or has been off.
-,DCD LATCH 12 Status signal.
DSR 11 Modem signals.
DCD 11
\f
F_
\f
F_ S_i_g_n_a_l_ _ _ _ _ _ _ _ _ _ _ _ _D_e_s_t_i_n_a_t_i_o_n_ _ _ _ _ _D_e_s_c_r_i_p_t_i_o_n_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
2 STATUS (0:7) 19 Status drivers.
-,INT R2 J2A13 Receiver and transmitter
-,INT T2 J2C13 interrupt requests. These
signals generate bus request to
set interrupt.
REQUEST TO SEND 2 J3-21 RTS modem signal.
DATA TERMINAL J3-31 DTR modem signal.
RATE SELECT 2 J3-34 Rate modem signal.
-,CTS 2 12 Clear to send modem signal.
-,DSR 2 11 Data set ready modem signal.
-,DCD 2 11 Data carrier detect modem
signal.
-,SQD 2 11 Signal quality detect modem
signal.
-,CI 2 11 Calling indicator modem signal.
\f
F_
\f
F_ S_i_g_n_a_l_ _ _ _ _ _ _ _ _ _ _ _ _D_e_s_t_i_n_a_t_i_o_n_ _ _ _ _ _D_e_s_c_r_i_p_t_i_o_n____________________
RCD V24 3 13 Receiver data from the modem.
-,TCL V24 3 13 Transmitter clock from the
modem.
-,RCL V24 3 13 Receiver clock from the modem.
TRM CLOCK V24 J3-43 Internal generated clock for
OUT 3 test purpose.
REC CLOCK V24 J3-44
OUT 3
TRM DATA V24 J3-35 Transmitter data to the modem.
OUT 3
RXSI 3 8 Receiver data from the modem.
-,RXC 3 8 Receiver clock from the modem.
TXC 3 8 Transmitter clock from the
modem.
SQD OFF LATCH 3 14 Signal quality detect has been
off, status signal.
CI ON LATCH 3 13 Calling indicator has raised
while enabled.
DSR OFF LATCH n/c Latching off fall of modem
DCD OFF LATCH n/c signals.
-,DSR LATCH 14 The modem is or has been off.
-,DCD LATCH Status signal.
DSR 13 Modem signals.
DCD 13
\f
F_
\f
F_ S_i_g_n_a_l_ _ _ _ _ _ _ _ _ _ _ _ _D_e_s_t_i_n_a_t_i_o_n_ _ _ _ _ _D_e_s_c_r_i_p_t_i_o_n_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
3 STATUS (0:7) 3 19 Status drivers.
-,INT R3 J2A14 Receiver and transmitter inter-
-,INT T4 J2-C14 rupt requests. These signals
generate bus request to set
interrupt.
REQUEST TO SEND 3 J3-37 RTS modem signal.
DATA TERMINAL J3-47 DTR modem signal.
READY 3
RATE SELECT 3 J3-50 Rate modem signal.
-,CTS 3 14 Clear to send modem signal.
-,DSR 3 13 Data set ready modem signal.
-,DCD 3 13 Data carrier detect modem
signal.
-,SQD 3 13 Signal quality detect modem
signal.
-,CI 3 13 Calling indicator modem signal.
\f
F_
\f
F_ S_i_g_n_a_l_ _ _ _ _ _ _ _ _ _ _ _ _D_e_s_t_i_n_a_t_i_o_n_ _ _ _ _ _D_e_s_c_r_i_p_t_i_o_n____________________
RCD V35 (0:1) J2, 9 Receiver data from modem.
-.TCL V35 (0:1) J2, 9 Transmitter clock from modem.
-,RCL V35 (0:1) J2, 9 Receiver clock from modem.
\f
F_
\f
F_ S_i_g_n_a_l_ _ _ _ _ _ _ _ _ _ _ _ _D_e_s_t_i_n_a_t_i_o_n_ _ _ _ _ _D_e_s_c_r_i_p_t_i_o_n____________________
RCD V35 (2:3) 11, 13 Receiver data from modem.
-.TCL V35 (2:3) 11, 13 Transmitter clock from modem.
-,RCL V35 (2:3) 11, 13 Receiver clock from modem.
\f
F_
\f
F_ S_i_g_n_a_l_ _ _ _ _ _ _ _ _ _ _ _ _D_e_s_t_i_n_a_t_i_o_n_ _ _ _ _ _D_e_s_c_r_i_p_t_i_o_n____________________
TRM DATA V35 J4 Transmitter data to modem.
OUT (0:1)
TRM CLOCK V35 J4 Transmitter clock for test
OUT (0:1) purpose.
REC CLOCK V35 J4 Receiver clock for test
OUT (0:1) purpose.
\f
F_
\f
F_ S_i_g_n_a_l_ _ _ _ _ _ _ _ _ _ _ _ _D_e_s_t_i_n_a_t_i_o_n_ _ _ _ _ _D_e_s_c_r_i_p_t_i_o_n____________________
TRM DATA V35 J4 Transmitter data to modem.
OUT (2:3)
TRM CLOCK V35 J4 Transmitter clock for test
OUT (2:3) purpose.
REC CLOCK V35 J4 Receiver clock for test
OUT (2:3) purpose.
\f
F_
\f
F_ S_i_g_n_a_l_ _ _ _ _ _ _ _ _ _ _ _ _D_e_s_t_i_n_a_t_i_o_n_ _ _ _ _ _D_e_s_c_r_i_p_t_i_o_n____________________
SLA BUS (0:7) 1 Internal SLA bus.
\f
F_
\f
F_ S_i_g_n_a_l_ _ _ _ _ _ _ _ _ _ _ _ _D_e_s_t_i_n_a_t_i_o_n_ _ _ _ _ _D_e_s_c_r_i_p_t_i_o_n____________________
-5 VOLT 15, 16, 17, 18 Minus 5 Volt for V35
driver/receivers.
12 VOLT 9, 10, 11, 12, Plus and minus 12 Volt for V24
13, 14 driver/receivers.
SELECT V35 (1:3) 9, 11, 13 Select switches for V35/V24.
\f
F_\f
F_ 5_._ _ _ _ _ _ _ _ _M_I_C_R_O_P_R_O_G_R_A_M_ 5.
5_._1_ _ _ _ _ _ _ _F_u_n_c_t_i_o_n_a_l_ _D_e_s_c_r_i_p_t_i_o_n_ 5.1
The microprogram sequence control consists of the elements shown
in the blockdiagram last page. The microprogram address can be
generated in 3 different ways:
1) An increment of the current address.
2) The contents of the microprogram (8:15) used for direct
jumps.
3) The contents of one of the 2 map proms, used to decode
I/O instruction and DMA transfers.
The microprogram is able to control the I/O instruction in the
following way.
First the CPU sends a write pulse with IORS (0:1) = (1,0). This
defines what kind of operation it wants. The controller is able
to handle 'Read status' and 'write control' commands. This write
pulse starts up the microprogram, which uses the map prom to jump
to an address where it waits for next pulse from the CPU. When
the CPU sends the next write pulse, the controller decodes the
instruction using the map once more. If the instruction is a read
the microprogram then waits for the CPU to issue a read pulse.
When the USRT wants to read or write data via DMA to main store,
it gives a busrequest. The microprogram is started up when the
bus acknowledge is received. At this time the channel that needs
serving is defined, and there is no change of channel under
microprogram control.
This means that the microprogram is exact the same for all chan-
nels.
5_._2_ _ _ _ _ _ _ _M_i_c_r_o_p_r_o_g_r_a_m_ _F_o_r_m_a_t_ 5.2
Microinstructions are divided into 4 types: The 'JUMP', 'IMID',\f
'FiFo' and 'USRT'. They all have a 160 nS cycle time except the
'USRT', which has a 480 nS cycle time. The MP (0:1) divides be-
tween the 4 types. The format is shown on the diagram.
The four types are expanded in the microassembler to several
types, indicating whether the operation is writing or reading in
the RAM or USRT (WRAM, WUSRT for writing).
\f
F_
\f
Buscontrol Register (active zero)
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
Bit 0 Reset bit 6 before loading ACC
1 - bit 7 - - -
2 Enable I/O command channel select
3 Disable bus request
4 Enable level to MSEL bus
5 Enable COM bus to MSEL bus
6 Enable byte addressing
_ _ _ _ _7_ _ _ _ _E_n_a_b_l_e_ _C_O_M_ _b_u_s_ _t_o_ _b_a_c_k_p_l_a_n_e_ _b_u_s_ _ _ _ _ _
Interrupt control register (RT)
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
0 Disable TXBE bus request
1 Enable - - -
2 Reset COM interrupt
3 Set - -
4 Clear overrun
5 Set overrun
6 Disable interrupt
_7_ _ _ _ _ _ _ _ _E_n_a_b_l_e_ _i_n_t_e_r_r_u_p_t_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
5_._3_ _ _ _ _ _ _ _I_n_t_e_r_r_u_p_t_ 5.3
Interrupting events:
1. RXSA from USRT (Receives status available).
2. Calling indicates changes from off to on.
3. The microprogram detects flag bits in the FiFo,
indicating an interrupt is wanted.
4. TXU from USRT (transmitter underrun).
When one or more of these events arrives, an internal interrupt
is set. Only when the I/O command "Enable interrupt" is received,
the interrupt gets any further.
Then a busrequest is issued, and the interrupt flip-flops in the\f
controller is set via the backplane bus. At the same time the in-
ternal interrupt is reset and disabled. The controller in this
way has an interrupt buffer.
\f
F_ 5_._4_ _ _ _ _ _ _ _M_i_c_r_o_ _A_s_s_e_m_b_l_e_r_ _L_i_s_t_i_n_g_ 5.4
\f
F_
\f
F_
\f
F_
\f
F_
\f
F_
\f
F_
\f
F_
\f
F_
\f
F_
\f
F_
\f
F_
\f
F_
\f
F_
\f
F_
\f
F_
\f
F_ 6_._ _ _ _ _ _ _ _ _A_S_S_E_M_B_L_Y_ _D_R_A_W_I_N_G_S_ 6.
\f
F_
\f
F_ 7_._ _ _ _ _ _ _ _ _P_L_U_G_ _L_I_S_T_ 7.
COM 203 - SLA 201 connections
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
_J_2_A_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _J_2_B_ _ _ _ _ _ _ _ _ _ _ _J_2_C_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
M_ 0 Volt 1
CPPOINTER OVERRUN 2
ENABLE TINT ENABLE RINT 3
-,CP 64 KHz 4
COM BUS 0 COM BUS 4 5
- - 1 - - 5 6
- - 2 - - 6 7
- - 3 - - 7 8
CURRENT CH 0 MPREG 10 9
- - 1 - 11 10
- - 2 SPARE 11
-,INT R1 -,INT T1 12
R2 T2 13
R3 T3 14
-,RXDA 1 -,TXBE 1 15
2 2 16
3 3 17
USRT TIME -,EN STATUS 18
RCD V35 -,CLEAR MODEM 19
-,RCL V35 CP MODEM 20
-,TCL V35 TXSO 21
SPARE CP RT 22
RTS 0 RECEIVE INTO 23
DTR 0 TRANSMIT INTO 24
ENABLE CI 0 ENABLE TXBE 0 25
RATE 0 DBEN 0 26
TXE 0 -,EN STATUS 0 27
RXE 0 -,CLEAR MODEM 0 28
-,TXA 1 -,RXA 1 29
-,TXA 2 -,RXA 2 30
-,TXA 3 -,RXA 3 31
P_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _0_ _V_o_l_t_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _3_2_ _
V24 connection
M_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _J_1_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
1 Gnd 26 -
2 TRM data 25 -
3 REC data 24
4 RTS 23 Rate
5 CTS 22 CI
6 DSR 21 SQD
7 Gnd 20 DTR
8 DCD 19 -
9 TRM clock out 18 -
10 REC clock out 17 REC clock
11 - 16 -
12 - 15 TRM clock
P_ _1_3_ _ _ _-_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _1_4_ _ _-_ _ _ _ _ _ _ _ _ _ _ _ _ _
COM 203/201 Front panel
connection J1.
\f
V24 connection
M_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _J_3_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
1 TRM Data 1 2 REC Data 1
3 RTS 1 4 Gnd
5 CTS 1 6 DSR 1
7 Gnd 8 OCD 1
9 TRM clock out 1 10 REC clock out 1
11 TRM clock 1 12 REC clock 1
13 DTR 1 14 SQD 1
15 CI 1 16 RATE 1
17 Gnd 18 Gnd
19 TRM data 2 20 REC data 2
21 RTS 2 22 Gnd
23 CTS 2 24 DSR 2
25 Gnd 26 OCD 2
27 TRM clock out 2 28 REC clock out 2
29 TRM clock 2 30 REC clock 2
31 DTR 2 32 SQD 2
33 CI 2 34 RATE 2
35 TRM Data 3 36 REC data 3
37 RTS 3 38 Gnd
39 CTS 3 40 DSR 3
41 Gnd 42 DCD 3
43 TRM clock out 3 44 REC clock out 3
45 TRM clock 3 46 REC clock 3
47 DTR 3 48 SQD 3
P_ _4_9_ _ _ _C_I_ _ _ _ _ _ _ _ _ _ _ _ _3_ _ _ _ _5_0_ _ _R_a_t_e_ _ _ _ _ _ _ _ _ _ _ _3_ _ _
SLA 201 Front panel connection J2
\f
V35 connection
M_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _J_4_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
1 REC data + 0 2 -
3 TRM data + 0 4 -
5 REC clock + 0 6 -
7 TRM clock + 0 8 -
9 REC clock out + 0 10 -
11 TRM clock out + 0 12 -
13 REC data + 1 14 -
15 TRM data + 1 16 -
17 REC clock + 1 18 -
19 TRM clock + 1 20 -
21 REC clock out + 1 22 -
23 TRM clock out + 1 24 -
25 Gnd 26
27 REC data + 2 28 -
29 TRM data + 2 30 -
31 REC clock + 2 32 -
33 TRM clock + 2 34 -
35 REC clock out + 2 36 -
37 TRM clock out + 2 38 -
39 REC data + 3 40 -
41 TRM data + 3 42 -
43 REC clock + 3 44 -
45 TRM clock + 3 46 -
47 REC clock out + 3 48 -
P_ _4_9_ _ _ _T_R_M_ _c_l_o_c_k_ _o_u_t_ _+_ _3_ _ _5_0_ _ _-_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
SLA 201 Front panel connection J1
V24 connection
M_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
_ _ _ _ _ _J_U_N_C_T_I_O_N_ _P_A_N_E_L_ _L_I_N_E_ _1_-_4_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
1 Gnd 14
2 TRM data V24 15 TRM clock V24
3 REC data V24 16
4 RTS 17 REC clock V24
5 CTS 18 REC clock V35-
6 DSR 19 REC clock V35+
7 Gnd 20 DTR
8 DCD 21 SQD
9 TRM data V35- 22 CI
10 TRM data V35+ 23 Rate
11 REC data V35- 24 TRM clock V35-
12 REC data V35+ 25 TRM clock V35+
P_ _1_3_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _-_-_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ \f
B_A_C_K_ _P_L_A_N_E_ _B_U_S_
PIN NO A B C
1 0 V 0 V 0 V
2 0 V 0 V 0 V
3 +5 V +5 V +5 V
4 -12 V -12 V -12 V
5 -,BUS 0 0 V -,BUS 8
6 - 1 - 9
7 - 2 - 10
8 - 3 - 11
9 - 4 - 12
10 - 5 - 13
11 - 6 - 14
12 - 7 - 15
13 - LP - RP
14 -,WRITE -,DMA REQ
15 -,READ -,DMA ACK
16 -,INTA -,FORW READ
17 -,BYTE EN -,XFER ACK
18 -,INTP IN -,INTP OUT
19 MSEL 0 MSEL 4
20 - 1 - 5
21 - 2 - 6
22 - 3 - 7
23 -,IORS 0 SPARE
24 - 1 -,DIN BUSY
25 -,BUSY -,DMA SYNC
26 -,EOI -,EXTEND CYCLE
27 -,PROM ADD -,RESET
28 -,SUP ITR 0 V -,ITR SYNC
29 +12 V +12 V +12 V
30 +5 V +5 V +5 V
31 -,DMA IN 0 V -,DMA OUT
32 0 V 0 V 0 V
\f
F_ 8_._ _ _ _ _ _ _ _ _C_O_M_P_O_N_E_N_T_ _L_I_S_T_ 8.
8_._1_ _ _ _ _ _ _ _C_O_M_2_0_3_ 8.1
2 74S00 1 74276
1 74S02 1 AM25LS2521
1 74S04 4 AM2911
2 74S08 1 AM2922
3 74S32 3 92422/93L422
1 74S74 1 2652
1 74S112 3 75150P
1 74LS125 2 75154
2 74S138 1 XTAL 12,8 MHz
1 74S139 4 SIL 9x1 K Ohm
1 74LS157 8 390 Ohm
1 74S194 2 1,6 K Ohm
2 74S240 2 560 Ohm
5 74LS240 3 1 K Ohm
1 74S244 1 1 nF
2 74LS244 1 47 pF
1 74S253 2 2 F
2 74LS259 13 47 nF
1 74LS280 1 74S288 PROM
2 74LS348 1 74S287 -
2 74LS373 3 74S471 -
7 74LS374 5 dual dipswitch
4 74S374 4 doppelt lysdiode
1 74LS390
\f
F_ 8_._2_ _ _ _ _ _ _ _S_L_A_2_0_1_ 8.2
3 74276 5 74LS259
6 75110 5 74LS374
9 75150P 4 DS3650
6 75154 3 2652
1 74S00 3 A79M05
2 74S139 15 47 nF/12 V
2 74S260 8 22 F/15 V
4 74LS00 5 1 F/35 V
1 74LS04 2 DIP switch
1 74LS10 4 1 K Ohm
4 74LS32 3 22 Ohm 0,5 W
3 74LS157 12 SIL 4 x 56 Ohm
1 74LS175 4 SIL 7 x 120 Ohm
2 74LS240 2 SIL 9 x 330 Ohm
6 74LS244 1 SIL 7 x 1 K Ohm
\f
F_ 9_._ _ _ _ _ _ _ _ _P_R_O_M_ _L_I_S_T_I_N_G_S_ 9.
ROA397
M_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
_A_d_d_r_e_s_s_ _(_o_c_t_a_l_)_ _ _ _ _ _ _ _-_,_I_N_T_R_O_ _ _ _
0-40 1
41-43 0
44 1
45-47 0
50-57 1
60-77 0
P_ _1_0_0_-_3_7_7_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _1_ _ _ _ _
ROA398
M_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
_A_d_d_r_e_s_s_ _(_o_c_t_a_l_)_ _ _ _ _ _M_A_P_ _a_d_d_r_e_s_s_ _
0-7 377
10 104
11 102
12 164
13 215
P_ _1_4_-_3_7_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _3_7_7_ _ _ _
\f
ROA407 (COM203 only)
M_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
_A_d_d_r_e_s_s_ _ _ _L_E_V_E_L_ _ _ _-_,_E_N_ _L_E_V_E_L_ _ _-_,_I_N_T_P_U_T_ _ _
0-177 111 0 1
200-277 110 0 1
300-337 101 0 1
340-357 100 0 1
360-367 011 0 1
370-373 010 0 1
374-375 001 0 1
376 000 0 1
377 000 1 0
P_ _4_0_0_-_7_7_7_ _ _ _ _0_0_0_ _ _ _ _ _ _ _ _1_ _ _ _ _ _ _ _ _ _ _ _1_ _ _ _ _ _
ROA399
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
_A_d_d_r_e_s_s_ _ _ _ _ _ _ _ _ _ _ _ _ _ _M_a_p_ _A_d_d_r_e_s_s_ _ _C_O_M_M_A_N_D_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
0-77 377 Error
100-103 346 Read FiFo address
104-107 377 Error
110-113 360 Read FiFo flags
114-117 377 Error
120-127 341 Read pointers
130-133 353 Read FiFo bytecount
134-137 377 Error
140 334 DMA reset
141-147 260 Write USRT
150 275 Write address low
151 277 - - high
152 301 - bytecount low
153 303 - - high
154 305 - flags low
155 307 - - high
156 311 - Module select
157 377 Error
160 313 Start receiver
161 327 Start transmitter
162 334 Enable interrupt
163 264 Write modem register
164 270 Count up pointer 3
165 266 - - - 0
166-337 377 Error
_3_4_0_-_3_7_7_ _ _ _ _ _ _ _ _ _ _ _ _ _ _2_5_1_ _ _ _ _ _ _ _ _ _ _I_/_O_ _c_o_m_m_a_n_d_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ \f
\f
«eof»