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F_O_R_E_W_O_R_D_

First edition: RCSL No 30-M277.
This manual describes a reliability test of the VDC. It can be
used for two purposes, one which is testing the video display
controller alone, testing most hardware functions (must be con-
nected to an auxiliary VDC), and another one which is testing the
circuit line with a maximum of 8 stations connected (each station
must contain the related test mirror process).

The VDC test is a test package in the RC3502 test system, TOP80,
and must have this as a parent process, see ref. 2.

It is written in Real Time Pascal (RC3502 implementation).

Jan Nielsen
A/S REGNECENTRALEN af 1979, March 1981

Second edition: RCSL No 30-M298.
This second edition is made to introduce dynamic test buffers and
a test log book.

The dynamic testbuffers can for test "a" be from 1 to 254 bytes,
for test "b" from 1 to 32000 bytes.

The log book can give an impression of how the hardware has been
handled.

Jan Nielsen
A/S REGNECENTRALEN af 1979, October 1981

F_ ii
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iii

T_A_B_L_E_ _O_F_ _C_O_N_T_E_N_T_S_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _P_A_G_E_

1. INTRODUCTION ........................................... 1
1.1 Configuration Requirements ........................ 1
1.2 Parameter Values .................................. 1
1.3 Load Test ......................................... 2

2. DYNAMIC TEST BUFFERS ................................... 3

3. TEST A, RC3502 MIRROR, RELIABILITY ..................... 4
3.1 Test Strategy ..................................... 4
3.2 Error Messages .................................... 7

4. TEST B, CIRCUIT LINE, RELIABILITY ...................... 9
4.1 Test Strategy ..................................... 9

5. LOG BOOK ............................................... 11
5.1 Controller Registers .............................. 11
5.2 Interrupt/Control Words ........................... 12

A_P_P_E_N_D_I_C_E_S_:

A. REFERENCES ............................................. 15

B. EXAMPLES OF OUTPUT ..................................... 16

C. SPECIALITIES ........................................... 18
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iv
\f

F_ 1_._ _ _ _ _ _ _ _ _I_N_T_R_O_D_U_C_T_I_O_N_ 1.

1_._1_ _ _ _ _ _ _ _C_o_n_f_i_g_u_r_a_t_i_o_n_ _R_e_q_u_i_r_e_m_e_n_t_s_ 1.1

A minimum configuration for the RC3502-test system with a connec-
tion to an RC8000 or another load medium possibility for loading
the test system TOP80 and the test. For test "A" there must be
two VDC's connected with a two pair cable and a mirror process,
which are linked, created, and started by the VDC test. The mir-
ror process could be placed in another RC3502. For test "B",
there is required one VDC, a two pair circuit line and at least
one terminal (RC850) including the related test mirror.

1_._2_ _ _ _ _ _ _ _P_a_r_a_m_e_t_e_r_ _V_a_l_u_e_s_ 1.2

Param No text default min. max.
000 TESTPROGRAM : A A B
001 NO OF RUNS : 20 1 integer
002 MODULE NO (MASTER) : 16 0 126
003 CHANNEL : -1 -1 7
004 MODULE NO (MIRROR) : 18 0 124
006 DATACHECK : YES NO YES
010 MIN BLOCKSIZE : 1 1 param No 011
011 MAX BLOCKSIZE : 254 1 254 for
test A
32000 for
test B
018 DATA KIND : 4 0, 1, 3, 4
049 MAX MESSAGE : 10 1 integer

Param No 003 specifies actual station number (if -1, it means all
possible).

1_._3_ _ _ _ _ _ _ _L_o_a_d_ _T_e_s_t_ 1.3

How to load in general, see ref. 1.

TOP80 and the VDC test is loaded and started as described in ref.
2. If testing against RC3502 mirror process is wanted, this can
either be done in the same or other RC3502. If it is wanted to be
done in the same RC3502, a mirror process for a slave VDC is
included when the test is loaded. Otherwise you must load the
second RC3502 with the bootfile BOOTMIR. The second RC3502 is
started in the following way, when loaded:

It will then write:

> mirror
**start of vdc test mirror**
**ver. 81.02.24**

mirror module no.:

When you have filled in a valid no. (10 <_ no < 126), normally 18,
it will write:

>>>mirror process started

if the creation of the slave VDC process was successful else it
will write:

******mirror creation error: error cause******

Up till 10 mirrors could be started, replying to the question.
(Note: That a mirror with a module no. 10 greater or smaller than
one already started could not be started. And that there always
should be a difference of 2 between a new mirror started and one
already existing, due to the controller occupying two interrupt
levels.
\f

F_ 2_._ _ _ _ _ _ _ _ _D_Y_N_A_M_I_C_ _T_E_S_T_ _B_U_F_F_E_R_S_ 2.

With the blocksize parameters an arbitrary databuffer size can be
selected. These buffers are not allocated when the test is init-
iated, but dynamic allocated when the test is started. There is
allocated 32 buffers of the maximum size, 2 transmitbuffers and 2
receivebuffers for each channel.

If the allocation meets limitations in memory, it is tried to
start the test with 1 transmitbuffer and 1 receivebuffer per
channel.

If this also fails the test tries to get buffers with half the
size and so on.

The buffer-allocation can fail in two ways. It finds no buffers
at all, OR it finds to few buffers of the size to have at least 1
transmitbuffer and 1 receivebuffer per channel. In the last case
it is recommendable to restart the test with smaller buffers. In
both cases the test will be terminated.

If the allocation of buffers succeeds the test will write as
follows:

*** maximum test buffer size : 254
*** maximum queue depth for xfer: 2

F_ 3_._ _ _ _ _ _ _ _ _T_E_S_T_ _A_,_ _R_C_3_5_0_2_ _M_I_R_R_O_R_,_ _R_E_L_I_A_B_I_L_I_T_Y_ 3.

Test A is a verification of proper operation of the video display
controller hardware by transferring data/commands between master
and mirror as defined by the circuit protocol, see ref. 3. To
check all controller operations possible, the VDC in test should
be placed in either ends of the circuit line, to test all of its
functions properly.

3_._1_ _ _ _ _ _ _ _T_e_s_t_ _S_t_r_a_t_e_g_y_ 3.1

The VDC test and the mirror process (with a slave VDC connected
in same or other RC3502) are intended to simulate a normal cir-
cuit line with 8 stations. It is the mirror process that handles
the slave VDC in a way, so that it acts as 8 secondary stations.
It is therefore recommended to run the test twice swopping the
VDCs. If this is done, all functions in the VDC are checked by
the test program. In fig. 1 left of the vertical line the con-
cerned processes are shown, right of the line, the hardware is
shown.

The testing starts with a connection phase, where an attempt to
connect the specified number of stations is made. Note that
switch S4 (right) on the VDC must be open (see fig. 2). This
causes the VDC to make longer flags so that the mirror can catch
up with the primary.

In the beginning of the test, it is tried to generate errors with
code (1, 2, 8, 12, 13) (ref. 4 or ref. 5), to check that
these are generated correctly. If this was not the case, an error
with associated error code no. is written. All except error code
13 is generated, when the test places the code no. in the first
byte of the databuffer.
\f

Figure 1: Test A, soft and hard configuration. \f

F_ Left Right

red dot
when S4 left is open the
VDC microprogram will loop in
s1 s2 s3 s4 its init phase.

white
dot

s4 right must be open on
primary when testing

Figure 2: VDC switch setting.

The mirror then performs the wanted action (e.g. when the mirror
receives code 8 for timeout it does not reply within the timeout
limit).

Error code 13 is generated by requesting a receive frame that is
smaller than the transmitted.

If all errors were generated correctly, the test will proceed to
the transfer data part. The first 4 "stations" will repeat their
transfer with an increasing buffersize from minimum size to
maximum size and decreasing back to minimum size (the growth is
one byte per transfer). The last 4 "stations" will repeat their
transfer with decreasing buffersize from maximum size to minimum
size and increasing back to maximum size. This will test the
frame recognition, when scanning the secondaries and use the line
as much as possible.

The data patterns used in the transferred buffers can either be
all zeroes (0), all ones (1) or counting (4). All ones can be
used to check the automatic zero insertion.

Note: That pointers in the data buffer is pointing in the part
that contains datapattern. The two first bytes are reserved for
information to the mirror about errorgeneration. That is why the
maximum blocksize of this subtest is 254 and not 256.
\f

first 4 secondaries

min max min
blocksize blocksize blocksize

last 4 secondaries

max min max
blocksize blocksize blocksize

Figure 3: Blocklength variation during one run.

3_._2_ _ _ _ _ _ _ _E_r_r_o_r_ _M_e_s_s_a_g_e_s_ 3.2

If an error is detected during operation an associated errortext
is written on the output media.

The errortexts associated to the hardware are:

<secondary has unsolited buffer>:
The related secondary has a buffer not yet returned, because of
a line disconnection.

<answer reset during communication>:
The station sent 'Anser Reset' during normal communication.
(code 1).

<reset req, station had short intervention>:
The station sent 'Reset' indicating it wants to be reset (code
2).

<time out in communication with station>:
Time-out, i.e. no response from the station within 10ms. (code
8).
\f

<cannot get access to line for 1 sec>:
Controller cannot get access to line for 1 sec, i.e. carrier
signal persists (code 15).

<CRC-error or abort detected>:
Framing or FCS error (code 15).

<data error, hard error>:
The expected and received patterns is printed.

<data received when not receive ready>:
I-field received when master's RR was 0 (code 12).

<data field too long for buffer>:
Received I-field was too long for buffer (code 13).

<sequence number error, not in synchronism>:
Sequence number in header invalid (code 14).

<error in event code generation>:
The errorcode was of a not expected type.

<underrun because of bustimeout>:
Receiver underrun, buserror (code 10).

<overrun because of bustimeout>:
Transmitter overrun, buserror (code 11).

<Blocklength error>.
The received datablock was not of expected size.

The following three error messages indicate that the concerned
process is not started correctly and proceeding has no meaning.

<fatal error in creation of tps>,
<fatal error in creation of mirror>,
<fatal error in creation of driver>,

F_ 4_._ _ _ _ _ _ _ _ _T_E_S_T_ _B_,_ _C_I_R_C_U_I_T_ _L_I_N_E_,_ _R_E_L_I_A_B_I_L_I_T_Y_ 4.

Test B is a verification of proper operation of the circuit line
with one or more RC850 connected (maximum 8) by transferring
data/commands between master and secondaries as defined by the
circuit protocol, ref. 3. The secondaries must contain the
associated mirror processes to run the test. The function in the
VDC by which it will act as a secondary is not checked when
running this subtest.

4_._1_ _ _ _ _ _ _ _T_e_s_t_ _S_t_r_a_t_e_g_y_ 4.1

This subtest is the same as test "A", except for the fact that it
does not make any attempt to generate error codes as in test "A"
and it is intended to run with maximum 8 RC850s. For further
description see sections 2.1 and 2.2. Fig. 4 shows the processes
concerned and the hardware (example with 4 stations).

It is possible to run this subtest with datapattern 3, which
generates a readable text on screen of the RC850.

The text is:

**VDC TEST IN PROGRESS**

If the buffer is greater than this, the rest will contain the
readable alphabet.
\f

Figure 4: Test B, soft and hard configuration. \f

F_ 5_._ _ _ _ _ _ _ _ _L_O_G_ _B_O_O_K_ 5.

The test contains a log book that can be used to get information
about the 64 internal controller register or a log of the past
(earlier control and interrupt words) from a cyclic buffer of 256
word resident in the driver. The log book is identified by the
name <VDCPRINT<NO>>, where <NO> is the same number identifying
the test.

Commands to <VDCPRINT<NO>> are:

<r> : giving a printout of the 64 internal controller registers.
See ref. 5.

<i> : giving a printout of the 256 words from cyclic buffer in
the controller. Each word is either a controlword or an
interrupt word.

5_._1_ _ _ _ _ _ _ _C_o_n_t_r_o_l_l_e_r_ _R_e_g_i_s_t_e_r_s_ 5.1

The layout of the 64 controller registers could be seen in ref.
5 fig. 3.2.1. It is printed on 16 lines with each line contain-
ing 4 register Pairs, equvalent to the way the registers are used
(one channel occupies 4 registers).
\f

Figure 5: Example of Controller Register output.

5_._2_ _ _ _ _ _ _ _I_n_t_e_r_r_u_p_t_/_C_o_n_t_r_o_l_ _W_o_r_d_s_ 5.2

The 256 words of the cyclic buffer are printed with 8 words per
line. The first printed word is the oldest event. If the buffer
has been filled more than once, a line like the following is
printed

97 mod 256 words lost.

The control words is presented in hexadecimal and must be one of
the controlwords to the controller, ref. 5.

The interrupt words are presented like this

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15

M_m_m_ RR SR SN U X RX RX TX error-event subdevice
P_p_p_ T T T T CHG Data Data

Where bit 12 is set to 1, to be able to differentiate interrupt
words from controlwords. An example of an interrupt word could
look like this: a4 08.
\f

Figure 6: Example of interrupt/control-words.
\f

F_
\f

F_ A_._ _ _ _ _ _ _ _ _R_E_F_E_R_E_N_C_E_S_ A.

1 RCSL No 52-AA988:
PASCAL80 on the RC3502 Computer, How to Use the RC3502

2 RCSL No 30-M280:
RC3502, TOP80, Test Operating System, User's Guide

3 RCSL No 31-D598:
CIRCUIT Protocol, Reference Manual

4 RCSL No 31-D616:
RC3502 VDC201 CIRCUIT Master Driver

5 RCSL No 31-D599:
VDC201/291, Reference Manual

6 RCSL No 31-D637:
VDC201, Technical Manual

7 RCSL No 31-D636:
VDC201/291 General Information
\f

F_ B_._ _ _ _ _ _ _ _ _E_X_A_M_P_L_E_S_ _O_F_ _O_U_T_P_U_T_ B.
\f

F_\f

F_C_._ _ _ _ _ _ _ _ _S_P_E_C_I_A_L_I_T_I_E_S_ C.

The RC850 mirror process will be supplied as PROM (ROA408-ROA409-
ROA410), which must be placed in the terminal(s) before running
test-B.

The driver is started when the test is started and not removed
before the test is killed by TOP. Therefore do not change p002
(module No) without killing the test first.
«eof»

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