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T_A_B_L_E_ _O_F_ _C_O_N_T_E_N_T_S_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _P_A_G_E_
1. INTRODUCTION ........................................... 1
1.1 Configuration Requirements ........................ 1
1.2 Parameter Values .................................. 2
1.3 Load and Start of Test ............................ 2
2. TEST SPECIFICATION ..................................... 3
2.1 Microinstruction Test ............................. 3
2.1.1 Jump ....................................... 3
2.1.2 Not, And, Or, Equal ........................ 4
2.1.3 Case ....................................... 5
2.1.4 Not Equal, Greater, Less ................... 5
2.1.5 Negation ................................... 6
2.1.6 Index ...................................... 6
2.1.7 Retrieve and Store Addressing .............. 6
2.1.8 Combinations of Retrieve and Store ......... 7
2.1.9 Multiplicate, Divide ....................... 8
2.1.10 Set Instructions ........................... 9
2.1.11 Move Dataparts ............................. 10
2.2 W-Register, ALU-Test .............................. 11
3. TERMINATING THE TEST ................................... 13
4. TESTOUTPUT ............................................. 14
4.1 Normal Output ..................................... 14
4.2 Error Output ...................................... 14
5. TURN AROUND TIME ....................................... 16
A_P_P_E_N_D_I_X_:
A. REFERENCES ............................................. 17
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1_._ _ _ _ _ _ _ _ _I_N_T_R_O_D_U_C_T_I_O_N_ 1.
This manual describes the RC3502 CPU reliability test. The test-
program is divided into two different sections, which run con-
secutive.
The first ("A") is the most differentiated. It is testing a large
amount of the microinstructions, except the monitor based in-
structions as SIGNAL, WAIT and PUSH, POP. The strategy of the
test is that no instruction not yet tested will be used for test-
ing others (as far as possible).
The second part ("B") is testing the W-registers which are not
already used, and some selected ALU-functions.
The CPU-test is a testpackage in the RC3502 test system, TOP80,
but it is deviating from the other testpackages, because it can
be started directly by ADAM.
This is done to have as few demands as possible to the capabili-
ties of the system, before running this test.
Although keep in mind still that this is a verification of the
CPU operationability and not a diagnostic test, and should be
regarded as such. Also meaning that though the test contains
routines for writing some readable texts, it could well be the
case that you would not have any hint of an occured error in the
CPU from this test (the principle of go or no-go).
It is written in REAL-TIME PASCAL (RC3502 implementation).
1_._1_ _ _ _ _ _ _ _C_o_n_f_i_g_u_r_a_t_i_o_n_ _R_e_q_u_i_r_e_m_e_n_t_s_ 1.1
A minimum configuration RC3502, consisting of CPU, at least two
memory modules, and a load possibility for the test (e.g. RC8000
connections or TES modules with the testsystem) and a debug con-
sole.
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1_._2_ _ _ _ _ _ _ _P_a_r_a_m_e_t_e_r_ _V_a_l_u_e_s_ 1.2
The test has no selective parameters. Even the number of runs
cannot be selected, meaning that the test will run an arbitrary
number of runs and has no terminating point.
1_._3_ _ _ _ _ _ _ _L_o_a_d_ _a_n_d_ _S_t_a_r_t_ _o_f_ _t_h_e_ _T_e_s_t_ 1.3
How to load in general, see ref. 1. The CPU-test is loaded as
described in ref. 2.
When the test is loaded, it is to be started by the following
commands:
> adam
link cpu
create cpu as cpu size 900
start cpu
No output is generated in the start of the test. See chapter 2
for description of the running test.
It is also possible to start the test by TOP80, the Test Opera-
ting System, if present. This is done by the command:
new/cpu.
which causes the test to be started without any further commands,
just like when started by ADAM.
Observe that it will have no meaning to start more than one in-
carnation of the CPU-test, because this could generate some
error-reactions when more than one test is changing the contents
of the W-registers at the same time.
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F_ 2_._ _ _ _ _ _ _ _ _T_E_S_T_ _S_P_E_C_I_F_I_C_A_T_I_O_N_ 2.
2_._1_ _ _ _ _ _ _ _M_i_c_r_o_i_n_s_t_r_u_c_t_i_o_n_ _T_e_s_t_ 2.1
This part of the testprogram is testing the micro instructions of
the CPU microprogram. Monitor based instructions such as SIGNAL,
WAIT and PUSH, POP are not tested.
In the following, the instructions tested are described with
related mnemonic codes and trace numbers. It is the same codes
and numbers which will be printed on the console if an error is
detected. The mnemonic codes are referring to the same codes of
the LMI-text. The trace numbers are telling, which test-loop went
wrong. They are in the range from 0 to 60.
2_._1_._1_ _ _ _ _ _J_u_m_p_ 2.1.1
Jump on true condition:
mnemonic code: jmzeg
trace No: 1
Do not jump on false condition:
mnemonic code: jmzeq
trace No: 2
Jump on inverted false condition:
mnemonic code: notinstr
trace No: 3
Do not jump on inverted true condition:
mnemonic code: notinstr
trace No: 4
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2_._1_._2_ _ _ _ _ _N_o_t_,_ _A_n_d_,_ _O_r_,_ _E_q_u_a_l_ 2.1.2
Is (NOT false) = true:
mnemonic code: notinstr
trace No: 5
Is (true AND true) = true:
mnemonic code: andinstr
trace No: 6
Is (NOT (true AND false)) = true:
mnemonic code: andinstr
trace No: 7
Is (NOT (false AND true)) = true:
mnemonic code: andinstr
trace No: 8
Is (NOT (false AND false)) = true:
mnemonic code: andinstr
trace No: 9
Is ((true OR true) AND (true OR false) AND (false OR true) AND
(NOT (false OR false))) = true:
mnemonic code: orinstr
trace No: 10
Is a variable earlier assigned to 1, equal 1 and not 0:
mnemonic code: eq
trace No: 11
Is the not equal instruction working on two different variables:
mnemonic code: ne
trace No: 12
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2_._1_._3_ _ _ _ _ _C_a_s_e_ 2.1.3
Testing the case jump instruction with switches from 0 to 3:
mnemonic code: jmcht
trace No: from 13 to 16
2_._1_._4_ _ _ _ _ _N_o_t_ _E_q_u_a_l_,_ _G_r_e_a_t_e_r_,_ _L_e_s_s_ 2.1.4
These instructions are tested on two variables, which will have
all combinations of the following values:
-32768, -32767, -6, -5, -4, -1, 0, 1, 4, 5, 6, 32766, 32767
not equal:
mnemonic code: ne
trace No: 17
greater than or equal:
mnemonic code: ge
trace No: 18
less than:
mnemonic code: lt
trace No: 19
greater than:
mnemonic code: gt
trace No: 20,21
less than or equal:
mnemonic code: le
trace No: 22
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2_._1_._5_ _ _ _ _ _N_e_g_a_t_i_o_n_ 2.1.5
Testing negation of two different variables (0,1):
mnemonic code: neg
trace No: 23
2_._1_._6_ _ _ _ _ _I_n_d_e_x_ 2.1.6
The index instruction is tested by writing indexed in a byte-
layout an checking in an indexed bit-layout bit by bit. The loop
is repeated with different length of the area to be indexed. The
length variates from 2 bytes to 256 bytes.
mnemonic code: index
trace No: 24
2_._1_._7_ _ _ _ _ _R_e_t_r_i_e_v_e_ _a_n_d_ _S_t_o_r_e_ _A_d_d_r_e_s_s_i_n_g_ 2.1.7
The CPU can address the memory with different instructions:
retreive, store local (word):
mnemonic code: revlw
trace No: 25
retreive, store intermidiate (word):
mnemonic code: revsw
trace No: 26
retreive, store intermidiate (word):
mnemonic code: reviw
trace No: 27
Retreive, store global (word):
mnemonic code revgw
trace No: 28
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2_._1_._8_ _ _ _ _ _C_o_m_b_i_n_a_t_i_o_n_s_ _o_f_ _R_e_t_r_i_e_v_e_ _a_n_d_ _S_t_o_r_e_ 2.1.8
It is tested that data stored by either word, byte or field
instructions can be retrieved by either word, byte or field
instructions.
store words, retrieve words:
mnemonic code: stvsw.revsw
trace No: 29
store words, retrieve bytes:
mnemonic code: stvsw.revsb
trace No: 30, 31
store words, retrieve field:
mnemonic code: stvsw.revsf
trace No: 31
store bytes, retrieve words:
mnemonic code: stvsb.revsw
trace No: 32
store bytes, retrieve bytes:
mnemonic code: stvsb.revsb
trace No: 33, 34
store bytes, retrieve field:
mnemonic code: stvsb.revsf
trace No: 34
store field, retrieve words:
mnemonic code: stvsf.revsw
trace No: 35
store field, retrieve bytes:
mnemonic code: stvsf.revsb
trace No: 36, 37
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store field, retrieve field:
mnemonic code: stvsf.revsf
trace No: 37
2_._1_._9_ _ _ _ _ _M_u_l_t_i_p_l_i_c_a_t_e_,_ _D_i_v_i_d_e_ 2.1.9
It is tested that the result of the divide, division remainder
and multiplication instructions is correct when calculated with
different factors.
The expressions tested are:
(i div 5 = q) AND (i div (-5) = -q)
(i mod 5 = r) AND (i mod (-5) = r)
(q * 5+r = i) AND (q * (-5)-r = -i)
where i, q and r has the following values:
_ _ _i_ _ _ _ _ _q_ _ _ _ _ _r_ _ _
-15 -3 0
-14 -2 -4
-13 -2 -3
-12 -2 -2
-11 -2 -1
-10 -2 0
-9 -1 -4
-8 -1 -3
-7 -1 -2
-6 -1 -1
-5 -1 0
-4 0 -4
-3 0 -3
-2 0 -2
-1 0 -1
0 0 0
1 0 1
2 0 2
3 0 3
4 0 4
5 1 0 \f
_ _ _i_ _ _ _ _ _q_ _ _ _ _ _r_ _ _
6 1 1
7 1 2
8 1 3
9 1 4
10 2 0
11 2 1
12 2 2
13 2 3
14 2 4
15 3 0
division:
mnemonic code: divinstr
trace No: 38
remainder of division:
mnemonic code: modinstr
trace No: 39
Multiplication:
mnemonic code: mul
trace No: 40
2_._1_._1_0_ _ _ _ _S_e_t_ _I_n_s_t_r_u_c_t_i_o_n_s_ 2.1.10
It is tested that a variable is member of a set, when it has the
value of one of the members in the set:
mnemonic code: settm
trace No: 41
It is tested that a set which is created can be empty or contains
the expected values within its boundaries:
mnemonic code: setcr
trace No: 42
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It is tested that sets can be adjusted from one number of members
to another.
mnemonic code: setad
trace No: 43
It is tested that adjusted sets can be equal:
mnemonic code: seteq
trace No: 44
Set union is tested:
mnemonic code: setun
trace No: 45
Set intersection is tested
mnemonic code: setinter
trace No: 46
Subsets are tested:
mnemonic code: setsb
trace No: 47
Supersets are tested:
mnemonic code: setsp
trace No: 48
Set difference is tested:
mnemonic code: setdi
trace No: 49
2_._1_._1_1_ _ _ _ _M_o_v_e_ _D_a_t_a_p_a_r_t_s_ 2.1.11
It is tested that the instruction, which moves dataportions from
one area to another, is performed.
Area of tree words is moved:
mnemonic code: moveg
trace No: 50
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Area of tree bytes is moved:
mnemonic code: moveg
trace No: 51
2_._2_ _ _ _ _ _ _ _W_-_R_e_g_i_s_t_e_r_,_ _A_L_U_-_T_e_s_t_ 2.2
This part of the testprogram is testing the W-registers and some
selected ALU-functions. But the first thing which is performed is
that the whole readable set of characters is written on the con-
sole.
The W-register test will, if the test is in the first run, exam-
ine all registers from 0 hex to 3DF hex, to see which is not
already occupied by some interrupt level. The ones occupied will
be listed (all 8 W-registers occupied by one level will not be
tested). It must be noted that the criteria for a not occupied
register are that the contents are all ones, so the list must be
examined to check that only wanted levels are occupied (see ref.
1), and that there are no instant errors. The W-register test
first performs a loop of 64 times of address test and then a loop
of 64 times of data test. The data pattern is either AAAA hex or
5555 hex every second time. If an error occurs, a message will be
written on the console telling about the read and expected
values. After these loops the registers are reset to all ones.
The ALU is tested to be able to do the following selected
functions:
Addition of logical one:
mnemonic code: loc 0
trace No: 56
The carry shift from slice with bit 12-15 to slice with bit 8-11:
mnemonic code: carry
trace No: 57
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The carry shift from slice with bit 8-11 to slice with bit 4-7:
mnemonic code: carry
trace No: 58
The carry shift from slice with bit 4-7 to slice with bit 0-3:
mnemonic code: carry
trace No: 59
All tree slice carries shifted at the same time:
mnemonic code: carry
trace No: 60
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F_ 3_._ _ _ _ _ _ _ _ _T_E_R_M_I_N_A_T_I_N_G_ _T_H_E_ _T_E_S_T_ 3.
When once started, the test will run forever. Each time a run
number is written on the console the test is completed.
When a termination is wanted, it must be done by addressing ADAM,
if he is the one that has started the test.
> adam
stop cpu
remove cpu
or demanding TOP to kill the test, if the test is a child of TOP.
N_o_t_e_: The only valid TOP-commands in relation with the CPU-test
are
new/cpu: starting the test,
kill/cpu: removing the test.
There will not be generated an errorstatistic as for other tests.
These specialities of the CPU-test are because of the need of
simplicity of the test.
It is recomendable to stop the test outside the phase where it
tests the W-registers, so that the not used registers will con-
tain all ones. This means that the test is to be stopped before
it writes the character set on the console or after the run num-
ber is written. Also do not start any device-test while the CPU-
test is running because it changes the registers used by the
interrupt levels.
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F_ 4_._ _ _ _ _ _ _ _ _T_E_S_T_O_U_T_P_U_T_ 4.
4_._1_ _ _ _ _ _ _ _N_o_r_m_a_l_ _O_u_t_p_u_t_ 4.1
When the test is running in a CPU with no failures, it will gene-
rate an output like the following:
The output "occupied level" is telling about which register sets
of 8 registers are used by an interrupt level (contents of at
least one of the 8 registers are different from all ones).
4_._2_ _ _ _ _ _ _ _E_r_r_o_r_ _O_u_t_p_u_t_ 4.2
The test has two different kinds of error-output.
The one is telling about an instruction or a function that gene-
rated a wrong result.
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The other is telling about a failure in the test of the W-re-
gisters in either the address or data test. Received, expected
and address is written in hexadecimal notation.
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F_ 5_._ _ _ _ _ _ _ _ _T_U_R_N_ _A_R_O_U_N_D_ _T_I_M_E_ 5.
The specified times are the approximate turn around times for
each part of the CPU-test run in the RC3502 computer without any
other test running at the same time.
SUBTEST TURN AROUND TIME
micro instruction test 2 min 05 s.
W-register, ALU-test 1 min 20 s.
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F_ A_._ _ _ _ _ _ _ _ _R_E_F_E_R_E_N_C_E_S_ A.
1 RCSL No 52-AA988:
PASCAL80 on the RC3502 Computer,
How to Use the RC3502
2 RCSL No 30-M280:
RC3502, TOP80, Test Operating System,
User's Guide
3 RCSL No 52-AA1010:
Technical Manual for CPU201/202
4 RCSL No 52-AA1011:
Debug Console Program for RC3502 Minicomputer
5 Microprogram/LMI-txt for RC3502
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