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└─⟦53be6501e⟧ Bits:30005867/disk02.imd Dokumenter (RCSL m.m.)
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\f
RC 3603 CPU
Programmer's reference manual
Second edition
A/S REGNECENTRALEN January 1979
Information Department RCSL 52-AA705\f
Author: Jens Lovmand Hvid
Technical Editor: Knud Erik Hansen
KEY WORDS: RC 3603, CPU 708, Revision 1.
ABSTRACT: This paper describes the logical structure of the
RC 3603 Central Processor Unit.
SUPPORTING AND REFERENCED DOCUMENTS:
Reservation
Copyright A/S Regnecentralen, 1978
Printed by A/S Regnecentralen, Copenhagen\f
CONTENTS Section
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ ______________________________________________
RC 3603 SPECIFICATIONS..................................1
Central Processor Unit .............................1.1
Memory .............................................1.2
Input/Output .......................................1.3
Interrupt Capability ...............................1.4
Data Channel .......................................1.5
Power Fail/Auto Restart ............................1.6
Real Time Clock ....................................1.7
Diagnostic Front Panel .............................1.8
INTERNAL CONFIGURATION ..................................2
Introduction.......................................2.1
Program Structure ..................................2.2
Program Execution .............................2.2.1
Program Flow Alteration .......................2.2.2
Program Size ..................................2.2.3
Program Flow Interruption .....................2.2.4
Information Formats ................................2.3
Fundamental Concepts...........................2.3.1
Bit Numbering .................................2.3.2
Binary Representation .........................2.3.3
Octal Representation ..........................2.3.4
Hexadecimal Notation ..........................2.3.5
Numerical Quantities ...............................2.4
Integers ......................................2.4.1
Logical Quantities ............................2.4.2
Addressing .........................................2.5
Word Addressing ...............................2.5.1
Page Zero Addressing .......................2.5.1.1
Relative Addressing ........................2.5.1.2
Index Register Addressing ..................2.5.1.3
Indirect Addressing ........................2.5.1.4
Auto Locations .............................2.5.1.5
Byte Addressing ...............................2.5.2
INSTRUCTIONS ............................................3
Introduction .......................................3.1
Instruction Formats ................................3.2
Mnemonic Description ...............................3.3
Program Flow Control................................3.4
JUMP ..........................................3.4.1
JUMP TO SUBROUTINE ............................3.4.2
INCREMENT AND SKIP IF ZERO ....................3.4.3 \f
DECREMENT AND SKIP IF ZERO ....................3.4.4
Data Transfer Operations ...........................3.5
LOAD ACCUMULATOR ..............................3.5.1
STORE ACCUMULATOR .............................3.5.2
Integer Arithmetic and Logical Operations ..........3.6
ADD ...........................................3.6.1
SUBTRACT ......................................3.6.2
NEGATE ........................................3.6.3
ADD COMPLEMENT ................................3.6.4
MOVE ..........................................3.6.5
INCREMENT .....................................3.6.6
COMPLEMENT ....................................3.6.7
AND ...........................................3.6.8
Examples ......................................3.6.9
Deciding the sign of a number ..............3.6.9.1
Dividing a number by a power of two ........3.6.9.2
Changing locations and inverting the order..3.6.9.3
INPUT/OUTPUT ............................................4
Introduction .......................................4.1
Operation of Input/Output Devices ..................4.2
Interrupt System ...................................4.3
Priority Interrupts ................................4.4
Direct Memory Access Data Channel ..................4.5
Input/Output Instructions ..........................4.6
DATA IN A .....................................4.6.1
DATA IN B .....................................4.6.2
DATA IN C .....................................4.6.3
DATA OUT A ....................................4.6.4
DATA OUT B ....................................4.6.5
DATA OUT C ....................................4.6.6
I/O SKIP ......................................4.6.7
NO I/O TRANSFER ...............................4.6.8
Central Processor Functions ........................4.7
INTERRUPT ENABLE ..............................4.7.1
INTERRUPT DISABLE .............................4.7.2
READ SWITCHES .................................4.7.3
INTERRUPT ACKNOWLEDGE .........................4.7.4
MASK OUT ......................................4.7.5
I/O RESET .....................................4.7.6
HALT ..........................................4.7.7
CPU SKIP ......................................4.7.8
PROCESSOR FEATURES ......................................5
Introduction .......................................5.1
Power Fail .........................................5.2 \f
Memory Extension ...................................5.3
PROCESSOR OPTIONS .......................................6
Real Time Clock ....................................6.1
Teletype Controller ................................6.2
Instructions ..................................6.2.1
READ CHARACTER BUFFER ......................6.2.1.1
LOAD CHARACTER BUFFER ......................6.2.1.2
Programming ...................................6.2.2
Input ......................................6.2.2.1
Output .....................................6.2.2.2
Programming Examples ..........................6.2.3
PROGRAMMING LOADING .....................................7
Introduction .......................................7.1
Automatic Loading ..................................7.2
SWITCHES AND INDICATORS .................................8
Switches ...........................................8.1
ENABLE TCP ....................................8.1.1
AUTOLOAD DEVICE SELECT ........................8.1.2
PARITY ERROR ..................................8.1.3
MEMORY EXTENSION SELECT .......................8.1.4
Indicators .........................................8.2
PARITY ERROR ..................................8.2.1
CPU-STATUS ....................................8.2.2
APPENDICES:
I/O DEVICE CODES AND MNEMONICS ............Appendix A
ASCII CHARACTER CODES .....................Appendix B
DOUBLE PRECISION ARITHMETIC ...............Appendix C
INSTRUCTION USE, EXAMPLES .................Appendix D
INSTRUCTION EXECUTION TIMES ...............Appendix E
F_\f
1 R_C_ _3_6_0_3_ _S_P_E_C_I_F_I_C_A_T_I_O_N_S_
1.1 C_e_n_t_r_a_l_ _P_r_o_c_e_s_s_o_r_ _U_n_i_t_
The RC 3603 Central Processor Unit is a micro-programmed,
general purpose stored-program computer with four accumulators.
The CPU works on the basis of a unit of information called a
word which consists of 16 bits. Arithmetic and logical
operations are performed on operands held in the accumulators,
which consequently also are 16 bits in length. Two of the
accumulators can be used as index registers for addressing
purposes.
T_ 1.2 M_e_m_o_r_y_
The main memory is available in two alternative modules:
&_ RC 3608 is a core memory with a capacity of 32K words and a
cycle time of 750 ns.
RC 3609 is a core memory with a capacity of 16K words and a
cycle timeof 650 ns.
The CPU can directly address 32K words of core memory and
provides for base page, relative, indexed and multi-level
indirect addressing modes. By the use of a special instruction
the CPU can be switched to a mode which will allow it to work
with up to 64K words of core memory.
Word length in memory is 16 + 2 = 18 bits. The two extra bits
are parity check bits. They are generated during each memory
write cycle and are checked during each memory read cycle. The
detection of a parity error can affect the operation of the CPU
in two alternative ways: the error can be indicated on the front
frame of the CPU board while processing continues uninterrupted
or processing can be brought to a halt. The selection of either
possibility is left to the operator's choice by means of a
switch also located on the CPU frame.
\f
T_ 1.3 I_n_p_u_t_/_O_u_t_p_u_t_
All peripheral devices are connected to the CPU through the
Input/Output bus. This consists of a six-line device selection
&_ network, interrupt circuitry, command circuitry and sixteen data
transmission lines. Each individual Input/Output device has a
unique six-bit device code and will only respond to commands if
its own device code is transmitted through the device selection
network of the Input/Output bus.
The six bits in the device code allows for 64 separate codes. A
number of these codes are reserved for specific uses, but the
remaining codes makes it possible to obtain an extremely
flexible handling of Input/Output devices.
T_ 1.4 I_n_t_e_r_r_u_p_t_ _C_a_p_a_b_i_l_i_t_y_
The interrupt circuitry included in the Input/Output bus
provides the capability for any peripheral device to interrupt
&_ normal program execution whenever the device is in need of
attention. When a peripheral device has requested an interrupt
the processor will transfer control of operations to the main
interrupt service routine, which will handle the servicing of
the device. The interrupt service routine will establish the
source of the interrupt either by polling all Input/Output
devices connected to the CPU or it can use a special instruction
to identify the device in question.
The interrupt system also provides the capability of
implementing up to sixteen levels of priority in connection with
interrupts, so that each individual peripheral device is
associated with a specific priority level. A standard priority
assignment is implemented by Regnecentralen, but the programmer
can change these assignments according to his own choice.
T_ 1.5 D_a_t_a_ _C_h_a_n_n_e_l_
Data transfers between peripheral devices and main memory under
program control occupies processor time and retards the rate of
&_ information transfer.
To avoid this restriction the Input/Output bus contains
circuitry allowing high-speed access direct to memory through
the data channel, this permits a peripheral device to transfer\f
data directly into/out of memory using a minimum of processor
time. At the maximum transfer rate the data channel effectively
stops the processor, but at lower rates processing continues
while the data transfer takes place.
T_ 1.6 P_o_w_e_r_ _F_a_i_l_/_A_u_t_o_ _R_e_s_t_a_r_t_
The RC 3603 computer incorporates a feature providing for
automatic restart in the event of an unexpected power loss. The
&_ delay between the initial decrease of voltage and the actual
automatic shut-down of the processor is utilized to bring the
interrupt service routine into action. This routine will under
these circumstances use the available interval of time to store
the contents of accumulators, the program restart address and
other information that will be necessary for restart and
continued operation when the power supply again has been
restored.
The Power Fail feature is entirely automatic and will restart
operations on its own whenever power is again available.
T_ 1.7 R_e_a_l_ _T_i_m_e_ _C_l_o_c_k_
A Real Time Clock can optionally be included in the RC 3603
computer. This clock will generate a train of pulses
independently of processor timing, this will allow the interrupt
&_ system to be activated at precisely spaced intervals of time.
The pulse train frequency can be selected by the programmer
among the following four possibilities: 10 Hz, 50 Hz, 100 Hz and
1000 Hz.
T_ 1.8 D_i_a_g_n_o_s_t_i_c_ _F_r_o_n_t_ _P_a_n_e_l_
A Diagnostic Front Panel can be connected to the CPU even during
&_ program execution. This will allow external, manual control of
the CPU and will thus facilitate error detection and correction.
The Diagnostic Front Panel is not described in detail in this
manual, for further information concerning this consult the
Reference Manual for the Diagnostic Front Panel - RCSL 52-AA542.
F_\f
2 I_N_T_E_R_N_A_L_ _C_O_N_F_I_G_U_R_A_T_I_O_N_
2.1 I_n_t_r_o_d_u_c_t_i_o_n_
This chapter and the following deals in some detail with the
basic concepts underlying the actual modus operandi of the RC
3603 CPU. A more intimate knowledge of this subject is not
strictly necessary for ordinary everyday use of the computer,
because the high-level programming languages available are
designed to allow symbolic programs to be written without
reference to the more specific information contained in this
manual. Thus the intention is not to establish guidelines for
actual programming, for which purpose separate manuals are
available, but to provide a source of background information for
the programmer and/or operator.
T_ 2.2 P_r_o_g_r_a_m_ _S_t_r_u_c_t_u_r_e_
Information about the type of operation - arithmetical or other
- which the computer at any particular time must perform, is
&_ given to the CPU in the shape of an "instruction". The CPU will
carry out successive instructions in strict sequence according
to the order in which the instructions have been specified. The
complete set of instructions is called a "program" and this must
at the time of execution reside in main memory in order to be
accessible to the CPU.
T_ 2.2.1 P_r_o_g_r_a_m_ _E_x_e_c_u_t_i_o_n_
Each individual instruction occupies a space in memory called a
"word" and although these words will usually occupy adjacent
&_ physical locations in memory, the program may incorporate
instructions with the specific purpose of altering the sequence
in which the instructions should be carried out.
Thus the CPU must be able to locate the correct word at the
correct point in the sequence in order to execute the program
properly. The actual physical location of a word is called its
"address" and consequently the establishing of location is
called "addressing".
Addressing the instructions is arranged by incorporating a
counting circuit called the "program counter". The program\f
counter contains one integer number, which always indicates the
memory address of the instruction currently being carried out.
When the operation specified by that particular instruction has
been completed, the number in the program counter is incremented
by one and the CPU will then retrieve the next instruction to be
carried out from the memory location now being indicated by the
number in the program counter. Succeeding addresses will thus
form a strictly ascending numerical sequence and this method of
operation is consequently called "sequential operation".
T_ 2.2.2 P_r_o_g_r_a_m_ _F_l_o_w_ _A_l_t_e_r_a_t_i_o_n_
The programmer can however purposely arrange to deviate from the
strict sequential operation. This is done by using the
&_ appropriate program flow control instructions which will make it
possible to achieve two distinctly different types of program
flow variation.
The "jump" type instruction will cause an arbitrary new number -
either larger or smaller than the current one - to be inserted
in the program counter. Thus when the jump instruction has been
executed, the next instruction to be located can have any of all
the possible addresses.
The "conditional skip" type instruction will first determine
whether a specified test condition is true or not. If true, it
will then cause the program counter to be increased by one, if
false, nothing further will be done. When the conditional skip
instruction has been executed, the program counter will be
increased by one as in the usual sequential operation and thus
the next instruction to be located will have either of the two
following addresses depending on the outcome of the test. Normal
sequential operation will be resumed after the completion of
either type of instruction - using the updated value of the
program counter - and will continue until the next program flow
alteration occurs. An illustration showing the two types of
program flow alteration appears on the following page.
Fig. 2.2.2. \f
T_ Fig. 2.2.2
SEQUENTIAL
PROGRAM
FLOW
INCREASING
ADDRESSES
I JUMP
N PROGRAM
S FLOW
T
R
U
C
T
I SKIP
O PROGRAM
N FLOW
S
T_ 2.2.3 P_r_o_g_r_a_m_ _S_i_z_e_
The integer number contained in the program counter will have a
magnitude between 0 and 32, 767 (both included) and will thus
&_ make it possible to address 32,768 separate memory locations
which is then the maximum program size. The program need not
necessarily start in memory location 0, but if the program
counter reaches the value 32,767 the next incrementation will
produce the value 0 and sequential operation will then continue
from here as previously explained. Notice should be taken of the
fact, that no indication whatsoever of this particular situation
will be given.
N_O_T_E_: The proceeding outlined above will change if Memory
Extension has been selected (cf. Section 5.3).
T_ 2.2.4 P_r_o_g_r_a_m_ _F_l_o_w_ _I_n_t_e_r_r_u_p_t_i_o_n_
During the normal running of a program a variety of situations
may arise which will make it necessary to interrupt the normal
&_ program flow, i.e. to stop ordinary processing temporarily. This
may be due to either quite normal occurrences - for instance the
necessity of performing an Input/Output operation - or it may be\f
due to exceptional occurrences - external or internal faults or
malfunctions.
In both cases the address of the next sequential instruction is
saved by the CPU while the interrupt condition lasts. On
termination of the interrupt condition the address saved by the
CPU is placed in the program counter anew and the interrupted
program resumes operation at the correct point in the sequence.
An illustration showing this variation in program flow appears
below. Fig. 2.2.4.
T_
SEQUENTIAL
PROGRAM
FLOW
INCREASING I/O
ADDRESSES INTERRUPT
I OCCURS
N
S
T JUMP
R
U
C
T SKIP
I
O
N CONTINUED
S PROGRAMRETURN
FLOW
Fig. 2.2.4
&_
T_ 2.3 I_n_f_o_r_m_a_t_i_o_n_ _F_o_r_m_a_t_s_
In any computer information is basically represented by some
&_ physical quantity - usually electric current or magnetism. The
actual nature of this quantity as well as its magnitude carries
no importance with respect to use of the computer; the important\f
property is that the relevant quantity can either be present or
not present.
T_ 2.3.1 F_u_n_d_a_m_e_n_t_a_l_ _C_o_n_c_e_p_t_s_
The two possible - but mutually exclusive - states as mentioned
&_ above form the basis for all considerations of information
processing. The two states are normally indicated by the
numerals 0 (zero) and 1 (one) and the nucleus of information
thus represented is called a "binary digit" - usually shortened
to "bit".
In the RC 3603 computer the standard unit of information is
however the "word", which is a string of 16 individual bits. As
each bit can attain either of two different states, the string
of 16 bits can represent 2UU16DD = 65,536 different pieces
of information, for instance the integer numbers from 0 up to
65,535. It should here be noted, that although the wellknown
mathematical symbolism - i.e. numbers - is often used to
describe the information content of a word (or a part of a
word), this is in reality only a matter of convenience and does
not restrict the actual meaning of the information to this
particular subject; nor does it restrict the use to which it may
be put. Although the word is the standard unit of information
handled by the RC 3603 computer it can at times be convenient to
subdivide a word into two parts of 8 bits each. Such a half-word
is called a "byte" and is capable of representing 2UU8DD = 256
different pieces of information.
T_2.3.2 B_i_t_ _N_u_m_b_e_r_i_n_g_
When considering the information contained in bytes or words it
is convenient to establish a definite method of referencing the
&_ individual bits of the byte or word. This is done simply by
ordinary numbering of the bits within the word or byte.
The numbering always proceeds from left to right, i.e. the
leftmost bit in a word is bit 0 while the rightmost bit in a
word is bit 15. Similarly the leftmost bit in a byte is bit 0
while the rightmost bit in a byte is bit 7. Notice that the
numbering always starts with bit 0.
The convention adopted here is illustrated in the figure which
appears on the following page. Fig. 2.3.2. \f
T_
WORD WORD
BYTE BYTE BYTE BYTE
0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
Fig. 2.3.2
&_
It should also be noted that the adoption of this convention
means, that if for instance the word contains a number then the
highest-order digit will have the lowest bit number while the
lowest-order digit will have the highest bit number.
T_ 2.3.3 B_i_n_a_r_y_ _R_e_p_r_e_s_e_n_t_a_t_i_o_n_
If the conventional mathematical notation is adopted by using
&_ the numerical values 0 and 1 to indicate the two possible states
of the bit, then a word will be read simply as an ordinary
16-digit number - although the number will be written in
somewhat unusual manner which in mathematics is called "binary
notation".
From our everyday lives we are accustomed to use of numbers in
very many contexts; take for instance an arbitrary number like
315. The important feature of a number like this is that the
actual value of the individual digit depends on its p_o_s_i_t_i_o_n_ in
the written number. In effect the way the number is written is
just a convenient short-hand way of indicating the magnitude:
3 x 100 + 1 x 10 + 5 x 1 = 3 x 10UU2DD + 1 x 10UU1DD + 5 x 10UU0DD.
This is called "decimal notation" or "base 10" representation
because successive digit positions in the number form a sequence
of increasing powers of 10.
To indicate that a number is written in base 10 representation a
subscript is used whenever there exists a possibility of
confusion:
315DD10UU.
It is obvious that decimal notation will require ten different
symbols to indicate the possible values of the individual
digits, namely the symbols: 0, 1, 2, 3, 4, 5, 6, 7, 8 and 9.
Binary notation - or base 2 representation - is in exactly the
same way a positional system, the only difference being that in
this case successive positions in the number form a sequence of\f
powers of 2. Whereas base 10 representation required ten
different symbols for the individual digits base 2
representation will only require two different symbols, namely 0
and 1; this is of course the reason for its dominant position in
all aspects of computer technology.
A binary number can of course be used to indicate any magnitude
just as well as a decimal number; consequently a binary number
can always be converted to the equivalent decimal number and
vice versa. Thus:
100111011DD2UU =
1 x 2UU8DD + 0 x 2UU7DD + 0 x 2UU6DD + 1 x 2UU5DD + 1 x 2UU4DD + 1 x 2UU3DD +
0 x 2UU2DD + 1 x 2UU1DD + 1 x 2UU0DD =
1 x 256DD10UU + 0 x 128DD10UU + 0 x 64DD10UU + 1 x 32DD10UU + 1 x 16DD10UU +
1 x 8DD10UU + 0 x 4DD10UU + 1 x 2DD10UU + 1 x 1DD10UU =
256DD10UU + 32DD10UU + 16DD10UU + 8DD10UU + 2DD10UU+ 1DD10UU =
315DD10UU.
T_ 2.3.4 O_c_t_a_l_ _R_e_p_r_e_s_e_n_t_a_t_i_o_n_
Internally the CPU will only recognize information given in base
2 representation, but from the example given above it will be
&_ clear that the simplicity of binary numbers, owing to the
limited number of different symbols used, is counteracted by the
necessity of using more digit positions to indicate any given
magnitude, i.e. binary numbers tend to become rather long and
unwieldy.
Extensive application of binary notation in a manual like this
can therefore be somewhat awkward and might even lead to
confusion. It cannot be completely avoided, but very often
numerical representation to yet another base is used instead.
Noting that a three-digit binary number can represent numerical
values from 000DD2UU = 0DD10UU to 111DD2UU = 7DD10UU
it is easily realised, that each group of three bits can
be uniquely represented by the eight digits 0, 1, 2,....6 and 7.
Therefore the use of a representation to base 8 - so-called
octal notation - will retain the basic structure of the binary\f
format, but it will on the other hand only require one third of
the positional places needed in pure binary notation.
Expressing the example used on the preceding page in octal
notation will yield:
315DD10UU = 100111011DD2UU = 473DD8UU.
Thus by dividing any string of bits into groups of three and
using octal notation a fairly compact and convenient
representation is achieved. The subdivision of the string always
starts with the rightmost group of three bits and proceeds
towards the left. If the number of places in the binary number
is not divisible by three the leftmost group will contain only
one or two bits. This is however of no particular consequence:
conversion to octal notation will take place as outlined above
on the additional assumption that the leftmost group is
filled-up to three digits by prefixing the necessary one or two
zeroes.
T_ 2.3.5 H_e_x_a_d_e_c_i_m_a_l_ _N_o_t_a_t_i_o_n_
In some cases still another base is used to represent binary
information, namely base 16 - also called hexadecimal notation
&_ ("hex"). Just as in the case of octal notation the binary number
is formed into groups, but now each group will consist of four
bits. These four bits can express the numerical values from
0000DD2UU = 0DD10UU to 1111DD2UU = 15DD10UU, and in "hex" it will
consequently be necessary to use sixteen individually different
symbols for the digits. The numerals from 0 to 9 are of course
still used to represent their usual values, whereas the values
from 10DD10UU to 15DD10UU will be represented by the initial six
letters of the alphabet: A to F. The example previously used
will then yield:
315DD10UU = 100111011DD2UU = 473DD8UU = 13BDD16UU.
T_2.4 N_u_m_e_r_i_c_a_l_ _Q_u_a_n_t_i_t_i_e_s_
The CPU does not intrinsically recognize one type of information
as being different from another, but it is quite obvious that in
&_ terms of application of the computer numerical quantities do
appear in the majority of situations. Numerical quantities
basically accepted by the CPU can be either integers or logical
quantities.
\f
T_ 2.4.1 I_n_t_e_g_e_r_s_
Operations on integer quantities can be performed on signed or
unsigned binary numbers, which may be carried by the CPU in
&_ either single or multiple precision. Single precision integers
are two bytes long (16 bits), while multiple precision integers
are four or more bytes long.
Unsigned integers use all available bits to represent the
magnitude of the number; thus an unsigned, single precision
integer can range in value from 0DD10UU to 65,535DD10UU (2UU16DD - 1)
corresponding to the sixteen bits available. Similarly two words
taken together as an unsigned, double precision integer can
range in value from 0DD10UU to 4,294,967,295DD10UU (2UU32DD - 1)
corresponding to the thirtytwo bits available. Signed integers
use bits 1 to 15 to represent the magnitude of the number while
bit 0 is reserved for use a sign bit. The aforesaid assumes
single precision; if multiple precision is employed the first
(leftmost) word will be structured in this same way while the
following word(s) will use all available bits to represent
numerical information.
For positive numbers the sign bit is 0 and the remaining bits
represent the magnitude of the number in standard binary
notation as explained above.
For negative numbers the sign bit is 1 and the remaining bits
represent the magnitude of the number in complemented binary
notation (also called two's complement form).
Complementing a number - whether in decimal, binary or any other
notation - simply means writing the negative number as the sum
of two numbers: a large negative number which is a power of the
base plus that positive number which will yield the original
number when added to the large negative one. For instance in
decimal notation:
- 315 = - 1,000,000,000 + 999,999,685.
The advantage of this form is that when working within a set
number of digit positions, the large negative number will
"vanish" - leaving simply a row of zeroes.
To produce the complement - "mechanically" speaking - of a
decimal number just subtract the individual digit from 9 to give
the digit value of the complement - and then finally add 1 to
the last digit. In exactly the same way binary complements are
produced by subtracting the individual digit from 1 and then
adding 1 to the last (rightmost) digit. \f
Thus:
T_ 315DD10UU = 0 000 000 100 111 011
1 111 111 011 000 100 - complementation
+______________________1_
- 315DD10UU = 1 111 111 011 000 101
&_
Note that the complementation of a negative number will of
course produce the positive of that number.
Complementing zero will produce a carry out of the leftmost bit
and leave the number again as zero:
0 000 000 000 000 000 - zero
1 111 111 111 111 111 - complementation
+_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _1_
0 000 000 000 000 000 - zero
Note that zero is a positive number!
As shown above complementation of zero will again produce zero
and there will thus always be one more negative number than
there are non-negative numbers within the given range of digit
positions. The numerically largest negative number is a number
with the sign bit 1 and all remaining bits 0. The positive value
of this number cannot be represented in the same number of
digit positions as used to represent the negative number.
Thus a single precision signed integer can lie in the range from
- 32,768 to + 32,767 while a double precision signed integer can
lie in the range from - 2,147,483,648 to + 2,147,483,647.
Note that addition and subtraction of signed numbers in two's
complement form is identical to the same operations on unsigned
numbers; the CPU just treats the sign bit as the most
significant (highest-order) magnitude bit.
T_ 2.4.2 L_o_g_i_c_a_l_ _Q_u_a_n_t_i_t_i_e_s_
Operations on logical quantities can be performed on individual
bits, bytes or words. In all cases the quantities operated on
&_ are treated as simple un-structured binary quantities. The
logical value "true" is represented by 1 while the logical value
"false" is represented by 0. Two logical quantities are
identical if and only if they have identical values in
corresponding bit positions. \f
The number of bits, bytes or words operated on will depend on
the instruction actually being used.
T_ 2.5 A_d_d_r_e_s_s_i_n_g_
It has already been mentioned in the section "Program Execution"
(section 2.2.1) that the CPU must be able to locate the
instructions stored in main memory. Similarly the CPU must be
able to locate the data involved in the operation to be
performed - the address of which data will usually be indicated
in the instruction.
T_ 2.5.1 W_o_r_d_ _A_d_d_r_e_s_s_i_n_g_
Main memory is subdivided into a number of words - the actual
magnitude of which depends on the CPU configuration actually
&_ being employed. Every single word in memory has a definite
address, which is given as a number: the first word in memory
has the address 0, the next word has the address 1, the next
word has the address 2 and so on. It will be recalled that the
address of the instruction currently in effect is held in the
one-word program counter during the execution of a program. The
instruction itself must contain information about the address of
data to be used during the execution of that particular
instruction.
In contrast to the address held in the program counter the
address information contained in the instruction will not always
directly specify the necessary address but may form the basis
for a calculation whose result will be the desired address. This
calculation is called "effective address calculation" and the
result of this is the "effective address".
The six instructions which directly reference memory in this way
use eleven bits of the word containing the instruction for
effective address calculation. The format of these six
instructions is shown below:
T_
IN-
Æ DEX DISPLACEMENT
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
&_
The eleven bits concerned are bits 5 to 15; of these bit 5 is\f
called the indirect bit, bits 6 and 7 are called the index bits
and the remaining eight bits (bits 8 to 15) are called the
displacement bits.
There are four essentially different modes of effective
address calculation available:
T_ 2.5.1.1 P_a_g_e_ _Z_e_r_o_ _A_d_d_r_e_s_s_i_n_g_. Page zero addressing is indicated by the
index bits being 00. Then the displacement bits are taken as an
&_ ordinary unsigned integer number indicating directly the
effective address. An 8-bit number will lie in the range from 0
to 255DD10UU; this first block of 256DD10UU words in
memory, which can be addressed directly in this way, is known as
page zero.
T_ 2.5.1.2 R_e_l_a_t_i_v_e_ _A_d_d_r_e_s_s_i_n_g_. Relative addressing is signified by the
index bits being 01. In this case the displacement bits are
taken as a signed, two's complement integer number. This number
&_ is added to the address - contained in the program counter - of
the instruction currently in effect; the result of the addition
is the effective address. By this means the effective address
can be any address in memory accessible to the program as it is
defined relative to the address of the instruction. A signed
8-bit number will lie in the range from -128DD10UU to
+127DD10UU and relative addressing therefore gives access to
a block of 256DD10UU words distributed evenly on either side
of the instruction.
T_ 2.5.1.3 I_n_d_e_x_ _R_e_g_i_s_t_e_r_ _A_d_d_r_e_s_s_i_n_g_. Index register addressing is
signified by the index bits being either 10 or 11. If they are
&_ 10 then accumulator 2 is used as an index register; if they are
11 then accumulator 3 is similarly used.
In both cases the displacement bits are taken as a signed, two's
complement integer number; this number is added to the number
contained in the accumulator indicated by the choice of index
bits. The result of the addition is the effective address.
N_O_T_E_: The addition performed in relative and index register
addressing is clipped to 15 bits, i.e. the high-order
bit (bit 0) of the resulting address is set to 0. For
example: if the displacement bits are 01 001 111 and
(in relative addressing) the program counter stands at
111 111 110 101 011, then the addition should produce
the result: 1 000 000 000 011 010, but bit 0 will be
set to 0 so that the result reads:
0 000 000 000 011010. \f
If however Memory Extension has been selectedthe
procedure outlined in this note will not apply(for
further details see section 5.3).
When index register addressing is used the addition of the
displacement to the number contained in the accumulator does not
change the value contained in the accumulator.
T_ 2.5.1.4 I_n_d_i_r_e_c_t_ _A_d_d_r_e_s_s_i_n_g_. While discussing the three addressing modes
hitherto covered it has been tacitly assumed, that the indirect
&_ bit (bit 5) of the instruction was 0, since only then will the
result of the address calculation be the effective address.
If the indirect bit is 1 then the word addressed by either of
the three previously mentioned address calculations is expected
in itself to contain an address (level 1 indirection). The word
concerned will of course contain the usual 16 bits of which now
bit 0 will be the indirect bit and bits 1 to 15 will contain the
address proper.
If now the indirect bit in the level 1 indirection address is 0
then the address contained in bits 1 to 15 is assumed to be the
effective address, but if the indirect bit is 1 then the level 1
indirection address is again expected to contain a further
address (level 2 indirection). This procedure will then be
repeated until an address is eventually retrieved where bit 0 is
0 and bits 1 to 15 consequently will be taken to be theeffec-
tive address.
It should be noted that there is no limit to the levels of
indirection accepted by the CPU. Neither is there any indication
if the chain of indirect addresses due to an error should form a
closed loop thus continuing indefinitely.
N_O_T_E_: Indirect addressing c_a_n_n_o_t_ be used to address the
extended memory area, as locations there will have
addresses in the range from 100000DD8UU to
177777DD8UU - i.e. bit 0 of addresses in this
range will always be 1. Consequently the indirection
chain will continue if that addressing mode is
attempted in this area.
T_ 2.5.1.5 A_u_t_o_ _L_o_c_a_t_i_o_n_s_. Two areas of main memory are reserved for
special addressing purposes.
&_ Locations in the range from 20DD8UU to 27DD8UU are
auto-increment locations, which means that if an indirect\f
addressing chain references an address in this range then the
word in that location will be retrieved, the number contained in
the word will be incremented by one and this will then be
written back into the location. The updated value is then used
to continue the chain of indirect addresses.
Locations in the range from 30DD8UU to 37DD8UU are
auto-drecrement locations. Exactly the same procedure as
outlined above applies here except that the contents of the
location will be decremented instead of incremented.
N_O_T_E_: When auto-increment or auto- decrement locations are
referenced in an indirection chain the state of bit 0
b_e_f_o_r_e_ the incrementation or decrementation will be
condition determining the continuation of the chain.
For example: if an auto-increment location containing
the number 177777DD8UU is referenced during an
indirection chain then the next address in the chain
will be location 000000DD8UU - and it will be
assumed that this location in itself will contain an
address due to the fact, that the original word
contained in the auto-increment location
(177777DD8UU) had a 1 bit in bit 0.
T_ 2.5.2 B_y_t_e_ _A_d_d_r_e_s_s_i_n_g_
Although the ordinary addressing routines will only allow
addressing of complete 16-bit words in memory a convenient
&_ programming method is available which will allow handling of
individual bytes.
This method involves the use of a "byte pointer" which is a word
containing in bits 0 to 14 address of normal two-byte word in
memory and where bit 15 is the "byte indicator". If the byte
indicator is 0 the referenced byte will be the leftmost byte
(containing bits 0 to 7) of the word whose address is given in
bits 0 to 14 of the byte pointer; if the byte indicator is 1 the
referenced byte will correspondingly be the rightmost byte
(containing bits 8 to 15).
Programming routines to handle individual bytes in this way are
listed in Appendix D of this manual.
Byte addressing cannot be used where locations in the extended
memory area are concerned. \f
F_
3 I_N_S_T_R_U_C_T_I_O_N_S_
3.1 I_n_t_r_o_d_u_c_t_i_o_n_
The complete set of operation instructions available for RC 3603
CPU is divided into four subsets. These are instruction sets for
program flow control, data transfer operations, integer
arithmetic and logical operations and a special subset for
programming the processor functions plus the optional features:
Real Time Clock, Power Fail/Auto-restart and Memory Extension.
T_ 3.2 I_n_s_t_r_u_c_t_i_o_n_ _F_o_r_m_a_t_s_
All instructions in the set are one 16-bit word in length but
&_ the lay-out will differ depending on the type of operation to be
performed; more specifically this will bear on the number of
accumulators employed in the execution of the instruction. In
the following description of the different subsets a discussion
of the general format in each separate case will appear
initially followed by a description of the individual
instructions which make up that particular subset.
T_ 3.3 M_n_e_m_o_n_i_c_ _D_e_s_c_r_i_p_t_i_o_n_
In the description of individual instructions the specific form
&_ of the instruction is given in the following generalized format:
MNEMONIC optional mnemonic OPERAND STRING optional operands
The main mnemonic is a group of letter symbols which must be
used to initiate the operation concerned in the instruction. To
this may in some cases be appended the optional mnemonics, which
will cause a modification of the execution of the instruction.
The operand string consists of the actual operands necessary to
the execution of the instruction. To this may likewise be
appended optional operands.
The symbols and == are used as an aid in defining the\f
specific form of each individual instruction:
indicates optional mnemonics or operands
==== used as underlining to identify where definite
substitution is required, i.e. where the actual
identification of accumulator, address, name, number
or mnemonic must be inserted in the instruction
string.
The following abbreviations are used throughout this manual:
AC Accumulator
ACD Destination accumulator
ACS Source accumulator.
T_ 3.4 P_r_o_g_r_a_m_ _F_l_o_w_ _C_o_n_t_r_o_l_
Program flow control operations are handled by way of the
&_ program counter - as outlined in section 2.2.1 - and thus do not
explicitly utilize any of the available accumulators. The
instruction lay-out in this subset is as follows:
T_ OP In-
0 0 0 Code Æ dex DISPLACEMENT
&_ 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
In this format bits 0, 1 and 2 are 000, bits 3 and 4 contain the
operation code and bits 5 to 15 contain the memory address as
described in section 2.5.1.
The symbol Æ - placed anywhere in the effective address operand
string - will set the indirect bit (bit 5) to 1.
The index bits (bit 6 and 7) are set by a comma followed by one
of the digits 0 to 3 as the last operand of the operand string.
If no index is coded, the index bits are automatically set to
00. The index bits can be set to 01 by using the character
"period" (.) at the beginning of the effective address operand
string. When the period is used, it is followed by either a plus
or a minus sign and the appropriate displacement, e.g. ".+7" or
".-2".
The subset contains the following four instructions: JUMP, JUMP
TO SUBROUTINE, INCREMENT AND SKIP IF ZERO and DECREMENT AND SKIP
IF ZERO.
\f
T_ 3.4.1 J_U_M_P_
JMP Æ displacement ,index
=================
In-
0 0 0 0 0 Æ dex DISPLACEMENT
&_ 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
The instruction will cause the effective address to be computed
and subsequently placed in the program counter. Sequential
operation will then continue with the word addressed by this new
value of the program counter.
T_ 3.4.2 J_U_M_P_ _T_O_ _S_U_B_R_O_U_T_I_N_E_
JSR Æ displacement ,index
=================
In-
0 0 0 0 1 Æ dexDISPLACEMENT
&_ 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
The instruction will cause the effective address to be computed.
The current value of the program counter is incremented by one
and this number is placed in AC 3, whereupon the previously
calculated effective address is placed in the program counter
and sequential operation then continues with the word addressed
by this new value of the program counter.
N_O_T_E_: The computation of the effective address is completed
before the incremented value in the program counter is
written into AC 3. This means that if the effective
address calculation involves AC 3 as an index
register, the original value contained in this
register will be used in the calculation before it is
overwritten with the incremented program counter.
As this instruction saves the incremented value of the program
counter in AC 3 the use of this instruction for subroutine calls
makes the return to the proper point in the main program
extremely simple necessitating only the instruction JMP 0,3.
\f
T_3.4.3 I_N_C_R_E_M_E_N_T_ _A_N_D_ _S_K_I_P_ _I_F_ _Z_E_R_O_
ISZ Æ displacement ,index
=================
In-
0 0 0 1 0 Æ dex DISPLACEMENT
&_ 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
This instruction will cause the effective address to be
computed. The word in this location is incremented by one and
the result is written back into the original location. If the
result of the incrementation is zero then the next sequential
instruction is skipped.
T_ 3.4.4 D_E_C_R_E_M_E_N_T_ _A_N_D_ _S_K_I_P_ _I_F_ _Z_E_R_O_
DSZ Æ displacement,index
=================
In-
0 0 0 1 1 Æ dexDISPLACEMENT
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
&_ This instruction will cause the effective address to be
computed. The word in this location is decremented by one and
the result is written back into the location. If the result of
the decrementation is zero then the next sequential instruction
will be skipped.
T_ 3.5 D_a_t_a_ _T_r_a_n_s_f_e_r_ _O_p_e_r_a_t_i_o_n_
Data transfer operations always involve one of the available
&_ accumulators as terminal point for the operation (except when
the Direct Memory Access feature is utilized, see section 4.5).
There are however slight differences in the instruction format
depending on whether the data transfer is internal (between main
memory and accumulator) or external (between peripheral device
and accumulator). This section will only describe the
instructions pertaining to internal data transfers, while\f
external transfers will be dealt with in chapter 4:
Input/Output.
Internal data transfer instructions use the following lay-out:
T_ OP In-
0 codeAC ÆdexDISPLACEMENT
&_ 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
In this format bit 0 is 0, bits 1 and 2 contain the operation
code, bits 3 and 4 specify the accumulator to be used in the
operation and bits 5 to 15 contain the memory address as
outlined in section 2.5.1.
The symbol Æ - placed anywhere in the effective address operand
string - will set the indirect bit to 1.
The index bits (bits 6 and 7) are set by a comma followed by one
of the digits 0 to 3 as the last operand of the operand string.
If no index is coded, the index bits are automatically set to
00.
The index bits can be set to 01 by using the character "period"
(.) at the beginning of the effective address operand string.
When the period is used it is followed by either a plus or a
minus sign and the appropriate displacement, e.g. ".+7" or
".-2".
The internal data transfer subset comprises the following two
instructions: LOAD ACCUMULATOR and STORE ACCUMULATOR.
T_3.5.1 L_O_A_D_ _A_C_C_U_M_U_L_A_T_O_R_
LDA ac, Æ displacement ,index
== =================
In-
0 0 1 AC Æ dexDISPLACEMENT
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
&_ This instruction will cause the effective address to be computed
and the word contained in this location will then be retrieved\f
and subsequently written into the accumulator specified. The
previous contents of that accumulator will be lost; the contents
of the location addressed will remain unchanged.
T_ 3.5.2 S_T_O_R_E_ _A_C_C_U_M_U_L_A_T_O_R_
STA ac, Æ displacement,index
== =================
In-
0 1 0 AC Æ dexDISPLACEMENT
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
&_ This instruction will cause the effective address to be computed
and the word presently located in the accumulator specified will
be retrieved and subsequently written into the main memory
location indicated by the result of the effective address
calculation. The previous contents of this location will be
lost; the contents of the accumulator will remain unchanged.
T_ 3.6 I_n_t_e_g_e_r_ _A_r_i_t_h_m_e_t_i_c_ _a_n_d_ _L_o_g_i_c_a_l_ _O_p_e_r_a_t_i_o_n_s_
Arithmetical and logical operations always use two of the
&_ available accumulators - usually designated "source accumulator"
and "destination accumulator" - to hold the operands involved.
Instructions in this subset have the following lay-out:
T_
OP
1 ACS ACD Code SH C # SKIP
&_ 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
In this format bit 0 is 1, bits 1 and 2 specify the source
accumulator, bits 3 and 4 specify the destination accumulator,
bits 5 to 7 contain the operation code, bits 8 and 9 specify the
action of the shifter, see figure 3.6, bits 10 and 11 specify
the initializing value of the carry, bit 12 indicates whether
the result of the operation must be loaded into the destination
accumulator or not and finally bits 13 to 15 specify the skip
test.
All operations initiated by instructions in this subset are
performed by way of an arithmetic unit whose logical\f
organisation is illustrated below:
T_ Fig. 3.6
ORGANIZATION OF ARITHMETIC UNIT
17 BITS
FUNCTIONSHIFTER
GENERATOR
17 BITS
1 BIT ACS ACD
16 16SKIP SENSOR
CARRY BITSBITS
Initializer
CARRY Accumulators
1 ACD17
BIT 16 BITS BITS
LOAD NO LOAD
&_
The instruction specifies two accumulators containing the two
operands which will have to be supplied to the function
generator. This then performs the desired function as specified
in bits 5 to 7 of the instruction. In addition to the actual
function result the function generator will produce a carry bit,
whose value depends on three quantities: an initial value
specified by the instruction, the input operands themselves and
the function actually performed.
The initial value of the carry bit may be derived from a
previous value of same or a completely independent value may be
specified via the instruction.
The 17-bit output from the function generator - made up of the
carry bit and the 16-bit function result - is then placed in the
shifter. Here the 17-bit result can be shifted one place either
to the right or to the left; alternatively the two 8-bit halves
of the function result can be swapped without affecting the
carry bit. The output from the shifter can then be tested for a
skip. The skip sensor will test whether the carry bit or the
function result itself is equal to zero or not.
After the skip test the output may be loaded into the carry bit
and the destination accumulator respectively. Note however that
loading is not an absolute necessity. \f
The diagrams below illustrate the possible actions taken by the
shifter:
T_
Optional Shifter
Mnemonic Operation
L All bits are moved one position to the left.
Hereby bit 0 is shifted into the carry position
while the carry bit is shifted into bit 15.
C 0-15
&_
T_ R All bits are moved one position to the right.
Hereby bit 15 is shifted into the carry position
while the carry bit is shifted into bit 0.
C 0-15
&_
T_ S The two halves of the 16-bit function result
change places bit by bit. The carry bit is not
affected by this operation.
C 0-7 8-15
C 0-7 8-15
&_
The following table lists the various options available for use
with the instruction format embodying the two-accumulator
multiple operation. The characters in the column headed "Class
Abbreviation" refer to the specific fields of the instruction
format as given at the beginning of this section. The characters
in the column headed "Optional Mnemonics" are those which may\f
optionally by appended to the main mnemonic. The binary numbers
in the column headed "Bit Settings" show the actual bits which
will appear in the appropriate field of the instruction word.
The comments in the column headed "Operation" describe the
resultant action of the option in question.
F_\f
T_ _ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ _ _ __ __ ___
Class Optional Bit
A_b_b_r_e_v_i_a_t_i_o_n_ _ _ _M_n_e_m_o_n_i_c_ _ _ _S_e_t_t_i_n_g_s_ _ _ _ _ _ _ _ _ _O_p_e_r_a_t_i_o_n_ ____________
C 00 Do not initialize the carry
(Carry bit.
Preset) Z 01 Initialize the carry bit to
0.
O 10 Initialize the carry bit to
1.
C 11 Initialize the carry bit to
the complement of its
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _p_r_e_s_e_n_t_ _v_a_l_u_e_._ _ _ ___________
SH 00 Leave the result of the
(Shifter) arithmetic or logical
operation unaffected.
L 01 Combine the carry and the
16-bit result into a 17-bit
number and shift it one bit
to the left.
R 10 Combine the carry and the
16-bit result into a 17-bit
number and shift it one bit
to the right.
S 11 Exchange the two 8-bit
halves of the 16-bit result
without affecting the carry
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _b_i_t_._ _______________________
# 0 Load the result of the
(Load) shift operation into ACD.
# 1 Do not load the result of
the shift operation into
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _A_C_D_._ _______________________
SKIP 000 Never skip.
SKP 001 Always skip.
SZC 010 Skip if carry equal to
zero.
SNC 011 Skif if carry not equal to
zero.
SZR 100 Skip if result equal to
zero.
SNR 101 Skip if result not equal to
zero.
SEZ 110 Skip if either carry or
result equal to zero.
SBN 111 Skip if both carry and
&_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _r_e_s_u_l_t_ _n_o_t_ _e_q_u_a_l_ _t_o_ _z_e_r_o_._ \f
The instruction subset pertaining to integer arithmetic and
logical operations include the following instructions: ADD,
SUBTRACT, NEGATE, ADD COMPLEMENT, INCREMENT and MOVE, all of
which refer to arithmetical operations, and the logical
operations COMPLEMENT and AND.
Integer arithmetic is performed in fixed point mode on 16-bit,
signed or unsigned operands in the accumulators. Logical
operations are performed on 16-bit unstructured binary operands
in the accumulators.
T_ 3.6.1 A_D_D_
ADD c sh # acs,acd ,skip
= == === === ====
1 ACS ACS 1 1 0 SH C SKIP
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
&_
This instruction will first initialize the carry bit to the
specified value. Then the number in ACS is added to the number
in ACD and the result is placed in the shifter. If the addition
produces a carry = 1 out of the high-order bit (bit 0) the carry
bit will be complemented, i.e. this will happen if the sum of
the two numbers being added is greater than 65,535DD10UU.
The specified shift operation is then performed and the result
of this is placed in ACD provided that the load bit of the
instruction has been set to 0. If the skip test demanded results
in the condition being true the next sequential instruction will
be skipped.
T_ 3.6.2 S_U_B_T_R_A_C_T_
SUB c sh # acs,acd ,skip
= == === === ====
1 ACS ACS 1 0 1 SH C # SKIP
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
&_
This instruction will first initialize the carry bit to the
specified value. Then the number in ACS is subtracted from the\f
number in ACD (the actual operation being performed by first
forming the two's complement of the number in ACS and then
adding this to the number in ACD) and the result of the
subtraction placed in the shifter. If the operation produces a
carry = 1 out of the high-order bit (bit 0) the carry bit will
be complemented, i.e. this will happen if the number in ACS is
less than or equal to the number in ACD. The specified shift
operation is performed and the result of this is placed in ACD
provided that the load bit of the instruction has been set to 0.
If the skip test demanded results in the condition being true
the next sequential instruction will be skipped.
T_ 3.6.3 N_E_G_A_T_E_
NEG c sh # acs,acd ,skip
= == === === ====
1 ACS ACD 0 0 1 SH C #SKIP
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
&_
This instruction will first initialize the carry bit to the
specified value. Then the two's complement of the number in ACS
will be formed and placed in the shifter. If the complementation
produces a carry out of the high-order bit (bit 0) the carry bit
will be complemented, i.e. this happens if the number in ACS is
zero. The specified shift operation is performed and the result
of this is placed in ACD provided that the load bit of the
instruction has been set to 0. If the skip test demanded results
in the condition being true the next sequential instruction will
be skipped.
T_3.6.4 A_D_D_ _C_O_M_P_L_E_M_E_N_T_
ADC c sh # acs,acd ,skip
= == === === ====
1 ACS ACD 1 0 0 SH C # SKIP
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
&_
This instruction will first initialize the carry bit to the
specified value. Then the logical complement of the number in
ACS is added to the number in ACD and the result is placed in\f
the shifter. If the addition produces a carry out of the
high-order bit (bit 0) the carry bit will be complemented, i.e.
this happens if the number in ACS is less than the number in
ACD. The specified shift operation is performed and the result
is placed in ACD provided that the load bit of the instruction
has been set to 0. If the skip test demanded results in the
condition being true the next sequential instruction will be
skipped.
T_ 3.6.5. M_O_V_E_
MOV c sh # acs,acd ,skip
= == === === ====
1 ACS ACD 0 1 0 SH C # SKIP
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
&_
This instruction will first initialize the carry bit to the
specified value. Then the number in ACS is placed in the
shifter, the specified shift operation is performed and the
result of this is placed in ACD provided that the load bit of
the instruction has been set to 0. If the skip test demanded
results in the test condition being true the next sequential
instruction will be skipped.
T_
T_3.6.6 I_N_C_R_E_M_E_N_T_
INC c sh # acs,acd ,skip
= == === === ====
1 ACS ACD 0 1 1 SH C # SKIP
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
&_
This instruction will first initialize the carry bit to the
specified value. Then the number in ACS is incremented by one
and the result is placed in the shifter. If the incrementation
produces a carry out of the high-order bit (bit 0) the carry bit
will be complemented, i.e. this will happen if the number in ACS
is 177777DD8UU. The specified shift operation is performed and the
result of this placed in ACD provides that the load bit of the
instruction has been set to 0. If the skip test demanded results \f
in the test condition being true the next sequential instruction
will be skipped.
T_ 3.6.7 C_O_M_P_L_E_M_E_N_T_
COM c sh # acs,acd ,skip
= == === === ====
1 ACS ACD 0 0 0 SH C # SKIP
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
&_
This instruction will first initialize the carry bit to the
specified value. The logical complement of the binary quantity
in ACS is formed and placed in the shifter. The specified shift
operation is performed and the result of this is placed in ACD
provided that the load bit of the instruction has been set to 0.
If the skip test demanded results in the test condition being
true the next sequential instruction will be skipped.
T_3.6.8 A_N_D_
AND c sh # acs,acd ,skip
= == === === ====
1 ACS ACD 1 1 1 SH C # SKIP
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
&_
This instruction will first initialize the carry bit to the
specified value. Then the logical "and" of the two binary
quantities in ACS and ACD is formed and placed in the shifter.
Each bit placed in the shifter is 1 if and only if the two
corresponding bits in ACS and ACD respectively are both 1; in
all other cases the result bit placed in the shifter will be 0.
The specified shift operation is performed and the result of
this is placed in ACD provided that the load bit of the
instruction has been set to 0. If the skip test demanded results
in the test condition being true the next sequential instruction
will be skipped.
T_ 3.6.9 E_x_a_m_p_l_e_s_
To show how these different instructions may be used under
&_ various circumstances consider the following examples: \f
T_ 3.6.9.1 D_e_c_i_d_i_n_g_ _t_h_e_ _s_i_g_n_ _o_f_ _a_ _n_u_m_b_e_r_. To determine whether an integer
contained in an accumulator is positive or negative can be done
&_ in several ways, but the most efficient will be to use the MOVE
instruction and thus the inherent power of the two-accumulator
multiple-operation format.
Assume that the number in question is contained in AC 3. Use of
the instruction:
MOVL#3,3,SZC
will place the number in the shifter and shift the number one
place to the left. This will place the original sign bit in the
carry bit position and the skip test can then be used to
determine whether this bit is 0 or 1. The two following
instructions in the program must of course be chosen in such a
way that appropriate action is taken in either case.
Note that by using the optional mnemonic # the load bit is set
to 1; thus the output from the shifter will not be loaded back
into AC 3 and the original number contained herein will
therefore be retained for further use.
T_ 3.6.9.2 D_i_v_i_d_i_n_g_ _a_ _n_u_m_b_e_r_ _b_y_ _a_ _p_o_w_e_r_ _o_f_ _t_w_o_. To divide a binary number
by 2 is simply equivalent to shifting all digits one position to
the right (compare with decimal notation where division with 10
- i.e. the base - is readily acknowledged to be produced by
this expedient). The fact that the rightmost bit of the
&_ original number will be discarded after the shift means that the
result of the division will be rounded down to the nearest
integer.
The division can be performed simply and efficiently by
employing the MOVE instruction as follows:
MOVL# 2,2,SZC
MOVOR 2,2,SKP
MOVZR 2,2,SKP
MOVOR 2,2,SKP
MOVZR 2,2
The number being divided is supposed to be placed in AC 2. The
first instruction is simply a repetition of the previous example
of deciding the sign of the number. If the number is positive
the second instruction will be skipped and operations will
continue with the third instruction. This will shift the number
one place to the right thus resulting in the division by 2 while\f
at the same time initializing the carry bit to 0 so that when
this bit is shifted into the sign bit position the number will
remain positive. Note that after division the number is now
loaded into AC 2 so that this accumulator now holds the result
of the division. Finally the fourth instruction is skipped and
the fifth repeats the division once more - following which there
is no further skip. The repetition means that the end effect
will be that the original number has been divided by four. If
the number is negative exactly the same sequence of operations
are performed with the appropriate alterations to cope with the
negative sign - the instructions now in force being the second
and fourth.
T_ 3.6.9.3 C_h_a_n_g_i_n_g_ _l_o_c_a_t_i_o_n_s_ _s_i_m_u_l_t_a_n_e_o_u_s_l_y_ _i_n_v_e_r_t_i_n_g_ _t_h_e_ _o_r_d_e_r_. Assume
that a block of 30DD10UU words, which at present occupy locations
2000DD8UU to 2035DD8UU, must be moved to locations 5150DD8UU to
&_ 5205DD8UU in such a way that the order of the individual words in the
block will be inverted.
To do this a section of a program is set up which will
auto-increment through one set of locations, auto-decrement
through the other set and decrement a control count to determine
when the block transfer has been completed. The program section
listed below will accomplish this:
T_ LDA 0,CNT ;comment: set up
STA 0,21 ; auto-increment location
LDA 0,CNT + 1 ; set up
STA 0,35 ; auto-decrement location
LOOP: LDA 0, Æ 21 ; get a word
STA 0, Æ 35 ; store it
DSZ CNT + 2 ; count down word count
JMP LOOP ; jumb back for next word,
skip to here when count
is zero
.
.
.
CNT: 001777 ; 1 before source block
+ 1: 005206 ; 1 after destinationblock
&_ + 2: 36 ; word count
F_\f
4 I_N_P_U_T_/_O_U_T_P_U_T_
4.1 I_n_t_r_o_d_u_c_t_i_o_n_
All useful information processing to be performed by the computer
depends on the existence of some means of communication between
the CPU and the outside world. For this purpose the CPU is
connected to a number of peripheral or Input/Output devices the
actual type, size and number of which is completely independent of
the internal logical structure of CPU.
The program must of course contain instructions designed to
handle the external data transfer operations; these are all
normally termed Input/Output - usually shortened to I/O -
operations and allow for the transfer of information in units of
bits, bytes, words or groups of words called "records" depending
on the device in use.
All instructions in the I/O subset are basically similar to the
previously mentioned internal transfer instructions (section
3.5) except for the fact that addressing as such is not
relevant; on the other hand the CPU must have information as to
which peripheral unit is to be employed for the actual data
transfer and secondly there must be instituted some means of
allocating the necessary time for the transfer.
To handle the control of peripheral devices - of which there may
be several units of widely differing types connected to the CPU
at any given time - the RC 3603 CPU is equipped with a six-line
device selection network. To initiate operation on a specific
device a signal must be transmitted on the selection network,
but each individual peripheral device will only respond to this
signal if it is identical to the device's own device code. The
device code is a six-bit integer number corresponding to the
lines in the selection network.
T_ 4.2 O_p_e_r_a_t_i_o_n_ _o_f_ _I_/_O_ _D_e_v_i_c_e_s_
In general all operations on individual I/O devices are handled
&_ by manipulation of two control bits which are called the "Busy"
and "Done" flags respectively. If the Busy and Done flags are\f
both 0 the device is idle and cannot perform any operation. To
initiate operation on a device the Busy flag must be set to 1,
and if the Done flag is not already 0 it must be set to this
value. When the device has finished its operation it will itself
set the Busy flag to 0 and the Done flag to 1. (If the Busy and
Done flags are both - erroneously - set to 1 the situation is
meaningless and will produce unpredictable effects.)
Thus to initiate operation on a particular device the program
must first determine whether that device is currently performing
an operation or not, i.e. it must check the state of the Busy
and Done flags. If the Busy and Done flags are 0 and 1
respectively, the program will be able to start the operation by
setting Busy to 1 and Done to 0 as described above. When the
operation has been completed the device will reset the two flags
and will thus be available for another operation whenever
necessary.
There are two ways in which the program can test the state of
the Busy and Done flags. One is to use the instruction I/O SKIP
(cf. section 4.6.7), the other is to employ the Interrupt
System whichis standard on the RC 3603.
T_ 4.3 I_n_t_e_r_r_u_p_t_ _S_y_s_t_e_m_
The interrupt system consists of an interrupt request line to
&_ which each I/O device is connected, an Interrupt On flag in the
CPU and a 16-bit interrupt priority mask.
An interrupt is initiated by an I/O device at the time when it
completes its operation and resets the Busy and Done flags;
simultaneously the device places an interrupt request on the
interrupt request line provided that the bit in the interrupt
priority mask, which corresponds to the priority level on the
device, is 0 (cf. section 4.4). If that particular bit of the
mask is 1, the device will still set the flags, but it will not
place an interrupt request on the line.
The Interrupt On flag controls the state of the interrupt system
in the sense that if the Interrupt On flag is set to 1 the CPU
will respond to the process interrupt requests; if the Interrupt
On flag is set to 0 it will not do so but will simply go on with
normal sequential execution of the program.
\f
The CPU responds to an interrupt request by immediately setting
the Interrupt On flag to 0 so that no further interrupts can
interfere with the interrupt service routine. The CPU then
places the program counter in memory location 0 and executes a
"jump indirect" to memory location 1 on the underlying
assumption, that this location contains the address - direct or
indirect - of the interrupt service routine.
When control has been transferred to the interrupt service
routine this routine will first ensure, that the contents of
accumulators to be used by the routine are saved, so that these
values again can be made available when control is eventually
returned to the program proper. The same applies to the carry
bit. When this has been accomplished the routine will determine
which device requested the interrupt; following this it will
proceed with the operations relevant to the servicing of the
interrupt.
The determination of which device is in need of service can be
accomplished through either the I/O SKIP instruction or the
INTERRUPT ACKNOWLEDGE instruction. This last-mentioned
instruction returns the six-bit device code of the device
requesting the interrupt, thereby initiating operation of that
particular device. If more than one device has requested an
interrupt, the code returned will be that belonging to the
device which is physically closest to the CPU on the I/O bus.
When the I/O device has completed its operation, the interrupt
service routine will restore all previously saved values, set
the Interrupt On flag to 1 and finally return control to the
interrupted program. For this purpose the instruction, that will
set the Interrupt On flag to 1, will allow the processor to
execute one further instruction before the next interrupt can
take place. This extra instruction must be the instruction which
returns control to the main program; otherwise the interrupt
service routine may go into a loop. However, since the updated
value of the program counter - as related above - was placed in
location 0 upon responding to the interrupt request, the final
instruction in the servicing routine can simply be the
instruction "JMP Æ 0"; this will transfer control to the main
program as intended.
\f
T_ 4.4 P_r_i_o_r_i_t_y_ _I_n_t_e_r_r_u_p_t_s_
If the Interrupt On flag remains 0 throughout the interrupt
service routine - as assumed above - all further interrupts will
&_ be ignored and there is thus only one level of device priority.
This level of priority - i.e. which devices will be able to
secure an interrupt - will be determined either by the order in
which I/O SKIP instructions are issued or - if the INTERRUPT
ACKNOWLEDGE instruction is used - by the relative physical
locations on the I/O bus of the various devices.
If the complete computer installation embodies I/O devices of
widely differing speeds of operation - such as for example a
teletypewriter versus a fixed head disc - it can be convenient
for the programmer to set up a multi-level interrupt schedule;
this is accomplished by the use of the priority mask coupled
with the appropriate instructions.
The priority mask is one 16-bit word to which the individual I/O
devices are connected in such a way, that each I/O device is
assigned to one specific bit of the mask. The standard mask bit
assignment are arranged in such a manner, that devices having
roughly the same speed of operation will correspond to the same
bit in the mask and will therefore be on the same priority
level. (Appendix A of this manual contains - in addition to the
device codes - the standard RC mask bit assignments.) Although
this standard is relevant for most purposes it is not necessary
to comply with it, and the programmer is completely free to
define his own levels of priority for the individual devices by
using the MASK OUT instruction (cf. section 4.7.5). Whenever a
bit in the priority mask is set to 1 all devices in the priority
level corresponding to that particular bit will be prevented
from requesting an interrupt. In addition all pending interrupt
requests from devices in that priority level will be ignored.
When multi-level priority handling is implemented, the interrupt
service routine must be written in such a way that it may itself
be interrupted without damage. This is done by arranging for the
main interrupt routine to save the state of the machine, - the
contents of the four accumulators, the carry bit and the return
address - whenever it takes over control.
The information concerned must be stored in separate locations
for each time the interrupt handler is entered, so that a higher
level of interrupt will not overlay the return information
corresponding to a lower priority level. Having thus saved the\f
necessary return information the main interrupt routine must
determine which device has requested service and then transfer
control to the correct interrupt handling routine. The actual
transfer is effected in the same way as for the previously
described single-level interrupt handler.
When the correct service routine has received control it will
save the current priority mask, establish the new priority mask
and activate the interrupt system. When it has finished
servicing the I/O device, the routine will de-activate the
interrupt system, reset the priority mask to its original form,
restore the state of the machine, again activate the interrupt
system and finally return control to the interrupted program.
T_ 4.5 D_i_r_e_c_t_ _M_e_m_o_r_y_ _A_c_c_e_s_s_ _D_a_t_a_ _C_h_a_n_n_e_l_
The handling of data transfers under program control as
described above requires an interrupt plus the execution of
&_ several instructions for each word transferred and therefore
occupies valuable time on the processor.
To avoid this and at the same time to obtain higher transfer
rates the RC 3603 CPU is equipped with a separate data channel
through which an I/O device - at its own request - can gain
direct access to main memory.
When an I/O device is ready to send or to receive data it
requests access to memory via the data channel. All such
requests are synchronized by the CPU at the beginning of each
memory cycle. The CPU will then pause at specified points during
the execution of an instruction; at each pause it will accept
all previously synchronized requests in which instance a word
will be transferred directly via the channel from the device to
memory or vice versa without interference with the program.
All requests are honoured in relation to the relative physical
positions on the I/O bus of the different requesting devices;
that is: the device being physically closest to the CPU is
serviced first, then the next closest device and so on until all
requests have been processed. As synchronization of new requests
occur continuously even while previous requests are being
attended to, a device can in effect saturate the channel if it
requests transfer continually. All devices further out on the
bus cannot gain access to the channel until the transfers\f
involving the closer device have been processed, although of
course devices which are closer still on the bus will not be
affected.
In addition to the pause intervals during the execution of an
instruction data channel request will be handled on completion
of an instruction. At this point furthermore, all outstanding
I/O interrupt requests will be accepted. When all such data
transfers have been accomplished the CPU will continue with
normal sequential operation.
T_4.6 I_/_O_ _I_n_s_t_r_u_c_t_i_o_n_s_
All I/O instructions use the format given below:
0 1 1 AC OP Con-
CODE trol DEVICE CODE
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
&_
In this format bits 0, 1 and 2 are 011, bits 3 and 4 specify the
accumulator involved, bits 5 to 7 contain the operation code,
bits 8 and 9 control the Busy and Done flags in the device and
bits 10 to 15 contain the device code. The six bits provided for
the device code will define 64DD10UU unique devices, but the
total number of separate devices which can be employed
simultaneously on any given installation will be slightly lower
than this as some of the available device codes are reserved for
the CPU and certain processor features. Of the remaining codes
some have been assigned to specific devices by Regnecentralen. A
complete listing of device codes appear in Appendix A.
The subset of I/O instructions has a number of options that can
be obtained by appending the appropriate optional mnemonic to
the standard mnemonic of the instruction. These optional
mnemonics are listed in the table below; the column headings
correspond to those given in section 3.6.
\f
T_ _ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ _ _ __ __ ___
Class Optional Bit
A_b_b_r_e_v_i_a_t_i_o_n_ _ _ _M_n_e_m_o_n_i_c_ _ _ _S_e_t_t_i_n_g_s_ _ _ _ _ _ _ _ _ _O_p_e_r_a_t_i_o_n_ ____________
F 00 Does not affect the Busy
(Flags) and Done flags.
S 01 Start the device by set-
ting Busy = 1 and Done = 0.
C 10 Idle the device by setting
both Busy and Done to 0.
P 11 Pulse the special in-out
bus control line. The
effect - if any - depends
on the actual device.
________________________________________________________________
T BN 00 Tests for Busy = 1.
(Tests) BZ 01 Tests for Busy = 0.
DN 10 Tests for Done = 1.
DZ 11 Tests for Done = 0.
&_ ________________________________________________________________
The I/O instruction subset contains the following instructions:
DATA IN A, DATA IN B, DATA IN C, DATA OUT A, DATA OUT B, DATA
OUT C, I/O SKIP and NO I/O TRANSFER.
T_ 4.6.1 D_A_T_A_ _I_N_ _A_
DIA f ac,device
= == ======
0 1 1 AC 0 0 1 F DEVICE CODE
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
&_
This instruction will place the contents of the A input buffer
on the specified device in the AC specified in the instruction.
After the data transfer has been completed the Busy and Done
flags are set as specified by "f".
The number of data bits moved depends on the size of the buffer
and the mode of operation of the device selected. Bits in the AC
not receiving any data are set to 0.
\f
4.6.2 D_A_T_A_ _I_N_ _B_
DIB f ac,device
= == ======
0 1 1 AC 0 1 1 F DEVICE CODE
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
&_
This instruction will have exactly the same effect as the one
previously described - except that it will utilize the B buffer
of the peripheral device.
T_ 4.6.3 D_A_T_A_ _I_N_ _C_
DIC f ac,device
= == ======
0 1 1 AC 1 0 1 F DEVICE CODE
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
&_
This instruction will have exactly the same effect as the two
previously described - except that it will utilize the C buffer
of the peripheral device.
T_4.6.4 D_A_T_A_ _O_U_T_ _A_
DOA f ac,device
= == ======
0 1 1 AC 0 1 0 F DEVICE CODE
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
&_
This instruction will place the contents of the specified AC in
the A output buffer of the selected device. After the data
transfer has been completed, the Busy and Done flags are set as
specified by "f". The contents of the AC will remain unaltered.
The number of data bits moved will depend on the size of the
buffer and on the mode of operation of the device. \f
T_ 4.6.5 D_A_T_A_ _O_U_T_ _B_
DOB f ac,device
= == ======
0 1 1 AC 1 0 0 F DEVICE CODE
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
&_
This instruction will have exactly the same effect as the one
previously described - except that it will utilize the B buffer
of the peripheral device.
T_ 4.6.6 D_A_T_A_ _O_U_T_ _C_
DOC f ac,device
= == ======
0 1 1 AC 1 1 0 F DEVICE CODE
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
&_
This instruction will have exactly the same effect as the two
previously described - except that it will utilize the C buffer
of the peripheral device.
T_4.6.7 I_/_O_ _S_K_I_P_
SKP t device
= ======
0 1 1 0 0 1 1 1 T DEVICE CODE
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
&_
This instruction will test the state of the Busy and Done flags
and will thus enable the programmer to decide on actions to be
taken in consequence of the values of these flags, i.e. whether
a device is in need of service from the interrupt system or not.
The test performed depends on the value of bits 8 and 9 of the
instruction and is selected by appending the appropriate\f
optional mnemonic to the instruction according to the table
given in section 4.6. If the test condition specified by "T" is
true the next sequential instruction will be skipped.
T_ 4.6.8 N_O_ _I_/_O_ _T_R_A_N_S_F_E_R_
NIO f device
= ======
0 1 1 0 0 0 0 0 F DEVICE CODE
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
&_
This instruction will set the Busy and Done flags in the
selected device according to the control code specified by "F".
T_4.7 C_e_n_t_r_a_l_ _P_r_o_c_e_s_s_o_r_ _F_u_n_c_t_i_o_n_s_
I/O instructions with a device code of 77DD8UU will perform
&_ a number of special functions rather than control a specific
peripheral device. With the exception of the I/O SKIP
instruction all I/O instructions having a device code of
77DD8UU will use bits 8 and 9 of the instruction format to
control the state of the Interrupt On flag. The I/O SKIP
instruction - when used with a device code of 77DD8UU - will
cause a test of the state of the Interrupt On flag.
(Alternatively it may be used to test the state of the Power
Fail flag; see section 5.2). The optional mnemonics for these
special instructions are the same as for normal I/O
instructions. The table below lists the resulting actions for
these instructions when used with the special device code
77DD8UU.
\f
T_ _ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ _ _ __ __ ___
Class Optional Bit
A_b_b_r_e_v_i_a_t_i_o_n_ _ _ _M_n_e_m_o_n_i_c_ _ _ _S_e_t_t_i_n_g_s_ _ _ _ _ _ _ _ _ _O_p_e_r_a_t_i_o_n_ ____________
F 00 Does not affect the state
(Flags) of the Interrupt On flag.
S 01 Set the Interrupt On flag
to 1.
C 10 Set the Interrupt On flag
to 0.
P 11 Does not affect the state
of the Interrupt On flag.
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ ___________________________
T BN 00 Tests for Interrupt On = 1.
(Tests) BZ 01 Tests for Interrupt On = 0.
DN 10 Tests for Power Fail = 1.
DZ 11 Tests for Power Fail = 0.
&_ ________________________________________________________________
In addition to use of the ordinary I/O instructions with the
special device code 77DD8UU, there is a subset of special
instructions for processor functions which contains the
following instructions: INTERRUPT ENABLE, INTERRUPT DISABLE,
READ SWITCHES, INTERRUPT ACKNOWLEDGE, MASK OUT, I/O RESET, HALT
and CPU SKIP.
T_ 4.7.1 I_N_T_E_R_R_U_P_T_ _E_N_A_B_L_E_
INTEN
NIOS CPU
0 1 1 0 0 0 0 0 0 1 1 1 1 1 1 1
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
&_
This set of instructions will set the Interrupt On flag to 1. If
the state of the Interrupt On flag is hereby changed, the CPU
will allow one more instruction to be executed before the first
I/O interrupt can occur.
\f
T_ 4.7.2 I_N_T_E_R_R_U_P_T_ _D_I_S_A_B_L_E_
T_ INTDS
NIOC CPU
0 1 1 0 0 0 0 0 1 0 1 1 1 1 1 1
&_ 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
This set of instructions will set the Interrupt On flag to 0.
&_
T_ 4.7.3 R_E_A_D_ _S_W_I_T_C_H_E_S_
READS ac
==
DIA f ac,CPU
= ==
0 1 1 AC 0 0 1 F 1 1 1 1 1 1
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
&_
This set of instructions will place the current setting of the
data switches on either the Diagnostic Front Panel (if
connected) or the front frame of the CPU-board in the AC
specified in the instructions. After the transfer has been
completed, the Interrupt On flag is set according to the control
code specified by "F".
T_ 4.7.4 I_N_T_E_R_R_U_P_T_ _A_C_K_N_O_W_L_E_D_G_E_
INTA ac
==
DIB f ac,CPU
= == ===
0 1 1 AC 0 1 1 F 1 1 1 1 1 1
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
&_
This set of instructions will cause the six-bit device code of
that device, which is physically closest to the CPU on the I/O\f
bus, to be placed in bits 10 to 15 of the AC specified in the
instructions. Bits 0 to 9 of the AC involved will be set to 0.
After the transfer has been completed the Interrupt On flag is
set according to the control code specified by "F".
T_ 4.7.5 M_A_S_K_ _O_U_T_
MSKO ac
==
DOB f ac,CPU
= ==
0 1 1 AC 1 0 0 F 1 1 1 1 1 1
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
&_
This set of instructions will place the contents of the AC
specified in the priority mask. After the transfer has been
completed, the Interrupt On flag is set according to the control
code specified by "F". The contents of the AC remain unaltered.
N_O_T_E_: The digit 1 in any bit position disables interrupt
requests from any peripheral device in the
corresponding priority level.
T_ 4.7.6 I_/_O_ _R_E_S_E_T_
IORST
DIC f ac,CPU
= == ===
0 1 1 AC 1 0 1 F 1 1 1 1 1 1
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
&_
This set of instructions will cause the Busy and Done flags in
all I/O devices to be set to 0; simultaneously all bits in the
16-bit priority mask are set to 0. The Interrupt On flag is set
according to the control code specified by "F".
\f
T_ 4.7.7 H_A_L_T_
HALT
DOC f ac,CPU
= ==
0 1 1 AC 1 1 0 F 1 1 1 1 1 1
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
&_
This set of instructions will set the Interrupt On flag
according to the control code specified by "F". Following this
the processor is stopped.
T 4.7.8 C_P_U_ _S_K_I_P_
SKP t CPU
= ===
0 1 1 0 0 1 1 1 T 1 1 1 1 1 1
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
&_
This instruction will cause the Interrupt On flag or the Power
Fail flag to be tested depending on the control code specified
by "T". If the test condition is true the next sequential
instruction will be skipped.
F_\f
5 P_R_O_C_E_S_S_O_R_ _F_E_A_T_U_R_E_S_
5.1 I_n_t_r_o_d_u_c_t_i_o_n_
Features included in the RC 3603 computer are a power monitor
which will handle automatic shut-down and restart in the event
of a failure of the power supply plus a special CPU function
allowing memory to be extended beyond the 32K words' capacity.
T_ 5.2 P_o_w_e_r_ _F_a_i_l_
Core memory in the RC 3603 computer is of magnetic type and
&_ information stored in it is therefore independent of power
supply and will be retained unaltered for a very considerable
time in event of the power supply being cut off. The same does
not, however, apply to the accumulators, program counter,
various flags etc. in the CPU; all values in these components
will be indeterminate following a break in the supply of power.
The Power Fail feature provides the capability to overcome this
difficulty.
In the event of an unexpected power failure the voltage will
rapidly decrease from its normal value to the value where the
processor automatically shuts down completely. There will
however be an interval of time - roughly one or two milliseconds
- between the initial drop-off of voltage and the actual
shut-down. The Power Fail circuit will sense the beginning
reduction of voltage, set the Power Fail flag and request an
interrupt. The interrupt service routine will then be able to
utilize the interval before shut-down to store the contents of
the accumulators, the carry bit and the current priority mask in
memory. In addition to this it will save memory location 0,
where it will store a jump instruction to the desired restart
location and finally it will execute a HALT. As one or two
milliseconds is sufficient time to execute up to 1500
instructions there is ample time to perform the power fail
routine.
When the power supply is again restored, the CPU will execute a
"JMP 0" instruction after an interval of 100 milliseconds. This
will effect a restart of the interrupted program. \f
The power fail feature has no device code and no interrupt
disable bit in the priority mask. Neither does it respond to the
INTERRUPT ACKNOWLEDGE instruction. The Power Fail flag can be
tested by means of the CPU SKIP instruction as described in
section 4.7.8.
T_ 5.3. M_e_m_o_r_y_ _E_x_t_e_n_s_i_o_n_
Normal memory capacity of the RC 3603 computer is 32K words (64K
&_ bytes). The Memory Extension feature provides the capability to
increase this capacity to 64K words (128K bytes).
To switch from running in normal configuration to running in
extended memory configuration the following instruction must be
applied:
T_ DICP ac, 1
==
0 1 1 x x 1 0 1 1 1 0 0 0 0 0 1
&_0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
This instruction will allow the CPU to utilize the extra block
of core memory and it will furthermore set the Memory Extension
flag to 1. For the instruction to have the desired effect the
switch 64K/128K BYTES on the front frame of the CPU-board must
be in the 128K BYTES position; otherwise the instruction is
dummy.
The state of the Memory Extension flag can be tested with the
I/O SKIP instruction using the device code (001) reserved for
the Extended Memory (see Appendix A). The testing of the flag
thus follows through the instruction:
T_ SKPDN 1
0 1 1 0 0 1 1 1 1 0 0 0 0 0 0 1
&_0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
As usual with this instruction the next sequential instruction
will be skipped if the test condition is true, i.e. if the
Memory Extension flag is 1. \f
If the 64K/128K BYTES switch on the front panel is returned to
the 64K BYTES position the Memory Extension flag is n_o_t_
automatically set back to 0 (although the CPU no longer will be
able to utilize the extended memory block). To return the Memory
Extension flag to 0 an I/O RESET instruction must be used. The
flag will also be set to 0 following a power up.
The CPU can only execute programs placed in the first block of
64K bytes in core memory, that is: the area having addresses
from 0 to 77777DD8UU. The extended area - which will have
addresses from 100000DD8UU to 177777DD8UU - can only be
used as data buffers addressed from the program by indexing to
this memory area (see section 2.5.1.3). Indirect addressing
cannot be used in this area, where addresses implicitly will
have a 1 in bit 0 of the address causing confusion with the role
of this bit as indirect bit.
The Disc Controller is capable of writing data into and reading
data from the extended area of memory.
N_O_T_E_: It is important to be aware of the fact, that when
Memory Extensionis applied the program counter will
continue from 77777DD8UU to 100000DD8UU in the
course of normal sequential operation. But as
explained above the program cannot address this area
where bit 0 is 1, as this bit is masked out in
execution of "JUMP TO SUBROUTINE", indirect address
calculations and the interrupt routine.
\f
6 P_R_O_C_E_S_S_O_R_ _O_P_T_I_O_N_S_
The RC 3603 CPU can be equipped with the following optional
features: a Real Time Clock and a Teletype Controller.
6.1 R_e_a_l_ _T_i_m_e_ _C_l_o_c_k_
The Real Time Clock generates a continuous sequence of pulses
independently of processor timing. The clock can be used
primarily for low resolution timing as compared to processor
speed, but it has a high long-term accuracy.
Following a power turn-on the various frequencies are only
available after an interval of 5 seconds, because the crystal
must be given this amount of time to settle down after
excitation in order to emit a steady pulse train.
Selection of clock frequency is accomplished by means of the I/O
instruction DATA OUT A, Real Time Clock:
T_
DOA f ac,RTC
= ==
0 1 1 AC 0 1 0 F 0 0 1 1 0 0
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
&_
This instruction will select the clock frequency according to
the values of bits 14 and 15 in the specified AC as listed
below:
T_
AC bits 14 & 15: 00 01 10 11
Frequency: 50 Hz 10 Hz 100 Hz 1000 Hz
&_
In addition the instruction will cause the Busy and Done flags
to be set according to the control code specified by "F" (cf.
section 4.6). Setting the Busy flag by means of this instruction
will allow the next pulse from the clock to set Done thus
requesting an interrupt if the Interrupt On flag is 1.
The interrupt priority level of this device is associated with
bit 13 of the interrupt priority mask.
The DATA OUT A instruction applied to select the clock frequency\f
is needed only once. The first interrupt after this instruction
has set Busy = 1 can come at any time up to the clock frequency,
but once the first interrupt has appeared the following
interrupts will adhere to the selected frequency - provided that
the program sets Busy = 1 before the next interrupt is due.
This is done by the instruction:
NIOS 14.
The I/O RESET instruction will - whether it appears in the
program or is generated by using the Diagnostic Front Panel -
reset the clock to a frequency of 50 Hz.
T_ 6.2 T_e_l_e_t_y_p_e_ _C_o_n_t_r_o_l_l_e_r_
The Teletype Controller provides for two-way communication
between the computer and the operator. The input device is the
&_ Teletype keyboard and the output device is the Teletype printer.
All information exchanges between the computer and the
keyboard/printer use a subset of the 128 character alphanumeric
ASCII code as listed in Appendix B. In addition to a keyboard
and a printer, some models of the Teletype terminal can be
equipped with a paper tape reader/punch combination. Terminals
so equipped are designated Automatic Send/Receive (ASR)
terminals, while those not so equipped are designated Keyboard
Send/Receive (KSR) terminals.
T_ 6.2.1 I_n_s_t_r_u_c_t_i_o_n_s_
Since the terminal is in effect two peripheral devices coupled
&_ together, the controller contains both an input buffer and an
output buffer. These buffers are independent of one another and
are both 8 bits in length.
Similarly two completely separate sets of Busy and Done flags
are available for input and output operations respectively.
The Busy and Done flags are controlled by means of the two
standard device flag commands in the instructions according to
the following list:
"F" = S Sets Busy = 1 and Done = 0 and either reads a
character into the input buffer or transfers a
character in the output buffer to the printer (or the
punch).
"F" = C Sets Busy = 0 and Done = 0 thereby stopping all data
transfer operations. This command - if issued while a\f
transfer is in process - will result in partial
reception of the character code being transferred.
"F" = P No effect.
The instructions used to read the character buffer and to load
the character buffer are the standard I/O instructions with the
appropriate device codes. An extract of Appendix A containing
these codes appear below:
T_
Octal
Code Mnemonic Maskbit Device
10 TTI 14 Teletype input, first controller
11 TT0 15 Teletype output, first controller
50 TTI1 14 Teletype input, second controller
51 TT01 15 Teletype output, second controller
&_
T_ 6.2.1.1 R_E_A_D_ _C_H_A_R_A_C_T_E_R_ _B_U_F_F_E_R_
DIA f ac,TTI
= ==
0 1 1 AC 0 0 1 F 0 0 1 0 0 0
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
&_
This instruction will place the contents of the input buffer in
bits 8 to 15 of the AC specified in the instruction. Bit 8 is a
parity check bit while bits 9 to 15 contain the character code
proper. Bits 0 to 7 of the AC are all set to 0.
After the data transfer has been completed the controller's Busy
and Done flags for input are set according to the control code
specified by "F".
T_ 6.2.1.2 L_O_A_D_ _C_H_A_R_A_C_T_E_R_ _B_U_F_F_E_R_
DOA f ac,TTO
= ==
0 1 1 AC 0 0 1 F 0 0 1 0 0 1
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
&_ \f
This instruction will place bits 9 to 15 of the specified AC in
the output buffer of the controller. After the transfer has been
completed the controller's Busy and Done flags for output are
set according to the control code specified by "F". The contents
of the AC specified in the instruction will remain unaltered.
T_ 6.2.2 P_r_o_g_r_a_m_m_i_n_g_
On account of the two-sided nature of the Teletype terminal this
section will describe input and output procedures separately.
&_
T_ 6.2.2.1 I_n_p_u_t_. Input operations - whether full- or half-duplex - do not
have to be initialized by the program because the striking of a
key on the keyboard automatically will transmit the
&_ corresponding character code to the controller. When the
character has been assembled the input Busy flag is set to 0,
the input Done flag is set to 1 and a program interrupt
consequently requested - provided that the priority mask bit is
0.
The character can then be read by issuing the READ CHARACTER
BUFFER instruction (DIA). The instruction should be issued with
either a C or an S command so that the input Done flag is set to
0; this will allow the controller to initiate a further program
interrupt request when the next character has been fully
assembled.
T_ 6.2.2.2 O_u_t_p_u_t_. Output operations are initiated by the program using the
LOAD CHARACTER BUFFER instruction (DOA). The instruction should
be issued with an S command, which will set the Busy flag to 1
&_ and allow the transmitting of the character to the terminal.
When the transmission has been completed the output Busy flag is
set to 0 and the output Done flag is set to 1 thus issuing a
program interrupt request.
The output buffer must be reloaded by means of the LOAD
CHARACTER BUFFER instruction every time a character is to be
sent to the terminal. Thus to transmit a multi-character message
a sequence of LOAD CHARACTER BUFFER instructions with S commands
must be issued. The program must make allowance for complete
transmission of every single character before transmission of
the next character is initiated.
T_ 6.2.3 P_r_o_g_r_a_m_m_i_n_g_ _E_x_a_m_p_l_e_s_
The following examples show sections of programs which will
&_ handle character operations involving the Teletype keyboard,\f
printer, paper tape reader and paper tape punch.
Example 1 reads a character from the Teletype keyboard, example
2 reads a character from Tape reader and example 3 prints a
character on the Teletype printer and - if the tape punch on an
ASR terminal is turned on - simultaneously punches the character
on the tape.
T_ 6.2.3.1 E_x_a_m_p_l_e_ _1_._
SKPDN TTI ;Character buffer loaded yet?
JMP .-1 ;No
DIAC 1,TTI ;Read character and clear Done
flag
&_
T_ 6.2.3.2 E_x_a_m_p_l_e_ _2_._
NIOS TTI ;Start reader
SKPDN TTI ;Frame buffer loaded yet?
JMP .-1 ;No
DIAC 1,TTI ;Read frame and clear Done flag
&_
T_6.2.3.3 E_x_a_m_p_l_e_ _3_._
SKPBZ TTO ;Printer free?
JMP .-1 ;No, try again
DOAS 1,TTO ;Print character
&_
T_ 6.2.3.4 E_x_a_m_p_l_e_ _4_._ The subroutine shown in this example and called from
the main program by a JUMP TO SUBROUTINE instruction (JSR to
TTYRD) illustrates reading and echoing characters on the
&_ Teletype, with Teletype interrupts disabled. AC 0 is used to
store the character.
TTYRD: SKPDN TTI ;Has character been typed?
JMP .-1 ;No, then wait
DIAC 0,TTI ;Yes, then read character and
clear Done flag
SKPBZ TTO ;Is TT0 ready?
JMP .-1 ;No, then wait
DOAS 0,TTO ;Yes, then echo character
JMP 0,3 ;Return
\f
T_ 6.2.3.5 E_x_a_m_p_l_e_ _5_._ This example shows how Teletype may be programmed
using the program interrupt facility. To do so makes it possible
&_ to perform a number of calculations in the intervals of time
between Teletype characters.
This routine will read a line and echo it on the Teletype
printer using the interrupt priority system. The characters are
read into a buffer area beginning at location 1000DD8UU. The
routine is terminated by either a carriage return character or line
overflow. Line overflow is determined by the value of MAXLL
(maximum line length).
.LOC O ;
0 ;Program counter stored here when
an interrupt occurs.
IHAND ;Address of interrupt handler
.LOC 400 ;
T_ START: LDA 1,BUFFER ;Set up buffer pointer in
auto-increment location 23
STA 1,23 ;
LDA 1,MAXLL ;Get maximum line length
STA 1,CNTR ;Initialize line overflow counter
SUBZL 1,1 ;Set AC 1 = 1
DOBS 1,CPU ;Mask out TTO and turn on
interrupts
.
&_ .
.
HANG: LDA 0,CNTR ;When need full line to continue
hang up here until reading is all
done
MOV 0,0,SZR ;
JMP .-2 ;
.
.
.
.
BUFFR: 777 ;Buffer begins at location 1000
MAXLL: 110 ;Maximum of 72DD10UU
characters per line
CNTR: 0 ;Line overflow counter
.
.
.
IHAND: SKPDN TTI ;Make sure TTI caused the
interrupt\f
HALT ;Error - some other peripheral
interrupted
STA 0,SAV0 ;Save accumulators that will be
used
STA 1,SAV1 ;
DIAC 0,TTI ;Read character and clear Done
STA 0, 23 ;Store character in buffer
SKPBZ TTO ;Make sure TT0 not busy
JMP .-1 ;
DOAS 0,TTO ;Echo character
LDA 1,CR ;Is it a carriage return?
SUB 0,1,SZR ;
JMP .+4 ;No
SUBC 0,0 ;Yes, clear AC 0 without changing
carry
STA 0,CNTR ;Zero out CNTR to indicate line
done
JMP .+3 ;
DSZ CNTR ;If not a carriage return,
decrement CNTR
JMP OUT ;Line not yet done, go dismiss
LDA 0,TTMSK ;Line is done
MSKO 0 ;Mask out TTI (and TT0) to inhibit
further input
OUT: LDA 0,SAV0 ;Restore accumulators
LDA 0,SAV1 ;
INTEN ;Turn interrupts back on
JMP 0 ;Return to interrupted program
SAV0: 0
SAV1: 0
CR: 215
TTMSK: 3
F_\f
7 P_R_O_G_R_A_M_ _L_O_A_D_I_N_G_
7.1 I_n_t_r_o_d_u_c_t_i_o_n_
Whenever the computer is used for information processing of any
kind the program must - as previously mentioned - reside in main
memory. But to read a program into memory is in itself a kind of
information processing and therefore requires the existence in
memory of a program - called a loading program - to perform this
duty.
Although the loading program will normally be present, it may
from time to time be necessary to read it into memory. This is
done by a small, specialized loading program which is called a
"bootstrap loader" and whose only function is to read into
memory the more general-purpose loading program.
Two methods are available for entering the bootstrap loader into
memory. One is for the operator to enter it manually utilizing
the data switches and the deposit switch on the Diagnostic Front
Panel. The other is to use the Automatic Program Load option if
the computer in question is so equipped.
In this chapter only automatic program loading is described. For
details about manual loading the reader must consult the
Reference Manual for the Diagnostic Front Panel - RCSL:
52-AA542.
T_ 7.2 A_u_t_o_m_a_t_i_c_ _L_o_a_d_i_n_g_
To use the Automatic Program Load option, the operator must
&_ first select the input device and set up the loading program on
this device in preparation to be read. In addition the device
code of this unit must be set up in its binary form on the data
switches 10 to 15 on the front frame of the CPU board (cf. the
illustration appearing in the following chapter). The setting of
data switch 0 on the front panel depends on the type of input
device selected. If this is a data channel device - for instance
magnetic tape - data switch 0 must be set to 1. If it is a
low-speed device - for instance a paper tape reader - data
switch 0 must be set to 0. \f
When this has been done, push the AUTOLOAD switch on the
operator panel. This will cause the bootstrap loader to be read,
deposited in memory locations 0 to 37DD8UU and started at
location 0. The bootstrap loader will then read the data
switches (0 and 10 to 15), set up its own I/O instructions with
the device code as read and finally perform a program load
procedure which depends on the setting of data switch 0.
If data switch 0 has been set to 1, the bootstrap loader will
start the device for data channel transfer starting storage at
location 0 and will then loop at location 377DD8UUuntil a
data channel transfer places a word in this location. When this
happens, the word placed in this location is executed as an
instruction; typically this will be a JUMP into the data which
have been placed in locations 0 to 376DD8UU.
N_O_T_E_: For proper program loading via the data channel the
device in use must be initialized for the reading
operation by an I/O RESET instruction followed by a
NIOS instruction. Furthermore the device must stop
reading when 256DD10UU words has been read;
otherwise the available memory locations will
overflow.
If data switch 0 has been set to 0, the bootstrap loader will
read the loading program via programmed I/O. The device must
supply data as 8-bit bytes; each pair of bytes read will be
stored in memory as a single word wherein the first and second
byte will become respectively the left and right halves of the
word. To simplify the positioning of the input medium - for
instance a paper tape - the bootstrap loader will ignore leading
null characters, i.e. it will not store any word until it has
read a non-zero synchronization byte.
The first word following this synchronization byte must be the
negative of the total number of words to be read including this
first word. The number of words to be read - including the first
- cannot exceed 192DD10UU. The bootstrap loader will store
the words read in memory starting in location 100DD8UU. When
the last word has been read the bootstrap loader will transfer
control to that location.
On the two following pages appear a listing of a 32 word
bootstrap loader (FO2) capable of loading in either of the
manners described above and a list of available bootstrap
loaders.\f
T_ B_O_O_T_S_T_R_A_P_ _L_O_A_D_E_R_ _F_O_R_
A_U_T_O_M_A_T_I_C_ _P_R_O_G_R_A_M_ _L_O_A_D_
Fig. 7.1
00000 060477 BEG: READS 0 ;READ SWITCHES INTO AC0
00001 105120 MOVZL 0,1 ;ISOLATE DEVICE CODE
00002 124240 COMOR 1,1 ;-DEVICE CODE -1
00003 010011 LOOP: ISZ OP1 ;COUNT DEVICE CONTROL INTO
ALL
00004 010031 ISZ OP2 ;I0 INSTRUCTIONS
00005 010033 ISZ OP3 ;
00006 010014 ISZ OP4 ;
00007 125404 INC 1,1,SZR ;DONE?
00010 000003 JMP LOOP ;NO INCREMENT AGAIN
00011 060077 OP1: 060077 ;START DEVICE;(NIOS 0) -1
00012 030017 LDA 2,C377 ;YES,PUTJMP 377INTO
LOCATION 377
00013 050377 STA 2,377 ;
00014 063377 OP4: 063377 ;BUSY ? :( SKPBN 0 ) -1
00015 000011 JMP OP1 ;NO, GO TO OP1
00016 101102 MOVL 0,0,SZC ;LOW SPEED DEVICE?(TEST
SWITCH 0)
00017 000377 C377: JMP 377 ;NO, GO TO 377 AND WAIT
FOR CHAN.
00020 004031 LOOP2:JSR GET+1 ;GET A FRAME
00021 101065 MOVC 0,0.SNR ;IS IT NONZERO?
00022 000020 JMP LOOP2 ;NO, IGNORE AND GET ANOTHER
00023 004030 LOOP4:JSR GET ;YES, GET A FULL WORD
00024 046027 STA 1,ÆC77 ;STORE STARTING AT 100
00025 010100 ISZ 100 ;COUNT WORD - DONE?
00026 000023 JMP LOOP4 ;NO, GET ANOTHER
00027 000077 C77: JMP 77 ;YES - LOCATION COUNTER AND
JUMP TO LAST WORD
00030 126420 GET: SUBZ 1,1 ;CLEAR AC1, SET CARRY
OP2:
00031 063577 LOOP3:063577 ;DONE ? : ( SKPDN 0)-1
00032 000031 JMP LOOP3 ;NO, WAIT
00033 060477 OP3: 060477 ;YES, READ INTO AC0:(DIAS
0,0) -1
00034 107363 ADDCS 0,1,SNC ;ADD 2 FRAMES SWAPPED-
GOTSECOND? \f
00035 000031 JMP LOOP3 ;NO, GO BACK AFTER IT.
00036 125300 MOVS 1,1 ;YES, SWAP AC1
00037 001400 JMP 0,3 ;RETURN WITH FULL WORD
L_I_S_T_ _O_F_ _A_V_A_I_L_A_B_L_E_
P_R_O_G_R_A_M_ _L_O_A_D_S_
&_
Device Code
Device Type Bit 0 Bits 10-15 (octal)
FO1 Magnetic Tape 1 30
FO2 PTR 0 12
FO3 CDR 0 16
FO4 FDD 0 61
FO5 DKP 0 73
FO6 ASL *) NOTE
FO8 DSC 0 20
(FO1) FPA 1 46
N_O_T_E_: Works together with another program load, i.e. FO4
&_
F_ \f
8 S_W_I_T_C_H_E_S_ _A_N_D_ _I_N_D_I_C_A_T_O_R_S_
This chapter contains a description of the switches and
indicators placed on the front frame of the CPU board. An
illustration of the front panel is found at the extreme end of
the chapter.
8.1 S_w_i_t_c_h_e_s_
Four groups of switches are placed on the front panel, namely
the ENABLE TCP switch, the AUTOLOAD DEVICE SELECT switches, the
PARITY ERROR switches and the MEMORY EXTENSION SELECT switch.
T_ 8.1.1 E_N_A_B_L_E_ _T_C_P_
This switch transfers control to and from the Diagnostic Front
&_ Panel, details of which can be found in Reference Manual for the
Diagnostic Front Panel - RCSL: 52-AA542.
When this switch is in the UP position, the Diagnostic Front
Panel can be connected to or disconnected from the CPU without
creating any disturbance for CPU program execution. Furthermore
the AUTOLOAD DEVICE SELECT switches are operative when ENABLE
TCP is in this position.
Whenever the Diagnostic Front Panel is not connected to the CPU,
the ENABLE TCP switch is inoperative, i.e. pushing this switch
will not affect the CPU.
When the ENABLE TCP switchis in the DOWN position all control
of the CPU is carried out from the Diagnostic Front Panel
connected to the CPU.
N_O_T_E_: The ENABLE TCP switch m_u_s_t_ be in the UP position
before the Diagnostic Front Panel is connected or
disconnected to the CPU.
T_ 8.1.2 A_U_T_O_L_O_A_D_ _D_E_V_I_C_E_ _S_E_L_E_C_T_
These switches are operative when the ENABLE TCP switch is in
the UP position as mentioned above. They are used for external,
&_ manual setting of specific bits of a word, the bits in question
being bit 0 and bits 10 to 15.
Setting these switches is imperative in connection with the use
of the Automatic Program Loading feature as outlined in the
previous chapter. In this case the switches 10 to 15 are set
according to the binary code of the input device being used,
whereas switch 0 is used to distinguish between the types of\f
device available, i.e. whether the device is a data channel
device or a programmed I/O device.
Apart from this the switches can be used in conjunction with
normal program operation by including the instruction READ
SWITCHES; this instruction will - as explained in section 4.7.3
- place the bit values indicated by these switches in their
respective positions in an accumulator specified by the
instruction. When loaded into the accumulator the bit setting
indicated will be accessible to the program. When the bits are
loaded into the accumulator bits 1 to 9 will be read as logic
zeroes.
T_ 8.1.3 P_A_R_I_T_Y_ _E_R_R_O_R_
This group contains two switches: STOP and RESET.
When the STOP switch is in the DOWN position a parity error
&_ detected during a memory read cycle will cause the CPU to
suspend processing in the microprogram. This will allow
connecting of the Diagnostic Front Panel to the CPU while the
CPU is still at that point of execution where the error was
registered. Thus information about the memory address giving
rise to the parity error can be read out from the memory address
register so that corrective action can be decided upon.
To restart the CPU following a parity error - if so desired - is
accomplished either by pushing the STOP switch to the UP
position or by pushing the RESET switch to the DOWN position.
When the STOP switch is in the UP position the detection of a
parity error will be indicated (cf. section 8.2.1), but
processing will continue without interruption.
When the RESET switch is pushed to the DOWN position the parity
error indicators (cf. section 8.2.1) will be reset; if the CPU
has suspended processing following the detection of a parity
error, this action will simultaneously restart the CPU.
CAUTION
If the switch AUTO is pushed while the RESET switch is still in
the DOWN position, the CPU will restart in the address determin-
ed by the positions of the AUTOLOAD DEVICE SELECT switches - di-
rect if switch 0 is set to 0, indirect if switch 0 is set to 1.
(A description of the AUTO switch mentioned above is not inclu-
ded in this manual. This switch is a feature of the Diagnostic
Front Panel and the external Autoload Panel; more detailed infor-
mation must be sought in the relevant manuals. \f
N_O_T_E_: Activating the RESET switch will only reset the
indicators. The parity error causing the indication
will still be present in the particular memory
location. Only a write operation into that location
will remove the error.
T_ 8.1.4 M_E_M_O_R_Y_ _E_X_T_E_N_S_I_O_N_ _S_E_L_E_C_T_
When this switch is in the DOWN position the Memory Extension
feature is inoperative. If the switch is in the UP position the
&_ programmer can utilize the extended block of core memory by
including the proper instructions in the program. (Refer to
section 5.3.)
T_ 8.2 I_n_d_i_c_a_t_o_r_s_
Two groups of indicators are placed on the front panel, namely
the PARITY ERROR indicators and the CPU-STATUS indicators.
&_
T_ 8.2.1 P_A_R_I_T_Y_ _E_R_R_O_R_
This group consists of two indicating lights: LEFT and RIGHT.
The LEFT indicator is lit whenever a parity error is detected in
&_ the left byte (bits 0 to 7) of a word being read during a memory
read cycle.
The RIGHT indicator is lit whenever a parity error is detected
in the right byte (bits 8 to 15) of a word being read during a
memory read cycle.
The indicators - either or both - can only be cleared by pushing
the RESET switch as previously described.
T_ 8.2.2 C_P_U_-_S_T_A_T_U_S_
This group consists of two indicating lights: FETCH and DEFER.
The FETCH indicator is lit whenever the CPUis reading an
&_ instruction from core memory.
The DEFER indicator is lit whenever the next microcycle will be
used to follow an indirect addressing chain. \f
Appendix A I/O Device and Mnemonics
Decimal Octal
code code Mnemonic Maskbit Device
01 01 Extended Memory
02 02
03 03
04 04
05 05 ASL Automatic System Load
06 06
07 07
08 10 TTI 14 Teletype input
09 11 TTO 15 Teletype output
10 12 PTR 11 Paper Tape Reader
11 13 PTP 13 Paper Tape Punch
12 14 RTC 13 Real Time Clock
13 15 PLT 12 Incremental Plotter
14 16 CDR 10 Card Reader
15 17 LPT 12 Line Printer
16 20 DSC 4 Disc Storage Channel
17 21 SPC 9 Standard Parallel Controller
18 22 SPC1 9 Second Standard Parallel
Controller
19 23 PTR1 11 Second Paper Tape Reader
20 24 TMX10 0 Second 64 Channel
21 25 TMX11 1 Asynchronous Multiplexer
22 26 TMX0 0 64 Channel Asynchronous
23 27 TMX1 1 Multiplexer
24 30 MT 5 Magnetic Tape
25 31 PTP1(IBM) 13 Second Paper Tape Punch, & IBM 1
26 32 (IBM)(13) OCP-Function Button Out, & IBM1
27 33 OCP-Function Button In
28 34 OCP-Numeric Keyboard In
29 35 DISP 7 OCP-Display
30 36 OCP-Autoload
31 37 LPS 12 Serial Printer
32 40 REC 8 BSC Controller
33 41 XMT 8
34 42 REC1 8 Second BSC Controller
35 43 XMT1 8
RC 3603A-1\f
T_ Decimal Octal
code code Mnemonic Maskbit Device
36 44 MT1 5 Second Magnetic Tape
37 45 CLP 12 Charaband Printer
38 46 FPAR 3 Inter Processor Channel
Receiver
39 47 FPAX 3 Inter Processor Channel
Transmitter
40 50 TTI1 14 Second Teletype Input
41 51 TTO1 15 Second Teletype Output
42 52 AMX 2 8 Channel Asynchronous
Multiplexor
43 53 AMX1 2 Second 8 Ch. Asynchronous Mpx.
44 54 HLCR 8 HDLC Controller Receiver
45 55 HLCX 8 HDLC Controller Transmitter
46 56 CDR1 10 Second Card Reader
47 57 LPT1 12 Second Line Printer
48 60 SMX Synchronous Multiplexor
49 61 FDD 7 Flexible Disc Drive
50 62 CRP 10 Card Reader Punch
51 63 CLP1 12 Second Charaband Printer
52 64 FDD1 7 Second Flexible Disc Drive
53 65
54 66
55 67 LPS1 12 Second Serial Printer
56 70 DST Digital Sense
57 71 DOT(IBM) (13) Digital Output, & IBM 2
58 72 CNT(IBM) (13) Digital Counter, & IBM 2
59 73 DKP 7 Moving Head Disc Channel
60 74 3 Second Inter Processor Channel
Receiver
61 75 3 Second Inter Processor Channel
Transm.
62 76
63 77 CPU Central Processor
&_ RC 3603 A-2\f
F_
T_ Appendix B ASCII C_H_A_R_A_C_T_E_R_ _C_O_D_E_S_
To Produce Even
ASCII On TTY Mod Parity
Deci- Cha- 33,35 8-bit
mal Octal Hex racter Control Function Cntr Shift Char code
0 000 00 NUL Null P 00
1 001 01 SOH Start of Heading A 81
2 002 02 STX Start of Text B 82
3 003 03 ETX End of Text C 03
4 004 04 EOT End of Transmission D 84
5 005 05 ENQ Enquiry E 05
6 006 06 ACK Acknowledge F 06
7 007 07 BEL Bell G 87
8 010 08 BS Backspace H 88
9 011 09 HT Horizontal Tap I 09
10 012 0A NL New Line line feed 0A
J OA*
line feed 8A
11 013 0B VT Vertical Tab K 8B
12 014 0C FF Form Feed L 0C
13 015 0D RT Return return 8D
M 8D*
return 0D
14 016 0E SO Shift Out N 8E
15 017 0F SI Shift In O 0F
16 020 10 DLE Data Link Escape P 90
17 021 11 DC1 Device Control 1 Q 11
18 022 12 DC2 Device Control 2 R 12
19 023 13 DC3 Device Control 3 S 93
* on even parity Teletypes these codes have odd parity
&_ RC 3603 B-1 \f
T_ To Produce Even
ASCII On TTY Mod Parity
Deci- Cha- 33,35 8-bit
mal Octal Hex racter Control Function Cntr Shift Char code
20 024 14 DC4 Device Control 4 T 14
21 025 15 NAK Negative Acknow-
ledge U 95
22 026 16 SYN Synchronous Idle V 96
23 027 17 ETB End Transmission
Block W 17
24 030 15 CAN Cancel X 18
25 031 19 EM End of Medium Y 99
26 032 1A SUB Substitute Z 9A
27 033 1B ESC Escape esc 1B
K 1B
28 034 1C FS File Separator L 9C
29 035 1D GS Group Separator M 1D
30 036 1E RS Record Separator N 1E
31 037 1F US Unit Separator O 9F
32 040 20 SP Space space A0
33 041 21 ! 1 21
34 042 22 " 2 22
35 043 23 # 3 A3
36 044 25 < 4 24
37 045 25 % 5 A5
38 046 26 & 6 A6
39 047 27 ' 7 27
40 050 28 ( 8 28
41 051 29 ) 9 A9
42 052 2A * : AA
43 053 2B + ; 2B
44 054 2C , , 2C
&_ RC 3603 B-2 \f
T_ To Produce Even
ASCII On TTY Mod Parity
Deci- Cha- 33,35 8-bit
mal Octal Hex racter Control Function Cntr Shift Char code
45 055 2D - - 2D
46 056 2E . . 2E
47 057 2F / / AF
48 060 30 0 0 30
49 061 31 1 1 B1
50 062 32 2 2 B2
51 063 33 3 3 33
52 064 34 4 4 B4
53 065 35 5 5 35
54 066 36 6 6 36
55 067 37 7 7 B7
56 070 38 8 8 B8
57 071 39 9 9 39
58 072 3A : : 3A
59 073 3B ; ; BB
60 074 3C , 36
61 075 3D = - BD
62 076 3E . BE
63 077 3F ? / 3F
64 100 40 Æ P C0
65 101 41 A A 41
66 102 42 B B 42
67 103 43 C C 43
68 104 44 D D 44
69 105 45 E E C5
&_ RC 3603 B-3 \f
T_ To Produce Even
ASCII On TTY Mod Parity
Deci- Cha- 33,35 8-bit
mal Octal Hex racter Control Function Cntr Shift Char code
70 106 46 F F C6
71 107 47 G G 47
72 110 48 H H 48
73 111 49 I I C9
74 112 4A J J CA
75 113 4B K K 4B
76 114 4C L L CC
77 115 4D M M 4D
78 116 4E N N 4E
79 117 4F O O CF
80 120 50 P P 50
81 121 51 Q Q D1
82 122 52 R R D2
83 123 53 S S 53
84 124 54 T T D4
85 125 55 U U 55
86 126 56 V V 56
87 127 57 W W D7
88 130 58 X X D8
89 131 59 Y Y 59
90 132 5A Z Z 5A
91 133 5B K DB
92 134 5C L 5C
93 135 5D M DD
94 136 5E N DE
&_ RC 3603 B-4 \f
T_ To Produce Even
ASCII On TTY Mod Parity
Deci- Cha- 33,35 8-bit
mal Octal Hex racter Control Function Cntr Shift Char code
95 137 5F _ O 5F
96 140 60 60
97 141 61 a E1
98 142 62 b E2
99 143 63 c 63
100 144 64 d E4
101 145 65 e 65
102 146 66 f 66
103 147 67 g E7
104 150 68 h E8
105 151 69 i 69
106 152 6A j 6A
107 153 6B k EB
108 154 6C l 6C
109 155 6D m ED
110 156 6E n EE
111 157 6F o 6F
112 160 70 p F0
113 161 71 q 71
114 162 72 r 72
115 163 73 s F3
116 164 74 t 74
117 165 75 u F5
118 166 76 v F6
119 167 77 w 77
120 170 78 x 78
121 171 79 y F9
122 172 7A z FA
123 173 7B 7B
124 174 7C FC
125 175 7D 7D
126 176 7E 7E
127 177 7F DEL rubout FF
&_ RC 3603 B-5 \f
F_
Appendix C D_O_U_B_L_E_ _P_R_E_C_I_S_I_O_N_ _A_R_I_T_H_M_E_T_I_C_
A double length number consists of two words concatenated into a
32-bit string wherein bit 0 is the sign and bits 1-31 are the
magnitude in two's complement notation. The high-order part of a
negative number is therefore in one's complement form unless the
low-order part is null (at the right only 0's are null
regardless of sign). Hence, in processing double length numbers,
two's complement operations are usually confined to the
low-order parts, whereas one's complement operations are
generally required for the high-order parts.
Suppose we wish to negate the double length number whose high
and low-order words respectively are in AC0 and AC1. We negate
the low-order part, but we simply complement the high-order part
unless the low order part is zero. Hence
T_ NEG 1,1,SNR
NEG 0,0,SKP ;LOW ORDER ZERO
&_ COM 0,0 ;LOW ORDER NON-ZERO
Note that the magnitude parts of the sequence of negative
numbers from the most negative toward zero are the positive
numbers from zero upward. In other words, the negative
representation -x is the sum of x and the most negative number.
Hence, in multiple precision arithmetic, low-order words can be
treated simply as positive numbers. In unsigned addition a
carry indicates that the low-order result is just too large and
the high-order part must be increased. We add the number in AC2
and AC3 to the number in AC0 and AC1.
ADDZ 3,1,SZC
INC 0,0
ADD 2,0
In two's complement subtraction a carry should occur unless the
subtrahend is too large. We could increment as in addition, but
since incrementing in the high-order part is precisely the
difference between a one's complement and a two's complement, we
can always manage with only two instructions. We subtract the
number in AC2 and AC3 from that in AC0 and AC1.
T_ SUBZ 3,1,SZC
SUB 2,0,SKP
ADC 2,0
&_ RC 3603 C-1\f
T_ Appendix D I_N_S_T_R_U_C_T_I_O_N_ _U_S_E_ _E_X_A_M_P_L_E_S_
On the following pages are examples of how the instruction set
of the RC 3603 computer may be used to perform some common
functions.
1. Clear an AC and the carry bit.
SUBO AC,AC
2. Clear an AC and preserve the carry bit.
SUBC AC,AC
3. Generate the indicated constants.
SUBZL AC,AC ;GENERATE +1
ADC AC,AC ;GENERATE -1
ADCZL AC,AC ;GENERATE -2
4. Let ACX be any accumulator whose contents are zero.
Generate the indicated constants in ACX.
INCZL ACX,ACX ;GENERATE +2
INCOL ACX,ACX ;GENERATE +3
INCS ACX,ACX ;GENERATE +400DD8UU
5. Subtract 1 from an accumulator without using a constant from
memory.
NEG AC,AC
COM AC,AC
6. Check if both bytes in an accumulator are equal.
MOVS ACS,ACD
SUB ACS,ACD,SZR
JMP --- ;NOT EQUAL
--- --- ;EQUAL
&_ RC 3603 D-1\f
T_ 7. Check if two accumulators are both zero.
MOV ACS,ACS,SNR
SUB# ACS,ACD,SZR
JMP --- ;NOT BOTH ZERO
--- --- ;BOTH ZERO
8. Check an ASCII character to make sure it is a decimal
digit. The character is in ACS and is not destroyed
by the test. Accumulators ACX and ACY are destroyed.
LDA ACX,C60 ;ACX=ASCII ZERO
LDA ACY,C71 ;ACY=ASCII NINE
ADCZ# ACY,ACS,SNC ;SKIPS IF (ACS) 9
ADCZ# ACS,ACX,SZC ;SKIPS IF (ACS) D=U0
JMP --- ;NOT DIGIT
--- --- ;DIGIT
C60: 60 ;ASCII ZERO
C71 71 ;ASCII NINE
9. Test an accumulator for zero.
MOV AC,AC,SZR
JMP --- ;NOT ZERO
--- --- ;ZERO
10.Test an accumulator for -1.
COM# AC,AC,SZR
JMP --- ;NOT -1
--- --- ;-1
11.Test an accumulator for 2 or greater.
MOVZR# AC,AC,SNR
JMP --- ;LESS THAN 2
--- --- ;2 OR GREATER
&_ RC 3603 D-2\f
T_ 12. Assume it is known that AC contains 0, 1, 2, or 3.
Find out which one.
MOVZR# AC,AC,SEZ
JMP THREE ;WAS 3
MOV AC,AC,SNR
JMP ZERO ;WAS 0
MOVZR# AC,AC,SZR
JMP TWO ;WAS 2
--- --- ;WAS 1
13.Multiply an AC by the indicated value.
MOV ACX,ACX ;MULTIPLY BY 1
MOVZL ACX,ACX ;MULTIPLY BY 2
MOVZL ACX,ACY ;MULTIPLY BY 3
ADD ACY,ACX
ADDZL ACX,ACX ;MULTIPLY BY 4
MOV ACX,ACY ;MULTIPLY BY 5
ADDZL ACX,ACX
ADD ACY,ACX
MOVZL ACX,ACY ;MULTIPLY BY 6
ADDZL ACY,ACX
MOVZL ACX,ACY ;MULTIPLY BY 7
ADDZL ACY,ACY
SUB ACX,ACY ;IN ACY
ADDZL ACX,ACX ;MULTIPLY BY 8
MOVZL ACX,ACX
MOVZL ACX,ACY;MULTYPLY BY 9
ADDZL ACY,ACY
ADD ACY,ACX
MOV ACX,ACY ;MULTIPLY BY 10DD10UU
ADDZL ACX,ACX
ADDZL ACY,ACX
MOVZL ACX,ACY ;MULTIPLY BY 12DD10UU
ADDZL ACY,ACX
MOVZL ACX,ACX
MOVZL ACX,ACY ;MULTIPLY BY 18DD10UU
ADDZL ACY,ACY
ADDZL ACY,ACX
&_ RC 3603 D-3\f
T_ 14. Perform the inclusive OR of the operands in AC0 and
AC1. The result is placed in AC1. The carry bit is
unchanged.
COM 0,0
AND 0,1
ADC 0,1
15. Perform the exclusive OR of the operands in AC0 and
AC1. The result is placed in AC1. The contents of
AC2 and the carry bit are destroyed.
MOV 1,2
ANDZL 0,2
ADD 0,1
SUB 2,1
16. Move 30 words from locations 2000DD8UU-2035DD8UU to
locations 3000DD8UU-3035DD8UU. The auto-increment locations
are used to hold the source and destination addresses.
LDA 0,ADDRS ;SET UP SOURCE ADDRESS
STA 0,20
LDA 0,ADDRD ;SET UP DESTINATION ADDRESS
STA 0,21
LOOP: LDA 0,Æ20 ;INCREMENT SOURCE ADDRESS
; AND GET WORD
STA 0,Æ21 ;INCREMENT DESTINATION
; ADDRESS AND STORE WORD
DSZ CNT ;DECREMENT COUNT
JMP LOOP ;GO BACK FOR NEXT WORD
... ;SKIP HERE WHEN COUNT IS
; ZERO
...
ADDRS: 1777 ;SOURCE ADDRESS MINUS ONE
ADDRD: 2777 ;DESTINATION ADDRESS MINUS
; ONE
CNT: 36 ;WORD COUNT --36DD8 EQUALS 30DD10
&_ RC 3603 D-4 \f
T_ 17. Perform the following unsigned integer comparisons.
SUB# ACS,ACD,SZR ;SKIP IF CONTENTS OF ACS =
; CONTENTS OF ACD
SUB# ACS,ACD,SNR ;SKIP IF CONTENTS OF ACS =
; CONTENTS OF ACD
ADCZ# ACS,ACD,SNC ;SKIP IF CONTENTS OF ACS
; CONTENTS OF ACD
SUBZ# ACS,ACD,SNC ;SKIP IF CONTENTS OF ACS D-U
; CONTENTS OF ACD
SUBZ# ACS,ACD,SZC ;SKIP IF CONTENTS OF ACS
; CONTENTS OF ACD
ADCZ# ACS,ACD,SZC ;SKIP IF CONTENTS OF ACS D-U
; CONTENTS OF ACD
18. Compare the signed, two's complement integer contained in
ACS to 0.
MOV# ACS,ACS,SZR ;SKIP IF CONTENTS OF ACS EQ 0
MOV# ACS,ACS,SNR ;SKIP IF CONTENTS OF ACS NE 0
ADDO# ACS,ACS,SBN ;SKIP IF CONTENTS OF ACS GT 0
MOVL# ACS,ACS,SZC ;SKIP IF CONTENTS OF ACS GE 0
MOVL# ACS,ACS,SNC ;SKIP IF CONTENTS OF ACS LT 0
ADDO# ACS,ACS,SEZ ;SKIP IF CONTENTS OF ACS LE 0
19. Simulate the operation of the MULTIPLY instruction.
.MPYU: SUBC 0,0 ;CLEAR AC0, DON'T DISTURB CARRY
.MPYA: STA 3,.CB03 ;SAVE RETURN
LDA 3,.CB20 ;GET STEP COUNT
:CB99 MOVR 1,1,SNC ;CHECK NEXT MULTIPLIER BIT
MOVR 0,0SKP ;0 SHIFT
ADDZR 2,0 ;1 - ADD MULTIPLICAND AND SHIFT
INC 3,3,SZR ;COUNT STEP, COMPLEMENTING CARRY ON
; FINAL COUNT
JMP .CB99 ;ITERATE LOOP
MOVCR 1,1 ;SHIFT IN LAST LOW BIT (WHICH WAS
; COMPLEMENTED BY FINAL COUNT) AND
JMP Æ.CB03 ;RESTORE CARRY
.CB03: 0
.DB20: -20 ;16DD10UU STEPS
&_ RC 3603 D-6\f
T_ 20. Simulate the operation of the DIVIDE instruction.
.DIVI: SUB0,0 ;INTEGER DIVIDE CLEAR HIGH PART
.DIVU: STA 3,.CC03 ;SAVE RETURN
SUB# 2,0,SZC ;TEST FOR OVERFLOW
JMP .CC99 ;YES, EXIT(AC0 AC2)
LDA 3,.CC20 ;GET STEP COUNT
MOVZL 1,1 ;SHIFT DIVIDEND LOW PART
.CC98 MOVL 0,0 ;SHIFT DIVIDEND HIGH PART
SUB# 2,0,SZC ;DOES DIVISOR GO IN?
SUB 2,0 ;YES
MOVL 1,1 ;SHIFT DIVIDEND LOW PART
INC 3,3,SZC ;COUNT STEP
JMP CC98 ;ITERATE LOOP
SUB0 3,3,SKP ;DONE, CLEAR CARRY
.CC99 SUBZ 3,3 ;SET CARRY
JMP Æ.CC03 ;RETURN
.CC03 0
.CC20 20 ;16DD10UU STEPS
21. Load a byte from memory. The routine is called via a JSR.
The byte pointer for the requested byte is in AC2. The
requested byte is returned in the right half of AC0. The
left half of AC0 and the carry are set to 0. AC1 and AC2 are
unchanged. AC3 is destroyed.
LBYT: STA 3,LRET ;SAVE RETURN ADDRESS
LDA 3,MASK
MOVR 2,2,SNC ;TURN BYTE POINTER INTO WORD ADDRESS
; AND SKIP IF REQUEST BYTE IS RIGHT
; BYTE
MOVS 3,3 ;SWAP MASK IF REQUESTED BYTE IS LEFT
; BYTE
LDA 0,0,2 ;PLACE WORD IN AC0
AND 3,0,SNC ;MASK OFF UNWANTED BYTE AND SKIP IF
; SWAP IS NOT NEEDED
MOVS 0,0 ;SWAP REQUESTED BYTE INTO RIGHT HALF
; OF AC0
MOVL 2,2 ;RESTORE BYTE POINTER AND CARRY
JMP Æ LRET ;RETURN
LRET: 0 ;RETURN LOCATION
MASK: 377
&_ RC 3603 D-7\f
T_ 22. Store a byte in memory. The routine is called via a JRS. The
byte to be stored is in the right half of AC0 with the left
half of AC0 set to 0. The byte pointer is in AC2. The word
written is returned in AC0. AC1 and AC2 are unchanged. AC3
and the carry bit are destroyed.
SBYT: STA 3,SRET ;SAVE RETURN
STA 1,SAC1 ;SAVE AC1
LDA 3,MASK
MOVR 2,2,SNC ;CONVERT BYTE POINTER TO WORD
; ADDRESS AND SKIP IF BYTE IS TO BE
; RIGHT HALF
MOVS 0,0,SKP ;SWAP BYTE AND LEAVE MASK ALONE
MOVS 3,3 ;SWAP MASK
LDA 1,0,2 ;LOAD WORD THAT IS TO RECEIVE BYTE
AND 3,1 ;MASK OFF BYTE THAT IS TO RECEIVE
; NEW BYTE
ADD 1,0 ;ADD MEMORY WORD ON TOP OF NEW BYTE
STA 0,0,2 ;STORE WORD WITH NEW BYTE
MOVL 2,2 ;RESTORE BYTE POINTER AND CARRY
LDA 1,SAC1 ;RESTORE AC1
JMP Æ SRET ;RETURN
SRET: 0 ;RETURN LOCATION
SAC1: 0
MASK: 377
&_ RC 3603 D-8\f
T_ Appendix E I_N_S_T_R_U_C_T_I_O_N_ _E_X_E_C_U_T_I_O_N_ _T_I_M_E_S_
RC 3608 RC 3609
INSTRUCTION MNEMONIC 32K memory 16 K memory
LDA 1.6 s 1.4 s
STA 1.6 s 1.4 s
ISZ, DSZ 2.4 s 2.1 s
JMP 0.8 s 0.7 s
JSR 1.25 s 1.2 s
COM, NEG, MOV, INC 1.15 s 1.0 s
ADC, SUB, ADD, AND
Each level of Æ, add 0.85 s 0.75 s
Each autoindex, add 0.85 s 0.75 s
Base register addr, add 0 s 0 s
Shift R, L, add 0.3 s 0.3 s
Swap, add 0.9 s 0.9 s
If SKIP occurs, add 0.2 s 0.2 s
I/O INPUT (incl. READS, INTA) 1.85 s 1.81 s
I/O OUTPUT (MSKO) 2 s 2 s
NIO (INTEN, INTDS) 1.7 s 1.7 s
I/O SKIP 1.4 s 1.4 s
If SKIP occurs, add 0.2 s 0.2 s
For S, C and P, add 0 s 0 s
D_A_T_A_ _C_H_A_N_N_E_L_
DMA Input 1.9 s 1.9 s
DMA Output 1.8 s 1.8 s
DMA Increment 2.7 s 2.6 s
DMA Add to Memory 3.2 s 3.2 s
&_
E-1\f
CPU 708
125K FETCH DEFER LEFT RIGHT RESET STOP 0 10 11 12 13 14 15 ENABLE TOP
CPU-STATUS PARITY ERROR
64K
FRONT FRAME OF CPU BOARD \f
i
I_N_D_H_O_L_D_S_F_O_R_T_E_G_N_E_L_S_E_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _S_I_D_E_
1. INTRODUKTION .......................................... 1
2. BETJENINGSKNAPPER ..................................... 2
3. BETJENINGSVEJLEDNING .................................. 5
4. GENEREL TASTATURBESKRIVELSE ........................... 6
4.1 Tegntaster ....................................... 6
4.2 Programtaster .................................... 6
4.3 Terminaltaster ................................... 7
5. RC822 TASTATURET ...................................... 8
5.1 Programtaster .................................... 8
5.2 Terminaltaster ................................... 8
6. RC828 TASTATURET ...................................... 11
6.1 Programtaster .................................... 11
6.2 Terminaltaster ................................... 11
\f
ii
\f
1_._ _ _ _ _ _ _ _ _I_N_T_R_O_D_U_K_T_I_O_N_ 1.
Figur 1: Dataskærm med tastatur.
De konsoller/terminaler, der beskrives i denne betjeningsvejled-
ning, er alle baseret på samme type dataskærm, hvorimod tastatu-
ret har forskelligt layout og forskellige funktionelle taster
afhængig af konsollens/terminalens specifikke RC produktnummer.
En dataskærm benævnes ofte >VDU> (Visuel Display Unit).
\f
F_ 2_._ _ _ _ _ _ _ _ _B_E_T_J_E_N_I_N_G_S_K_N_A_P_P_E_R_ 2.
Figur 2: Betjeningsknapper.
POWER ON/OFF - dataskærmen er forsynet med en af-
bryder på højre side.
Når dataskærmen anvendes som kon-
sol, kan afbryderen stilles i ON
position første gang konsollen be-
tjenes og derefter forblive i ON
positionen. Dataskærmen vil så
blive tændt/slukket, når systemet
tændes/slukkes.
\f
1) Kontaktvælgere - når en kontakt trykkes ned, vælges
blandt mulighederne som beskrevet
nedenfor. Kontakterne er selvlåsen-
de, tryk n gang mere for at udløse
kontakten.
TAPE - kun til servicebrug.
FULL DUP (D_u_p_lex) - trykket ind: fuld duplex;
trykket ud: halv duplex.
DATA RATE - med denne kontakt kan der vælges
mellem to forudindstillede transmis-
sionshastigheder.
Kontakten betjenes normalt ikke af
operatøren, idet indstillingen er
systembestemt.
EIA - kun til servicebrug.
Trykket ind, bevirker denne kon-
takt, at EIA (eller V.24) signaler
vælges.
2) Indikatorer - når en indikator tændes, betyder
dette:
CD (Carrier Detect): kommunikationsudstyret indikerer,
at kommunikationsforbindelsen er
etableret.
RS (Ready to Send): som CD, men med betydningen, at det
nu er muligt at sende fra tastatu-
ret.
Både CD og RS skal være tændt, når
terminalen er on-line.
\f
3) Indstilling vedr. - disse to justeringsknapper gør det
skærmbilledet muligt at justere lys- og kontrast-
forhold på skærmen.
- justeringsknap
nærmest forsiden: indstilling af lysstyrke.
(Kan være betegnet BRIGHTNESS)
- justeringsknap
nærmest bagsiden: indstilling af kontrast.
(Kan være betegnet CONTRAST)
4) Indstilling vedr. - med justeringsknappen indstilles
lydkilde lydstyrken af det signal, der høres
fra den indbyggede højtaler.
Lydsignalet høres, når der modtages
et BELL kodetegn.
\f
F_ 3_._ _ _ _ _ _ _ _ _B_E_T_J_E_N_I_N_G_S_V_E_J_L_E_D_N_I_N_G_ 3.
Terminalen tændes med POWER ON/OFF kontakten. Anvendes dataskær-
men som konsol, tændes/slukkes den, når systemet tændes/slukkes,
forudsat POWER kontakten forbliver i ON stilling efter første
betjening.
Kontaktvælgerne skal normalt stå i følgende stillinger:
TAPE : ud
FULL DUP : ind, eller som specificeret
DATA RATE : som specificeret
EIA : ind
Når kommunikationsudstyret er driftsklart, vil først CD og der-
næst også RS indikatoren lyse. Sålænge terminalen er on-line,
skal begge fortsat lyse.
Hvorledes man kommer i forbindelse med systemet og information
iøvrigt om terminalbrug findes i de publikationer, der vedrører
programmelsystemer og deres anvendelse.
Første gang terminalen betjenes og ellers, når det er belejligt,
ved start af arbejdet, udføres følgende kontrolrutiner:
1. Dataskærmens funktion kontrolleres, idet FULL DUP kontaktvæl-
geren trykkes ud, et tegn udvælges og tasten trykkes ned -
tryk samtidig REPT tasten ned. Skærmen skal nu fyldes med det
pågældende tegn. (NB: Husk at sætte FULL DUP kontaktvælgeren i
korrekt stilling efter denne kontrol.) Proceduren er kun
anvendelig på RC822.
2. Indstil lysstyrken, så punktdannelsen ikke længere fornemmes.
Kontrastreguleringen indstilles dernæst, så tegnene fremtræder
mest behageligt. En omhyggelig indstilling lønner sig, idet
gode lys- og kontrastforhold mindsker betjeningstræthed - og
husk, indstillingen bør ændres, såsnart lysforholdene omkring
dataskærmen ændres mærkbart.
Indstillingen af lys- og kontrastforhold foretages med regule-
ringsknapperne på højre side af terminalen.
\f
F_4_._ _ _ _ _ _ _ _ _G_E_N_E_R_E_L_ _T_A_S_T_A_T_U_R_B_E_S_K_R_I_V_E_L_S_E_ 4.
De forskellige RC produktnumre har hver deres specifikke tasta-
tur. De forskellige tastaturer, der benyttes sammen med den
beskrevne VDU, er omtalt i de følgende afsnit.
Fælles for alle tastaturtyper er, at de omfatter tre slags
taster:
- tegntaster
- programtaster
- terminaltaster
4_._1_ _ _ _ _ _ _ _T_e_g_n_t_a_s_t_e_r_ 4.1
Tegntasterne virker tilsvarende som tegntaster på en almindelig
skrivemaskine, dvs. ved at trykke på en af disse taster sendes et
tegn til systemet svarende til indgraveringen på tasten. Selve
layoutet er også det samme som anvendes på skrivemaskiner.
Forskellige layout kan forekomme afhængig af de nationale
tegnsæt, der anvendes.
4_._2_ _ _ _ _ _ _ _P_r_o_g_r_a_m_t_a_s_t_e_r_ 4.2
Det er vigtigt at mærke sig, at disse taster vil virke forskel-
ligt fra system til system. Konkret information om virkemåden og
brugen af disse taster skal således læses i de publikationer, der
vedrører programmelsystemer og deres anvendelse. Programtasterne
bliver i denne vejledning omtalt som de generelt forefindes
uagtet mulige options.
\f
4_._3_ _ _ _ _ _ _ _T_e_r_m_i_n_a_l_t_a_s_t_e_r_ 4.3
Terminaltasterne bruges til almindelige skrivemaskinefunktioner,
cursorstyring, osv. På en universel dataskærmtype vil der typisk
være få programtaster og mange terminaltaster modsat en specifik
dataskærmtype, hvor det omvendte vil være tilfældet. Terminaltas-
ternes funktioner (især cursorstyretasterne) kan være afhængige
af programmelsystemet.
\f
F_ 5_._ _ _ _ _ _ _ _ _R_C_8_2_2_ _T_A_S_T_A_T_U_R_E_T_ 5.
5_._1_ _ _ _ _ _ _ _P_r_o_g_r_a_m_t_a_s_t_e_r_ 5.1
ESCAPE
LINE FEED
RETURN - funktion programmelbestemt.
RUB OUT
BREAK
BACK SPACE
CTRL - bruges til at sende styrekoder, der
ikke er defineret med egen taste.
CTRL holdes nedtrykket og samtidig
trykkes en alfanumerisk taste ned,
- en styrekode svarende til den på-
gældende alfanumeriske taste trans-
mitteres så. Hvilket alfanumerisk
tegn, der i en given situation skal
bruges og hvilken funktion det ud-
løser, er programmelbestemt.
5_._2_ _ _ _ _ _ _ _T_e_r_m_i_n_a_l_t_a_s_t_e_r_ 5.2
SHIFT - bruges sammen med alfabetiske og nu-
meriske taster; foranlediger skift
til store bogstaver, respektive
tegn indeholdt i det "øvre tegn-
sæt".
ALPHA LOCK - tilsvarende SHIFT skiftes til "øvre
tegnsæt" på alfabetiske taster,
hvorimod numeriske taster ikke be-
røres. Selvlåsende, udløses ved at
trykke n gang mere.
\f
REPT (R_e_p_eat_) - nedtrykkes denne taste, vil et
tegn, der aktiveres dernæst, blive
gentaget sålænge REPT holdes nede.
HOME - returnerer cursor til første tegn,
første linie.
-' - cursor flyttes en tegnposition til
(FORWARD CURSOR) højre; overskrides linielængden,
fortsættes i første position på
næste linie. Flyttekoden er ikke-
destruktiv, dvs. ingen tegn slet-
tes, selvom cursoren flyttes via en
>optaget> tegnposition.
<- - som FORWARD CURSOR, men flytning en
(BACK CURSOR) tegnposition til venstre.
- flytter cursor en linie op; har
(UP ROW CURSOR) cursor nået øverste linie, forbli-
ver den der.
- som UP ROW CURSOR, men flytning
(DOWN ROW CURSOR) linievis nedad; har cursor nået
nederste linie, vil næste aktive-
ring forårsage, at linierne flyttes
en linie op, og den nederste linie
efterlades som en blank linie.
TAB - horisontal tabulation, normalt
springvis til hver 4. tegnposition,
- springpositionerne er fast ind-
stillede og afhænger således ikke
af cursors startposition.
ERAS EOL - sletter data fra cursor position
(E_r_a_se to E_nd o_f L_ine) til liniens slutposition.
\f
ERAS EOS - sletter data fra cursor position
(E_r_a_se to E_nd o_f S_creen) frem til skærmens slutposition.
CLEAR - sletter alle data og flytter cur-
sor til første tegn, første linie.
PRINT - en skriver kan tilsluttes termina-
len (som option). Aktiveres PRINT
tasten, fås udskrift af alle ind-
og uddata.
PRINT OFF - afbryder forbindelsen til skrive-
ren.
TAPE - kun til serviceformål; selvlåsende,
udløses ved at trykke n gang mere
Bevirker at alle ankommende tegn
vises på skærmen, også styrekoder.
LOAD TAPE - kun til serviceformål.
\f
F_ 6_._ _ _ _ _ _ _ _ _R_C_8_2_8_ _T_A_S_T_A_T_U_R_E_T_ 6.
6_._1_ _ _ _ _ _ _ _P_r_o_g_r_a_m_t_a_s_t_e_r 6.1
ESCAPE
CLEAR
SUB FORM
DUP
CHAR
REC - funktion programmelbestemt.
FIELD
REC REL
ERROR REL
ENTER
BY-PASS
RECORD
LOG IN
6_._2_ _ _ _ _ _ _ _T_e_r_m_i_n_a_l_t_a_s_t_e_r_ 6.2
SHIFT - bruges sammen med alfabetiske og
numeriske taster; foranlediger
skift til store bogstaver, respek-
tive tegn indeholdt i det "øvre
tegnsæt".
SHIFT LOCK - tilsvarende SHIFT skiftes til "øvre
tegnsæt". Selvlåsende, udløses ved
at trykke n gang mere.
\f
\f
i
I_N_D_H_O_L_D_S_F_O_R_T_E_G_N_E_L_S_E_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _S_I_D_E_
1. INTRODUKTION .......................................... 1
2. BETJENINGSKNAPPER ..................................... 2
3. BETJENINGSVEJLEDNING .................................. 5
4. GENEREL TASTATURBESKRIVELSE ........................... 7
4.1 Tegntaster ....................................... 7
4.2 Programtaster .................................... 7
4.3 Terminaltaster ................................... 8
5. RC819 TASTATURET ...................................... 9
5.1 Programtaster .................................... 9
5.2 Terminaltaster ................................... 9
6. RC822B TASTATURET ..................................... 11
6.1 Programtaster .................................... 11
6.2 Terminaltaster ................................... 11
7. RC828B TASTATURET ..................................... 14
7.1 Programtaster .................................... 14
7.2 Terminaltaster ................................... 14
\f
ii
\f
1_._ _ _ _ _ _ _ _ _I_N_T_R_O_D_U_K_T_I_O_N_ 1.
Figur 1: Dataskærm med tastatur.
De konsoller/terminaler, der beskrives i denne betjeningsvejled-
ning, er alle baseret på samme type dataskærm, hvorimod tastatu-
ret har forskelligt layout og forskellige funktionelle taster
afhængig af konsollens/terminalens specifikke RC produktnummer.
En dataskærm benævnes ofte >VDU> (Visuel Display Unit).
\f
F_ 2_._ _ _ _ _ _ _ _ _B_E_T_J_E_N_I_N_G_S_K_N_A_P_P_E_R_ 2.
Figur 2: Betjeningsknapper.
POWER ON/OFF - dataskærmen er forsynet med en af-
bryder på højre side.
Når dataskærmen anvendes som kon-
sol, kan afbryderen stilles i ON
position første gang konsollen be-
tjenes og derefter forblive i ON
positionen. Dataskærmen vil så
blive tændt/slukket, når systemet
tændes/slukkes.
1) Indikatorer - når en indikator tændes, betyder
dette:
PR (Program Ready): Systemet indikerer, at det er parat
til at betjene brugeren.
\f
CD (Carrier Detect): Kommunikationsudstyret indikerer,
at kommunikationsforbindelsen er
etableret.
RS (Ready to Send): Som CD, men med betydningen, at det
nu er muligt at sende fra tastatu-
ret.
Både CD og RS skal være tændt, når
terminalen er on-line.
2) BAUD RATE - når kontakten drejes, kan forskel-
omskifter lige datatransmissionshastigheder
vælges. Betjenes normalt ikke af
operatøren, idet indstillingen er
systembestemt.
3) Kontaktvælgere - når en kontakt trykkes ned, vælges
blandt mulighederne som beskrevet
nedenfor. Kontakterne er selvlåsen-
de, tryk n gang mere for at udløse
kontakten.
TAPE - kun til servicebrug.
DUP (D_u_p_lex) - trykket ind: fuld duplex;
trykket ud: halv duplex.
EIA - kun til servicebrug.
Trykket ind, bevirker denne kon-
takt, at EIA (eller V.24) signaler
vælges.
SPLIT - bruges ikke
uden betegnelse - bruges ikke
\f
LOCAL - kun til servicebrug
PARITY ODD - trykket ind: ulige paritet;
trykket ud : lige paritet.
PARITY ON - trykket ind: med paritetskontrol;
trykket ud : uden paritetskontrol.
Kontakterne vedrørende paritet be-
tjenes normalt ikke af operatøren,
idet indstillingen er systembe-
stemt.
4) Indstilling vedr. - disse to justeringsknapper gør det
skærmbilledet muligt at justere lys- og kontrast-
forhold på skærmen.
- justeringsknap
nærmest forsiden: indstilling af lysstyrke.
(Kan være betegnet BRIGHTNESS)
- justeringsknap
nærmest bagsiden: indstilling af kontrast.
(Kan være betegnet CONTRAST)
5) Indstilling vedr. - med justeringsknappen indstilles
lydkilde lydstyrken af det signal, der høres
fra den indbyggede højtaler.
Bemærk: Justeringsknappen kan være
placeret på tastaturets bagside.
Lydsignalet høres, når der modtages
et BELL kodetegn.
På RC819 og RC828B benyttes højta-
leren endvidere til at frembringe
de klik-lyde, der høres, når tas-
terne betjenes (denne funktion kan
afbrydes med en kontakt).
\f
F_ 3_._ _ _ _ _ _ _ _ _B_E_T_J_E_N_I_N_G_S_V_E_J_L_E_D_N_I_N_G_ 3.
Terminalen tændes med POWER ON/OFF kontakten. Anvendes dataskær-
men som konsol, tændes/slukkes den, når systemet tændes/slukkes,
forudsat POWER kontakten forbliver i ON stilling efter første
betjening.
Kontaktvælgerne skal normalt stå i følgende stillinger:
TAPE : ud
DUP : ind, eller som specificeret
EIA : ind
SPLIT : ud
uden betegnelse : ud
LOCAL : ud
PARITY ODD : som specificeret
PARITY ON : som specificeret
Når kommunikationsudstyret er driftsklart, vil først CD og der-
næst også RS indikatoren lyse. Sålænge terminalen er on-line, skal
begge fortsat lyse.
Hvorledes man kommer i forbindelse med systemet og information
iøvrigt om terminalbrug findes i de publikationer, der vedrører
programmelsystemer og deres anvendelse.
Første gang terminalen betjenes og ellers, når det er belejligt,
ved start af arbejdet, udføres følgende kontrolrutiner:
1. Dataskærmens funktion kontrolleres, idet DUP kontaktvælgeren
trykkes ud, et tegn udvælges og tasten trykkes ned - tryk
samtidig REPT tasten ned. På RC819/828B kan man nøjes med at
holde tegntasten trykket ned, idet disse modeller har auto-
repeat. Skærmen skal nu fyldes med det pågældende tegn. (NB:
Husk at sætte DUP kontaktvælgeren i korrekt stilling efter
denne kontrol.)
\f
2. Indstil lysstyrken, så punktdannelsen ikke længere fornemmes.
Kontrastreguleringen indstilles dernæst, så tegnene fremtræder
mest behageligt. En omhyggelig indstilling lønner sig, idet
gode lys- og kontrastforhold mindsker betjeningstræthed - og
husk, indstillingen bør ændres, såsnart lysforholdene omkring
dataskærmen ændres mærkbart.
Indstillingen af lys- og kontrastforhold foretages med regule-
ringsknapperne på højre side af terminalen.
\f
F_4_._ _ _ _ _ _ _ _ _G_E_N_E_R_E_L_ _T_A_S_T_A_T_U_R_B_E_S_K_R_I_V_E_L_S_E_ 4.
De forskellige RC produktnumre har hver deres specifikke tasta-
tur. De forskellige tastaturer, der benyttes sammen med den
beskrevne VDU, er omtalt i de følgende afsnit.
Fælles for alle tastaturtyper er, at de omfatter tre slags
taster:
- tegntaster
- programtaster
- terminaltaster
4_._1_ _ _ _ _ _ _ _T_e_g_n_t_a_s_t_e_r_ 4.1
Tegntasterne virker tilsvarende som tegntaster på en almindelig
skrivemaskine, dvs. ved at trykke på en af disse taster sendes et
tegn til systemet svarende til indgraveringen på tasten. Selve
layoutet er også det samme som anvendes på skrivemaskiner. For-
skellige layout kan forekomme afhængig af de nationale tegnsæt,
der anvendes.
4_._2_ _ _ _ _ _ _ _P_r_o_g_r_a_m_t_a_s_t_e_r_ 4.2
Det er vigtigt at mærke sig, at disse taster vil virke forskel-
ligt fra system til system. Konkret information om virkemåden og
brugen af disse taster skal således læses i de publikationer, der
vedrører programmelsystemer og deres anvendelse. Programtasterne
bliver i denne vejledning omtalt som de generelt forefindes
uagtet mulige options.
\f
4_._3_ _ _ _ _ _ _ _T_e_r_m_i_n_a_l_t_a_s_t_e_r_ 4.3
Terminaltasterne bruges til almindelige skrivemaskinefunktioner,
cursorstyring, osv. På en universel dataskærmtype vil der typisk
være få programtaster og mange terminaltaster modsat en specifik
dataskærmtype, hvor det omvendte vil være tilfældet. Terminaltas-
ternes funktioner (især cursorstyretasterne) kan være afhængige
af programmelsystemet.
\f
F_ 5_._ _ _ _ _ _ _ _ _R_C_8_1_9_ _T_A_S_T_A_T_U_R_E_T_ 5.
5_._1_ _ _ _ _ _ _ _P_r_o_g_r_a_m_t_a_s_t_e_r_ 5.1
ESC (E_s_c_ape)
BELL
LOCAL ATT
DELETE LINE- funktion programmelbestemt.
RETURN
DELETE CHAR
RUB OUT
CTRL - bruges til at sende styrekoder, der
ikke er defineret med egen taste.
CTRL holdes nedtrykket og samtidig
trykkes en alfanumerisk taste ned,
- en styrekode svarende til den på-
gældende alfanumeriske taste trans-
mitteres så. Hvilket alfanumerisk
tegn, der i en given situation skal
bruges og hvilken funktion det ud-
løser, er programmelbestemt.
5_._2_ _ _ _ _ _ _ _T_e_r_m_i_n_a_l_t_a_s_t_e_r_ 5.2
SHIFT - bruges sammen med alfabetiske og nu-
meriske taster; foranlediger skift
til store bogstaver, respektive
tegn indeholdt i det "øvre tegn-
sæt".
SHIFT LOCK - tilsvarende SHIFT skiftes til "øvre
tegnsæt" på alfabetiske taster,
hvorimod numeriske taster ikke be-
røres. Selvlåsende, udløses ved at
trykke n gang mere.
\f
PRINT ON - en skriver kan tilsluttes
terminalen (som option). Aktiveres
PRINT ON tasten, fås udskrift af
alle ind- og uddata.
PRINT OFF - afbryder forbindelsen til
skriveren.
TAPE - kun til serviceformål; selvlåsende,
udløses ved at trykke n gang mere.
Bevirker at alle ankommende tegn
vises på skærmen, også styrekoder.
FF (Form Feed) - funktion i forbindelse med tilslut-
tet skriver; bevirker sideskift.
LF (Line Feed) - funktion i forbindelse med tilslut-
tet skriver; bevirker linieskift.
Auto-repeat - tastaturet har automatisk repeti-
tion, når en taste holdes nedtryk-
ket længere end ca. 1 sek.
\f
F_ 6_._ _ _ _ _ _ _ _ _R_C_8_2_2_B_ _T_A_S_T_A_T_U_R_E_T_ 6.
6_._1_ _ _ _ _ _ _ _P_r_o_g_r_a_m_t_a_s_t_e_r_ 6.1
ESCAPE
LINE FEED
RETURN - funktion programmelbestemt.
RUB OUT
BREAK
BACK SPACE
CTRL - bruges til at sende styrekoder, der
ikke er defineret med egen taste.
CTRL holdes nedtrykket og samtidig
trykkes en alfanumerisk taste ned,
- en styrekode svarende til den på-
gældende alfanumeriske taste trans-
mitteres så. Hvilket alfanumerisk
tegn, der i en given situation skal
bruges og hvilken funktion det ud-
løser, er programmelbestemt.
6_._2_ _ _ _ _ _ _ _T_e_r_m_i_n_a_l_t_a_s_t_e_r_ 6.2
SHIFT - bruges sammen med alfabetiske og nu-
meriske taster; foranlediger skift
til store bogstaver, respektive
tegn indeholdt i det "øvre tegn-
sæt".
ALPHA LOCK - tilsvarende SHIFT skiftes til "øvre
tegnsæt" på alfabetiske taster,
hvorimod numeriske taster ikke be-
røres. Selvlåsende, udløses ved at
trykke n gang mere.
\f
REPT (R_e_p_eat_) - nedtrykkes denne taste, vil et
tegn, der aktiveres dernæst, blive
gentaget sålænge REPT holdes nede.
HOME - returnerer cursor til første tegn,
første linie.
-' - cursor flyttes en tegnposition til
(FORWARD CURSOR) højre; overskrides linielængden,
fortsættes i første position på
næste linie. Flyttekoden er ikke-
destruktiv, dvs. ingen tegn slet-
tes, selvom cursoren flyttes via en
>optaget> tegnposition.
<- - som FORWARD CURSOR, men flytning en
(BACK CURSOR) tegnposition til venstre.
- flytter cursor en linie op; har
(UP ROW CURSOR) cursor nået øverste linie, forbli-
ver den der.
- som UP ROW CURSOR, men flytning
(DOWN ROW CURSOR) linievis nedad; har cursor nået
nederste linie, vil næste aktive-
ring forårsage, at linierne flyttes
en linie op, og den nederste linie
efterlades som en blank linie.
TAB - horisontal tabulation, normalt
springvis til hver 4. tegnposition,
- springpositionerne er fast ind-
stillede og afhænger således ikke
af cursors startposition.
ERAS EOL - sletter data fra cursor position
(E_r_a_se to E_nd o_f L_ine) til liniens slutposition.
\f
ERAS EOS - sletter data fra cursor position
(E_r_a_se to E_nd o_f S_creen) frem til skærmens slutposition.
CLEAR - sletter alle data og flytter cur-
sor til første tegn, første linie.
PRINT - en skriver kan tilsluttes termina-
len (som option). Aktiveres PRINT
tasten, fås udskrift af alle ind-
og uddata.
PRINT OFF - afbryder forbindelsen til skrive-
ren.
TAPE - kun til serviceformål; selvlåsende,
udløses ved at trykke n gang mere
Bevirker at alle ankommende tegn
vises på skærmen, også styrekoder.
LOAD TAPE - kun til serviceformål.
\f
F_ 7_._ _ _ _ _ _ _ _ _R_C_8_2_8_B_ _T_A_S_T_A_T_U_R_E_T_ 7.
7_._1_ _ _ _ _ _ _ _P_r_o_g_r_a_m_t_a_s_t_e_r 7.1
ESCAPE
CLEAR
SUB FORM
DUP
CHAR
REC - funktion programmelbestemt.
FIELD
REC REL
ERROR REL
ENTER
BY-PASS
RECORD
LOG IN
7_._2_ _ _ _ _ _ _ _T_e_r_m_i_n_a_l_t_a_s_t_e_r_ 7.2
SHIFT - bruges sammen med alfabetiske og
numeriske taster; foranlediger
skift til store bogstaver, respek-
tive tegn indeholdt i det "øvre
tegnsæt".
SHIFT LOCK - tilsvarende SHIFT skiftes til "øvre
tegnsæt". Selvlåsende, udløses ved
at trykke n gang mere.
Auto-repeat - tastaturet har automatisk repeti-
tion, når en taste holdes nedtryk-
ket længere end ca. 1 sek.
\f
«eof»