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Length: 4608 (0x1200)
Types: RcTekst
Names: »99109820.WP«
└─⟦dedaa6eab⟧ Bits:30005866/disk1.imd Dokumenter i RcTekst format (RCSL 99-1-*)
└─⟦this⟧ »99109820.WP«
╱04002d4e0a0006000000000301413100000000000000000000000000000000000000000000000000050f19232d37414b555f69737d8791ff04╱ ┆06┆i↲ ↲ ┆a1┆TABLE OF CONTENTS┆05┆PAGE↲ ↲ 1. GENEREL ................................................. 1↲ ════════════════════════════════════════════════════════════════════════ ↓ ┆06┆ii↲ ════════════════════════════════════════════════════════════════════════ ↓ ┆14┆┆b3┆┆b0┆┆a1┆┆e1┆┆f0┆┆06┆┆0b┆┆06┆↲ ┆a1┆┆b0┆1. GENEREL↲ ↲ This manual contains the drawings for MEM752, which is used as ↓ the main memory (256k byte) in the RC750 system.↲ ↲ ════════════════════════════════════════════════════════════════════════ ↓ ┆a1┆┆b0┆Signal name┆06┆Description┆05┆↲ ↲ MD0-15 Memory data bus.┆05┆↓ ↲ RC0-8 ┆84┆Time multiplexed row and colomn ↓ ┆19┆┆9b┆┄┄addresses.↲ ↲ -,REFR Referesh request.↲ ↲ -,WELO Write enable, low byte.↲ ↲ -,WEHI Write enable, high byte.↲ ↲ RASEN Row address strobe.↲ ↲ -,CAS Colomn address strobe.↲ ↲ -,RESET Reset signal from CPU.↲ ↲ A16-19 memory address signals.↲ ↲ ════════════════════════════════════════════════════════════════════════ ↓ ↲ ════════════════════════════════════════════════════════════════════════ ↓ ┆a1┆┆b0┆Signal name┆06┆Description┆05┆↲ ↲ MDPOUT0 Stored parity bit 0↲ ↲ MDPOUT1 Stored parity bit 1↲ ↲ -,MEMIDENT0-1 ┆84┆Memory size identification signals.↲ ↲ ════════════════════════════════════════════════════════════════════════ ↓ ↲ ════════════════════════════════════════════════════════════════════════ ↓ ┆b0┆┆a1┆Signal name┆06┆Description┆05┆↲ ↲ MDPOUT0-1 Memory parity bits.↲ ↲ ════════════════════════════════════════════════════════════════════════ ↓ ↲ ════════════════════════════════════════════════════════════════════════ ↓ ┆b0┆┆a1┆Signal name┆06┆Description┆05┆↲ ↲ -,RAS0 ┆84┆Row address strobe in the address ↓ ┆19┆┆9b┆┄┄space: 00000H - 1FFFFH.↲ ↲ -,RAS1 ┆84┆Row address strobe in the address ↓ ┆19┆┆9b┆┄┄space: 20000H - 3FFFFH.↲ ↲ -,RAS2 ┆84┆Row address strobe in the address ↓ ┆19┆┆9b┆┄┄space: 40000H - 5FFFFH.↲ ↲ -,RAS3 ┆84┆Row address strobe in the address ↓ ┆19┆┆9b┆┄┄space: 60000H - 7FFFFH.↲ ↲ -,RAS4 ┆84┆Row address strobe in the address ↓ ┆19┆┆9b┆┄┄space: 80000H - 9FFFFH.↲ ↲ -,RAS5 ┆84┆Row address strobe in the address ↓ ┆19┆┆9b┆┄┄space: A0000H - BFFFFH.↲ ↲ -,RASXT ┆84┆Row address strobe in the address ↓ ┆19┆┆9b┆┄┄space: C0000H - FFFFFH.↲ ↲ -,PERROR0 ┆84┆Parity error signal.↲ ↲ ════════════════════════════════════════════════════════════════════════ ↓ ↲ ════════════════════════════════════════════════════════════════════════ ↓ ┆b0┆┆a1┆Signal name┆06┆Description┆05┆↲ ↲ MDPIN0 ┆84┆Memory parity signal generated from ↓ ┆19┆┆9b┆┄┄MD0-7.↲ ↲ MDPIN1 ┆84┆MEMORY PARITY SIGNAL GENERATED FROM ↓ ┆19┆┆9b┆┄┄MD8-15.↲ ↲ PU1 Pull-up level.↲ ↲ -,WE ┆84┆Write enable signal used by the parity ↓ ┆19┆┆9b┆┄┄error detect circuit.↲ ↲ Parity ┆84┆Parity error signal to the CPU. ↓ ┆19┆┆9b┆┄┄Generates NMI-interrupt signals.↲ ↲ ════════════════════════════════════════════════════════════════════════ ↓ ↓ ════════════════════════════════════════════════════════════════════════ ↓ ┆14┆┆b3┆┆b0┆┆a1┆┆e1┆┆f0┆┆06┆┆0b┆┆06┆↲ ┆a1┆┆b0┆1. GENEREL↲ ↲ This manual contains the drawings for MEM752, which is used as ↓ the main memory (256k byte) in the RC750 system.↲ ↲ ════════════════════════════════════════════════════════════════════════ ↓ ┆a1┆┆b0┆Signal name┆06┆Description┆05┆↲ ↲ MD0-15 Memory data bus.┆05┆↓ ↲ RC0-8 ┆84┆Time multiplexed row and colomn ↓ ┆19┆┆9b┆┄┄addresses.↲ ↲ -,REFR Referesh request.↲ ↲ -,WELO Write enable, low byte.↲ ↲ -,WEHI Write enable, high byte.↲ ↲ RASEN Row address strobe.↲ ↲ -,CAS Colomn address strobe.↲ ↲ -,RESET Reset signal from CPU.↲ ↲ A16-19 memory address signals.↲ ↲ ════════════════════════════════════════════════════════════════════════ ↓ ↲ ════════════════════════════════════════════════════════════════════════ ↓ ┆a1┆┆b0┆Signal name┆06┆Description┆05┆↲ ↲ MDPOUT0 Stored parity bit 0↲ ↲ MDPOUT1 Stored parity bit 1↲ ↲ -,MEMIDENT0-1 ┆84┆Memory size identification signals.↲ ↲ ════════════════════════════════════════════════════════════════════════ ↓ ↲ ════════════════════════════════════════════════════════════════════════ ↓ ┆b0┆┆a1┆Signal name┆06┆Description┆05┆↲ ↲ MDPOUT0-1 Memory parity bits.↲ ↲ ════════════════════════════════════════════════════════════════════════ ↓ ↲ ════════════════════════════════════════════════════════════════════════ ↓ ┆b0┆┆a1┆Signal name┆06┆Description┆05┆↲ ↲ -,RAS0 ┆84┆Row address strobe in the address ↓ ┆19┆┆9b┆┄┄space: 00000H - 1FFFFH.↲ ↲ -,RAS1 ┆84┆Row address strobe in the address ↓ ┆19┆┆9b┆┄┄space: 20000H - 3FFFFH.↲ ↲ -,RAS2 ┆84┆Row address strobe in the address ↓ ┆19┆┆9b┆┄┄space: 40000H - 5FFFFH.↲ ↲ -,RAS3 ┆84┆Row address strobe in the address ↓ ┆19┆┆9b┆┄┄space: 60000H - 7FFFFH.↲ ↲ -,RAS4 ┆84┆Row address strobe in the address ↓ ┆19┆┆9b┆┄┄space: 80000H - 9FFFFH.↲ ↲ -,RAS5 ┆84┆Row address strobe in the address ↓ ┆19┆┆9b┆┄┄space: A0000H - BFFFFH.↲ ↲ -,RASXT ┆84┆Row address strobe in the address ↓ ┆19┆┆9b┆┄┄space: C0000H - FFFFFH.↲ ↲ -,PERROR0 ┆84┆Parity error signal.↲ ↲ ════════════════════════════════════════════════════════════════════════ ↓ ↲ ════════════════════════════════════════════════════════════════════════ ↓ ┆b0┆┆a1┆Signal name┆06┆Description┆05┆↲ ↲ MDPIN0 ┆84┆Memory parity signal generated from ↓ ┆19┆┆9b┆┄┄MD0-7.↲ ↲ MDPIN1 ┆84┆MEMORY PARITY SIGNAL GENERATED FROM ↓ ┆19┆┆9b┆┄┄MD8-15.↲ ↲ PU1 Pull-up level.↲ ↲ -,WE ┆84┆Write enable signal used by the parity ↓ ┆19┆┆9b┆┄┄error detect circuit.↲ ↲ Parity ┆84┆Parity error signal to the CPU. ↓ ┆19┆┆9b┆┄┄Generates NMI-interrupt signals.↲ ↲ ════════════════════════════════════════════════════════════════════════ ↓ ↓ ┆1a┆┆1a┆tion┆05┆ly hit in order to type, f