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F_ PREFACE

The RC 8000 Computer Family is a family of medium scale general
purpose computers designed and manufactured by A/S Regnecentra-
len. The models in the family share a common architecture with an
asynchronous unified bus giving full compatibility with respect
to peripheral devices and allowing multi CPU configuration. The
common instruction set includes multiply/divide and floating
point arithmetic and support for mutually protected multiprogram-
ming. The models differ in CPU implementation and in physical
specification resulting in different sets of instruction execu-
tion times and different configuration possibilities.

This manual provides the common basic programming information for
programmers and users of the RC 8000 Computers:

- Chapter 1 lists the common specifications.
- Chapter 2 contains a survey of design features and gives a
preliminary introduction to concepts used in chapters 3-9 in
an attempt to reduce the need for forward references during
the first sequential reading of these.
- Chapters 3-5 describe data formats, instruction format, memory
addressing and arithmetic.
- Chapter 6 describes the multiprogrammming facilities.
- Chapter 7 describes the facilities for program error
diagnostis and debugging.
- Chapter 8 describes the input/output control.
- Chapter 9 describes the power restart and autoload facilities.
- Chapter 10 completes the picture with a formal algorithmic
description of the information in the preceeding chapters.

Although the manual contains hints and examples of efficient use
of the instruction set, no attempt is made to teach programming
techniques.

Instruction execution times and other model specific information
are given in the General Information Manual for each model.

The function of peripheral devices is described in separate
manuals. \f

TABLE OF CONTENTS

PREFACE Page 11

1 RC 8000 SPECIFICATIONS 12

2 DESIGN FEATURES 14
2.1 Operand Length 14
2.2 Registers and Addressing 14
2.2.1 Registers Structure 14
2.2.2 Program Relocation 17
2.2.3 Address Calculation 17
2.3 Escape and Exception 17
2.4 Monitor Control 18
2.4.1 Memory Protection 18
2.4.2 Privileged Instructions 18
2.4.3 Program Interruption 18
2.4.4 Monitor Calls 19
2.5 Input/Output System 19
2.5.1 Bus Control 20
2.5.2 Bus Communication 20

3 DATA FORMATS AND INSTRUCTION 21
3.1 Data Formats 21
3.2 Working Registers 21
3.3 Instruction Format 22
3.3.1 Notation of Examples 23
3.3.2 Address Modification in Next Instruction 25
3.4 Use of the Effective Address as an Operand 26
3.4.1 Load of Immediate Values 26
3.4.2 Skip instructions 27
3.4.3 Shift instructions 28
3.5 Use of the Effective Address
to refer to Memory Locations 28
3.5.1 Process Area 29
3.5.2 Common Protected Area 30
3.5.3 Working Registers and Non-accessible Area 30
3.5.4 Memory Addressing. Example of user Program 31
3.6 Jump Instructions 32
3.6.1 Jump, Example 1 33
3.6.2 Jump, Example 2 33
3.6.3 Jump, Example 3 34
3.7 Register Transfer Instructions 34
3.8 Logical Operations 36
3.9 Skip if no protection 37\f

4 INTEGER ARITHMETIC 38
4.1 Number Representation 38
4.2 Halfword Arithmetic 38
4.3 Word Arithmetic 39
4.4 Doubleword Arithmetic 39
4.5 Multiplication and Division 40
4.6 Overflow and Carry Indication 41
4.7 Exception Register Instructions 43

5 FLOATING-POINT ARITHMETIC 47
5.1 Number Representation 47
5.2 Arithmetic Operations 48
5.3 Normalization and Rounding 48
5.4 Underflow, Overflow and Non-normalized Operands 49
5.5 Floating Point Instruction 50
5.6 Number Conversion 50
5.7 Examples 51

6 MONITOR CONTROL 54
6.1 System Table 54
6.2 Entering the Monitor Program 55
6.3 Reactivation of User Program 56
6.4 Monitor Calls 57
6.5 Interrupts 58
6.5.1 Internal Interrupt 58
6.5.2 Power Failure and Timer 58
6.5.3 External Interrupts 59
6.6 Disabling of Interrupts 59
6.7 Interrupt Response 60
6.8 Control of Monitor Registers 60

7 EXCEPTIONS AND ESCAPE 61
7.1 Exception 61
7.1.1 Register Dump at Exception 61
7.1.2 Program Exception 62
7.1.3 Arithmetic Exceptions 62
7.1.4 Exception Routine 62
7.2 Escape 65
7.2.1 Escape in Indirect Address Calculation 65
7.2.2 Escape Mask and Escape Pattern 66
7.2.3 Escape Active 66
7.2.4 Register Dump at Escape 66
7.2.5 Escape Routine 68
7.2.6 Return from Escape 68
7.2.7 Examples and Hints 69
\f

8 INPUT/OUTPUT SYSTEM 74
8.1 Main Characteristics 74
8.2 Input and Output Operations 74
8.2.1 Data In Instruction 74
8.2.2 Data Out Instruction 75
8.2.3 Exception Indication 76
8.2.4 Memory Addressing 76
8.3 Standardized Block-oriented Device Controllers 76
8.3.1 Device Address 77
8.3.2 Device Descriptions 78
8.3.3 Channel Program 78
8.3.4 Standard Status Information 80

9 POWER RESTART AND AUTOLOAD 82
9.1 Power Restart 82
9.2 Autoload 83

10 FORMAL DESCRIPTION 86
10.1 Introduction 86
10.2 Notation 87
10.2.1 Registers 87
10.2.2 Booleans 88
10.2.3 Integer Arithmetics 88
10.2.4 Memory Access 88
10.2.5 Bitpatterns 89
10.2.6 Abbreviations 89
10.3 Common routines 90
10.3.1 procedure getword; 90
10.3.2 procedure getdouble1; 91
10.3.3 procedure getdouble2; 92
10.3.4 procedure get nonprotected; 92
10.3.5 procedure get address; 93
10.3.6 procedure get instruction; 93
10.3.7 procedure store word; 94
10.3.8 procedure set bus exceptions; 95
10.3.9 normalize and round; 95
10.3.10 exit to program; 96
10.4 Instruction Control 97
10.4.1 next instruction: 98
10.5 Address Calculation 100
10.6 Instruction Execution 101
10.6.1 aa: 101
10.6.2 ac: 102
10.6.3 ad: 102
10.6.4 al: 103\f

10.6.5 am: 103
10.6.6 as: 103
10.6.7 cf: 104
10.6.8 ci: 105
10.6.9 di: 105
10.6.10 dl: 105
10.6.11 do: 106
10.6.12 ds: 106
10.6.13 ea: 107
10.6.14 el: 107
10.6.15 es: 108
10.6.16 fa: 108
10.6.17 fd: 110
10.6.18 fm: 111
10.6.19 fs: 111
10.6.20 gg: 113
10.6.21 gp: 113
10.6.22 hl: 114
10.6.23 hs: 114
10.6.24 jd: 114
10.6.25 je: 115
10.6.26 jl: 115
10.6.27 la: 116
10.6.28 ld: 116
10.6.29 lo: 116
10.6.30 ls: 117
10.6.31 lx: 117
10.6.32 nd: 117
10.6.33 ns: 118
10.6.34 re: 119
10.6.35 ri: 119
10.6.36 rl: 119
10.6.37 rs: 119
10.6.38 rx: 120
10.6.39 se: 120
10.6.40 sh: 120
10.6.41 sl: 121
10.6.42 sn: 121
10.6.43 so: 121
10.6.44 sp: 122
10.6.45 ss: 122
10.6.46 sx: 122
10.6.47 sz: 123
10.6.48 u0: u30: u31: u51: u58: u59:
u60: u61: u62: u63: 123\f

10.6.49 wa: 123
10.6.50 wd: 124
10.6.51 wm: 124
10.6.52 ws: 125
10.6.53 xl: 125
10.6.54 xs: 126
10.6.55 zl: 126
10.7 Monitor calls and interrupt 126
10.7.1 external interrupt: 127
10.7.2 fetch error: 127
10.7.3 operand error: 127
10.7.4 call: 128
10.7.5 ri algorithm: 130
10.8 Exception and escape 131
10.8.1 program exception: 131
10.8.2 integer exception: 132
10.8.3 floating point exception: 132
10.8.4 escape: 133
10.8.5 re algorithm: 135

A1 Appendix 1 137
A1.1 Instructions in Alphabetic Order by Mnemonics 137

A2 Appendix 2 139
A2.1 Instructions in Order of Numeric Code 139

A3 Appendix 3 141
A3.1 Instructions in Order of Escape Pattern 141

A4 Appendix 4 143
\f

F_ 1 RC 8000 SPECIFICATIONS

I_m_p_l_e_m_e_n_t_a_t_i_o_n_
Large-scale integrated circuits extensively used.
Compromise between hardwired logic and microprogramming, balan-
cing flexibility and speed.

B_u_s_ _S_t_r_u_c_t_u_r_e_
Asynchronous unified bus.
Parallel data lines (24 bits + 3 parity bits) and address lines
(23 bits + 1 parity bit).

P_r_i_m_a_r_y_ _M_e_m_o_r_y_
Direct addressing of up to 4 194 304 words. Each word contains 24
data bits. Parity check or error recovery are supplied in all
models. Memory type and configuration depends on model.

P_e_r_i_p_h_e_r_a_l_s_
Complete range of input/output devices, interfaced through peri-
pheral processors or programmable front end. Both processor types
are connected to the unified bus.

W_o_r_k_i_n_g_ _R_e_g_i_s_t_e_r_s_
Four 24-bit working registers, three of which also function as
index registers.
The registers are addressable as the first four words of the
primary memory.

D_a_t_a_ _F_o_r_m_a_t_s_
12-bit halfwords and 24-bit words for integer arithmetic.
48-bit double words for integer and floating-point arithmetic.

I_n_s_t_r_u_c_t_i_o_n_ _F_o_r_m_a_t_
24-bit single-address instruction. Address modification includes
indexing, indirect addressing and relative addressing.
Dynamic relocation through use of modified base register tech-
nique.

I_n_s_t_r_u_c_t_i_o_n_s_
Comprise 64 function codes, each working on 4 registers, with 16
address calculation modifications and a 12-bit displacement.
Arithmetic includes add, subtract, multiply and divide.
Data manipulation aided by halfword operations and word compa-
rision. \f

Logical operations permit setting and testing af single bits.
Escape facility permits programmed actions on any or all instruc-
tions.
Exception concept permits programmed diagnostics on programming
errors.

P_r_o_t_e_c_t_i_o_n_ _S_y_s_t_e_m_
Privileged instructions and memory protection associated with a
monitor mode ensure complete monitor control.
Monitor mode is entered through monitor calls and interrupts.
Violation of protection system leads to exceptions.

I_n_t_e_r_r_u_p_t_i_o_n_ _S_y_s_t_e_m_
Program interruption system with priority levels.
Assignment of levels and disabling of interrupts under program
control.
Power failure interrupt and power restart are standard.

I_n_p_u_t_/_o_u_t_p_u_t_ _S_y_s_t_e_m_
All peripherals are connected to the unified bus.
Blockoriented controllers are standardized and perform all in-
put/output functions under the control of channel programs in
primary memory.
Data is transferred directly between the controllers and the
primary memory. An asynchronous, fully interlocked request/
acknowledge communication technique is employed.
CPU>s have no special status on the bus.
Interrupts are achieved by addressing a CPU. \f

F_ 2. DESIGN FEATURES

T_2.1 O_p_e_r_a_n_d_ _L_e_n_g_t_h_

A_r_i_t_h_m_e_t_i_c_ _a_n_d_ _L_o_g_i_c_a_l_ _O_p_e_r_a_n_d_s_
&_ The basic arithmetic or logical operand is a 24-bit word. Double-
length operands of 48 bits satisfy the requirements of engi-
neering computation and administrative data processing.

H_a_l_f_w_o_r_d_ _H_a_n_d_l_i_n_g_
Direct addressing of 12-bit halfwords aids efficient packing of
data.

T_2.2 R_e_g_i_s_t_e_r_s_ _a_n_d_ _A_d_d_r_e_s_s_i_n_g_

2.2.1 R_e_g_i_s_t_e_r_s_ _S_t_r_u_c_t_u_r_e_
The 8 dynamic registers define the current state of a program.
&_ They are dumped when control is transferred to the monitor
program or to the exception or escape service routines of the
program and are reloaded when the program is resumed. The dynamic
registers comprise:

The four working registers, "w0", "w1", "w2" and "w3", see 3.2.
Each instruction specifies one of these, see 3.3. The working
registers except for "w0" can function as index registers.

The status register, "status", contains the following
information. Bits are numbered 0-23 with 0 indicating the most
significant bit.

Bit no. Contents

0 monitor mode: privileged instructions allowed, see 6.
1 escape mode: escape facility active, see ch.7.
2 after address modify: address calculation in next
instruction starts from present contents of the
address register, see 3.3.2.
3 after escape: address calculation in next instruction
is skipped. The contents of the address register is
used as resulting address. If the "after address mo-
dify" bit is set too, the contents of the word pointed
out by the address register is used, see ch. 7.
4 integer exception active, see ch. 4. \f

5 floating point exception active, see ch. 5
6-11 escape mask, see ch. 7.
12-15 dump error count: used in connection with memory
errors in registerdump at interrupt or monitor
calls, see 10.7.4.
16-19 not used.
20 disable: disable level of interrupt limit register
active, see 6.6.
21-23 exception: contains status information after arithme-
tic and input/output operations. Accessible as the
exception register, ex, through special instructions,
see ch. 4, 5 and 8.

The instruction counter, "ic", is a 24-bit register. Bit 23 is
always zero. Bit 0 is ignored in instruction fetch, but the full
register is used as a 24 two>s complement integer in relative
address calculation.

The cause register, "cause", indicates the cause of deviations
from normal program flow, i.e. interruptnumber, monitor call
number, exception cause and escape cause, see ch. 6 and 7.

The address register, "addr", is used internally as a working
register for address calculations. Dumped values of addr are used
in return from interrupt and escape, and are very useful in
connection with the exception and escape facilities.

The process definition registers define the relocation, memory
protection and interrupt disabling for the currently active pro-
gram. The contents of the registers is changed under monitor
control by interrupts and monitor calls and at return from these,
see ch. 6.

The process definition registers comprise:

cpa the common protected area limit register de-
fines the upper limit of the nonrelocated,
read-only lower part of memory, see 3.5.

base the base register defines the displacement of
physical addresses compared to logical ad-
dresses, see 3.5.
\f

lowlim the lower limit register defines the physical
lower limit of the write accessible part of
memory, see 3.5.

uplim the upper limit register defines the physical
upper limit of the write accessible part of
memory, se 3.5.

intlim the interrupt limit register defines two le-
vels of interrupt disabling. The program
shifts between the levels, which may be equal
and describe no disabling, by execution of
the special jump instructions: "jump disable"
and "jump enable", that respectively sets and
clears the disable bit in "status", see 6.6.

The monitor registers (ch. 6) are used in connection with inter-
rupts and monitorcalls.

inf the system information register points to a
system table of 6 words. The table contains
register dump and entry addresses for inter-
rupt, monitor call, exception and escape. At
interrupt and monitor call inf is decreased
by 12. This allows specification of special
actions for the mentioned events during exe-
cution of the monitor program. At return from
interrupt, inf is increased by 12 again.

size defines upper limit of memory. Size is used
for initialization of the upper limit regis-
ter when monitormode is entered at interrupt
or monitor calls.

montop defines the number of monitor calls. Monitor
calls are provoked by execution of the "jump
disable" instruction with a resulting address
fullfilling
-2048 _ addr - montop
The monitor call cause is given as addr +
2048 and is used for switching to the speci-
fied monitor function.
\f

rtc The real time clock register is a 16 bit read
only register. Rtc is incremented by 1 every
0.1 milliseconds and counts modulo 65536. A
timer interrupt is generated every timer in-
terrupt period, 25.6 milliseconds in most mo-
dels.

T_2.2.2 P_r_o_g_r_a_m_ _R_e_l_o_c_a_t_i_o_n_
Efficient relocation requires that programs can be written in
such a way that their execution is independent of their location.
&_ This is achieved in the RC 8000 in two ways:

First, the instruction format contains a bit that specifies rela-
tive addressing. It indicates that the address part of the in-
struction is to be interpreted relative to its current location
in the primary memory. This permits relocation of programs during
loading.

Second, the process definition registers define the current rela-
tion between the logical address as seen by the program and the
actual physical address, thereby ensuring that programs can use
saved address information after restarting in new memory areas.

T_ 2.2.3 A_d_d_r_e_s_s_ _C_a_l_c_u_l_a_t_i_o_n_
Besides relative addressing RC 8000 supplies indexing and indi-
rect addressing. The addressing modes can be used in any combina-
&_ tion. The possibilities are enhanced by the fact that the 3 index
registers are also working registers and through the address mo-
dify instruction. The address modify instruction makes indirect
addressing in multiple levels, use of the contents of any memory-
word as index, multiple indexing and conditional address calcula-
tion possible.

T_2.3 E_s_c_a_p_e_ _a_n_d_ _E_x_c_e_p_t_i_o_n_

The RC 8000 is provided with an escape facility, implemented by
means of an escape mode and an escape mask, which permits inde-
&_ pendent supervision of instruction execution as well as program-
med emulation of virtual memory, instruction sets and the like.
The exception concept allows specification of a diagnostic rou-
tine, which will be called when programming errors such as ille-
gal instructions or addressing occurs. The concept may also be
used for trapping of arithmetic overflow and underflow and for
definition of breakpoints. \f

T_ 2.4 M_o_n_i_t_o_r_ _C_o_n_t_r_o_l_

In a multiprogramming system, where many concurrent tasks are
performed, it is vital that erroneous programs can be prevented
&_ from interfering destructively with other programs. The various
tasks are therefore co-ordinated by a monitor program that has
complete control of the system. Monitor control in the RC 8000 is
guaranteed by memory protection, privileged instructions, program
interruption and monitor calls.

T_2.4.1 M_e_m_o_r_y_ _p_r_o_t_e_c_t_i_o_n_
An erroneous program may attempt to destroy data or instructions
within other programs. Mutual memory protection is accomplished
&_ in the RC 8000 through limit registers, so that a program can
only alter the contents of memory locations in its own area. The
remainder of the memory is divided into a read-accessible and a
read-protected part. The read-accessible part is addressed inde-
pendently of dynamic program relocation. Any attempt to violate
the protection system leads to a program exception.

T_2.4.2 P_r_i_v_i_l_e_g_e_d_ _I_n_s_t_r_u_c_t_i_o_n_s_
Further protection is achieved through privileged instructions
that can only be executed within the monitor program. These in-
&_ structions include input/output functions as well as control of
the interruption system, memory protection and dynamic program
relocation. Attempts to execute privileged instructions in normal
mode leads to program exception.

T_2.4.3 P_r_o_g_r_a_m_ _I_n_t_e_r_r_u_p_t_i_o_n_
Multiprogrammed computers must respond quickly to exceptional
events. In the RC 8000 this is made possible by a program inter-
&_ ruption system that can register a number of signals simulta-
neously. Any of these signals interrupts the current program im-
mediately and starts the monitor program. Register dump and re-
gister initialization for fast switch to service routine are exe-
cuted by firmware. Return to program and restoring of registers
are carried out by a privileged instruction, return from inter-
rupt. Critical actions can be protected against interruption by
partial or total disabling.
\f

T_2.4.4 M_o_n_i_t_o_r_ _C_a_l_l_s_
To ensure the legal interaction between parallel programs and be-
tween programs and the input/output system, the monitor program
&_ must supply a set of service functions. Activation of these take
place by execution of a monitor call instruction. The calling
program is interrupted and the monitor program is started as for
interrupts, but at a different entry address and with "cause" de-
fined by the monitor call instruction.

T_2.5 I_n_p_u_t_/_O_u_t_p_u_t_ _S_y_s_t_e_m_

The input/output system is based on a unified bus, i.e. a common
&_ bus for communication between all devices and CPU>s connected to
it, none of which has a special status. Besides permitting the
implementation of a wide range of systems, including multiproces-
sing systems, the unified bus facilitates communication with
other systems and provides a basis for implementation of other
bus structures.

The connection of peripheral devices is standardized in such a
way that the central processors are unaware of the types of de-
vices attached to the bus. All peripheral devices except the pri-
mary memory are connected to the bus via standardized device con-
trollers (peripheral processors). Data transfers between the cen-
tral processor and the peripheral processors are handled by a
single input and a single output operation.

In order not to suspend program execution while an input or out-
put operation is in progress, the direct transfer of data between
processors is minimized; thus the peripheral processor, as soon
as it is started, will fetch its commands from the channel pro-
gram in the primary memory and execute them without engaging the
central processor, which continues with its program.

When the central processor attempts to initiate an input or out-
put operation, the peripheral device may reject it. Information
about this as well as other exceptional events is made available
in the exception register, which can be tested by the program in
order to take appropriate action. Device status will be trans-
ferred to the memory and the central processor will be interrup-
ted when the channel program is terminated.

Peripheral devices may also be connected to the bus in a more
primitive manner, i.e. without the channel program concept. In\f

this case, the device controller will be regarded as a set of
registers, to which the central processor transfers control in-
formation, and from which it obtains device information by means
of the input and output instructions.

T_2.5.1 B_u_s_ _C_o_n_t_r_o_l_
Since the bus is shared by numerous devices, only one may have
control of it at a time. This device is called the bus master and
&_ the device which it addresses, is called the slave.

When a device that is capable of being a bus master (viz. a cen-
tral processor or peripheral processor) desires to obtain
control, it sends a request to the bus control unit.

The control unit responds with a select signal, which is daisy-
chained through all the devices on the bus. The first device ha-
ving sent a request, breaks the chain and returns an acknowledge-
ment, completing the selection procedure. If the control unit
does not receive an acknowledge signal, it generates a bus time-
out, after which the selection procedure may be repeated.

As soon as the current master completes its transfer and releases
the bus, the selected device becomes the new master and sends a
busy signal while using the bus. During this time the next bus
master is selected.

T_2.5.2 B_u_s_ _C_o_m_m_u_n_i_c_a_t_i_o_n_
To facilitate interfacing with other systems, an asyncronous ful-
ly interlocked technique is used for bus communication. This so-
&_ called handshake technique, in which each request that is sent by
a master must be acknowledged by the slave to complete the trans-
fer, permits operations between devices having different response
times.
\f

F_3 DATA FORMATS AND INSTRUCTIONS

T_3.1 Data Formats

The data structure of the RC 8000 is shown in the following
figure:

&_
The basic arithmetic or logical operand is an integer of 24 bits.
The 12-bit halfwords are directly addressable, and may be used as
signed numbers. Double words are used to represent integers of 48
bits and floating-point numbers with 36-bit fractions and 12-bit
exponents.

T_ 3.2 Working Registers

The register structure includes four 24-bit working registers,
one of which is specified in each instruction. Three of the
working registers also function as index registers. The current
&_ index register is selected by the instruction format.

The working registers are addressable as the first eight half-
word (or four words) of the primary memory, (see 3.5).

Two adjacent working registers can be used to hold a double-\f

length operand of 48 bits. In double-length operations, the four
registers are connected cyclically as follows:

T_ w3 concatenate with w0
w0 concatenate with w1
w1 concatenatewith w2
&_ w2 concatenate with w3

These connections are established by specifying the second regis-
ter of the concatenation in the instruction format.

T_3.3 Instruction Format

The instruction format is divided into an operation halfword and
&_ an address halfword, each containing 12 bits:

T_ F W M X D
&_ 0 5 6 7 8 9101112 23

Bits 0:5 F_ _f_i_e_l_d_._ Contains the function code, specifying one of
sixty-four basic operations.

Bits 6:7 W_ _f_i_e_l_d_._ Specifies one of four working registers as
the result register.

Bits 8:9 M_ _f_i_e_l_d_._ Specifies one of four address modes, used to
control generation of the effective address (see be-
low).

Bits 10:11 X_ _f_i_e_l_d_._ Selects the current index register. Only
working registers w1, w2, and w3 act as index
registers (X field = 0 indicates no indexing).

Bits 12:23 D_ _f_i_e_l_d_._ Contains a truncated address, specifying a
displacement from -2048 to +2047 halfwords within the
program.

A full address of 24 bits is formed by means of the displacement,
D, in conjunction with the contents of an index register, X, and
the content of the instruction counter, "ic". The generation of
the effective address, "addr", is controlled by the address mode
field, M, as follows:
\f

T_ M = 00 addr = X + D
M = 01 addr = word (X + D)
M = 10 addr = X + IC + D
&_ M = 11 addr = word (X + IC + D)

In the address calculation, the displacement is treated as a
12-bit signed integer that is extended towards the left to 24
bits before being added to the index register and the instruction
counter. In the final addition of X, IC, and D, overflow is
ignored.

The address modes 01 and 11 permit indirect addressing on one
level. The indirect address fetched from the memory is assumed to
be a full address of 24 bits.

The address modes 10 and 11 modify the indexed displacement with
the current load address of the instruction. This permits re-
location of programs during loading.

T_ 3.3.1 N_o_t_a_t_i_o_n_ _o_f_ _E_x_a_m_p_l_e_s_
The examples in the remaining part of this manual is given in a
primitive pseudo assembly language. Basic instruction format is

mn' w' d' ; comments'
&_
mn' is the instruction mnemonic. Instructions and their
mnemonics are introduced before they are used in
examples. Survey of instruction by mnemonic is given in
Appendix 1, which also gives the reference to the de-
tailed instruction descriptions in chapter 10.

w' specifying the working register as w0, w1, w2 or w3.
The w' may be left out, specifying W-field = 0, but
this is only done, when the instruction does not use a
working register.

d' specifies the displacement either as an integer or as
the name of a label in which case the displacement is
the address of the labelpoint. Labelpoints are given as
>names'> in front of an instruction, a constant or the
name of a label.

comment' may be any text, comments are terminated by new line.
\f

The principles of the instruction mnemonics are:

- Each instruction has a full name describing the instruction as
well as possible. Word choice and structure is uniform for the
different instructions.

- A short name is defined by the first word and one other signi-
ficant word of the full name, indicated by underlining.
The short name is the normal reference to the instruction.

- The acronym derived from the short name defines the mnemonic.

To show the notation the "r_e_g_i_s_t_e_r_:l_o_a_d_" instruction is intro-
duced preliminarily. The "r_e_g_i_s_t_e_r_:l_o_a_d_" instruction, "rl", loads
the specified working register with the contents of the memory
word pointed out by the effective address.

T_ constant: 2
addr: constant
.
.
rl w1 constant; w1 = 2
&_ rl w3 addr ; w3 = address (constant)

Constant and addr must represent addresses that can be contained
in the D-field, i.e. less than 2048.

Relative addressing is indicated by a point after the instruction
mnemonic, while a point after the labelname in an instruction
means that the D-field of the instruction is the displacement
between the labelpoint and the instruction. Thus, with same da-
ta definitions as above:

T_ rl. w1 constant. ; w1 = 2
&_ rl. w3 addr. ; w3 = address (constant)

Now the displacement between the data and the instructions must
be less than 2048 and greater than or equal to -2048.

Indexing is indicated by placing an index register specification
in front of the displacement. Thus, still keeping the data defi-
nitions:
\f

T_ rl. w3 addr. ; w3 = address (constant)
rl w1 x3+0 ; w1 = 2
rl w2 x3+2 ; w2 = address (constant)
&_ rl. w0 x1+constant. ; w0 = address (constant)

Indirect addressing is indicated by placing the address part of
the instruction in parenteses. Thus, again with same data defini-
tions:

T_ rl. w1 (addr.) ; w1 = 2
&_ rl. w3 (x1+constant.); w3 = 2
T_
3.3.2 A_d_d_r_e_s_s_ _m_o_d_i_f_i_c_a_t_i_o_n_ _i_n_ _n_e_x_t_ _i_n_s_t_r_u_c_t_i_o_n_
"A_d_d_r_e_s_s_ : m_o_d_i_f_y_ that of next instruction", "am", sets the "after
"am" bit in the status register. This will modify the address cal-
culation in the next instruction as follows depending on the M-
field:

T_ M = 00 addr = X + D + addr
M = 01 addr = word (X + D + addr)
M = 10 addr = X + ic + D + addr
&_ M = 11 addr = word (X + ic + D + addr)

I.e. the effective address of the "am" instruction is added to the
displacement before it is used in the address calculation. The
"after am" bit is cleared, when it has had its effect.

The "am" instruction expands the addressing possibilities as
indicated in the following examples, the corresponding
datastructures are not shown.

T_ Indirect addressing in two levels:

am. (addr.) ; addr points to the address of a
; value
&_ rl w1 (0) ; w1 = value

T_ Indexing by a memory word:

am. (addr.) ; contents of addr points to first
; word in table
&_ rl w1 4 ; w1 = third word in table
\f

T_ Double indexing:

rl. w2 relrecord.; relrecord contains relative
; position of record in block
am. (relfield.); relfield contains relative
; position of field in record
rl. w0 x2+block. ; block points at blockstart
&_ ; w0 = fieldvalue

Conditional address calculation is possible through conditioning
of the execution of the "am" instruction (see 3.4.2).

T_ 3.4 Use of the effective Address as an Operand

For some function codes, the effective address is used directly
&_ as an operand. This is done in three different ways.

The effective address or its two>s complement can be assigned to
the addressed register.

The contents of the working register can be compared with the effec-
tive address (word comparison) in several ways, the result of the
comparison determining whether the following instruction is to be
executed or skipped.

The effective address can define a number of shifts to be per-
formed on the addressed register.

T_ 3.4.1 L_o_a_d_ _o_f_ _i_m_m_e_d_i_a_t_e_ _V_a_l_u_e_s_
The "a_d_d_r_e_s_s_:l_o_a_d_ into register" instruction, "al", assigns the
effective address to the specified register.

c1: 4711
:
al w0 10 ; w0 = 10
al. w1 c1. ; w1 = address (4711)
al w2 x1-2 ; w2 = w1 - 2
&_ al w1 x1+10 ; w1 = w1 + 10

The "a_d_d_r_e_s_s_ c_o_m_p_l_e_m_e_n_t_e_d_:load into register" instruction, "ac",
assigns the two>s complement of the effective address to the
specified register.
\f

T_ ac w1 x1+1 ; w1 = -w1 -1, the ones complement
ac w0 10 ; w0 = -10
ac. w2 (c1.) ; w2 = -4711
&_ ac w3 x1-10 ; w3 = 10 - w1

Complementation of the maximum negative number will produce an
overflow (see 4.4).

T_ 3.4.2 S_k_i_p_ I_n_s_t_r_u_c_t_i_o_n_s_
"S_k_i_p_ if register h_i_g_h_", "sh", compares the value of the speci-
fied working register and the effective address interpreted as
&_ integers in two>s complement representation. If the register
value is greater than the effective address the following in-
struction is skipped.

T_ sh w1 -1 ; if w1 _ -1 then
&_ al w1 0 ; w1 = 0

This piece of code ensures that the following instructions are
never entered with a negative value of w1. Note that the comment
illustrates another way of looking at the skip instruction. The
skip instruction and the following instruction is considered one
conditional instruction conditioned by the negated condition.

"S_k_i_p_ if register l_o_w_", "sl", skips the following instruction if
the register value is less than the effective address.

T_ sl w1 0 ; if w1 '_ 0
am -2 ; then w0 = 43 (iso character
; value of "+")
al w0 45 ; else w0 = 45 (iso character
; value of "-")
sh w1 -1 ; if w1 _ -1 then
&_ ac w1 x1 ; w1 = -w1

The character value of the sign of the number in w1 is assigned
to w0 (an example of conditional address calculation). After that
w1 is assigned the absolute value of the number.

"S_k_i_p_ if register e_q_u_a_l_", "se", skips the following instruction
if the register value and the effective address is equal.

"S_k_i_p_ if register n_o_n_e_q_u_a_l_", "sn", skips the following instruc-
tion if the register value and the effective address is not
equal. \f

"S_k_i_p_ if selected register bits all o_n_e_s_", "so", uses the effec-
tive address as a masc to test selected bits in the working re-
gister. If a_l_l_ bits in the working register that correspond to
ones in the effective address are one, the following instruction
is skipped.

"S_k_i_p_ if selected register bits all z_e_r_o_s_", "sz", is analog to
"so". If a_l_l_ bits in the working register that corresponds to
ones in the effective address are zero, the following instruction
is skipped.

T_ sz w1 1 ; if w1 is odd then
&_ al w1 x1-1 ; make it even.

T_ 3.4.3 S_h_i_f_t_ I_n_s_t_r_u_c_t_i_o_n_s_
"L_o_g_i_c_a_l_ shift of s_i_n_g_l_e_ register", "ls", shifts the content of
the specified working register the number of places given by the
&_ effective address. If the effective address is negative the shift
is a right shift with zeroes shifted in at the most significant
bits else it is a left shift with zeroes shifted in at the least
significant bits.

"L_o_g_i_c_a_l_ shift of d_o_u_b_l_e_ register", "ld". As "ls" but the shift
is performed on the 48 bit double register specified.

"A_r_i_t_h_m_e_t_i_c_ shift of s_i_n_g_l_e_ register", "as". As "ls", but with
sign extension for right shifts. Left shifts may produce an over-
flow (see further 4.4).

"A_r_i_t_m_e_t_i_c_ shift of d_o_u_b_l_e_ register", "ad". As "as", but the
shift is performed on the 48 bit double register.

T_ 3.5 Use of the effective Address to refer to Memory Locations

In instructions for register transfer, instructions for arithmetic
and logical operations and some other instructions the effective
address is used as a logical address pointing to a memory loca-
&_ tion.

Memory addresses are always expressed as halfword addresses. The
halfword locations are numbered consecutively starting with zero.
In word operations, the right-most bit in the effective address\f

is ignored; thus it is irrelevant whether a word operation refers
to the left or the right half of a word. In double-word opera-
tions, the right-most bit in the effective address is also ig-
nored; the word thus specified is the second word of the ope-
rand.

The working registers are addressable as the first four words of
memory. The programmer can therefore perform operations directly
between two registers by specifying a memory address between 0
and 7. It is also possible to execute instructions stored in the
working registers.

T_ HALFWORD ADDRESS
0 24 BITS WORKING REGISTER 0 (w0)
2 24 BITS WORKING REGISTER 1 (w1)
4 24 BITS WORKING REGISTER 2 (w2)
&_ 6 24 BITS WORKING REGISTER 3 (w3)

The relation between logical addresses and physical addresses,
i.e. true locations in the memory, is defined by the contents of
the process definition registers base, cpa, lowlim and uplim.
These contents define the memory protection given by the division
of the logical address space in process area, common protected
area, working registers and nonaccessible area.

Control of the contents of the process definition registersis
described in chapter 6.

T_ 3.5.1 P_r_o_c_e_s_s_ _A_r_e_a_
The process area is defined by the value of the limit registers.

&_ Inside the process area the effective address is increased by
the contents of the base register before it is used as a physical
address. The limit registers contain physical addresses, the pro-
cess area is therefore defined by

lowlim _ addr + base uplim

The process area must be contained in true memory, this means
that the condition

8 _lowlim _ uplim memory size

must be fulfilled at all times.
\f

The logical process area should be kept constant throughouta
program>s lifetime to ensure consistent program behaviour. This
means that the values "lowlim - base" and "uplim - base" should
be kept constant.

The process area allows read- and write access. Doubleword refe-
rence with effective address equal to "lowlim - base" will lead
to program exception.

T_ 3.5.2 C_o_m_m_o_n_ _P_r_o_t_e_c_t_e_d_ _A_r_e_a_
Effective addresses outside the process area may refer to the
common protected area defined by

&_ 8 _ addr cpa

Inside the common protected area, the effective address is used
directly as a physical address and only read access is allowed.
The contents of the cpa limit register must fulfill the condition

8 _ cpa memory size

The common protected area may overlap the process area. Con-
sistent program behaviour is only fully ensured in this case if
base is kept constant. The overlap belongs to the process area.
Double word reference with effective address equal to 8 and write
access in the common protected area will lead to program excep-
tion.
T_
3.5.3 W_o_r_k_i_n_g_ _R_e_g_i_s_t_e_r_s_ _a_n_d_ _N_o_n_a_c_c_e_s_s_i_b_l_e_ _A_r_e_a_
As described before effective addresses 0 through 7 refers to the
working registers. All other logical addresses outside the pro-
&_ cess area and the common protected area are considered nonacces-
sible and reference to them leads to program exception.
\f

T_ 3.5.4 M_e_m_o_r_y_ _A_d_d_r_e_s_s_i_n_g_._ _E_x_a_m_p_l_e_ _o_f_ _U_s_e_r_ _P_r_o_g_r_a_m_
The following figure shows the physical address as a function of
the logical address for a user program:

PHYSICAL ADDRESSES

upper common
limit areas
inaccessible
addresses

lower
limit

base
LOGICAL
ADDRESSES
a b c d e

upper limit less base
lower limit less base
&_ CPA limit

The division of the logical address space in this example is as
follows:

a. 0 _ logical address 8

The working registers. Full access.

b. 8 _ logical address cpa

Common protected area used for references to system
parameters. Read-access only. Physical address = logical
address.

T_ c. cpa _ logical addres lower limit - base
&_ Non-accessible area.
\f

T_ d. lower limit - base _ logical address upper limit - base
&_ Process area.

Relocatable (physical address = logical address + base).
Full access.

T_ e. upper limit - base _ logical address
&_ Non-accessible area.

T_ 3.6 Jump Instructions

The jump instructions represent a special kind of memory referen-
ce, as they transfer program control to the instruction pointed
out by the effective address.
&_
The effective address is treated as a logical address as des-
cribed above, and program execution is regarded as read access.
Reference to the non-accessible area leads to program exception.

Subroutine jumps are supported as follows: If the W field is dif-
ferent from zero, the logical address of the return point, i.e.
the instruction following the subroutine jump, is placed in the
specified working register. A jump is then made to the effective
address.

At the end of the subroutine, a return jump is made as a simple
jump, i.e. with W field equal to zero.

Conditional jumps are defined by use of the skip instructions.

The "j_u_m_p_ with l_i_n_k_ in register" instruction, "jl", is the basic
jump instruction.

The "j_u_m_p_ and select d_i_s_a_b_l_e_ limit", "jd", and "j_u_m_p_ and select
e_n_a_b_l_e_ limit", "je", instructions work like "jl", but have an
effect on the interrupt system. A subset of negative effective
addresses will, used in connection with the "jd" instruction,
define moni- tor calls. These features are described in chapter
6.
\f

T_ 3.6.1 J_u_m_p_,_ _e_x_a_m_p_l_e_ _1_

sub: - ; subroutine code that does
- ; not change the contents of w3
- ;
jl x3+0 ; return jump

- ;
jl. w3 sub. ; subroutine call
- ; return point
&_
The example sketches a simple subroutine structure. Parameters
are given in the remaining registers.

T_ 3.6.2 J_u_m_p_,_ _e_x_a_m_p_l_e_ _2_

sub: - ; subroutine entry point
- ; code
rl w1 x3+0 ; load of parameter 1
- ; code
- ;
sh w0 -1 ; if result 0
am -2 ; then error return
jl x3+6 ; else normal return

- ; code
- ;
jl. w3 sub. ; subroutine call with
47 ; parameter 1 : number
text ; parameter 2 : address of text
jl. error. ; error return point : goto error
- ; normal return point
- ; code
&_
This example sketches a little more sophisticated subroutine
structure. Parameters are given following the call and an error
return is supplied.
\f

T_ 3.6.3 J_u_m_p_,_ _e_x_a_m_p_l_e_ _3_

table: - ; table of records : key,
- ; value
- ;
; records
- ;
last: - ; last record : key,
- ; value
- ;
al. w1 table. ; initialize pointer to first
- ; record
loop: sn w0 (x1+0) ; if w0 = key (record) then
jl. found. ; goto found
al w1 x1+4 ; increase pointer to next
; record
sh. w1 last. ; if table not exhausted then
jl. loop. ; goto loop
- ; not found code
- ;

found: rl w2 x1+2 ; load value
- ; found code
&_ - ;

The example shows a simple loop. The contents of w0 is searched
in a table of double word records containing a key and a corres-
ponding value. If w0 matches one of the keys, control is trans-
ferred to the found code which loads the value and proceeds. If
the table is exhausted without a match the not-found code after
the loop is executed. The end of the loop shows a typical condi-
tional jump.

T_3.7 Register Transfer Instructions

The "r_e_g_i_s_t_e_r_:l_o_a_d_" instruction,"rl", loads the specified working
register with the contents of the memory word pointed out by the
effective address. If the effective address is 0 through 7, "rl
is a register to register transfer. Reference to the non-access-
&_ ible area leads to program exception.

The "r_e_g_i_s_t_e_r_:s_t_o_r_e_" instruction, "rs", stores the contents of
the specified working register in the memory word pointed out b
the effective address. If the effective address is 0 through 7,\f

"rs" is a register to register transfer. Other reference outsid
the process area leads to program exception.

The "r_e_g_i_s_t_e_r_ : e_x_c_h_a_n_g_e_ with word" instruction, "rx", exchanges
the contents of the specified working register and the memory
word pointed out by the effective address. If the effective ad-
dress is 0 through 7, "rx" exchanges the contents of two regis-
ters. Other reference outside the process area leads to program
exception.

The "z_e_r_o_-_e_x_t_e_n_d_e_d_ halfword : l_o_a_d_ into register" instruction,
"zl", loads the least significant 12 bits of the specified wor-
king register with the content of the halfword pointed out by the
effective address. The most significant 12 bits are cleared. If
the effective address is 0 through 7 "zl" is a half register to
register transfer. Reference to the nonaccessible area leads to
program exception.

The "e_x_t_e_n_d_e_d_ halfword : l_o_a_d_ into register" instruction, "el".
As "zl" but the most significant 12 bits will contain a sign
extension of the loaded halfword.

The "h_a_l_f_ register : l_o_a_d_" instruction, "hl". As "zl" but the
most significant 12 bits are left unchanged.

The "h_a_l_f_ register : s_t_o_r_e_" instruction, "hs", stores the least
significant 12 bits of the specified working register in the
halfword pointed out by the effective address. If the effective
address is 0 through 7, "hs" is a register to half register
transfer. Other references outside the process area leads to pro-
gram exception.

The "d_o_u_b_l_e_ register : l_o_a_d_" instruction, "dl", loads the speci-
fied double register with the contents of the doubleword pointed
out by the effective adress. If the effective address is 0
through 7, "dl" is a double register to double register transfer;
in this case it is important to note that the least significant
register is assigned before the most significant register is
transfered. Reference to the nonaccessible area and to the lower
limits of the process area (addr = lowlim - base) and the common
protected area (addr = 8) will lead to program exception.

The "d_o_u_b_l_e_ register : s_t_o_r_e_" instruction, "ds", stores the con-
tents of the specified double register in the doubleword pointed
out by the effective address. If the effective address is 0\f

through 7, "ds" is a double register to double register transfer
(note as for "dl"). Other references outside the process area and
reference to the lower limit of the process area will lead to
program exception.

T_ 3.8 Logical Operations

The instructions for logical operations combine the contents of
the working register with the operand, i.e., the contents of the
&_ word pointed out by the effective address, by a logical bit by
bit operation. If the effective address is 0 through 7, the re-
sult is a combination of two registers. Reference to the non-ac-
cessible area leads to program exception.

T_ The "l_o_g_i_c_a_l_ a_n_d_ : combine word with register" instruction, "la",
executes the logical and- operation defined by

register bit operand bit result bit
1 1 1
1 0 0
0 1 0
0 0 0
&_
T_ The "l_o_g_i_c_a_l_ o_r_ : combine word with register" instruction, "lo",
executes the logical or-operation defined by

T_ The "l_o_g_i_c_a_l_ e_x_c_l_u_s_i_v_e_ or : combine word with register" instruc-
tion, "lx", executes the logecal exclusive-or-operaton defined
by

3.9 Skip if no protection

The "s_k_i_p_ if word not p_r_o_t_e_c_t_e_d_" instruction, "sp", skips the
following instruction if the effective address of the instruction
points to the process area or to a register, i.e. if storing in
the word addressed is allowed. \f

F_ 4INTEGER ARITHMETIC

T_ 4.1 Number Representation

The standard arithmetic operands are signed integers of 12, 24
and 48 bits:

S
0 11 HALFWORD INTEGER

S
0 23 WORD INTEGER

S
&_ 0 47 DOUBLE WORD INTEGER

Positive numbers are represented in true binary form with a zero
in the sign bit. Negative numbers are represented in two>s com-
plement notation with a one in the sign bit. The two>s complement
of a number may be obtained by inverting each bit in the number
and adding 1 to the right-most bit.

T_ 4.2 Halfword Arithmetic

A signed integer represented by a 12-bit halfword must be con-
fined to the following range:

&_ -2**11 = -2048 _ integer halfword _ 2047 = 2**11-1

The instruction "e_x_t_e_n_d_e_d_ halfword : l_o_a_d_ into register", "el"
(see 3.7) serves to extend a signed 12-bit halfword towards the
left to 24-bits, as it is placed in a working register.

The arithmetic instructions "e_x_t_e_n_d_e_d_ _ halfword : a_d_d_ to regis-
ter", "ea", and "e_x_t_e_n_d_e_d_ halfword : s_u_b_t_r_a_c_t_ from register",
"es", adds or subtracts the contents of the halfword pointed out
by the effective address to or from the specified working regis-
ter after sign extension. If the effective address is 0 through 7
the operation is a register- halfregister operation. Reference to
non-accessible area leads to program exception. Overflow and car-
ry is registered in the exception register and integer exception\f

may occur as described in 4.6.

The "h_a_l_f_ register : s_t_o_r_e_" instruction, "hs", (see 3.7) is used
for storing halfword results in memory.

The sign extension of halfword operands makes it posible to per-
form integer arithmetic with mixed 12-bit and 24-bit operands.

T_ 4.3 Word Arithmetic

A signed integer represented by a 24 bit word or register is con-
fined to the following range

-2**23 = -8388608 _ integer word _ 8388607 = 2**23-1
&_
The "w_o_r_d_ : a_d_d_ to register" instruction, "wa", and the "w_o_r_d_ :
s_u_b_t_r_a_c_t_ from register" instruction, "ws", adds or subtracts the
contents of the word pointed out by the effective address to or
from the specified working register. If the effective address is
0 through 7 the operation is a register-register operation. Refe-
rence to non-accessible area leads to program exception. Overflow
and carry is registered in the exception register and integer ex-
ception may occur as described in 4.6.

T_ 4.4 Doubleword Arithmetic

A signed integer represented by a 48 bit doubleword or double-
register is confined to the following range

&_ -2**47 _ integer double word _ 2**47-1

Note that bit 24 of the integer i.e. bit 0 of the least signifi-
cant word or register is not a sign bit, but contains a normal
significant digit.

The "a_d_d_ d_o_u_b_l_e_ word to double register" instruction, "aa", and
the "s_u_b_t_r_a_c_t_ d_o_u_b_l_e_ word from double register" instruction,
"ss", adds or subtracts the contents of the doubleword pointed
out by the effective address to or from the specified doublere-
gister. If the effective address is 0 through 7, the operation is
a doubleregister-doubleregister operation. In this case it is im-
portant to remember that the operation on the least significant
registers is completed before the operation on the most signifi-\f

cant registers and carry is executed. Reference to non-accessible
area and reference to the lower limits of process area (addr =
lowlim - base) and common protected area (addr = 8) leads to pro-
gram exception. Overflow and carry is registered in the exception
register and integer exception may occur as described in 4.6.

T_ 4.5 Multiplication and Division

Integer multiplication of the contents of a working register with
the contents of a memory word produces a double-length product
that is placed in a double register of 48 bits with the sign bit
&_ at the extreme left.

A double-length product will normally consist of a sign bit plus
at most 46 digits. In this case, bit 1 in the double register
will be identical with the sign bit.

T_ The only exception to this occurs in the multiplication of two
maximum negative numbers:

&_ (-2**23)*(-2**23) = 2**46

This result will be represented as bit 1 = 1, all other bits = 0.

The contents of a double register can be divided by the contents
of a memory word. The dividend is then replaced by a 24-bit re-
mainder in the left-hand register and a 24-bit quotient in the
righthand register. A non-zero remainder satisfies the following
requirements:

T_ (1) dividend = divisor * quotient + remainder
(2) 0 _ abs (remainder) abs (divisor)
&_ (3) sign (remainder) = sign (dividend)

T_ S SIGNIFICANT BITS OF DIVIDEND
0 47

S SIGNIF. BITS OF REMAIND. S SIGNIF. BITS OF QUOTIENT
&_ 0 23 0 23

The "w_o_r_d_ : m_u_l_t_i_p_l_y_ by register giving double register" instruc-
tion, "wm", multiplies the specified working register by the con-
tents of the word pointed out by the effective address. The re-
sult is placed in the corresponding double register. If the ef-\f

fective address is 0 through 7, the operation is a register-re-
gister operation. Reference to nonaccessible area leads to pro-
gram exception. Exception register is unchanged and integer ex-
ception can not occur.

The "w_o_r_d_ : d_i_v_i_d_e_ into double register" instruction, "wd", divides
the specified double register by the contents of the word pointed
out by the effective address. The quotient is placed in the least
significant register while the remainder is placed in the most sig-
nificant register. If the effective address is 0 through 7, the
operation is a double register-register operation. Reference of
nonaccesible area leads to program exception. Carry = 0 and over-
flow is registered in the exception register and integer exception
may occur as described in 4.6. At overflow the dividend is left
unchanged.

If the dividend is represented by an integer word, the sign must be
extended before division
T_
rl. w1 dividend. ;
al w0 0 ; sign extension of positive
; dividend
wd. w1 divisor. ;

rl. w0 dividend. ;
ad w1 -24 ; sign extension of any dividend
wd. w1 divisor. ;

rl. w1 dividend. ;
sl w1 0 ; sign extension of any dividend
am 1 ;
al w0 -1 ; faster in most models
&_ wd. w1 divisor. ;

T_ 4.6 Overflow and Carry Indication

Arithmetic operations except integer multiplication indicate a
normal or an exceptional result by setting the right-most two
bits of the 3-bit exception register. Physically, the exception
&_ register is the last three bits in the status register, but it is
treated by special instructions as a logically independent regis-
ter. See 4.7.

After a normal result, exception bit 22 is set to zero. An integer\f

overflow will set exception bit 22 to one, and will provoke an in-
teger exception if the "integer exception active" bit in the status
register is set, see further chapter 7.

An overflow condition is recognized in the following situations:

T_ (l) The result of an addition, subtraction or division
exceeds the range or a 24-bit signed integer, viz.

&_ -2**23 = -8 388 608 _ integer word _ 8 388 607 = 2**23-1

T_ Or the result of doubleword addition or subtraction
exceeds the range of a 48 bit signed integer, viz.

&_ -2**47 _ integer doubleword _ 2**47-1

Note that multiplication can never produce overflow and
leaves the exception register unchanged.

T_ (2) The instruction "a_d_d_r_e_s_s_ c_o_m_p_l_e_m_e_n_t_e_d_ : load into re-
gister", "ac", specifies complementation of the maxi-
mum negative number:

&_ -(-2**23) = 2**23

T_ (3) One or more significant digits are lost during arithme-
tic shifts toward the left. (The shift instructions
test overflow conditions after each single-bit shift).
&_
If overflow occurs in division, the dividend remains unchanged in
the working register. All other arithmetic operations deliver the
result modulo 2**24 after an overflow.

Exception bit 23 is set, when addition or subtraction produces a
carry from bit 0. For addition this means, that a carry is pro-
duced when the sum of the operands interpreted as unsigned num-
bers of 24 bits (or 48 bits) exceeds 2**24-1 (or 2**48-1). For
subtraction the carry is to be interpreted as not borrow, i.e. a
carry is produced when the register operand interpreted as an un-
signed number is greater than or equal to the "memory" operand
interpreted as an unsigned number.

The carry indication in the exception register can be used for
multiple length arithmetic and in connection with comparison of
unsigned numbers, see examples in 4.7. \f

The exception register, then, has the following meaning after an
integer arithmetic operation:

T_ B_i_t_ M_e_a_n_i_n_g_
21 (unchanged)
22 integer overflow
&_ 23 integer carry

T_ 4.7 Exception Register Instructions

The "s_k_i_p_ if selected e_x_c_e_p_t_i_o_n_ bits all zero" instruction, "sx",
uses the 3 least significant bits of the effective address to
&_ test selected bits in the exception register. If all selected
bits, i.e. the bits corresponding to 1>s in the effective ad-
dress, are zero the following instruction is skipped.

The "sx" instruction may be used to test for overflow and carry.

- ; integer operation
sx 2 ; if overflow then
jl. overflow. ; goto overflow
-

- ; integer operation
sx 1 ; if carry then
jl. w3 carry. ; call carry action
- ;

The "e_x_c_e_p_t_i_o_n_ register : s_t_o_r_e_ in halfword" instruction, "xs",
stores the exception register in the 3 least significant bits of
the halfword pointed out by the effective address. The most sig-
nificant 9 bits are set to zero. If the effective address is 0
through 7, "xs" is an exception register to halfregister trans-
fer. Other references outside the process area lead to program
exception.

The "e_x_c_e_p_t_i_o_n_ register : l_o_a_d_ from halfword" instruction, "xl",
loads the exception register with the 3 least significant bits of
the halfword pointed out by the effective address. If the effec-
tive address is 0 through 7, "xl" is a halfregister to exception
register transfer. Reference to non-accessible area leads to pro-
gram exception.
\f

T_ Example 1:

;comparison of unsigned integers

rl. w1 int1. ;
ws. w1 int2. ;
sx 2.01 ; if int1 '= int2 then
jl. greq. ; goto greq;
&_
rl. w1 int1. ;
ws. w1 int2. ;
sx 2.01 ; if int1 int2 then
jl. 4 ;
jl. less. ; goto less;

Since the dataformats of RC 8000 is sufficient for nearly all
applications little attention has been paid to the ease of im-
plementation of multilength arithmetic. Thus no facility for di-
rect carry propagation is included. The causual reader may skip
the following example of the use of exception bit 23 in multi-
length addition.

T_ Example 2:

;Routine for multilength addition
;The routine performs addition of multilength integers
;represented in consequtive doublewords.
;At call the registers must contain
; w0: length of integers in halfwords:
; integral multiplum of 4, at least 8.
; w1: address of last word of first integer
; w2: address of last word of second integer
; w3: link
;At return the result will have overwritten the second integer.
;Return is made to link + 2, i.e. the second instruction after
;the call, except in case of total overflow, where return is to
&_ ;link.

0 ;
dzero: 0 ; double length zero
done: 1 ; double length one
stop: 0 ; saved stop criteria
return: 0 ; saved return
\f

multiadd: ws w2 0 ; entry point:
al w2 x2+4 ; stop criteria;
ds. w3 return. ; save stop criteria and return;
al w2 x2-4 ;
wa w2 0 ; restore second pointer;
xl. 0 ; clear ex;

next: dl w0 x1 ; loop for addition of tail parts
sx 2.01 ; if ex(23) then
aa. w0 done. ; add carry; x
xs. oldcarry.+1; save ex in displ. below x
aa w0 x2 ; add second tailpart x
ds w0 x2 ; save partial result

oldcarry: al w0 0-0-0 ; load saved ex from carry
; addition
sz w0 2.01 ; if saved carry then
xl. 1 ; ex(23):= 1;
al w1 x1-4 ;
al w2 x2-4 ; decrease pointers;
sl. w2 (stop.) ; if more tail parts then
jl. next. ; loop;
dl w0 x1 ; load head of first
sx 2.01 ;
am done-zero ; if ex(23) then y
aa. w0 dzero. ; add carry; note ex always
; assigned y
xs 3 ; w1:= oldex:= ex; y
aa w0 x2 ; add head of second; y
ds w0 x2 ; save result;
sx 2.01 ; if overflow then
al w1 x1+2 ; oldex. overflow:=
; -, oldex. overflow;
rl. w3 return. ;
sz w1 2.01 ; if oldex. overflow then
jl x3 ; return to link
jl x3+2 ; else return to link + 2;

The corresponding routine for multilength subtraction can be
obtained by changing instructions marked "x" by:

jl. 4 ; if -, carry then
ss. w0 done. ; subtract borrow;
xs. oldcarry.+1; save ex in displ. below;
ss w0 x2 ; subtract tailpart;
\f

and instructions marked "y" by:

am dzero-done ; if -, carry then
ss. w0 done. ; subtract borrow;
xs 3 ; w1:= oldex:= ex;
ss w0 x2 ; subtract first doubleword;
\f

F_ 5 FLOATING-POINT ARITHMETIC

T_ 5.1 Number Representation

&_ A floating-point number F = fraction * 2 ** exponent is stored in
a double word or a pair of working registers:
T_

FRACTION EXPONENT
S S
0 23 24 35 36 47

FIRST WORD SECOND WORD

&_
The address of a floating-point number refers to the second word
of the memory operand. The working register field within a floa-
ting-point instruction refers to the second word of the register
operand.

The left-most 36 bits of a floating-point number represent a signed,
normalized fraction in two>s complement notation. The right-most
12 bits are a signed exponent, also in the two>s complement form.

The range of floating-point numbers is the following:
T_
-1*2**2047 = F -0.5*2**(-2048) F negative
F = 0*2**(-2048) F zero
0.5*2**(-2048) = F 1*2**2047 F positive
or approximately:
&_ 10**(-616) abs(F) 10**616

T_ The relative precision of a floating-point number is 2**(-35) /
abs(fraction), which lies between 2**(-35)=3*10**(-11) and
&_ 2**(-34)=6*10**(-11).

The left-most two bits of a normalized fraction are 01 and 10,
respectively, for positive and negative numbers.

The floating-point zero is represented by the fraction 0 and the
exponent -2048.

Accordingly, the sign or zero value of a floating-point number\f

may be determined by examining its first word only. This can be
done by means of skip instructions.

The following instructions will load a floating-point number in
w0 and w1 and test whether it is negative:

T_ dl. w1 float. ; w0-1 = number ; float points to
second word
sh w0 -1 ; if number 0 then
&_ jl. negative.; goto negative

T_ 5.2 Arithmetic Operations

Addition and subtraction require an alignment of radix points.
This is done by shifting the fraction with the smaller exponent
&_ to the right a number of positions equal to the difference in ex-
ponents. After alignment, the addition or subtraction of the frac-
tions is performed, and the larger exponent is attached to the
result. The resulting fraction is normalized and rounded as de-
scribed below.

Multiplication is performed by addition of the exponents and mul-
tiplication of the fractions. The fraction product is formed by
repetition of an add-and-shift cycle. Normalization and rounding
of the resulting fraction proceeds as for addition and subtrac-
tion (see below).

Division is performed by subtraction of the exponents and divi-
sion of the fractions. The fraction quotient is formed by the
non-restoring division method. Rounding of the quotient is per-
formed as described below. The remainder is thrown away.

T_ 5.3 Normalization and Rounding

If the resulting fraction is zero, a floating-point zero with
&_ exponent -2048 is delivered as the final result.
\f

A non-zero fraction is normalized either by left shifts to elimi-
nate leading sign bits or by a single right shift to correct for
overflow of the fraction. The exponent is decreased (increased)
by the number of left (right) shifts performed.

A non-zero, normalized fraction is rounded by adding 1 in bit 36.
After rounding, the fraction may require normalization once more
before the high-order 36 bits and the exponent are delivered as
the final result.

The maximum value of the rounding error is 0.5 in the least
significant position of the 36-bit fraction of the result.

T_ 5.4 Underflow, Overflow and Non-normalized Operands

Underflow and overflow occur when the exponent of the final re-
&_ sult (after normalization, rounding and renormalization) is less
than -2048 or greater than 2047, respectively. This will be re-
gistered in the exception register as shown below and will lead
to a floating point exception if the "floating point exception
active" bit is set in the status register.

After underflow or overflow, the fraction is correct, while the
exponent is taken modulo 4096.

Division by zero leaves the register operand unchanged and is
defined as overflow even if zero is divided by zero. Considering
the range of floating point numbers, both underflow and overflow
will usually indicate a programming error.

No check is made of whether operands are correctly normalized
floating point numbers. Results of operations on non-normalized
numbers must be regarded as undefined, they may be non-normalized
and they may be different on different versions of RC 8000. See
however the descriptions in chapter 10.

The exception register has the following meaning after a floating
point operation:

T_ Bit Meaning
21 (unchanged)
22 floating point overflow
&_ 23 floating point underflow

T_ 5.5 Floating Point Instructions

The "f_l_o_a_t_i_n_g_ point : a_d_d_ to double register" instruction, "fa",
adds the contents of the doubleword pointed out by the effective
address to the specified double register. If the effective ad-
dress is 0 through 7, the operation is a doubleregister - double-
register operation. Reference to non-accessible area and to the
lower limits of the process area (addr = lowlim - base) and the
common protected area (addr = 8) leads to program exception. Un-
derflow and overflow conditions are indicated in the exception
register. If the "floating point exception active" bit is set in
the status register underflow and overflow will lead to a floa-
ting point exception. After underflow and overflow the fraction
of the result is correc while the exponent is taken modulo 4096.

The "f_l_o_a_t_i_n_g_ point : s_u_b_t_r_a_c_t_ from double register" instruction,
"fs", subtracts the contents of the doubleword pointed out by the
effective address from the specified double register. Otherwise
as "fa".

The "f_l_o_a_t_i_n_g_ point : m_u_l_t_i_p_l_y_ by double register" instruction,
"fm", multiplies the specified double register with the contents
of the doubleword poin ted out by the effective address.
Otherwise as "fa".

The "f_l_o_a_t_i_n_g_ point : d_i_v_i_d_e_ into double register" instruction,
"fd", divides the specified double register with the contents of
the doubleword pointed out by the effective address. The quotient
is placed in the doubl register, the remainder is thrown away.
Otherwise as "fa".

T_ 5.6 Number Conversion

Mixed arithmetic is supported by number conversion instructions
and normalizing shift instruction. The normalize instructions may
&_ of cause be used for other purposes.

The "c_o_n_v_e_r_t_ i_n_t_e_g_e_r_ to floating point" instruction, "ci", con-
verts the integer value of the specified register to a floating
point number and places the result in the corresponding double
register. The effective address is used for scaling, such that
the value of the result is two to the power of effective address
times the integer. Floating point overflow and underflow may oc-
cur through scaling and is handled as for the floating point in-
structions.

The "c_o_n_v_e_r_t_ f_l_o_a_t_i_n_g_ point to integer" instruction, "cf", con-\f

verts the floating point value of the specified double register
to an integer and places the result in the least significant re-
gister. The effective address is used for scaling, such that the
value of the result is two to the power of effective address
times the floating point number rounded to nearest integer. Carry
= 0 and integer overflow is registered in the exception register.
Integer overflow will lead to integer exception if the "integer
exception active" bit is set in the status register.

The "n_o_r_m_a_l_i_z_e_ s_i_n_g_l_e_ register" instruction, "ns", normalizes the
contents of the specified working register by shifting it to the
left until bit 0 and bit 1 have opposite values. The negative
number of shifts necessary is stored in the halfword pointed out by
the effective address. Normalization of zero will give zero and
store the value -2048.

Effective address 0 through 7 will cause the negative shift value
to be assigned to the corresponding half register. Other referen-
ces outside the process area will lead to program exception.

The "n_o_r_m_a_l_i_z_e_ d_o_u_b_l_e_ register" instruction, "nd", works as "ns"
but on the specified double register.

T_ 5.7 Examples

; variables and constants; addresses of doublewords point at second
; word
fhalf : 0.5 ; rounding of floating
; point
roundconst: d.1024 ; rounding double integer
; = bit 37
integer1 : 24 bit integer value' ; variable
integer2 : 24 bit integer value' ; -
float1 : floating point value' ; -
float2 : floating point value' ; -
&_ dinteger : 48 bit integer value' ; -
\f

T_ ; mixed arithmetic

rl. w1 integer1. ;
ci w1 0 ;
rl. w3 integer2. ;
ci w1 0 ;
fd w1 6 ;
ds. w1 float1. ; float1 = integer1/integer2

rl. w1 integer1. ;
ci w1 0 ;
fa. w1 float1. ;
cf w1 0 ;
rs. w1 integer2. ; integer2 = integer1 + float1
&_
T_ ; conversion of double register to floating point

dl. w1 dinteger. ;
nd. w1 3 ; negative shifts are
; stored as displacement
; in next instruction
al w2 0-0-0 ; note notation for changed
; displacement
sn w2 -2048 ; if dinteger = 0 then
jl. assignexp.; goto assignexp; result
; = 0.0
al w2 x2+48 ; exponent = - shifts +48
ad w1 -1 ; prevent rounding overflow

aa. w1 roundconst.; add bit 37 to round
nd. w1 3 ; renormalize
al w2 x2+0-0-0 ; exponent = exponent
; -(1 or 0)
assignexp: hs w2 3 ; assign exponent
&_ ds. w1 float1. ; float1 = dinteger
\f

T_ ; if rounding of large double integers is not needed the code is
; reduced to

dl. w1 dinteger. ;
nd. w1 3 ;
al w2 ;
se w2 -2048 ;
al w2 x2+47 ;
hs w2 3 ;
&_ ds. w1 float1. ; float1 = dinteger

T_ ; conversion of floating point to double integer

dl. w1 float1. ;
fa. w1 fhalf. ; round
el w2 3 ; load exponent
ad w1 -12 ; remove exponent bits
ad w1 x2-35 ; shift according to exponent
; overflow may occur
ds. w1 dinteger. ; dinteger = float1

Without giving examples it may be noted that correct integer
arithmetic with 35 significant bits can be simulated by the
floating point instructions. \f

F_6 MONITOR CONTROL

The RC 8000 is designed to operate a multiprogramming system
under the control of a monitor program, defining the specific
multiprogramming environment. Full monitor control is ensured by
the protection system, which consists of the memory protection
and the concept af privileged instructions. The memory protection
is described in chapter 3.

Privileged instructions are the i-o instructions and the instruc-
tions that may change the protection situation. These instruc-
tions may only be executed in monitormode.

The monitor program is entered through interrupts and monitor
calls. The current user program is suspended, registers and sta-
tus are dumped and the monitor program is entered according to
the cause with memory protection and program relocation disabled.
Dump and entry addresses are defined by a system table pointed
out by the system information register, "inf". This table and the
register must be set up by the monitor program according to moni-
torstructure and current system status. User programs are reac-
tivated through the privileged "return interrupt" instruction,
which restores the dumped registers and the protection situation.

T_ 6.1 System Table

The system table consists of 6 consequtive words with the
following contents.

inf-5 : monitor call service address
inf-3 : interrupt service address
inf-1 : status/intlim initialization
inf+1 : register dump address
inf+3 : exception service address
&_ inf+5 : escape service address

The system information register, inf, points to the s_e_c_o_n_d_ half-
word of the status/intlim initialization.

The exception and escape service addresses define register dumps
and entry points for the current userprogram>s use of the excep-
tion and escape facilities, see further 6.5.1 and chapter 7.\f

These addresses are logical addresses, the remaining addresses
are physical addresses in true memory.

T_ 6.2 Entering the monitor program

Entry of the monitor program proceeds in the same way for moni-
&_ torcalls and interrupts except for the initial assignment of
cause and the final selection of service address.

The 8 dynamic registers are dumped starting at the register dump
address:

T_ register dump address + 0 : w0
- + 2 : w1
- + 4 : w2
- + 6 : w3
- + 8 : status
- +10 : ic
- +12 : cause
&_ - +14 : addr

The 12 most significant bits of the status register is assigned
the value of the most significant halfword of status/intlim ini-
tialization. The 12 least significant bits are cleared.

The enable limit in the intlim register is assigned the value of
the 12 least significant bits of status/intlim initialization,
the disable limit is set to zero, see further 6.6.

T_ Status/intlim initialization:

0 1 2 3 4 5 6 11 12 23
1 0 0 escapemasc intlim initialization

aritmetic exceptions active
after address modify,after
escape, should be zero
escape mode
&_ monitor mode, should be one

The remaining process definition registers are initialized as
follows:
\f

T_ base = 0
lowlim = 8
uplim = size, the size register must contain memory
&_ size

This initialization disables program relocation and memory pro-
tection.

The working registers are initialized thus:

T_ w0 = unchanged user value
w1 = register dump address + 16
w2 = cause
&_ w3 = unchanged user value

After this the relevant service address is fetched from the sys-
tem table. The inf register is decreased by 12 defining a new sy-
stem table and the monitor program is started at the service
address.

The definition of a new system table and the way status is ini-
tialized allows use of the exception and escape facilities in
connection with the monitor program and allows special handling
of not disabled interrupts during execution of the monitor pro-
gram. Total disabling is obtained by specifying an intlim ini-
tialization zero. Interrupts that can not be disabled, i.e. the
internal interrupts see 6.5.1, will halt the cpu if intlim is
zero.

Errors during entering the monitor program will increase the dump
error count in status, decrease inf by 12 and repeat the action
with the new system table. For details see chapter 10.

6.3 Reactivation of User Program

Reactivation of the user program is done by execution of the "r_e_-
t_u_r_n_ from i_n_t_e_r_r_u_p_t_" instruction, "ri".

The "inf" register is increased by 12 reselecting the system
table valid at monitor entry. The monitor program selects the
user program by assigning values to this system table.

The 8 dynamic registers are restored from the register dump
pointed out by the register dump address in the systemtable.\f

The process definition registers are restored from 5 consequtive
words pointed out by the sum of the register dump address and the
effective address of the ri instruction:

T_ register dump addr + effective address + 0 : cpa
- + 2 : base
- + 4 : lowlim
- + 6 : uplim
&_ - + 8 : intlim

The user program is entered at the dumped instruction counter.

"ri" is a privileged instruction.

T_ 6.4 Monitor Calls

Programmed activation of the monitor program from a user program
&_ is executed as a special case of the "j_u_m_p_ and select d_i_s_a_b_l_e_
limit" instruction, "jd", see 6.6. If the effective address of
the "jd" instruction fullfill the condition:

T_ -2048 _ addr -2048 + function limit
where
&_ function limit = 2048 - montop
a monitor call is executed. The montop register must have been
initialized by the monitor program. The address space used for
definition of monitor calls would otherwise have lead to program
exception, since it is contained in the non-accessible area.

After the common interrupt and monitor call action described in
6.2, the monitor program is entered at the monitor call service
address specified in the system table. The cause is defined as
function number equal to effective address plus 2048. If the
least significant bit of the function number is ignored a fast
selection of the monitor function is obtained in the monitor
program by

call entry : jl. (x2 + functiontable.) ; switch to function
T_ functiontable: function 0 ; address of code for function 0
function 2 ; - 2
- ; -
- ; -
&_ \f

Parameters and results may be exchanged between the user program
and monitor program via the register dump. Return is through the
"ri" instruction.

T_ 6.5 Interrupts

RC 8000 has a program interrupt system with priority levels. The
&_ interrupt levels are described by levelnumbers, lowest numbers
having highest priority.

T_ 6.5.1I_n_t_e_r_n_a_l_ _I_n_t_e_r_r_u_p_t_
The level numbers 0 through 5 are assigned to program events de-
fined as internal interrupts. These interrupts can not be dis-
abled.

Level no. meaning
0 program interrupt
1 integer interrupt
2 floating point interrupt
3 system table error, see chapter 10
4 buserror in operand reference
&_ 5 buserror in instruction fetch

Program interrupt is defined when a program exception occurs and
the exception service address in the system table is zero or when
an escape takes place with escape service address zero.

Integer and floating point interrupt ire analogous to program
interrupt, but refer to arithmetic exceptions.

Buserror interrupts are usually triggered by memory faults. See
further 8.2.

T_ 6.5.2 P_o_w_e_r_ _F_a_i_l_u_r_e_ _a_n_d_ _T_i_m_e_r_
Level 6 is assigned to powerfailure interrupt. The power failure
&_ interrupt leaves at least 1 millisecond to prepare the power re-
start and force a halt. Level 6 should only be disabled in excep-
tional situations and only for very short periods.

Level 7 is assigned to timer interrupt. RC 8000 is supplied with
a 16 bit real time clock register, rtc, which is increased by one
every 0.1 millisecond. A timer interrupt is generated every timer
interrupt period, 25.6 milliseconds in most of the RC 8000 mo-
dels.
\f

T_ 6.5.3 E_x_t_e_r_n_a_l_ _I_n_t_e_r_r_u_p_t_s_
The remaining levels are used for exteral events. External inter-
&_ rupts are defined by the processors on the unified bus by addres-
sing the cpu and transferring the levelnumber as data. The number
of levels available depends on model. Assignment of external lev-
els is under program control, see further chapter 8.

T_ 6.6 Disabling of Interrupts

Interrupt request are registered in the interrupt register "int-
reg", one bit for each level. "Intreg" is continously scanned.
When a bit equal one is found an interrupt flag is set and the
corresponding level number is saved in the current level register
"curlev", and the scan is stopped. Disabling is implemented by
restricting the scan to level numbers lower than or equal to a
limit defined by the interrupt limit register and the disable bit
in the status register.

T_ Interrupt limit register:

disable level enable level
&_ 0111223

When the "disable" bit in "status" is one, the scan limit is
defined as the disable limit and when it is zero as the enable
limit.

The "disable" bit is controlled by the special jump
instructions:

The "j_u_m_p_ and select e_n_a_b_l_e_ limit" instruction, "je", sets the
"disable" bit to zero and proceeds as a "jl" instruction.

The "j_u_m_p_ and select d_i_s_a_b_l_e_ limit" instruction, "jd", tests the
effective address against the monitor call definition, 6.3, if it
is not a monitor call the "disable" bit is set to one and the
"jl" actions are executed.

A normal user program will have "disable level" equal to "enable
level" equal to maximum level number, this means no disabling and
"je" and "jd" reduced to normal jumps except for the monitor call
function of "jd".

The monitor program is entered with disable bit zero, disable
level zero and enable level initialized from the systemtable,
usually to 6, disabling all levels but power failure. \f

T_ 6.7 Interrupt Response

The interrupt flag is examined at the completion of every in-
&_ struction. If the flag is set, the cause is defined as two times
the saved levelnumber in "curlev" and the corresponding bit in
"intreg" is cleared. After the common interrupt and monitor call
action the monitor is entered at the interrupt service address
defined in the system table, with the interruptflag cleared and
the interruptscan restarted according to the new value of "int-
lim".

T_ 6.8 Control of Monitor Registers

&_ The "g_e_n_e_r_a_l_ p_u_t_ into processor register" instruction, "gp",
transfers the contents of the specified working register to the
register pointed out by the effective address. "gp" is a privi-
leged instruction.

T_ Effective addres Effect
26 inf = working register
30 size = working register
32 montop = working register
94 the contents of the working register
is interpreted as an interrupt level
and the corresponding bit in "intreg"
is cleared. Only used at power restart
and in testprograms.
other depends on model, may be destructive,
&_ used for technical testprograms.

The "g_e_n_e_r_a_l_ g_e_t_ from processor register" instruction, "gg",
transfers the contents of the register pointed out by the
effective address to the specfied working register.

T_ Effective address Effect
26 working register = inf
30 working register = size
32 working register = montop
100 working register = rtc
The contents of the 16 bit real time clock
register is transferred to the 16 least
significant bits of the working register.
Remaining bits are cleared. rtc is
unchanged.
other depends on model. Used for technical
&_ testprograms.\f

F_ 7 EXCEPTIONS AND ESCAPE.

An exception occurs, when the protection system is violated, when
execution of an unassigned instruction code is attempted and, if
wanted, when results of arithmetic operations are outside the
range of number representation. These events are caused by pro-
gramming errors. As an aid in finding these errors the exception
concept offers the possibility of register and statusdump com-
bined with activation of a programmed exception routine. A large
part of programming errors will result in exceptions, but in many
cases the original cause is obscured. The escape facility pro-
vides a tool for tracking down these and other errors and for
gathering information on program flow and data usage to aid in
program tuning.

T_ 7.1 Exception

When an exception occurs the exception service address is fetched
&_ from the system table. If the address is zero, the monitor pro-
gram is called through an internal interrupt. If the address is
nonzero, the 8 dynamic registers are dumped and the program is
restarted at the address following the dump.

T_ 7.1.1 R_e_g_i_s_t_e_r_ _D_u_m_p_ _a_t_ _E_x_c_e_p_t_i_o_n_
address contents after exception
exc. service addr. + 0: w0
- + 2: w1
- + 4: w2
- + 6: w3
- + 8: status
- +10: ic
- +12: cause
- +14: addr
- +16: entry point for
&_ routine'

The register dump must be inside the process area defined by the
limit registers. The registers are dumped with the values they
had when the exception occurred. Exact interpretation may require
knowledge of the details in instruction excecution given in chap-
ter 10, but in most cases the following general principles are
sufficient for the analysis. \f

The cause register gives the cause of the exception

T_ cause = 0 : program exception i.e. protection viola-
tion or unassigned instruction code
cause = 2 : integer exception i.e. overflow
cause = 4 : floating point exception i.e. over- or
&_ underflow

The instructon counter points to the word after the instruction
causing the exception.

T_ 7.1.2 P_r_o_g_r_a_m_ _E_x_c_e_p_t_i_o_n_
Exception caused by attempts to execute privileged or unassigned
instruction codes leaves working registers and status unchanged
&_ but the address calculation has been carried out before the ex-
ception is recognized and the result is given in the dumped addr
register.

At memory protection violation the addr register contains the lo-
gical address causing the violation. In multiword instructions
this address may point to any of the addressed words. Early steps
in the instruction may have changed the contents of the specified
working register(s). Violation in indirect address calculation
will leave the intermediate address in the addr register and set
the after am bit in the dumped status register, this bit is zero
at all other exceptions. This indication of exception in indirect
addressing is not implemented on RC 8000/45.

T_ 7.1.3 A_r_i_t_h_m_e_t_i_c_ _E_x_c_e_p_t_i_o_n_s_
At arithmetic exceptions the exception part of the status regis-
ter expand the cause. For memory referring arithmetic instruc-
tions the addr register contains the logical address of the ope-
rand, (for doubleword instructions the logical address of the
preoperand).

T_ 7.1.4 E_x_c_e_p_t_i_o_n_ _R_o_u_t_i_n_e_
Before entering the exception routine the registers are initia-
lized thus:

w0: dumped instruction counter
w1: w-field of cause instruction
w2: dumped addr register
w3: cause
&_ ex: dumped exception register

Protection, relocation, escapemode, escapemask, "integer exception\f

active" and "floating point exception active" are unchanged.

What the exception routine does is up to the programmer.

A primitive exception routine regards any exception as an error,
the register dump is output for analysis by the program
maintenance staff and the program is aborted after dumping of
program and variables.

An advanced exception routine classifies the exceptions as non-
repairable, repairable and intentional.

Non-repairable exceptions may be handled as above. Repairable
exceptions trigger a corrective action after which return is made
to the instruction pointed out by the dumped instruction
counter.
\f

T_ Example: repairing of floating point exception:

; replaced by dump of
exaddr: 0 ; w0
w01: 0 ; w1
0 ; w2
w23: 0 ; w3
0 ; status
ic: 0 ; ic
0 ; cause
0 ; addr
;
entry: sn w3 4 ;if cause = 4 then
jl. float. ; goto float
- ;
- ; code for non-repairable error
- ;

float: ls w1 1 ; w1=2*w1, w1=rel addr of reg in
; dump
al w2 x1-2 ; w2=w1-2
sh w2 -1 ; if w2 0 then
al w2 6 ; w2=6, w2= rel addr of reg pre
; in dump
sx 2.1 ; if underflow then
jl. underflow.; goto underflow
rl. w0 x2+exaddr. ; w0= first part of result,
; prepare last sign of result
sl w0 0 ; if result '_ 0
am pos-neg ; then w3-0 = maxpos
am neg-fzero ; else w3-0 = macneg
underflow: dl. w0 fzero. ; underflow : w3-0=zero
rs. w3 x2+exaddr. ; overwrite dumped result
rs. w0 x1+exaddr. ; with corrected result in w3-0
dl. w1 w01. ; restore w0-1 contents
dl. w3 w23. ; restore w2-3 contents
jl. (ic.) ; continue with instruction after
&_ ; exception.
T_
fzero: 0.0 ; floating point zero, double-
; word, addr points to second
; word.
neg: -1.6x10**616 ; maximum negative floating
; point number
pos: 1.6x10**616 ; maximum positive floating
&_ ; point number \f

The coding of this example aims to illustrate practical use of
the facilities in address calculation f.ex. the am-construction
loading the corrected result. Floating point exceptions are re-
paired by substituting the result with zero in case of underflow
and a maximum number with correct sign in case of overflow.

Intentional exceptions may be produced by inserting illegal in-
structions as breakpoint to trigger testoutput or similar action.
A more sophisticated use is to program in such a way that rare
conditions automatically will result in an exception f.ex.
through a table lookup that in all normal cases gives a legal
address, but in special cases gives an illegal address. This may
give a speed-up of a program by eliminating the need for in-line
testing for special cases.

Exception routines can as shown return to the program through a
normal jump. It is however in some cases useful to consider to
return by means of the "return from escape" instruction, see
further 7.2.5 and 7.2.6.

T_
7.2 Escape

&_ The escape facility is controlled by the escape mode bit and the
escape mask in the status register. If the escape mode bit is ze-
ro the escape facility is inactive. If it is one the escape faci-
lity is active, which means that every instruction execution in-
clude an escapetest which may lead to an escape depending on the
result of a logical comparison between the escape masc and an
escape pattern defining the properties of the instruction.

T_7.2.1 E_s_c_a_p_e_ _i_n_ _I_n_d_i_r_e_c_t_ _A_d_d_r_e_s_s_ _C_a_l_c_u_l_a_t_i_o_n_
The escape action is triggered after the completion of the add-
ress calculation and before any instructon execution has taken
place. Information is set up for fast analysis and for resuming
the execution. There is one exception, if the escape mask speci-
fies escape on memory load, statusbit 10, an escape is triggered
by the memory load in indirect address calculation. In this case
preparation is made for resuming the address calculation with the
load of the effective address, after which a normal instruction
escape may take place, see further below.

T_7.2.2 E_s_c_a_p_e_ _M_a_s_k_ _a_n_d_ _E_s_c_a_p_e_ _P_a_t_t_e_r_n_
As described in 2.2.1 the escape mask occupies bit 6-11 of the
status register. The meaning of the bits are given below. If a
bit in the escape mask is one and escapemode is active the es-
capeaction will be triggered for all instructions having the
corresponding property. The instruction properties are described
by their escape patterns.

T_ status-
bit property

6 privileged,jd,je, unassigned
7 may modify ic,jumps, skips, ri and re
8 multiword operand, doubleword instructions,
ri and re.
9 stores in memory
10 loads from memory
&_ 11 auxiliary bit

The auxiliary bit is used in the escape patterns to ensure that
an all one escapemask trigger on all instructions. Escape pat-
terns are given in the instruction tables Appendix 1 to 3.

T_7.2.3 E_s_c_a_p_e_ _A_c_t_i_o_n_
When the escape action is triggered the escape service address is
fetched from the system table. If the address is zero, the moni-
tor program is called through an internal interrupt. If the ad-
&_ dress is nonzero, the 8 dynamic registers are dumped and the
program is restarted at the address following the dump.

T_7.2.4 R_e_g_i_s_t_e_r_ _D_u_m_p_ _a_t_ _E_s_c_a_p_e_
address content after escape
escape service addr + 0 :w0
- + 2 : w1
- + 4 : w2
- + 6 : w3
- + 8 : status
- +10 : ic
- +12 : cause
- +14 : addr
- +16 : entry point for routine'\f

The working registers are dumped with the values they had at com-
pletion of the previous instruction.

The status register is dumped in the same way, except that the
"after escape" bit is one, and that the "after address modify"
bit is zero for a normal escape and one for an escape in indirect
address calculation.

T_ Status register

0 1 2 3 4 5 6 11 20 21 23

exception register
disable
escapemask
aritm. except active
after escape = 1
after address modify
escape mode = 1
monitor mode
&_
The dumped instruction counter points to the instruction causing
the escape.

The dumped cause register specifies the cause by the F-field and
the escape pattern of the instruction.

T_ Cause register at normal escape:

0 11 12 17 23
0 F-field pattern
&_
T_ Cause register at escape in indirect address calculation:

0 10 11 12 17 18 23
0 1 0 0 0 0 0 0 0 0 0 0 1 0
&_
The dumped addr register contains the effective address of the
instruction except at escape in indirect address calculation
where it contains the logical address pointing to the effective
address.
\f

T_ 7.2.5 E_s_c_a_p_e_ _R_o_u_t_i_n_e_
Before entering the escape routine the working registers are
&_ intialized thus:
T_ w0 : dumped instruction counter

w1 : F-field and W-field of instruction

16 21 22 23
0 F-field W
&_
T_ or at escape in indirect address calculation

15 16 21 22 23
0 1 0 0 0 0 0 0 0W

w2 : dumped address register

w3 : escape pattern

18 23
0 pattern
&_
T_ or at escape in indirect address calculaton

18 23
0 0 0 0 0 1 0
&_
Monitormode, disable and exception register are left unchanged,
escapemode, escapemask and arithmetic exceptions active are
cleared in the status register.

What the exception routine does is up to the programmer. A few
examples and hints are given later in this chapter.

T_ 7.2.6 R_e_t_u_r_n_ _f_r_o_m_ _E_s_c_a_p_e_
The register dump is prepared for return to the instruction exe-
cution through the "r_e_t_u_r_n_ from e_s_c_a_p_e_" instruction. If the dump
is not modified the instruction is completed as if the escape had
not taken place at all.

The "r_e_t_u_r_n_ from e_s_c_a_p_e_" instruction, "re", restores the working
register, status, ic, cause and addr from 8 consecutive logical
addresses starting at the effective address of the instruction.
Each of the logical addresses must be either in the process area
or in the common protected area or a program exception will take\f

place. The address calculation in the instruction pointed out by
the restored ic will be modified according to the value of the
"after address modify" and "after escape" bits in the restored
status register as follows:

T_ after addressaftermeaning
modify escape
0 0 normal address calculation
0 1 no address calculation
addr is used directly
1 0 as after an "am" instruction
&_ 1 1 addr = word (addr)

In the last case another escape may be triggered by the same in-
struction depending on escapemode, escapemask and escape pattern.
After address calculation the execution of next instruction
proceeds normally.

Modification of the register dump or selection of a simulted
register dump is possible. This means that the "re" instruction
may be looked upon as a combined jump and register initializa-
tion. Note however that attempts to switch to monitor mode is
ignored, i.e. the monitor mode bit can not be changed from zero
to one, but it may be changed from one to zero.

T_ 7.2.7 E_x_a_m_p_l_e_s_ _a_n_d_ _H_i_n_t_s_
The first example shows a simple jump tracing with a window. The
aim is to trace the program flow leading to an exception, the
&_ cause of which can not be found from the exception information.
The exception triggers a program dump for further analysis, so
the tracing need only generate memory information. Escape mode,
escape serviceaddress and an escape mask only containing "may
modify ic" ("status" bit 7) are supposed to have been set up by a
monitor call. \f

T_ ; contents at entry of escape
; routine
escaddr: 0 ; w0
0 ; w1
0 ; w2
0 ; w3
0 ; status
0 ; ic
0 ; cause
0 ; addr

entry: se w3 2.010000 ; if not true jump then
re. escaddr. ; return, skips etc are
; ignored
rl. w1 pointer. ; load pointer

al w1 x1+4 ; increase pointer
sl. w1 top. ;
al. w1 first. ; cyclically
rs. w1 pointer. ; save increased pointer
rs w0 x1 ; save from addr
rs w2 x1+2 ; save to address
&_ re. escaddr. ; return
T_
pointer: top ; initial value ensures
; correct start

first: 0 ; first word in cyclical buffer
0 ; of double words for storing
- ; of trace information
- ;
0 ; last doubleword
0 ;
top: ;
&_

Skips are ignored since the escape pattern for skips contain the
auxiliary bit. For each true jump the position and the effective
address is stored cyclically in the buffer. The programdump
triggered by the exception will have the n latest jump leading to
the exception displayed in the buffer.

Next example supposes following situation. A programming error is
found to be caused by a wrong contents of a memory word with the
address, memaddr. Study of the programtext does not reveal the\f

illegal updating. The escaperoutine of the example identifies all
store references to the memory word, but does not include the
explicit action on a hit. The escape mask is "stores in memory".

T_ ; content at entry of escape
; routine
escaddr: 0 ; w0
0 ; w1
0 ; w2
0 ; w3
0 ; status
0 ; ic
0 ; cause
0 ; addr

entry: sz w2 1 ; make effective address even
al w2 x2-1 ;
sn. w2 (critical.); if effective addr = critical
; addr
jl. hit. ; then goto hit
so w3 2.001000 ; if escape pattern does not
re. escaddr. ; contain multiword bit then
; return
; next test is thus only executed
; for "ds"
al w2 x2-2 ;
se. w2 (critical.); if effective adress of pre-
; operand '
re. escaddr. ; critical address then return
hit: - ;
- ; code for a hit

- ;
re. escaddr. ; return
&_ critical: memaddr ; address of critical word

These simple examples illustrates the use of the escape facility
as a debugging tool. Another use of the facility is study of pro-
gram behaviour with escape routines generating various kinds of
statistical information.

The escape facility should not be used as a direct programming
tool mainly because of the overhead involved. This argument does
not cover use for theoretical studies. \f

It is tempting but not recommended to use the "re" instruction
for initialization of registers and return from subroutines. The
catch is the implicit assignment of the status register, which,
unless one is very carefull, will eliminate independant use of
the escape facility and independant control of the arithmetic
exceptions.

There is one important exception to this rule. The "re" instruc-
tion is very well suited to return from exception routines. In
this case the status register can be assigned based on the dumped
status which takes care of above argument. The following example
shows the structure of an exception routine handling pagefaults
in a paging system programmed in such a way, that a pagefault
shows up as a negative effective address in the instruction re-
ferring the page. After adjustment of the pagesituation the in-
struction is repeated with correct effective address.
\f

T_ ; contents at entry of exception
; routine
excaddr: 0 ; w0
0 ; w1
0 ; w2
0 ; w3
status: 0 ; status
ic: 0 ; ic
0 ; cause
addr: 0 ; addr

entry: sl w2 0 ; if not pagefault then
jl. error. ; goto error
;
jl. w3 getpage. ; call getpage
; returns with referred page
; in memory, updated pagetable
; and w2 pointing to referred
; word on page
;
rs. w2 addr. ; overwrite dumped addr with
; corrected
dl. w2 ic. ;
lo. w1 aftesc. ; set after escape in dumped
; status
al w2 x2-2 ; dumped ic = dumped ic-2
ds. w2 ic. ;
re. excaddr. ; return

&_ aftesc: 2.0001 0000 0000 0000 0000 0000 ; after escape bit.

In this simple example programming errors leading to negative
effective addresses is handled as pagefaults. Further checks are
supposed to take place in the getpage routine.
\f

F_8 INPUT/OUTPUT SYSTEM

8.1 Main Characteristics

The input/output system is based on a common bus for communica-
tion between all central units, primary memories and peripheral
device controllers, none of which has a special bus status.

UNIFIED BUS UNIFIED BUS

CENTRAL PRIMARY DISC GENERAL
UNIT MEMORY PROCESSOR DEVICE
PROCESSOR

&_
Input/output devices on the bus are regarded as sets of regis-
ters. The only way to communicate with a device is to transfer
data to and from these registers.

Device control functions are performed by addressing a device re-
gister and transferring the appropriate bit pattern to it. Device
status is checked by addressing the status register of the device
and transferring the contents to the central processor. The cur-
rent bus master (see 2.5.1) may interrupt a central processor on
the bus by addressing and transferring the level number to a spe-
cific register in that processor.

T_8.2 I_n_p_u_t_ _a_n_d_ _O_u_t_p_u_t_ _O_p_e_r_a_t_i_o_n_s_

&_ All input and output operations are handled by two privileged in-
structions, "d_a_t_a_ i_n_", "di" and "d_a_t_a_ o_u_t_", "do", which have the
standard instruction format (see chapter 3). Here, the W field
selects the working register to be connected to the bus, while
the effective address of the instruction is used to address the
device register (see below). The basic bus communication tech-
nique used in these operations is described in chapter 2.

T_8.2.1 D_a_t_a_ _I_n_ _I_n_s_t_r_u_c_t_i_o_n_
This instruction is used for input operations, i.e. whenever data
&_ is to be received from a device address on the bus. The contents
of the addressed device register is transferred to the specified
working register.
\f

The CPU clears bit 21-23 in the status register (i.e. the excep-
tion register) and addresses the device register. If the address
is correct, the device places the data on the bus and sends an
acknowledge signal. The CPU receives the data and this signal,
and checks the data for parity completing the transfer by placing
the received data in the specified working register.

If the received data contains a parity error, the parity error
status bit is set in the exception register.

If the device accepts the addressing, but is unable to handle the
request, it sends a not-acknowledge signal, rejecting the opera-
tion. If this signal is received, the communication error status
bit is set in the exception register.

If no signal whatsoever is received by the CPU inside a maximum
responsetime, the timeout status bit is set in the exception re-
gister. Since parity check is carried out independantly on the
undefined data, parity error is usually set too. Timeout is
caused by no one recognizing the address, i.e. noneexisting de-
vice, devicefailure or error in address.

T_8.2.2 D_a_t_a_ _O_u_t_ _I_n_s_t_r_u_c_t_i_o_n_
This instruction is used for output operations, i.e. whenever da-
ta is to be sent to a device address on the bus. The contents of
the specified working register is transferred to the addressed
device register.

The CPU clears the exception register, addresses the device re-
gister and places the data in the specified working register on
the bus. If the address is correct, the device checks the recei-
ved data for parity error and sends an acknowledge signal comple-
ting the transfer.

If the data contains a parity error, the device sends a not-ac-
knowledge signal rejecting the operation.

If the device is unable to handle the request, it also sends a
not-acknowledge signal. In both cases the cause is indicated in
the device status register according to device specifications.
Communication error and timeout is indicated in the exception re-
gister as for Data In. Parity error is not possible.
\f

T_8.2.3 E_x_c_e_p_t_i_o_n_ _I_n_d_i_c_a_t_i_o_n_
The exception bits of the status register have the following
meaning after an operation:

B_i_t_ I_n_p_u_t_ O_u_t_p_u_t_
21 bus parity error 0
22 bus timeout bus timeout
23 bus communicationbus communication
&_ error (device dependent)error (device dependent)

T_8.2.4 M_e_m_o_r_y_ _A_d_d_r_e_s_s_i_n_g_
It is inherent in the unified bus concept that addressing of de-
&_ vice registers in no way differs from the addressing of memory
words. Therefore the data in and data out instructions may be
used for memory reference in monitor mode. Bus communication er-
ror during input will signal memory error in the addressed word.
I/O reference of memory may be used for memory test and for test
of memory size and relieves the programmer from handling busin-
terrupts.

The memory references in instruction fetch and operand references
follow the same pattern, but the assignment of the exception re-
gister is only carried out in case of errors and is accompanied
by generation of an internal interrupt as described in chapter 6.
The Data In and Data Out instructions differ from this in always
assigning the exception register and never generating interrupts.

T_8.3 S_t_a_n_d_a_r_d_i_z_e_d_ _B_l_o_c_k_-_o_r_i_e_n_t_e_d_ _D_e_v_i_c_e_ _C_o_n_t_r_o_l_l_e_r_s_

&_ Standardized block-oriented controllers, such as the disc proces-
sor and the general device processor, are started by means of an
output operation, which addresses the controller as described
below. Here, the contents of the working register is irrelevant.

Once started, the controller fetches its commands from a channel
program in the primary memory and executes them without engaging
the central processor.

Data to be read from or written to a device is transferred di-
rectly between the device controller and the primary memory.
The channel program is normally terminated by a STOP command,
which transfers the standard status information to the primary
memory and interrupts the controlling central processor.
\f

T_8.3.1 D_e_v_i_c_e_ _A_d_d_r_e_s_s_
Device addresses have the following format:

1
0 1 20212223

Bit 0 Logical 1, indicating I/O address.
&_
Bits 1:20 D_e_v_i_c_e_ _n_u_m_b_e_r_. Bits 1:20 are also used to calculate
the device description address (see below). In the
case of multi device controllers, the address is
divided into a main device number and a sub-device
number. In a disc storage system, for example, bits
1:18 may contain the binary number of the addressed
disc processsor, preceded by zeros, while bits 19:20
contains the logical number of one of the four disc
drives.

The function of direct controller commands is de-
fined by the effective address; the data transferred
by the instruction is irrelevant in case of stan-
dardized blockoriented devices.

T_ Bits 21:22 D_e_v_i_c_e_ _f_u_n_c_t_i_o_n_. Bits 21:22 have the following mea-
ning:

00 START CHANNEL PROGRAM
01 RESET DEVICE
10 (reserved)
&_ 11 (reserved)

START CHANNEL PROGRAM causes the address controller
to start the channel program pointed out by the
first word of the device description (see below).
During program execution the controller will not
accept further START CHANNEL PROGRAM commands.

RESET DEVICE causes the addressed controller to
enter an idle and unassigned state, in which it
awaits addressing and can generate no interrupts.

Bit 23 Irrelevant.
\f

T_8.3.2 D_e_v_i_c_e_ _D_e_s_c_r_i_p_t_i_o_n_s_
The address of the device description is calculated using the de-
vice number (bits 1:20) as follows:
&_ device base + device number x 8

The device base, which is common to all devices, is the contents
of word 8 in the primary memory.

The device description contains the following:

1st word: S_t_a_r_t_ _o_f_ _c_h_a_n_n_e_l_ _p_r_o_g_r_a_m_. Address of the first
channel program command.

2nd word: S_t_a_t_u_s_ _a_d_d_r_e_s_s_. First address of the area in the
primary memory to which the standard status informa-
tion is to be transferred at the termination of the
channel program.

3rd word: I_n_t_e_r_r_u_p_t_ _d_e_s_t_i_n_a_t_i_o_n_. I/O address of the central
processor to be interrupted at the termination of
the channel program. The format is a device address.
In single CPU-systems the CPU will usually have
device number 0. In special cases interrupt destina-
tion may be a memory address.

4th word: I_n_t_e_r_r_u_p_t_ _l_e_v_e_l_. Interrupt level to be transferred
to the central processor when delivering the inter-
rupt, see 6.5.3..

T_8.3.3 C_h_a_n_n_e_l_ _P_r_o_g_r_a_m_
Channel programs consist of sequences of three-word commands,
each of which contains a channel command and two parameters. The
command proper (the first word) has the following format:

0 11 12 15 16 17 18 23

Bits 0:11 Irrelevant.
Bits 12:15 C_o_m_m_a_n_d_ _f_i_e_l_d_. Contains the function code.
Bit 16 D_ _f_i_e_l_d_. Indicates data chaining.
Bit 17 S_ _f_i_e_l_d_. Indicates skipping.
Bits 18:23 M_o_d_i_f_i_e_r_ _f_i_e_l_d_. Used to change the effect of
&_ the basic command.

C_o_m_m_a_n_d_ _F_i_e_l_d_
The basic commands can be divided into three groups according to
parameter structure: some require two parameters, others only\f

one, still others none whatsoever. I.e. while two parameter words
are required, the contents may be irrellevant.

The parameter FIRST CHAR ADDRESS specifies the start address of
the memory area to or from which characters (i.e. 8 bit units)
are to be transferred or fetched.

The parameter CHAR COUNT specifies the maximum number of charac-
ters to be transferred.

The parameters DATA 1 and DATA 2, will be interpreted in a device
dependent way.

For some device controllers, only three bits of the command field
are interpreted, in which case the bit pattern x111 indicates
STOP.

T_ Bits Basic
1_2_:_1_5_ C_o_m_m_a_n_d_P_a_r_a_m_e_t_e_r_ _1_ P_a_r_a_m_e_t_e_r_ _2_

0000 SENSE FIRST CHAR ADDRESS CHAR COUNT
0001 READ " "
0010 CONTROL " "
0011 WRITE " "
0100 WAIT (irrelevant) (irrelevant)
0101 (unassigned) " "
0110 CONTROL NO PARAM " "
0111 (unassigned) " "
1000 (unassigned) DATA 1 (irrelevant)
1001 " " "
1010 " " "
1011 " " "
1100 (unassigned) DATA 1 DATA 2
1101 " " "
1110 " " "
&_ 1111 STOP (irrelevant) (irrelevant)

SENSE transfers data from the internal registers or memory of the
controller.

READ transfers data from the external data medium.

CONTROL transfers data to the internal registers or memory of the
controller.

WRITE transfers data to the external data medium. \f

WAIT permits the controller to generate an interrupt on certain
events, such as power low or intervention. The controller enters
a semi-idle state, in which it can accept a new START CHANNEL
PROGRAM command (see section 8.3.1).

For devices used for autoloading, CONTROL NO PARAM with modifica-
tion 0 performs either an initializing function or no function at
all.

STOP terminates the channel program.

O_t_h_e_r_ _F_i_e_l_d_s_
Other fields in the command word are not necessarily inter-
preted; if they are, they have the following meanings:

The D field indicates data chaining and is used to link the cur-
rent command to the next command, so that a connected data trans-
fer may take place to or from a non-connected memory area, indi-
cated by a sequence of FIRST CHAR ADDRESS and CHAR COUNT parame-
ters.

The S field means "skip data transfer" and is used for check
reading and in conjunction with data chaining to transfer
portions of connected data.

The meaning of the modifier field is device dependent, but modi-
fication 0 always indicates normal use of the device.

T_8.3.4 S_t_a_n_d_a_r_d_ _S_t_a_t_u_s_ _I_n_f_o_r_m_a_t_i_o_n_
Standard status information is transferred as 4 words to the pri-
mary memory starting from the status address, contained in the
second word of the device description, either on normal termina-
tion of the channel program by the STOP command or on abnormal
termination by a device error.

The standard status information includes the following:

1st word: C_h_a_n_n_e_l_ _p_r_o_g_r_a_m_ _a_d_d_r_e_s_s_. Indicates the command follow-
ing the current command.
\f

2nd word: R_e_m_a_i_n_i_n_g_ _c_h_a_r_a_c_t_e_r_ _c_o_u_n_t_. Refers to the latest read or
write command or chain of such commands; in the latter
case, the count will be the total count for the chain.
The count may be modified or left undefined by other
commands. The stop command will leave it unchanged.

3rd word: C_u_r_r_e_n_t_ _s_t_a_t_u_s_. Reflects the status of the device at
the termination of the program.

4th word: E_v_e_n_t_ _s_t_a_t_u_s_. Contains information about events that
have occurred since the last sensing of the event sta-
tus register.

The four standard status words are transferred as the first 12
characters by an unmodified sense command. \f

F_ 9 POWER RESTART AND AUTOLOAD

Power restart and autoload are external signals that activate the
corresponding actions immediately. Only features common to all
models are described here.

T_ 9.1 Power Restart

RC 8000 is supplied with a power supervising logic that detects
&_ power failure and generates a restart signal on return of power.
Built-in delays ensures against the effects of rapid oscillation
of power.

A power failure will generate a power failure interrupt while the
system still has at least one millisecond of operable time left.
On systems with non-volatible primary memory this leaves time to
prepare a power restart by saving the inf register or comparable
action and force a halt, preventing undefined actions during the
failure.

The power restart signal will activate the system at the power
restart address, the contents of the word with address = 10. The
following register initializations are performed:

T_ register initialization
status monitormode, all other bits cleared
base 0, no relocation
lowlim 8
uplim 2047 x 4096, no memory protection
intlim 0, totally disabling
&_ inf 1, non disable events leads to halt

The power restart code must reinitialize the registers montop,
size and inf and must clear all bits in the interrupt memory.
Further power restart actions are system dependant, but should
include triggering of power restart actions in all device
handlers and in the system clock routine.

After the specified power restart actions, return to the
interrupted action is obtained by the return interrupt
instruction.

T_ 9.2 Autoload

Autoload triggers the load of one block of program and data from
&_ a standard block oriented device. After loading control is trans-
ferred to the loaded program, which then continues loading and
initialization.

RC 8000 has 2 autoload signals. The first is connected to an
operators panel and triggers autoload from device number 4, which
usually is a magnetic disc storage. The other triggers autoload
from device 2. Device 2 is usually the input channel of a
Frontend Processor interface. In this case the second autoload
signal is connected to the interface and is activated from the
Frontend after local selection of the load medium and preparation
of the first block transfer. This connection is reciprocal, such
that RC 8000 also can perform an autoload of the Frontend.

The autoload action starts by issuing a system reset signal on
the unified bus. After that memory is initialized as described
below, and the device corresponding to the autoload signal is
activated.

address initialization interpretation

8 12-8 * device no. device base
10 -4096 + 1536 power restart address
12 10
14 20 device description, 12-18
16 256 channel program, 10-20
18 22
20 768
&_ 532 jl. 0 end-less loop

The device base value makes the device select the device descrip-
tion starting in address 12 regardless of device number.

The device description selects the channel program starting in
address 10. Standard status will be delivered in words 20-24, and
the interrupt level 22 will be delivered in memory word address
256, and not as an interrupt, see 8.3.2.

The channel program contains an init device command, command
value 6 (parameters are irrelevant), and a read command with
first address 22 and a character count of 768 defining load of
256 words to addresses 22-532. The first words of the load will\f

be interpreted as a continuation of the channel program, while
the last word will overwrite the jl. 0 instruction and liberate
the cpu from the end-less loop. Note that words 22-26 and 256 of
the load will be overwritten when a stop command is reached in
the continuation of the channelprogram.

Before the device is started and control is transferred to the
end-less loop the following register initializations are per-
formed:

T_ register initialization meaning

status 0 user mode
base 0 no relocation
lowlim 534 all memory
uplim 534 writeprotected
cpa 534 only load read accessible
intlim 0 total disable, interrupts
cause halt
size 2047x4096 nearly maximum
montop 2047 only monitor call 0
allowed
inf 525 a system table must be
loaded just before the
instruction overwriting
&_ the end-less loop

The initial underprivileged state, which can only be left through
a monitor call 0 gives a very high assurance against destructive
effects from erroneous autoloads. All errors during the autoload
sequence leads to a halt.

If the autoload device is not activated (rejected or bus time
out), device number is decreased by 1, device base is adjusted
and the new device is activated. In this case the cpu will halt
to await a new autoload signal.

Device number 1 is usually unassigned, such that unsuccesfull
autoload from device 2 leads to halt.

Devicenumber 3 is usually the output channel of the Frontend
interface. In this case the init command value 6 will trigger a
Frontend autoload. This allows the operator to perform a system
load from a Frontend device by disconnecting device 4 and press\f

the autoload button on the RC 8000 operator>s panel, since the
Front End autoload will end by activating the second autoload
signal of RC 8000.

The following example gives a rough idea of how an autoload block
may be structured (nummeric labels indicate resulting addresses
in memory):

T_ 22: 15*256 ; stop command, will be overwritten
0 ; by the 3 last words of the stan-
0 ; dard status
check: value' ; checksum of load block adjusted
; for correct value of overwrite
start: rl w0 check ; entry after load
al w2 22 ;
next: ws w0 x2 ; code for check of load
al w2 x2+2 ;
sh w2 532 ;
jl next ;
se w0 0 ; if checksum error then force
jl -1 ; halt
jd -2048 ; enter monitor mode at init

init: - ; code for further initialization
- ; and loading
&_ - ;

T_ 256: 22 ; overwritten by interrupt
; level = 22
- ;
- ; more code
- ;

0 ; rudimentary system table:
0 ; exception and monitorcalls
0 ; lead to half after jd - 2048
init ; system table: mon call address
0 ; interrupt address
2048*4096 ; mon mode/0
534 ; reg. dump address
0 ; exc address
0 ; esc address
532 jl start ; overwrites end-less loop
&_ ; goto start
\f

«eof»

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